repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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sh-chris110/chris | FPGA/chris.convolution.ok/db/ip/soc_design/submodules/soc_design_niosII_core_cpu_mult_cell.v | 8,060 | module MODULE1 (
VAR56,
VAR3,
VAR24,
clk,
VAR37,
VAR30,
VAR1,
VAR38
)
;
output [ 31: 0] VAR30;
output [ 31: 0] VAR1;
output [ 31: 0] VAR38;
input [ 31: 0] VAR56;
input [ 31: 0] VAR3;
input VAR24;
input clk;
input VAR37;
wire [ 31: 0] VAR30;
wire [ 31: 0] VAR1;
wire [ 31: 0] VAR38;
wire VAR55;
wire [ 31: 0] VAR10;
wire ... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_makq_ctl.v | 7,503 | module MODULE1(
VAR2, VAR3, VAR1, VAR31, VAR29,
VAR33, VAR24, VAR16,
clk, VAR6, VAR11, VAR49, VAR23,
VAR27, VAR46, VAR25
);
input clk;
input VAR6;
input VAR11;
input VAR49;
input VAR23;
input VAR27;
input [VAR32-1:0] VAR46;
output VAR2;
output [VAR19-1:0] VAR3;
output [VAR19-1:0] VAR1;
input VAR25;
output VAR31;
output... | gpl-2.0 |
Cognoscan/BoostLogic | verilog/src/receivers/ClkRecoverSetCounter.v | 2,738 | module MODULE1 #(
parameter VAR10 = 10 )
(
input clk, input rst, input VAR9, output reg VAR11, output reg VAR6 );
parameter VAR12 = VAR1(VAR10-1) - 1;
wire VAR2;
reg [VAR12:0] VAR4; reg VAR5; reg VAR3; reg VAR8;
wire VAR13;
reg VAR7;
assign VAR13 = (VAR4 == 'd0) && ~VAR7;
always @(posedge clk) begin
VAR7 <= VAR4 == 'd0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf.symbol.v | 1,262 | module MODULE1 (
input VAR5,
output VAR2
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
JohnOrlando/gnuradio-bitshark | gr-sounder/src/fpga/lib/sounder_tx.v | 1,557 | module MODULE1(VAR1,VAR6,VAR4,VAR9,VAR8,VAR7,VAR5,VAR3);
input VAR1;
input VAR6;
input VAR4;
input VAR9;
input [13:0] VAR8;
input [15:0] VAR7;
output [13:0] VAR5;
output [13:0] VAR3;
wire VAR11;
wire [13:0] VAR13 = (~VAR8)+14'b1;
VAR2 VAR12
( .VAR1(VAR1),.VAR6(VAR6),.VAR4(VAR4),.VAR9(VAR9),.VAR7(VAR7),.VAR10(VAR11) );
... | gpl-3.0 |
alankarkotwal/lca-processor | USE THESE FILES PRAVEEN/execute.v | 14,319 | module MODULE1( clk, reset, VAR18, VAR16,VAR67, VAR32, VAR87, VAR25, VAR13, VAR15,VAR11,
VAR68, VAR73, VAR48, VAR12,
VAR72,VAR21,VAR83,VAR20,VAR50,VAR61,VAR57,VAR31,VAR33,VAR42,VAR98,
VAR97,VAR64,VAR45,VAR39,VAR30,VAR88,VAR90,VAR27,
VAR7,VAR65,VAR3,VAR10,VAR82,VAR76,VAR92);
parameter VAR86 = 6'b000000;
parameter VAR5 =... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_18.v | 14,328 | module MODULE5 (
clk,
reset,
VAR98,
VAR96,
VAR63,
VAR20,
VAR104
);
parameter VAR12 = 18;
parameter VAR66 = 18;
parameter VAR113 = 9;
localparam VAR62 = 19;
input clk;
input reset;
input VAR98;
input VAR96;
input [VAR12-1:0] VAR63; output VAR20;
output [VAR12-1:0] VAR104;
localparam VAR65 = 18; localparam VAR89 = 36; lo... | mit |
rkrajnc/minimig-de1 | rtl/minimig/PS2Keyboard.v | 37,615 | module MODULE2
(
input clk, input reset, inout VAR61, inout VAR6, input VAR16, input VAR15, output VAR52, output VAR56, output [7:0] VAR68, output reg VAR7, input VAR33, output [7:0] VAR67, output VAR46, output VAR26, output [5:0] VAR3, output VAR13, output [5:0] VAR42,
output [5:0] VAR44
);
reg VAR27; wire VAR64; wire... | gpl-3.0 |
skyfex/svo-raycaster | orlink/hw/orlink_crc16.v | 1,438 | module MODULE1(clk, rst, en, din, dout);
input clk rst, en;
input [7:0] din;
output [15:0] dout;
wire [15:0] VAR3;
reg [15:0] VAR1;
wire [15:0] VAR2;
assign VAR2[0] = din[4] ^ din[0];
assign VAR2[1] = din[5] ^ din[1];
assign VAR2[2] = din[6] ^ din[2];
assign VAR2[3] = din[7] ^ din[3];
assign VAR2[4] = din[12] ^ VAR1[8]... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_sdram_pll.v | 2,154 | module MODULE1(
input wire VAR1,
input wire rst,
output wire VAR54,
output wire VAR5,
output wire VAR51
);
VAR68 #(
.VAR44("false"),
.VAR64("100.0 VAR20"),
.VAR46("VAR24"),
.VAR40(2),
.VAR32("143.000000 VAR20"),
.VAR53("0 VAR49"),
.VAR59(50),
.VAR36("143.000000 VAR20"),
.VAR2("-3758 VAR49"),
.VAR38(50),
.VAR28("0 VAR20... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/mcm_4.v | 5,023 | module MODULE1(
clk ,
rst ,
VAR33 ,
VAR3 ,
VAR27 ,
VAR31 ,
VAR19 ,
VAR22,
VAR39,
VAR11,
VAR16
);
input clk;
input rst;
input VAR33;
input signed [18:0] VAR3;
input signed [18:0] VAR27;
input signed [18:0] VAR31;
input signed [18:0] VAR19;
output reg signed [18+7+2:0] VAR22;
output reg signed [18+7+2:0] VAR39;
output re... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/nfc-substrate/bch_shared_kes-1.0.0/d_KES_PE_ELU_MINodr.v | 5,169 | module MODULE1 (
input wire VAR16,
input wire VAR14,
input wire VAR5,
input wire VAR6,
input wire [VAR13-1:0] VAR15,
output reg [VAR13-1:0] VAR11,
output reg VAR2,
output reg [VAR13-1:0] VAR1
);
parameter [11:0] VAR12 = 12'b000000000000;
parameter [11:0] VAR10 = 12'b000000000001;
parameter VAR4 = 2'b01; parameter VAR7 ... | gpl-3.0 |
colinww/spi-core-generator | example/results_verilog/spi_top.v | 30,557 | module MODULE1(
VAR263, VAR143, VAR123,
VAR254, VAR94, VAR212, VAR170,
VAR161, VAR179, VAR132, VAR51,
VAR208, VAR191,
VAR88, VAR61,
VAR146, VAR71, VAR148,
VAR30, VAR103, VAR57,
VAR249, VAR22,
VAR16, VAR98, VAR206,
VAR134, VAR192,
VAR241, VAR205, VAR33, VAR24,
VAR182, VAR108, VAR12,
VAR83, VAR101, VAR73,
VAR160, VAR260,... | gpl-3.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_div.v | 59,412 | module MODULE1
(
VAR226,
VAR181,
VAR110,
VAR86,
VAR47,
VAR71) ;
input VAR226;
input VAR181;
input VAR110;
input [31:0] VAR86;
input [31:0] VAR47;
output [31:0] VAR71;
tri0 VAR226;
tri1 VAR181;
wire [8:0] VAR7;
reg VAR74;
reg VAR163;
reg VAR120;
reg VAR25;
reg VAR112;
reg VAR164;
reg VAR206;
reg VAR90;
reg VAR185;
reg V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b_1.v | 2,311 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR7 ,
VAR10 ,
VAR9 ,
VAR8,
VAR2,
VAR5 ,
VAR3
);
output VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR10 ;
input VAR9 ;
input VAR8;
input VAR2;
input VAR5 ;
input VAR3 ;
VAR11 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR... | apache-2.0 |
zhaoyang10/mips-cpu | verilog/alu.v | 1,233 | module MODULE1(
input [3:0] VAR2,
input [31:0] VAR4, VAR5,
output reg [31:0] out,
output VAR1);
wire [31:0] VAR8;
wire [31:0] VAR3;
wire VAR10;
wire VAR7;
wire VAR9;
wire VAR6;
assign VAR1 = (0 == out);
assign VAR8 = VAR4 - VAR5;
assign VAR3 = VAR4 + VAR5;
assign VAR10 = (VAR4[31] == VAR5[31] && VAR3[31] != VAR4[31]) ?... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_ps_pp_pkg_sn/sky130_fd_sc_hs__udp_dff_ps_pp_pkg_sn.symbol.v | 1,532 | module MODULE1 (
input VAR6 ,
output VAR5 ,
input VAR9 ,
input VAR2 ,
input VAR8 ,
input VAR4 ,
input VAR3,
input VAR7 ,
input VAR1
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/example_design/PIO_EP_MEM_ACCESS.v | 12,651 | module MODULE1 #(
parameter VAR46 = 1
) (
clk,
VAR4,
VAR63, VAR33, VAR24,
VAR35, VAR65, VAR34, VAR71, VAR38
);
input clk;
input VAR4;
input [10:0] VAR63;
input [3:0] VAR33;
output [31:0] VAR24;
input [10:0] VAR35;
input [7:0] VAR65;
input [31:0] VAR34;
input VAR71;
output VAR38;
localparam VAR74 = 3'b000;
localparam VA... | lgpl-3.0 |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_8/synth/design_1_xbar_8.v | 17,130 | module MODULE1 (
VAR132,
VAR114,
VAR79,
VAR115,
VAR36,
VAR37,
VAR52,
VAR4,
VAR124,
VAR50,
VAR112,
VAR63,
VAR84,
VAR105,
VAR58,
VAR38,
VAR89,
VAR8,
VAR130,
VAR22,
VAR91,
VAR125,
VAR101,
VAR49,
VAR53,
VAR97,
VAR108,
VAR128,
VAR21,
VAR107,
VAR96,
VAR19,
VAR14,
VAR120,
VAR71,
VAR41,
VAR103,
VAR47,
VAR65,
VAR73
);
input wir... | gpl-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_splitter.v | 4,369 | module MODULE1 #
(
parameter integer VAR6 = 2 )
(
input wire VAR2,
input wire VAR5,
input wire VAR7,
output wire VAR3,
output wire [VAR6-1:0] VAR4,
input wire [VAR6-1:0] VAR8
);
reg [VAR6-1:0] VAR1;
wire VAR10;
wire [VAR6-1:0] VAR9;
always @(posedge VAR2) begin
if (VAR5 | VAR10) VAR1 <= {VAR6{1'b0}};
end
else VAR1 <= V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbn/sky130_fd_sc_hs__dlxbn_1.v | 2,177 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR4 ,
VAR1,
VAR8 ,
VAR6
);
output VAR5 ;
output VAR2 ;
input VAR4 ;
input VAR1;
input VAR8 ;
input VAR6 ;
VAR7 VAR3 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR5 ,
VAR2 ,
VAR4 ,
VAR1
);
output VAR5 ;
output VAR2 ;
input ... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_phy_10g_tx.v | 3,094 | module MODULE1 #
(
parameter VAR3 = 64,
parameter VAR4 = (VAR3/8),
parameter VAR2 = 2,
parameter VAR11 = 0,
parameter VAR7 = 0,
parameter VAR5 = 0,
parameter VAR10 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR3-1:0] VAR1,
input wire [VAR4-1:0] VAR9,
output wire [VAR3-1:0] VAR12,
output wire [VAR2-1:0] VAR6,
i... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/source/cmm_errman_cnt_nfl_en.v | 5,926 | module MODULE1 (
VAR12,
VAR3, VAR6,
enable,
rst,
clk
);
output VAR12;
input VAR3; input VAR6; input enable; input rst;
input clk;
parameter VAR7 = 1;
reg VAR2;
reg VAR10;
reg VAR8;
reg VAR5;
wire VAR1;
wire VAR9;
wire VAR4;
always @(posedge clk or posedge rst)
begin
if (rst) {VAR10, VAR2} <= #VAR7 2'b00;
end
else if (~... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1p/sky130_fd_sc_hd__lpflow_inputiso1p.blackbox.v | 1,387 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR5
);
output VAR7 ;
input VAR2 ;
input VAR5;
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/micron/sdram/mobile_sdr.v | 97,106 | module MODULE1 (
clk ,
VAR68 ,
addr ,
VAR122 ,
VAR10 ,
VAR1 ,
VAR149 ,
VAR61 ,
VAR14 ,
VAR30
);
parameter VAR59 = 13; parameter VAR2 = 13; parameter VAR76 = 32; parameter VAR40 = 4; parameter VAR19 = 9; parameter VAR85 = 2; else VAR6 VAR44
parameter VAR59 = 13; parameter VAR2 = 13; parameter VAR76 = 16; parameter VAR40... | gpl-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/MySource/r7lite_top.v | 21,303 | module MODULE1 #(
parameter VAR204 = 0,
parameter VAR2 = 4,
parameter VAR227 = 64,
parameter VAR3 = 2, parameter VAR242 = 3, VAR94
parameter VAR3 = 1, parameter VAR242 = 2, VAR94
parameter VAR139 = 12,
parameter VAR280 = 15,
parameter VAR79 = 3, parameter VAR96 = 2, parameter VAR178 = 2, parameter VAR61 = 1, parameter ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuflp/sky130_fd_sc_lp__clkbuflp.pp.blackbox.v | 1,270 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3,
VAR6,
VAR1 ,
VAR5
);
output VAR4 ;
input VAR2 ;
input VAR3;
input VAR6;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkSoC_Map.v | 13,589 | module MODULE1(VAR41,
VAR13,
VAR16,
VAR30,
VAR33,
VAR7,
VAR37,
VAR39,
VAR9,
VAR5,
VAR20,
VAR43,
VAR45,
VAR34,
VAR25,
VAR14,
VAR26,
VAR23,
VAR24,
VAR17,
VAR15,
VAR22,
VAR6,
VAR1,
VAR12,
VAR38,
VAR32,
VAR46,
VAR11,
VAR40,
VAR36,
VAR42,
VAR18,
VAR35,
VAR31,
VAR27,
VAR2,
VAR4,
VAR8,
VAR28,
VAR10);
input VAR41;
input VAR13;... | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v2_0_fi_xor.v | 5,555 | module MODULE1 #
(
parameter integer VAR2 = 72,
parameter integer VAR8 = 9,
parameter integer VAR3 = 4
)
(
input wire clk ,
input wire [2*VAR3*VAR2-1:0] VAR9 ,
output wire [2*VAR3*VAR2-1:0] VAR6 ,
input wire VAR4 ,
input wire [VAR8-1:0] VAR1 ,
input wire [VAR2-1:0] VAR5
);
localparam VAR11 = VAR2 / VAR8;
reg [VAR2-1:0]... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp.behavioral.v | 2,148 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR16 ,
VAR7
);
output VAR1 ;
input VAR8 ;
input VAR16 ;
input VAR7;
supply1 VAR4;
supply0 VAR20;
supply1 VAR14 ;
supply0 VAR5 ;
wire VAR6 ;
wire VAR10 ;
reg VAR13 ;
wire VAR17 ;
wire VAR12;
wire VAR11 ;
wire VAR19 ;
wire VAR21 ;
wire VAR18 ;
not VAR9 (VAR10 , VAR12 );
VAR2 VAR3 (VAR6 , V... | apache-2.0 |
comododragon/SHA256_FPGA | DelayedSPI/Verilog/SPISlaveDelayedResponse.v | 5,409 | module MODULE1#(
parameter VAR5 = 32,
parameter VAR7 = 32
) (
VAR10,
VAR4,
VAR11,
VAR3,
VAR2,
VAR1,
VAR8
);
generate
if((2 * VAR5) + VAR7 - 'h1 >= 4096) begin
VAR9();
end
endgenerate
input VAR10;
input VAR4;
input VAR11;
output VAR3;
output [VAR5-1:0] VAR2;
input [VAR5-1:0] VAR1;
output VAR8;
reg [VAR5-1:0] VAR12;
reg ... | mit |
omicronns/studies-sys-rek | de1-soc-proc/ip/alu_mul.v | 4,350 | module MODULE1 (
VAR2,
VAR17,
VAR1);
input [7:0] VAR2;
input [7:0] VAR17;
output [15:0] VAR1;
wire [15:0] VAR3;
wire [15:0] VAR1 = VAR3[15:0];
VAR11 VAR14 (
.VAR2 (VAR2),
.VAR17 (VAR17),
.VAR1 (VAR3),
.VAR15 (1'b0),
.VAR8 (1'b1),
.VAR16 (1'b0),
.sum (1'b0));
VAR14.VAR5 = "VAR18=5",
VAR14.VAR6 = "VAR4",
VAR14.VAR12 = "... | mit |
eda-globetrotter/MarcheProcessor | final/src/tosynth Folder/control.v | 6,055 | module MODULE1(VAR25,
VAR14, VAR33,
VAR21, VAR2, VAR4, VAR31,
VAR16, VAR27, VAR20, VAR22,
VAR17,
VAR24,
VAR5);
input [0:31] VAR25;
output [0:4] VAR14, VAR27, VAR20, VAR22;
output [0:2] VAR16;
output [0:1] VAR33;
output [0:20] VAR4;
output VAR21, VAR2;
output VAR17, VAR24;
output [0:15] VAR31;
output [0:127] VAR5;
reg [... | mit |
calee0219/Course | DLAB/Lab02/01_RTL/CONVCOR.v | 4,290 | module MODULE1(VAR41,VAR36,VAR9,VAR46);
input [15:0] VAR9, VAR46;
output [17:0] VAR41, VAR36;
wire signed [7:0] VAR21, VAR39, VAR50, VAR56;
assign VAR21 = VAR9[15:8]; assign VAR39 = VAR9[7:0];
assign VAR50 = VAR46[15:8]; assign VAR56 = VAR46[7:0];
assign VAR41 = VAR21*VAR50 - VAR39*VAR56;
assign VAR36 = VAR21*VAR56 + V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2.behavioral.pp.v | 1,832 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR3,
VAR10,
VAR5 ,
VAR9
);
output VAR7 ;
input VAR4 ;
input VAR3;
input VAR10;
input VAR5 ;
input VAR9 ;
wire VAR6 ;
wire VAR1;
buf VAR12 (VAR6 , VAR4 );
VAR11 VAR2 (VAR1, VAR6, VAR3, VAR10);
buf VAR8 (VAR7 , VAR1 );
endmodule | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_spram_2048x32.v | 12,680 | module MODULE1(
VAR38, VAR37, VAR1,
clk, rst, VAR46, VAR15, VAR32, addr, VAR58, VAR68
);
parameter VAR39 = 11;
parameter VAR4 = 32;
input VAR38;
input [VAR7 - 1:0] VAR1;
output VAR37;
input clk; input rst; input VAR46; input VAR15; input VAR32; input [VAR39-1:0] addr; input [VAR4-1:0] VAR58; output [VAR4-1:0] VAR68;
as... | gpl-2.0 |
titorgalaxy/Titor | rtl/verilog/core/Register_Bank.v | 6,282 | module MODULE1 (
din,
dout,
address,
VAR9,
enable,
VAR13,
VAR21,
VAR3,
VAR68,
VAR1,
VAR33,
VAR5,
VAR45,
VAR30,
VAR4,
VAR2,
VAR63,
VAR37,
VAR29,
VAR46,
VAR54,
VAR64,
VAR48,
VAR20,
VAR31,
VAR14,
VAR19,
VAR25,
VAR26,
VAR11,
VAR7,
state,
clk,
reset
);
parameter VAR52 = 0; parameter VAR34 = 0; parameter VAR28 = 0;
input [VA... | gpl-3.0 |
omicronns/studies-sys-rek | de1-soc/DE1_SoC_CAMERA.v | 13,789 | module MODULE1(
inout VAR188,
output VAR140,
input VAR252,
output VAR259,
input VAR60,
inout VAR255,
inout VAR172,
output VAR9,
inout VAR204,
output VAR72,
input VAR213,
input VAR216,
input VAR47,
input VAR76,
output [12:0] VAR211,
output [1:0] VAR14,
output VAR4,
output VAR78,
output VAR183,
output VAR19,
inout [15:0]... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/Comparator_Equal.v | 1,057 | module MODULE1
(
input wire [VAR2-1:0] VAR3,
input wire [VAR2-1:0] VAR1,
output wire VAR4
);
assign VAR4 = (VAR3 == VAR1) ? 1'b1 : 1'b0;
endmodule | gpl-3.0 |
workcraft/workcraft | ci/substitution-rules/vme-tm.tsmc_ghp.v | 2,672 | module MODULE1 (VAR27, VAR4, VAR9, VAR42, VAR53, VAR39);
input VAR42, VAR53, VAR39;
output VAR27, VAR4, VAR9;
wire VAR37, VAR52, VAR46, VAR41, VAR38, VAR10, VAR65, VAR33, VAR32, VAR47, VAR20, VAR43, VAR62, VAR34, VAR8, VAR25, VAR36, VAR11;
VAR5 VAR6 (.VAR19(VAR37), .VAR58(VAR36), .VAR66(VAR39), .VAR54(VAR42));
VAR28 VA... | mit |
rkrajnc/minimig-mist | rtl/minimig/gayle_fifo.v | 1,920 | module MODULE1
(
input clk, input VAR5,
input reset, input [15:0] VAR10, output reg [15:0] VAR8, input rd, input wr, output VAR2, output VAR1, output VAR3 );
reg [15:0] VAR11 [4095:0]; reg [12:0] VAR6; reg [12:0] VAR4; wire VAR9; reg VAR7;
always @(posedge clk)
if (VAR5) begin
if (wr)
VAR11[VAR6[11:0]] <= VAR10;
end
al... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtp/sky130_fd_sc_ms__dlxtp.pp.symbol.v | 1,333 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR7,
input VAR4 ,
input VAR2,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdaptevaLib/src/ecfg/dv/dv_ecfg.v | 3,531 | module MODULE1();
reg clk;
reg reset;
reg VAR1;
reg [19:0] VAR3;
reg [31:0] VAR4;
reg VAR2;
reg [1:0] VAR5;
begin
begin
begin
begin
begin | lgpl-3.0 |
hoglet67/CoPro6502 | src/m32632/ADDR_UNIT.v | 14,018 | module MODULE1 ( VAR42, VAR18, VAR106, VAR1, VAR74, VAR86, VAR70, VAR101, VAR66, VAR73, VAR34, VAR21, VAR20, VAR69, VAR25, VAR40,
VAR37, VAR16, VAR91, VAR30, VAR81, VAR26, VAR4, VAR102, VAR49, VAR6, VAR98, VAR71,
VAR53, VAR88, VAR13, VAR95, VAR17, VAR5, VAR15, VAR52, VAR3, VAR99, VAR43, VAR35, VAR28, VAR57,
VAR85 );
in... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/ddr2/ddr2_ex_lfsr8.v | 1,393 | module MODULE1 (
clk, VAR6, enable, VAR2, VAR7, VAR1, VAR5);
parameter VAR4 = 32;
input clk;
input VAR6;
input enable;
input VAR2;
input VAR7;
output[8 - 1:0] VAR1;
wire[8 - 1:0] VAR1;
input[8 - 1:0] VAR5;
reg[8 - 1:0] VAR3;
assign VAR1 = VAR3 ;
always @(posedge clk or negedge VAR6)
begin
if (!VAR6)
begin
VAR3 <= VAR4[... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/ip_top/clk_ibuf.v | 4,264 | module MODULE1 #
(
parameter VAR20 = "VAR4" )
(
input VAR8, input VAR3,
input VAR17,
output VAR2
);
wire VAR13;
generate
if (VAR20 == "VAR4") begin: VAR1
VAR5 #
(
.VAR19 ("VAR6"),
.VAR11 ("VAR7")
)
VAR15
(
.VAR16 (VAR8),
.VAR9 (VAR3),
.VAR10 (VAR13)
);
end else if (VAR20 == "VAR14") begin: VAR12
VAR18 #
(
.VAR11 ("VAR7... | lgpl-3.0 |
khldragon/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/dma_ctrl_status_reg_file.v | 79,015 | module MODULE1(
input clk,
input VAR106,
input rst,
output reg VAR210,
input [23:0] VAR3, input [23:0] VAR218,
input VAR314,
output VAR60,
input [31:0] VAR65,
input [11:0] VAR4,
input VAR242,
input VAR191,
input [31:0] VAR70,
input [31:0] VAR153,
input [31:0] VAR118,
input [23:0] VAR75,
input [7:0] VAR246,
output reg V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/conb/sky130_fd_sc_hs__conb.behavioral.v | 1,573 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR8,
VAR3
);
output VAR9 ;
output VAR1 ;
input VAR8;
input VAR3;
wire VAR5;
pullup VAR4 (VAR5);
VAR6 VAR7 (VAR9 , VAR5, VAR8, VAR3);
pulldown VAR2 (VAR1 );
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/axis_gmii_rx.v | 10,228 | module MODULE1 #
(
parameter VAR6 = 8,
parameter VAR8 = 0,
parameter VAR2 = 96,
parameter VAR1 = (VAR8 ? VAR2 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR6-1:0] VAR10,
input wire VAR4,
input wire VAR17,
output wire [VAR6-1:0] VAR9,
output wire VAR12,
output wire VAR15,
output wire [VAR1-1:0] VAR7,
input... | mit |
sirchuckalot/zet | cores/vga/rtl/fml/vga_linear_fml.v | 4,710 | module MODULE1 (
input clk,
input rst,
input enable,
output [17:1] VAR24,
input [15:0] VAR12,
output VAR1,
input [9:0] VAR17,
input [9:0] VAR5,
input VAR16,
input VAR2,
output VAR7,
output [7:0] VAR8,
output VAR22
);
reg [ 9:0] VAR13;
reg [ 6:0] VAR21;
reg [14:1] VAR14;
reg [ 1:0] VAR23;
reg [ 1:0] VAR6;
reg [ 7:0] VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_1.behavioral.v | 2,309 | module MODULE1( VAR5, VAR1, VAR3, VAR4, VAR8 );
input VAR4, VAR8, VAR1, VAR5;
output VAR3;
VAR2 VAR7(.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3),.VAR4(VAR4),.VAR8(VAR8));
VAR2 VAR6(.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3),.VAR4(VAR4),.VAR8(VAR8)); | apache-2.0 |
pradeep9676/pradeep_9676 | logarithmic.v | 1,686 | module MODULE1( VAR13,VAR4);
input [47:0]VAR13;
output reg signed [30:0]VAR4;
wire valid;
wire [5:0] VAR15;
reg [5:0] VAR7;
reg [47:0] VAR12;
reg [47:0] VAR11, VAR3;
reg [53:0] VAR14;
reg [7:0]address;
reg [69:0]VAR8;
reg [108:0] VAR5;
VAR9 VAR1( .in(VAR13), .out(VAR15), .valid(valid));
reg [29:0] VAR2[255:0];
reg [21:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21boi/sky130_fd_sc_ms__a21boi_1.v | 2,332 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR7 ,
VAR3,
VAR5,
VAR4,
VAR8 ,
VAR10
);
output VAR9 ;
input VAR6 ;
input VAR7 ;
input VAR3;
input VAR5;
input VAR4;
input VAR8 ;
input VAR10 ;
VAR1 VAR2 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODULE1 ... | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | contador_AD_DAY_2dig.v | 3,229 | module MODULE1
(
input wire clk,
input wire reset,
input wire [3:0] VAR9,
input wire VAR1,
input wire VAR6,
output wire [7:0] VAR3
);
localparam VAR8 = 5; reg [VAR8-1:0] VAR2, VAR10;
wire [VAR8-1:0] VAR7;
reg [3:0] VAR4, VAR5;
always@(posedge clk, posedge reset)
begin
if(reset)
begin
VAR2 <= 5'b0;
end
else
begin
VAR2 <... | mit |
wgml/sysrek | hdmi_example/src/rx/serdes_1_to_5_diff_data.v | 14,282 | module MODULE1 # (
parameter VAR32 = "VAR52",
parameter VAR42 = 49,
parameter VAR23 = "VAR31"
)(
input wire VAR25, input wire VAR71, input wire VAR26, input wire VAR41, input wire VAR19, input wire reset, input wire VAR5, input wire VAR51, output wire [4:0] VAR86 );
wire VAR47;
wire VAR95;
wire VAR83;
wire VAR56;
wire ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18.pp.blackbox.v | 1,309 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR4,
VAR5,
VAR3 ,
VAR6
);
output VAR1 ;
input VAR2 ;
input VAR4;
input VAR5;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3/sky130_fd_sc_ls__or3.pp.symbol.v | 1,274 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR7 ,
output VAR4 ,
input VAR2 ,
input VAR1,
input VAR8,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill_diode/sky130_fd_sc_ls__fill_diode.behavioral.v | 1,141 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ddr3_source/clocking/mig_7series_v1_9_infrastructure.v | 24,469 | module MODULE1 #
(
parameter VAR20 = "VAR23", parameter VAR18 = 100, parameter VAR59 = 3000, parameter VAR36 = 2, parameter VAR52 = "VAR8",
parameter VAR4 = "VAR23",
parameter VAR57 = 4, parameter VAR54 = 1, parameter VAR38 = 45.0, parameter VAR21 = 16, parameter VAR46 = 4, parameter VAR41 = 64, parameter VAR22 = 16,
p... | gpl-2.0 |
nliu96/openHMC_Altera | src/openhmc_top.v | 22,769 | module MODULE1 #(
parameter VAR134 = 2, parameter VAR151 = 4, parameter VAR31 = VAR151*128, parameter VAR4 = 3, parameter VAR92 = 2**VAR4, parameter VAR125 = VAR151*16, parameter VAR196 = 64,
parameter VAR13 = 64,
parameter VAR123 = 4,
parameter VAR106 = 8, parameter VAR166 = 1, parameter VAR99 = 1, parameter VAR94 = 1... | lgpl-3.0 |
EmbeddedANT/ALTERA_DE0-Nano | DE0Nano_Button/DE0Nano_Button.v | 4,371 | module MODULE1(
VAR9,
VAR18,
VAR20
);
parameter VAR10 =8'b10000000;
parameter VAR14 =8'b01000000;
parameter VAR29 =8'b00100000;
parameter VAR26 =8'b00010000;
parameter VAR12 =8'b00001000;
parameter VAR1 =8'b00000100;
parameter VAR28 =8'b00000010;
parameter VAR6 =8'b00000001;
input VAR9;
output [7:0] VAR18;
input [1:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and2/sky130_fd_sc_hvl__and2_1.v | 2,094 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR2 ,
VAR4,
VAR5,
VAR6 ,
VAR9
);
output VAR7 ;
input VAR1 ;
input VAR2 ;
input VAR4;
input VAR5;
input VAR6 ;
input VAR9 ;
VAR8 VAR3 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR7,
VAR1,
VAR2
);
output VAR7;
... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/ucb_flow_2buf.v | 18,046 | module MODULE1 (
VAR113, VAR116, VAR111, VAR52, VAR112,
VAR109, VAR49, VAR25, VAR33, VAR101, VAR22,
VAR56,
clk, VAR59, VAR126, VAR48, VAR75, VAR95,
VAR60, VAR90, VAR58, VAR97, VAR6, VAR45,
VAR119, VAR65, VAR114, VAR35, VAR127, VAR88
);
parameter VAR124 = 32; parameter VAR15 = 8; parameter VAR24 = 64;
input clk;
input V... | gpl-2.0 |
antmicro/yosys | techlibs/gatemate/cells_bb.v | 5,023 | module MODULE2 #(
parameter VAR45 = "", parameter VAR31 = "", parameter VAR55 = "", parameter VAR3 = 1,
parameter VAR96 = 2,
parameter VAR42 = 4
)(
input VAR14, VAR38, VAR75,
input VAR133,
output VAR35, VAR53,
output VAR126, VAR114, VAR49, VAR68, VAR2
);
endmodule
module MODULE5 #(
parameter [95:0] VAR57 = 96'VAR66,
pa... | isc |
borti4938/sd2snes | verilog/sd2snes_gsu/dac.v | 7,433 | module MODULE1(
input VAR41,
input VAR44,
input VAR43,
input[10:0] VAR52,
input[7:0] VAR21,
input[7:0] VAR1,
input VAR56,
input [2:0] VAR45,
input [8:0] VAR4,
input VAR40,
input reset,
input VAR42,
output VAR7,
output VAR50,
output VAR16,
output VAR23,
output VAR22
);
assign VAR7 = 0;
assign VAR50 = 0;
assign VAR16 = 0... | gpl-2.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_ethmac/eth_wishbone.v | 76,446 | module MODULE1
(
VAR179, VAR48, VAR231,
VAR114, VAR2, VAR97,
VAR16,
VAR140,
VAR240, VAR54, VAR227,
VAR94, VAR283, VAR282,
VAR145, VAR166, VAR222,
VAR63, VAR168,
VAR112, VAR92, VAR292, VAR249, VAR248,
VAR284, VAR3, VAR219, VAR99, VAR288,
VAR318,
VAR281, VAR115, VAR238, VAR314, VAR89, VAR183,
VAR107,
VAR91, VAR21, VAR198... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.behavioral.v | 2,790 | module MODULE1 (
VAR26 ,
VAR5 ,
VAR25 ,
VAR27 ,
VAR23 ,
VAR31
);
output VAR26 ;
input VAR5 ;
input VAR25 ;
input VAR27 ;
input VAR23 ;
input VAR31;
supply1 VAR6;
supply0 VAR19;
supply1 VAR12 ;
supply0 VAR20 ;
wire VAR16 ;
wire VAR1 ;
wire VAR3 ;
reg VAR7 ;
wire VAR30 ;
wire VAR11 ;
wire VAR28 ;
wire VAR9;
wire VAR8 ;
w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfsbp/sky130_fd_sc_ls__dfsbp.pp.blackbox.v | 1,372 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR7 ,
VAR4 ,
VAR9,
VAR2 ,
VAR8 ,
VAR5 ,
VAR1
);
output VAR3 ;
output VAR6 ;
input VAR7 ;
input VAR4 ;
input VAR9;
input VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_pointer_basic_0_1/design_1_pointer_basic_0_1_stub.v | 3,150 | module MODULE1(VAR3,
VAR7, VAR4,
VAR5, VAR6,
VAR2, VAR12,
VAR13, VAR9,
VAR16, VAR8,
VAR15, VAR18,
VAR14, VAR11,
VAR10, VAR17, VAR1, VAR19,
interrupt)
;
input [4:0]VAR3;
input VAR7;
output VAR4;
input [31:0]VAR5;
input [3:0]VAR6;
input VAR2;
output VAR12;
output [1:0]VAR13;
output VAR9;
input VAR16;
input [4:0]VAR8;
inp... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9144/axi_ad9144_core.v | 9,453 | module MODULE1 (
VAR77,
VAR37,
VAR2,
VAR87,
VAR43,
VAR9,
VAR25,
VAR64,
VAR51,
VAR69,
VAR36,
VAR30,
VAR79,
VAR82,
VAR34,
VAR23,
VAR73,
VAR22,
VAR29,
VAR17,
VAR49,
VAR38,
VAR31,
VAR26,
VAR47,
VAR80,
VAR76,
VAR89,
VAR42,
VAR63,
VAR54,
VAR32,
VAR71,
VAR5,
VAR45,
VAR28,
VAR68,
VAR39,
VAR90,
VAR35,
VAR55,
VAR59);
parameter V... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_passthrough.v | 3,035 | module MODULE1 #( parameter VAR38(VAR42 )
, parameter VAR38(VAR43 )
, parameter VAR41 = 0
)
( input VAR18
, input VAR26
, input VAR31
, input [VAR43-1:0][VAR42-1:0] VAR21
, output VAR29
, output VAR5
, output [VAR42-1:0] VAR22
, input VAR3
);
logic [VAR43-1:0] VAR35;
if (VAR43 == 1)
begin : VAR9
assign VAR35 = 1'b1;
as... | bsd-3-clause |
jncronin/jca | cpu/spi.v | 6,129 | module MODULE1(clk, rst, VAR15, addr, VAR14, VAR8, VAR10, VAR9, VAR13, VAR7, VAR1);
input clk;
input rst;
inout [7:0] VAR15;
input [7:0] addr;
input VAR14;
input VAR8;
input VAR10;
output [7:0] VAR9;
output VAR13;
output VAR7;
input VAR1;
parameter VAR3 = 32'd125;
reg [7:0] VAR6[0:11];
assign VAR15 = (~VAR14 & ~VAR8) ?... | mit |
iori-yja/ball_detector | divider.v | 4,447 | module MODULE1 (
VAR16,
VAR6,
VAR3,
VAR2,
VAR4);
input VAR16;
input [4:0] VAR6;
input [10:0] VAR3;
output [10:0] VAR2;
output [4:0] VAR4;
wire [4:0] VAR23;
wire [10:0] VAR12;
wire [4:0] VAR4 = VAR23[4:0];
wire [10:0] VAR2 = VAR12[10:0];
VAR7 VAR1 (
.VAR16 (VAR16),
.VAR6 (VAR6),
.VAR3 (VAR3),
.VAR4 (VAR23),
.VAR2 (VAR12... | mit |
jas0n1ee/THU-DSD | FB/key.v | 2,296 | module MODULE1 (
address,
VAR8,
clk,
VAR4,
VAR3,
VAR7,
VAR5,
irq,
VAR9
)
;
output irq;
output [ 31: 0] VAR9;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR4;
input VAR3;
input VAR7;
input [ 31: 0] VAR5;
wire VAR10;
wire VAR2;
wire irq;
reg VAR6;
wire VAR1;
reg [ 31: 0] VAR9;
assign VAR10 = 1;
assign VAR1 = ({1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4.functional.v | 1,296 | module MODULE1 (
VAR2,
VAR6,
VAR1,
VAR4,
VAR8
);
output VAR2;
input VAR6;
input VAR1;
input VAR4;
input VAR8;
wire VAR5;
and VAR7 (VAR5, VAR6, VAR1, VAR4, VAR8 );
buf VAR3 (VAR2 , VAR5 );
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/db/ip/tracking_camera_system/submodules/tracking_camera_system_sram_0.v | 7,232 | module MODULE1 (
clk,
reset,
address,
VAR9,
read,
write,
VAR7,
VAR10,
VAR5,
VAR6,
VAR14,
VAR8,
VAR4,
VAR3,
VAR13,
VAR12
);
input clk;
input reset;
input [17: 0] address;
input [ 1: 0] VAR9;
input read;
input write;
input [15: 0] VAR7;
inout [15: 0] VAR10;
output reg [15: 0] VAR5;
output reg VAR6;
output reg [17: 0] VAR... | gpl-2.0 |
nickdesaulniers/Omicron | instruction_decode.v | 1,956 | module MODULE1(
input VAR21,
input [6:0] VAR11,
input [15:0] VAR3,
input VAR12,
input [15:0] VAR17,
input [2:0] VAR16,
output [3:0] VAR1, output [6:0] VAR20,
output [15:0] VAR19,
output [15:0] VAR8,
output [6:0] VAR7, output [2:0] VAR9 );
assign VAR20 = VAR11;
assign VAR1 = VAR3[15:12];
assign VAR9 = VAR3[8:6];
assign ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41a/sky130_fd_sc_hs__o41a.pp.symbol.v | 1,340 | module MODULE1 (
input VAR4 ,
input VAR7 ,
input VAR8 ,
input VAR6 ,
input VAR3 ,
output VAR2 ,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp.symbol.v | 1,542 | module MODULE1 (
input VAR5 ,
output VAR3 ,
output VAR7 ,
input VAR6,
input VAR11 ,
input VAR2 ,
input VAR8
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR9 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decap/sky130_fd_sc_lp__decap.functional.v | 1,039 | module MODULE1 ();
endmodule | apache-2.0 |
siamumar/TinyGarbled | circuit_synthesis/cordic/alpha_table.v | 7,592 | module MODULE1
parameter VAR4 = 2,
parameter VAR12 = 14,
parameter VAR10 = VAR5 )
(
VAR1,
VAR8
);
localparam VAR9 = VAR4 + VAR12;
localparam VAR14 = VAR12 + 1;
localparam VAR7 = VAR15(VAR14);
input [VAR7-1:0] VAR1;
output reg [VAR9-1:0] VAR8;
generate
if(VAR9== 16) begin: VAR13
if(VAR10 == VAR5) begin:VAR2
always @ beg... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/riffa/sg_list_reader_64.v | 5,056 | module MODULE1 #(
parameter VAR4 = 9'd64
)
(
input VAR2,
input VAR22,
input [VAR4-1:0] VAR21, input VAR8, output VAR9,
output VAR10, output VAR24, input VAR18, output [63:0] VAR7, output [31:0] VAR11 );
reg [1:0] VAR13=VAR12, VAR13=VAR12;
reg [1:0] VAR23=VAR5, VAR23=VAR5;
reg [VAR4-1:0] VAR14={VAR4{1'd0}}, VAR14={VAR4{... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31o/sky130_fd_sc_hdll__a31o_2.v | 2,353 | module MODULE2 (
VAR2 ,
VAR10 ,
VAR8 ,
VAR9 ,
VAR6 ,
VAR3,
VAR11,
VAR1 ,
VAR5
);
output VAR2 ;
input VAR10 ;
input VAR8 ;
input VAR9 ;
input VAR6 ;
input VAR3;
input VAR11;
input VAR1 ;
input VAR5 ;
VAR4 VAR7 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.... | apache-2.0 |
gbraad/minimig-de1 | rtl/ctrl/ctrl_top.v | 14,380 | module MODULE1 (
input wire VAR6,
input wire VAR4,
output wire VAR8,
output wire VAR32,
output wire VAR38,
output wire VAR36,
input wire VAR24,
input wire [ 4-1:0] VAR37,
output wire VAR19,
output wire VAR2,
output wire VAR27,
output wire VAR17,
output wire [ 4-1:0] VAR41,
input wire [ 4-1:0] VAR31,
output wire [ 18-1:... | gpl-3.0 |
yanhongwang/ColorImage | CTC/CTC_not_synthesis.v | 46,606 | module MODULE2
(
input VAR2,
input reset,
input[ VAR23 - 1 : 0 ]VAR13,
input[ VAR23 - 1 : 0 ]VAR39,
input[ VAR23 - 1 : 0 ]VAR34,
output reg[ VAR8 - 1 : 0 ]VAR7,
output reg[ VAR8 - 1 : 0 ]VAR3
);
reg[ 3 : 0 ]VAR14;
reg[ 3 : 0 ]VAR22;
parameter[ 1 : 0 ]VAR15 = 0; parameter[ 1 : 0 ]VAR36 = 1;
reg[ VAR8 - 1 : 0 ]VAR17;
reg... | mit |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/soc_system_hps_0.v | 30,548 | module MODULE1 #(
parameter VAR154 = 3,
parameter VAR177 = 2
) (
output wire VAR182, input wire VAR164, input wire [7:0] VAR138, input wire [31:0] VAR60, input wire [3:0] VAR82, input wire [2:0] VAR52, input wire [1:0] VAR168, input wire [1:0] VAR30, input wire [3:0] VAR19, input wire [2:0] VAR55, input wire VAR46, out... | mit |
ptracton/pmodacl2 | soc/uart_pb/pb_uart_regs.v | 5,160 | module MODULE1 (
VAR22, interrupt, VAR25, VAR21, VAR13,
enable, VAR23,
clk, reset, VAR27, VAR7, VAR4, VAR14,
VAR8, VAR28, VAR2, VAR1,
VAR15, VAR26, VAR29
) ;
input clk;
input reset;
input [7:0] VAR27;
input [7:0] VAR7;
output [7:0] VAR22;
input VAR4;
input VAR14;
output interrupt;
output VAR25;
output [7:0] VAR21;
outp... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.functional.pp.v | 3,028 | module MODULE1( VAR24, VAR29, VAR20, VAR19, VAR10, VAR30, VAR28, VAR37, VAR14 );
input VAR30, VAR28, VAR10, VAR19, VAR24, VAR20;
inout VAR37, VAR14;
output VAR29;
wire VAR1;
not VAR6( VAR1, VAR30 );
wire VAR31;
not VAR12( VAR31, VAR10 );
wire VAR16;
not VAR22( VAR16, VAR24 );
wire VAR35;
and VAR7( VAR35, VAR1, VAR31, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b.behavioral.v | 1,513 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR13 ,
VAR6
);
output VAR3 ;
input VAR2 ;
input VAR13 ;
input VAR6;
supply1 VAR5;
supply0 VAR12;
supply1 VAR11 ;
supply0 VAR7 ;
wire VAR10 ;
wire VAR8;
nor VAR9 (VAR10 , VAR2, VAR13 );
and VAR1 (VAR8, VAR6, VAR10 );
buf VAR4 (VAR3 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr.behavioral.v | 1,493 | module MODULE1 (
VAR2,
VAR10
);
output VAR2;
input VAR10;
supply1 VAR8 ;
supply0 VAR5 ;
supply1 VAR3;
supply1 VAR4 ;
supply0 VAR9 ;
wire VAR7;
buf VAR1 (VAR7, VAR10 );
buf VAR6 (VAR2 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_1.v | 2,350 | module MODULE1 (
VAR4 ,
VAR1,
VAR3,
VAR8 ,
VAR6 ,
VAR5,
VAR7
);
output VAR4 ;
input VAR1;
input VAR3;
input VAR8 ;
input VAR6 ;
input VAR5;
input VAR7;
VAR2 VAR9 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR4 ,
VAR1,
VAR3,
VAR8 ,
VAR6
);
ou... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_2.v | 2,316 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR4 ,
VAR8 ,
VAR7 ,
VAR10 ,
VAR9,
VAR3
);
input VAR5 ;
input VAR1 ;
output VAR4 ;
output VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR9;
input VAR3;
VAR2 VAR6 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODU... | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/fp_mult_slow.v | 30,031 | module MODULE1
(
VAR58,
VAR1,
VAR45,
VAR3,
VAR49) ;
input VAR58;
input VAR1;
input [63:0] VAR45;
input [63:0] VAR3;
output [63:0] VAR49;
reg VAR33;
reg VAR29;
reg VAR31;
reg VAR61;
reg VAR42;
reg VAR48;
reg VAR5;
reg VAR6;
reg [12:0] VAR19;
reg [12:0] VAR20;
reg VAR60;
reg VAR39;
reg [11:0] VAR36;
reg [10:0] VAR10;
reg... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_async/bsg_launch_sync_sync.v | 16,462 | \
module MODULE1 \
(input VAR4 \
, input VAR5 \
, input VAR24 \
, input [VAR26-1:0] VAR20 \
, output [VAR26-1:0] VAR33 \
, output [VAR26-1:0] VAR7 \
); \
\
\
genvar VAR45; \
\
logic [VAR26-1:0] VAR2; \
assign VAR33 = VAR2; \
\
VAR43 @(VAR22 VAR4) \
begin \
\
if (VAR5) \
VAR2 <= {VAR26{1'b0}}; \
end
else \
VAR2 <= VAR20... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/mc_phy_wrapper.v | 44,770 | module MODULE1 #
(
parameter VAR248 = 100, parameter VAR130 = 2500, parameter VAR333 = "VAR16",
parameter VAR309 = 4, parameter VAR297 = 1, parameter VAR182 = 3, parameter VAR178 = 1, parameter VAR10 = 1, parameter VAR186 = "VAR294", parameter VAR58 = 8, parameter VAR321 = 16, parameter VAR256 = 3, parameter VAR296 = 8... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probe_p/sky130_fd_sc_hvl__probe_p_8.v | 2,062 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR4,
VAR5,
VAR1 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR4;
input VAR5;
input VAR1 ;
input VAR3 ;
VAR8 VAR2 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR7,
VAR6
);
output VAR7;
input VAR6;
supply1 VAR4;
supply0 VAR5;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfstp/sky130_fd_sc_ms__dfstp.functional.v | 1,624 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR3 ,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR7;
wire VAR9;
wire VAR11 ;
not VAR4 (VAR11 , VAR7 );
VAR10 VAR8 VAR2 (VAR9 , VAR3, VAR1, VAR11 );
buf VAR6 (VAR5 , VAR9 );
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N8_R1_P2_syn.v | 2,363 | module MODULE1 ( VAR62, VAR65, VAR12 );
input [7:0] VAR62;
input [7:0] VAR65;
output [8:0] VAR12;
wire VAR21, VAR40, VAR84, VAR58, VAR67, VAR17, VAR43, VAR87, VAR11, VAR2, VAR24, VAR83, VAR71, VAR31,
VAR63, VAR29, VAR18, VAR45, VAR41, VAR30, VAR59, VAR16, VAR61, VAR50;
VAR10 VAR88 ( .VAR73(VAR62[0]), .VAR33(VAR65[0]), ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.behavioral.pp.v | 1,784 | module MODULE1( VAR11, VAR3, VAR7, VAR4, VAR5 );
input VAR3, VAR11;
inout VAR4, VAR5;
output VAR7;
reg VAR6;
VAR10 VAR13(.VAR11(VAR11),.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6));
VAR10 VAR1(.VAR11(VAR11),.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6));
not VAR9(VAR2,VAR3);
buf VAR8(VAR12,... | apache-2.0 |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/7-segment_displays/SEG7_LUT.v | 2,449 | module MODULE1 ( VAR2,VAR1 );
input [3:0] VAR1;
output [6:0] VAR2;
reg [6:0] VAR2;
always @(VAR1)
begin
case(VAR1)
4'h1: VAR2 = 7'b1111001; 4'h2: VAR2 = 7'b0100100; 4'h3: VAR2 = 7'b0110000; 4'h4: VAR2 = 7'b0011001; 4'h5: VAR2 = 7'b0010010; 4'h6: VAR2 = 7'b0000010; 4'h7: VAR2 = 7'b1111000; 4'h8: VAR2 = 7'b0000000; 4'h9:... | gpl-3.0 |
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