repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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teknohog/Xilinx-Serial-Miner | sources/hdl/fpgaminer_top.v | 5,696 | module MODULE1 (VAR34, VAR24, VAR49, VAR35, VAR14, VAR37);
parameter VAR50 = VAR32;
parameter VAR50 = 5;
localparam [5:0] VAR43 = (6'd1 << VAR50);
localparam [31:0] VAR6 = (32'd1 << (7 - VAR50)) + 32'd1;
input VAR34;
reg [255:0] state = 0;
reg [511:0] VAR45 = 0;
reg [31:0] VAR44 = 32'h00000000;
wire VAR10;
VAR7 VAR30 (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai.pp.blackbox.v | 1,355 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR8 ,
VAR1 ,
VAR7 ,
VAR2 ,
VAR3,
VAR4
);
output VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR3;
input VAR4;
endmodule | apache-2.0 |
yipenghuang0302/csee4840_14 | rtl/ik_swift_32/full_jacobian/full_mat/t_block/sincos/mult_21_coeff_26561/mult_21_coeff_26561.v | 2,242 | module MODULE1 (
VAR9,
VAR7,
VAR2,
VAR22);
input VAR9;
input VAR7;
input [20:0] VAR2;
output [41:0] VAR22;
wire [41:0] VAR23;
wire [20:0] VAR15 = 21'd26561;
wire [41:0] VAR22 = VAR23[41:0];
VAR6 VAR20 (
.VAR7 (VAR7),
.VAR17 (VAR15),
.VAR9 (VAR9),
.VAR2 (VAR2),
.VAR22 (VAR23),
.VAR16 (1'b0),
.sum (1'b0));
VAR20.VAR5 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o_2.v | 2,485 | module MODULE1 (
VAR11 ,
VAR8 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR6 ,
VAR1,
VAR12,
VAR2 ,
VAR3
);
output VAR11 ;
input VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR12;
input VAR2 ;
input VAR3 ;
VAR10 VAR4 (
.VAR11(VAR11),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.functional.v | 1,378 | module MODULE1( VAR13, VAR7, VAR6, VAR10, VAR1 );
input VAR1, VAR10, VAR7, VAR13;
output VAR6;
wire VAR5;
not VAR12( VAR5, VAR1 );
wire VAR8;
not VAR14( VAR8, VAR10 );
wire VAR2;
not VAR4( VAR2, VAR7 );
wire VAR9;
not VAR3( VAR9, VAR13 );
and VAR11( VAR6, VAR5, VAR8, VAR2, VAR9 );
endmodule | apache-2.0 |
secworks/ChaCha20-Poly1305 | src/rtl/poly1305_mulacc.v | 3,735 | module MODULE1(
input wire clk,
input wire VAR9,
input wire VAR6,
input wire VAR10,
input wire [63 : 0] VAR11,
input wire [31 : 0] VAR5,
output wire [63 : 0] VAR12
);
reg [63 : 0] VAR4;
reg [63 : 0] VAR7;
assign VAR12 = VAR4;
always @ (posedge clk)
begin : VAR1
if (!VAR9)
begin
VAR4 <= 64'h0;
end
else
begin
if (VAR10)
... | bsd-2-clause |
KiwiOnChip/Projet_VHDL_-_Paint | 04_IP_Xillinx/Clk_Wizard/Clk_Wizard_clk_wiz.v | 7,098 | module MODULE1
( output VAR89,
output VAR6,
input VAR53,
output VAR90,
input VAR31
);
wire VAR38;
wire VAR43;
VAR70 VAR61
(.VAR69 (VAR38),
.VAR4 (VAR31));
wire VAR27;
wire VAR5;
wire VAR50;
wire VAR78;
wire VAR30;
wire VAR67;
wire VAR72;
wire [15:0] VAR52;
wire VAR29;
wire VAR41;
wire VAR32;
wire VAR76;
wire VAR84;
wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor2/sky130_fd_sc_hd__xor2_2.v | 2,117 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR6 ,
VAR3,
VAR2,
VAR5 ,
VAR1
);
output VAR8 ;
input VAR9 ;
input VAR6 ;
input VAR3;
input VAR2;
input VAR5 ;
input VAR1 ;
VAR7 VAR4 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR8,
VAR9,
VAR6
);
output VAR8;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcon/sky130_fd_sc_ls__fahcon_1.v | 2,412 | module MODULE2 (
VAR4,
VAR3 ,
VAR11 ,
VAR6 ,
VAR8 ,
VAR9 ,
VAR10 ,
VAR2 ,
VAR7
);
output VAR4;
output VAR3 ;
input VAR11 ;
input VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR10 ;
input VAR2 ;
input VAR7 ;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR2(VAR2)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3.functional.v | 1,265 | module MODULE1 (
VAR5,
VAR4,
VAR2,
VAR6
);
output VAR5;
input VAR4;
input VAR2;
input VAR6;
wire VAR7;
or VAR3 (VAR7, VAR2, VAR4, VAR6 );
buf VAR1 (VAR5 , VAR7 );
endmodule | apache-2.0 |
chebykinn/university | circuitry/lab3/src/hdl/ex_stage.v | 4,096 | module MODULE1( input clk,
input rst,
input VAR32,
input VAR6,
input VAR21,
input VAR37,
input VAR16,
input VAR40,
input VAR3,
input [1:0] VAR2,
input VAR27,
input [31:0] VAR31,
input [31:0] VAR20,
input [31:0] VAR35,
input [4:0] VAR23, input [4:0] rd, input [5:0] VAR33,
input [1:0] VAR25, input [1:0] VAR11, input [31:... | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/ram_1clk_1w_1r.v | 3,210 | module MODULE1
parameter VAR10 = 32,
parameter VAR3 = 1024
)
(
input VAR1,
input [VAR2(VAR3)-1:0] VAR11,
input VAR9,
input [VAR2(VAR3)-1:0] VAR4,
input [VAR10-1:0] VAR8,
output [VAR10-1:0] VAR7
);
localparam VAR12 = VAR2(VAR3);
reg [VAR10-1:0] VAR6 [VAR3-1:0];
reg [VAR10-1:0] VAR5;
assign VAR7 = VAR5;
always @(posedge ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.behavioral.v | 1,121 | module MODULE1( VAR2, VAR4 );
input VAR2;
output VAR4;
VAR1 VAR5(.VAR2(VAR2),.VAR4(VAR4));
VAR1 VAR3(.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
jhol/butterflylogic | rtl/core.v | 11,554 | module MODULE1 #(
parameter integer VAR44 = 32, parameter integer VAR88 = 32 )(
input wire VAR31,
input wire VAR26, input wire [7:0] VAR67, input wire [31:0] VAR40,
input wire VAR41, input wire VAR2,
input wire VAR70,
output wire VAR68,
output wire VAR28,
output wire VAR71,
output reg VAR6,
output reg VAR59,
output wir... | gpl-2.0 |
jeichenhofer/chuck-light | SoC/ip/altsource_probe/hps_reset.v | 4,076 | module MODULE1 (
VAR30,
VAR8,
VAR19);
input VAR30;
input VAR8;
output [2:0] VAR19;
wire [2:0] VAR5;
wire [2:0] VAR19 = VAR5[2:0];
VAR3 VAR18 (
.VAR30 (VAR30),
.VAR8 (VAR8),
.VAR19 (VAR5)
,
.VAR27 (),
.VAR24 (),
.VAR20 (),
.VAR22 (),
.VAR12 (),
.VAR2 (),
.VAR14 (),
.VAR7 (),
.VAR15 (),
.VAR10 (),
.VAR16 (),
.VAR13 (),
.... | gpl-3.0 |
DoctorWkt/CSCv2 | Verilog/ULX3S.v | 2,579 | module MODULE1(VAR21, VAR10, VAR12);
input wire VAR21;
output wire [31:0] VAR10; output wire VAR12;
module MODULE1 (input VAR18, output VAR24, output [7:0] VAR16);
wire VAR21;
assign VAR21= VAR18;
assign VAR24= VAR12; assign VAR16= VAR31;
reg [15:0] counter=0;
always @(posedge VAR21) counter <= counter + 1;
wire VAR9;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxtp/sky130_fd_sc_ls__sedfxtp.pp.blackbox.v | 1,420 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR1 ,
VAR9 ,
VAR10 ,
VAR2 ,
VAR8,
VAR7,
VAR4 ,
VAR3
);
output VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR10 ;
input VAR2 ;
input VAR8;
input VAR7;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.functional.pp.v | 2,839 | module MODULE1 (
VAR24 ,
VAR29,
VAR7 ,
VAR12 ,
VAR6
);
output VAR24 ;
input VAR29;
input VAR7 ;
input VAR12 ;
input VAR6;
wire VAR15 ;
wire VAR22 ;
wire VAR3;
wire VAR23 ;
wire VAR16 ;
wire VAR17 ;
wire VAR8 ;
wire VAR28 ;
VAR9 VAR26 (.VAR27(VAR15) , .VAR14(VAR22), .VAR6(VAR6), .VAR29(VAR29), .VAR7(VAR7), .VAR12(VAR12)... | apache-2.0 |
himingway/PIC16C5x | src/ControlUnit.v | 5,988 | module MODULE1 (
input clk , input VAR10 , input [ VAR17-1:0] VAR3 , output [ VAR1-1:0] VAR21 , output [ VAR12-1:0] VAR9, output [VAR5-1:0] VAR2 , output [ 1:0] VAR14 );
reg[VAR1 - 1 : 0] VAR20;
reg[VAR12 - 1 : 0] VAR8;
reg[VAR1 - 1 : 0] VAR11;
reg[VAR12 - 1 : 0] VAR7;
assign VAR21 = VAR20;
assign VAR9 = VAR8;
assign V... | mit |
combinatorylogic/soc | backends/c2/hw/nexys4ddr/vga640x480grey.v | 3,982 | module MODULE1(input clk, input rst,
input VAR25,
input [7:0] VAR2,
output [19:0] VAR35,
output VAR20,
output VAR27,
output VAR1,
output [3:0] VAR6 );
reg VAR7;
reg VAR16;
wire [7:0] VAR22;
wire VAR8;
wire [7:0] VAR32;
wire VAR21;
reg [19:0] VAR28;
assign VAR35 = VAR28;
assign VAR22 = VAR2;
parameter VAR15 = 640*480/2 ... | mit |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_ddr_carry_latch_and.v | 4,310 | module MODULE1 #
(
parameter VAR5 = "VAR1"
)
(
input wire VAR2,
input wire VAR11,
output wire VAR3
);
generate
if ( VAR5 == "VAR8" ) begin : VAR6
assign VAR3 = VAR2 & ~VAR11;
end else begin : VAR10
wire VAR7;
assign VAR7 = ~VAR11;
VAR13 VAR12
(
.VAR3(VAR3),
.VAR4(VAR2),
.VAR9(VAR7)
);
end
endgenerate
endmodule | mit |
cstratton/xc3sprog-code | bscan_spi/xc3s500e_godil.v | 1,777 | module MODULE1
(
output wire VAR30,
output wire VAR6,
output wire VAR37,
input VAR31
);
wire VAR32;
wire VAR5;
wire VAR14;
wire VAR3;
reg [47:0] VAR41;
reg [15:0] VAR24;
reg VAR13 = 0;
assign VAR30 = VAR14 ;
wire VAR4;
wire VAR44;
wire VAR2;
reg VAR34 = 0;
reg VAR22 = 0;
reg VAR17 = 0;
reg VAR28 = 0;
reg [13:0] VAR43;
... | gpl-2.0 |
P3Stor/P3Stor | DDR3/controller/arb_mux.v | 17,638 | module MODULE1 #
(
parameter VAR55 = 100,
parameter VAR63 = "1T",
parameter VAR51 = 11,
parameter VAR69 = 3,
parameter VAR3 = "8",
parameter VAR87 = 4,
parameter VAR68 = 31,
parameter VAR56 = 8,
parameter VAR90 = "VAR22",
parameter VAR62 = "VAR1",
parameter VAR41 = "VAR1",
parameter VAR81 = 4,
parameter VAR79 = 2, para... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2/sky130_fd_sc_ls__nand2_8.v | 2,097 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR1 ,
VAR2,
VAR7,
VAR6 ,
VAR4
);
output VAR9 ;
input VAR3 ;
input VAR1 ;
input VAR2;
input VAR7;
input VAR6 ;
input VAR4 ;
VAR8 VAR5 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR9,
VAR3,
VAR1
);
output VAR9;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dlatch_lp_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_lp_pp_pg_n.blackbox.v | 1,426 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR6 ,
VAR4,
VAR5 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR4;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/axi_dmac.v | 22,700 | module MODULE1 (
input VAR239,
input VAR160,
input VAR25,
input [31:0] VAR179,
output VAR81,
input [2:0] VAR32,
input VAR176,
input [31:0] VAR43,
input [ 3:0] VAR214,
output VAR159,
output VAR175,
output [ 1:0] VAR258,
input VAR15,
input VAR72,
input [31:0] VAR204,
output VAR140,
input [2:0] VAR113,
output VAR236,
inpu... | gpl-3.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/eth_tcr_pack.v | 5,287 | module MODULE1 #(parameter VAR15 = 48'h001F293A10FD,VAR13 = 48'hAABBCCDDEEFF,VAR10 = 16'd1024)
(
output VAR22,
output VAR26,
input [7:0] VAR24,
input VAR3,
output VAR17,
input VAR25,
input VAR23,
input VAR16,
output reg VAR6,
output reg [7:0] VAR1,
output reg VAR7,
input VAR5
);
wire [11:0] VAR12;
reg [15:0] VAR2;
reg ... | mit |
mossmann/unambiguous-encapsulation | code-search/verilog/icblbc/icblbc.v | 5,014 | module MODULE1 (
input wire VAR14,
input wire [7:0] VAR1, VAR23,
output reg [3:0] VAR11
);
wire [7:0] VAR37;
assign VAR37 = VAR1 ^ VAR23;
always @(posedge VAR14) begin
VAR11 = VAR37[0] + VAR37[1] + VAR37[2] + VAR37[3]
+ VAR37[4] + VAR37[5] + VAR37[6] + VAR37[7];
end
endmodule
module MODULE3 (
input wire VAR14,
input wi... | gpl-2.0 |
secworks/fpga_entropy | src/rtl/fpga_entropy_core.v | 5,515 | module MODULE1(
input wire clk,
input wire VAR9,
input wire [31 : 0] VAR2,
input wire [31 : 0] VAR4,
input wire VAR11,
output wire [31 : 0] rnd
);
reg [31 : 0] VAR17;
reg VAR20;
reg [31 : 0] VAR12;
reg [4 : 0] VAR14;
reg VAR13;
wire [7 : 0] VAR3;
wire [7 : 0] VAR10;
wire [7 : 0] VAR1;
assign rnd = VAR12;
genvar VAR7;
g... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s.functional.pp.v | 1,865 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR12,
VAR11,
VAR5 ,
VAR10
);
output VAR1 ;
input VAR4 ;
input VAR12;
input VAR11;
input VAR5 ;
input VAR10 ;
wire VAR2 ;
wire VAR8;
buf VAR6 (VAR2 , VAR4 );
VAR3 VAR9 (VAR8, VAR2, VAR12, VAR11);
buf VAR7 (VAR1 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbn/sky130_fd_sc_lp__dfbbn.blackbox.v | 1,451 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR10 ,
VAR8 ,
VAR7
);
output VAR9 ;
output VAR1 ;
input VAR6 ;
input VAR10 ;
input VAR8 ;
input VAR7;
supply1 VAR5;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/yf32/mem_ctrl.v | 13,202 | module MODULE1 (clk, reset, VAR37, VAR20, VAR32, VAR31,
VAR4, VAR8, VAR24, VAR19, VAR12,
VAR6, VAR25, VAR23, VAR1, VAR10);
parameter VAR15 = 1'b0;
parameter VAR45 = 2'b00;
parameter VAR18 = 2'b01;
parameter VAR36 = 2'b10;
parameter VAR44 = 2'b11;
input clk;
input reset;
input VAR37;
input VAR20;
input [31:0] VAR32;
inp... | mit |
combinatorylogic/soc | backends/small1/hw/rtl/cpu.v | 5,775 | module MODULE1(
input clk, input rst,
input [31:0] VAR60, input VAR8, input VAR18,
output VAR19, output VAR30, output [31:0] VAR61, output [31:0] VAR50,
input irq, input [3:0] VAR9, output VAR22, output VAR15,
output [31:0] VAR13,
input [3:0] VAR14,
input VAR33,
input VAR29,
output VAR47,
input VAR3
);
wire [31:0] VAR4... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/wb_conmax/wb_conmax_arb.v | 9,741 | module MODULE1(clk, rst, req, VAR4, VAR11);
input clk;
input rst;
input [7:0] req; output [2:0] VAR4; input VAR11;
parameter [2:0]
VAR5 = 3'h0,
VAR6 = 3'h1,
VAR1 = 3'h2,
VAR3 = 3'h3,
VAR2 = 3'h4,
VAR10 = 3'h5,
VAR9 = 3'h6,
VAR8 = 3'h7;
reg [2:0] state, VAR7;
assign VAR4 = state;
always@(posedge clk or posedge rst)
if(r... | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/impl/ip/hdl/verilog/image_filter_Loop_1_proc.v | 42,523 | module MODULE1 (
VAR172,
VAR76,
VAR32,
VAR116,
VAR25,
VAR96,
VAR7,
VAR78,
VAR151,
VAR148,
VAR194,
VAR136,
VAR42,
VAR123,
VAR73,
VAR45,
VAR82,
VAR51,
VAR10,
VAR179,
VAR117,
VAR29,
VAR22,
VAR57,
VAR53,
VAR52,
VAR138,
VAR109,
VAR41,
VAR114,
VAR20,
VAR30,
VAR153,
VAR164,
VAR14,
VAR62,
VAR167,
VAR21,
VAR98,
VAR15,
VAR70,
VA... | gpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/bench/verilog/eth_host.v | 4,621 | module MODULE1
(
VAR6, VAR13,
VAR10, VAR12, VAR1, VAR7, VAR9, VAR8, VAR3, VAR11, VAR4
);
parameter VAR2=1;
input VAR6, VAR13;
input [31:0] VAR7;
input VAR11, VAR4;
output [31:0] VAR10, VAR9;
output [3:0] VAR12;
output VAR8, VAR3, VAR1;
reg [31:0] VAR10, VAR9;
reg [3:0] VAR12;
reg VAR8, VAR3, VAR1;
integer VAR5;
begin
b... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ip_top/mig_v3_4.v | 34,482 | module MODULE1 #
(
parameter VAR38 = 200,
parameter VAR107 = "VAR133",
parameter VAR134 = 6,
parameter VAR70 = 2,
parameter VAR72 = 3,
parameter VAR117 = 2,
parameter VAR223 = 2500,
parameter VAR219 = "VAR256",
parameter VAR76 = "VAR24",
parameter VAR251 = "VAR24",
parameter VAR35 = 1,
parameter VAR119 = 3,
parameter V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrbp/sky130_fd_sc_ls__dfrbp_1.v | 2,441 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR1,
VAR11 ,
VAR6 ,
VAR3 ,
VAR9
);
output VAR7 ;
output VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR1;
input VAR11 ;
input VAR6 ;
input VAR3 ;
input VAR9 ;
VAR4 VAR10 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR3(VAR3),
.... | apache-2.0 |
sergev/vak-opensource | hardware/verilog/example/example.v | 1,280 | module MODULE1;
reg VAR4;
reg reset;
reg enable;
reg [3:0] VAR1;
always begin
VAR4 <= 0;
VAR4 <= 1;
end
always @(posedge VAR4) begin
if (reset)
VAR1 <= 0;
end
else if (enable) begin
VAR5 VAR3 %VAR2", , VAR1);
VAR1 <= VAR1 + 1;
end
end | apache-2.0 |
rkrajnc/minimig-de1 | rtl/minimig/Denise.v | 21,143 | module MODULE4
(
input VAR71, input clk, input VAR45 , input VAR76,
input VAR39, input reset, input VAR43, input [8:1] VAR12, input [15:0] VAR33, output [15:0] VAR20, input VAR55, output [3:0] VAR27, output [3:0] VAR36, output [3:0] VAR4, input VAR46, input VAR52, output reg VAR13 );
parameter VAR62 = 9'h08E;
parameter... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/host_interface/generic/ppfifo_host_interface.v | 14,167 | module MODULE1 (
input rst,
input clk,
input VAR8,
output VAR9,
output reg VAR7,
output reg [31:0] VAR33,
output reg [31:0] VAR12,
output reg [31:0] VAR10,
output reg [27:0] VAR31,
output reg VAR61,
input VAR37,
input [31:0] VAR63,
input [31:0] VAR57,
input [31:0] VAR21,
input [27:0] VAR29,
input VAR24,
output reg VAR4... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb_2.v | 2,330 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR6 ,
VAR1 ,
VAR11 ,
VAR9,
VAR8,
VAR7 ,
VAR5
);
output VAR10 ;
input VAR2 ;
input VAR6 ;
input VAR1 ;
input VAR11 ;
input VAR9;
input VAR8;
input VAR7 ;
input VAR5 ;
VAR3 VAR4 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Inverse_Clarke_Transform.v | 3,800 | module MODULE1
(
VAR12,
VAR8,
VAR7,
VAR11,
VAR15
);
input signed [17:0] VAR12; input signed [17:0] VAR8; output signed [17:0] VAR7; output signed [17:0] VAR11; output signed [17:0] VAR15;
wire signed [35:0] VAR2; wire signed [35:0] VAR6; wire signed [35:0] VAR9; wire signed [35:0] VAR4; wire signed [37:0] VAR18; wire s... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_034.v | 1,476 | module MODULE1 (
VAR13,
VAR10
);
input [31:0] VAR13;
output [31:0]
VAR10;
wire [31:0]
VAR2,
VAR11,
VAR12,
VAR4,
VAR9,
VAR8,
VAR3,
VAR1;
assign VAR2 = VAR13;
assign VAR8 = VAR12 << 1;
assign VAR4 = VAR2 << 7;
assign VAR9 = VAR2 + VAR4;
assign VAR12 = VAR11 - VAR2;
assign VAR11 = VAR2 << 9;
assign VAR1 = VAR3 << 3;
assig... | mit |
monotone-RK/FACE | MCSoC-15/8-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_rdlvl.v | 144,853 | module MODULE1 #
(
parameter VAR368 = 100, parameter VAR220 = 2, parameter VAR424 = 3333, parameter VAR49 = 64, parameter VAR259 = 3, parameter VAR310 = 8, parameter VAR136 = 8, parameter VAR264 = 1, parameter VAR405 = "VAR64", parameter VAR30 = "VAR437", parameter VAR194 = "VAR359", parameter VAR89 = "VAR409", paramet... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/decap/sky130_fd_sc_hdll__decap.functional.pp.v | 1,180 | module MODULE1 (
VAR1,
VAR2,
VAR4 ,
VAR3
);
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222oi/sky130_fd_sc_ls__a222oi.functional.v | 1,735 | module MODULE1 (
VAR2 ,
VAR11,
VAR15,
VAR8,
VAR6,
VAR4,
VAR10
);
output VAR2 ;
input VAR11;
input VAR15;
input VAR8;
input VAR6;
input VAR4;
input VAR10;
wire VAR13 ;
wire VAR3 ;
wire VAR16 ;
wire VAR9;
nand VAR7 (VAR13 , VAR15, VAR11 );
nand VAR12 (VAR3 , VAR6, VAR8 );
nand VAR1 (VAR16 , VAR10, VAR4 );
and VAR14 (VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha.pp.blackbox.v | 1,276 | module MODULE1 (
VAR3,
VAR6 ,
VAR5 ,
VAR7 ,
VAR2,
VAR4,
VAR8 ,
VAR1
);
output VAR3;
output VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR2;
input VAR4;
input VAR8 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlxtp/sky130_fd_sc_lp__srdlxtp.pp.blackbox.v | 1,373 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2 ,
VAR9,
VAR6 ,
VAR4 ,
VAR5 ,
VAR8 ,
VAR7
);
output VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR9;
input VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR8 ;
input VAR7 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.functional.v | 1,557 | module MODULE1( VAR15, VAR2, VAR14, VAR3 );
input VAR2, VAR15, VAR14;
output VAR3;
wire VAR19;
and VAR11( VAR19, VAR2, VAR15, VAR14 );
wire VAR12;
not VAR6( VAR12, VAR15 );
wire VAR16;
not VAR5( VAR16, VAR14 );
wire VAR18;
and VAR13( VAR18, VAR12, VAR16, VAR2 );
wire VAR7;
not VAR1( VAR7, VAR2 );
wire VAR8;
and VAR9( V... | apache-2.0 |
SymbiFlow/yosys-symbiflow-plugins | ql-qlf-plugin/qlf_k4n8/arith_map.v | 4,133 | module MODULE1(
module 80quicklogicalu (VAR28, VAR21, VAR15, VAR14, VAR31, VAR22, VAR12);
parameter VAR5 = 0;
parameter VAR4 = 0;
parameter VAR27 = 1;
parameter VAR7 = 1;
parameter VAR8 = 1;
parameter VAR35 = 0;
parameter VAR20 = 0;
input [VAR27-1:0] VAR28;
input [VAR7-1:0] VAR21;
output [VAR8-1:0] VAR31, VAR22;
input ... | isc |
asicguy/gplgpu | stim/avalon_fast_model_256.v | 17,524 | parameter VAR116 = 10;
parameter VAR60 = VAR116+1;
parameter VAR42 = 32'h100000;
parameter VAR121 = 26;
parameter VAR35 = 23;
parameter VAR61 = 1;
module MODULE1
(
VAR106,
VAR90,
VAR89,
VAR15,
VAR76,
VAR101,
VAR115,
VAR53,
VAR4,
VAR1,
VAR25,
VAR74,
VAR38,
VAR103,
VAR33,
VAR99,
VAR69,
VAR102,
VAR57,
VAR37,
VAR55,
VAR59,... | gpl-3.0 |
ueokande/async_benchmark_circuit | src/gcd16/gcd16.v | 35,343 | module MODULE23 (
VAR297,
MODULE23,
MODULE6,
MODULE16,
MODULE10
);
output VAR297;
input MODULE23;
input MODULE6;
input MODULE16;
input MODULE10;
wire [1:0] VAR219;
VAR206 VAR249 (VAR297, VAR219[0], VAR219[1]);
VAR192 VAR55 (VAR219[1], MODULE16, MODULE10);
VAR192 VAR211 (VAR219[0], MODULE23, MODULE6);
endmodule
module M... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4bb/sky130_fd_sc_hd__or4bb.behavioral.pp.v | 1,988 | module MODULE1 (
VAR11 ,
VAR13 ,
VAR12 ,
VAR14 ,
VAR15 ,
VAR3,
VAR5,
VAR1 ,
VAR10
);
output VAR11 ;
input VAR13 ;
input VAR12 ;
input VAR14 ;
input VAR15 ;
input VAR3;
input VAR5;
input VAR1 ;
input VAR10 ;
wire VAR4 ;
wire VAR9 ;
wire VAR6;
nand VAR7 (VAR4 , VAR15, VAR14 );
or VAR16 (VAR9 , VAR12, VAR13, VAR4 );
VAR2 ... | apache-2.0 |
mda-ut/SubZero | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_key.v | 3,676 | module MODULE1 (
address,
VAR2,
clk,
VAR3,
VAR10,
VAR11,
VAR7,
irq,
VAR15
)
;
output irq;
output [ 31: 0] VAR15;
input [ 1: 0] address;
input VAR2;
input clk;
input [ 1: 0] VAR3;
input VAR10;
input VAR11;
input [ 31: 0] VAR7;
wire VAR13;
reg [ 1: 0] VAR5;
reg [ 1: 0] VAR8;
wire [ 1: 0] VAR6;
reg [ 1: 0] VAR9;
wire VAR1... | mit |
jhol/butterflylogic | rtl/trigger_adv.v | 23,221 | module MODULE1 #(
parameter integer VAR26 = 32
)(
input wire clk,
input wire rst,
input wire VAR11,
input wire VAR5,
input wire VAR23,
input wire VAR10,
input wire [31:0] VAR31,
input wire VAR30,
input wire [VAR26-1:0] VAR34, output reg VAR3, output reg VAR17 );
reg [4:0] VAR33, VAR19;
reg [6:0] VAR7, VAR15;
reg [31:0]... | gpl-2.0 |
jz0229/open-ephys-pcie | kc705-host-firmware/Sources/Verilog/pcie_k7_8x_pipe_clock.v | 2,064 | module MODULE1 #
(
parameter VAR21 = "VAR25",
parameter VAR7 = "VAR25",
parameter VAR12= "VAR25",
parameter VAR23 = 1,
parameter VAR19 = 3,
parameter VAR11 = 0,
parameter VAR9 = 2,
parameter VAR16 = 2,
parameter VAR14 = 1,
parameter VAR18 = 0
)
(
input VAR5,
input VAR10,
input [VAR23-1:0] VAR6,
input VAR28,
input [VAR2... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/controller/arb_mux.v | 18,394 | module MODULE1 #
(
parameter VAR2 = 100,
parameter VAR84 = "1T",
parameter VAR60 = 11,
parameter VAR11 = 3,
parameter VAR10 = "8",
parameter VAR88 = 4,
parameter VAR39 = 5,
parameter VAR43 = 31,
parameter VAR9 = 8,
parameter VAR90 = "VAR42",
parameter VAR73 = "VAR48",
parameter VAR105 = "VAR48",
parameter VAR34 = 4,
pa... | lgpl-3.0 |
rkrajnc/minimig-mist | rtl/sdram/dpram_inf_be_1024x16.v | 1,087 | module MODULE1 (
input wire VAR1,
input wire VAR11,
input wire [ 2-1:0] VAR13,
input wire [ 10-1:0] VAR7,
input wire [ 16-1:0] VAR2,
output reg [ 16-1:0] VAR4,
input wire VAR5,
input wire [ 2-1:0] VAR6,
input wire [ 10-1:0] VAR12,
input wire [ 16-1:0] VAR3,
output reg [ 16-1:0] VAR9
);
reg [8-1:0] VAR10 [0:1024-1];
reg... | gpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/or1200-generic/bench/verilog/orpsoc_top.v | 8,808 | module MODULE1
(input VAR185,
input VAR98,
output VAR103,
input VAR30,
input VAR51,
input VAR67);
localparam VAR128 = 32;
localparam VAR124 = 32;
localparam VAR83 = 23;
wire VAR127 = VAR185;
wire VAR195 = VAR98;
wire VAR10;
wire VAR180;
wire VAR26;
wire VAR42;
wire VAR47;
wire VAR138;
wire VAR168;
VAR214 VAR179 (
.VAR1... | gpl-2.0 |
UA3MQJ/fpga-synth | modules/midi_in.v | 4,978 | module MODULE1(clk, rst, MODULE1,
VAR7,
VAR11, VAR8, VAR3, VAR1, VAR2 );
input wire clk; input wire rst; input wire MODULE1; output wire [3:0] VAR11; output wire [6:0] VAR8;
output wire [6:0] VAR3;
output wire [6:0] VAR1;
output wire [6:0] VAR2;
output wire [3:0] VAR7;
reg [23:0] VAR9;
reg [7:0] VAR6;
reg [7:0] VAR5;
r... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3.functional.pp.v | 1,742 | module MODULE1 (
VAR12,
VAR6,
VAR2 ,
VAR7 ,
VAR9 ,
VAR1
);
input VAR12;
input VAR6;
output VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
wire VAR5 ;
wire VAR4;
nor VAR11 (VAR5 , VAR1, VAR7, VAR9 );
VAR10 VAR3 (VAR4, VAR5, VAR12, VAR6);
buf VAR8 (VAR2 , VAR4 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9625/axi_ad9625_if.v | 9,312 | module MODULE1 (
VAR5,
VAR35,
VAR4,
VAR7,
VAR25,
VAR21,
VAR39,
VAR48,
VAR10,
VAR29);
parameter VAR49 = 0;
input VAR5;
input [255:0] VAR35;
output VAR4;
input VAR7;
output [191:0] VAR25;
output VAR21;
output VAR39;
output [ 15:0] VAR48;
input [ 3:0] VAR10;
output [ 3:0] VAR29;
reg [191:0] VAR25 = 'd0;
reg [ 15:0] VAR48 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.v | 2,156 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR4 ,
VAR2 ,
VAR6,
VAR3 ,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR6;
input VAR3 ;
input VAR5 ;
VAR9 VAR1 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR8,
VAR7
);
output VAR8;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr.behavioral.v | 1,453 | module MODULE1 (
VAR4,
VAR9
);
output VAR4;
input VAR9;
supply1 VAR3;
supply1 VAR6 ;
supply0 VAR7 ;
supply1 VAR2 ;
supply0 VAR10 ;
wire VAR8;
buf VAR5 (VAR8, VAR9 );
buf VAR1 (VAR4 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25.pp.blackbox.v | 1,343 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR6,
VAR2,
VAR3 ,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR6;
input VAR2;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
yunqu/PYNQ | boards/ip/trace_generator_controller_1.1/trace_generator_controller.v | 2,694 | module MODULE1 #(parameter VAR2 = 18)(
input clk,
input [5:0] VAR12,
input [VAR2-1:0] VAR6, input VAR16,
output reg VAR17
);
reg VAR18, VAR19;
wire VAR3;
wire VAR10;
wire VAR14;
wire VAR8;
reg [VAR2-1:0] VAR5;
reg VAR20;
VAR11 VAR15(.VAR13(VAR12[0]&VAR12[4]), .VAR1(clk), .VAR7(VAR3));
VAR11 VAR9(.VAR13(VAR12[1]&VAR12[4... | bsd-3-clause |
GREO/gnuradio-git | gr-gpio/src/fpga/lib/gpio_input.v | 4,076 | module MODULE1
(input VAR17, input reset, input enable,
input VAR4,
input wire [6:0] VAR23, input wire [31:0] VAR9, input VAR16,
input wire [15:0] VAR6, input wire [15:0] VAR2,
output reg VAR13, output reg VAR10,
output reg VAR18, output reg VAR15 );
reg VAR19,VAR20,VAR1,VAR3;
always @(posedge VAR17)
begin
VAR19 <= VAR... | gpl-3.0 |
ychaim/FPGA-Litecoin-Miner | experimental/CM1/uart_baudgenerator.v | 1,274 | module MODULE1(
clk,
VAR7
);
parameter VAR1 = 25000000; parameter VAR6 = 9600;
parameter VAR3 = 16;
parameter VAR4 = 5;
parameter VAR5 = ((VAR6<<(VAR3-(VAR4-1)))+(VAR1>>VAR4))/(VAR1>>(VAR4-1));
input clk;
output VAR7;
reg [VAR3:0] VAR2 = 0;
assign VAR7 = VAR2[VAR3];
always @(posedge clk)
VAR2 <= VAR2[VAR3-1:0] + VAR5;
... | gpl-3.0 |
aap/pdp6 | verilog/membus_3_connect.v | 2,176 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR24,
input wire VAR25,
input wire VAR22,
input wire VAR35,
input wire [21:35] VAR19,
input wire [18:21] VAR28,
input wire VAR9,
input wire [0:35] VAR31,
output wire VAR11,
output wire VAR41,
output wire [0:35] VAR15,
output wire VAR1,
output wire VAR5,
outp... | mit |
cr88192/bgbtech_bjx1core | bjx1c32b/DcTile2.v | 12,614 | module MODULE1(
VAR26, reset,
VAR48, VAR13,
VAR46, VAR15,
VAR53, VAR51,
VAR12,
VAR17, VAR6,
VAR19, VAR4,
VAR27, VAR2,
VAR40
);
input VAR26;
input reset;
input[31:0] VAR46; input[63:0] VAR48; input VAR53; input VAR51; input[4:0] VAR12;
output[63:0] VAR13; output[1:0] VAR15;
input[127:0] VAR17; output[127:0] VAR6; output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3/sky130_fd_sc_hdll__and3.behavioral.v | 1,379 | module MODULE1 (
VAR6,
VAR1,
VAR10,
VAR4
);
output VAR6;
input VAR1;
input VAR10;
input VAR4;
supply1 VAR3;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR9 ;
wire VAR11;
and VAR2 (VAR11, VAR4, VAR1, VAR10 );
buf VAR8 (VAR6 , VAR11 );
endmodule | apache-2.0 |
GustavoOS/ARMAria | src/RegBank.v | 3,333 | module MODULE1
parameter VAR22 = 32,
parameter VAR10 = 32'hffffffff,
parameter VAR15 = 15,
parameter VAR29 = 14,
parameter VAR24 = 4,
parameter VAR19 = 7167,
parameter VAR1 = 8191,
parameter VAR5 = 3072,
parameter VAR3 = 6,
parameter VAR7 = 7,
parameter VAR23 = 13
)(
input enable, reset, VAR9, VAR26,
input [2:0] VAR8,
... | mit |
hanw/sonic-lite | hw/bsv/BRAM2.v | 6,486 | module MODULE1(VAR83,
VAR75,
VAR73,
VAR96,
VAR13,
VAR50,
VAR68,
VAR65,
VAR72,
VAR71,
VAR67,
VAR109
);
parameter VAR20 = 0;
parameter VAR12 = 1;
parameter VAR33 = 1;
parameter VAR52 = 1;
input VAR83;
input VAR75;
input VAR73;
input [VAR12-1:0] VAR96;
input [VAR33-1:0] VAR13;
output [VAR33-1:0] VAR50;
input VAR68;
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0p/sky130_fd_sc_lp__iso0p_lp.v | 2,156 | module MODULE2 (
VAR9 ,
VAR2 ,
VAR4,
VAR6,
VAR3 ,
VAR8 ,
VAR5
);
output VAR9 ;
input VAR2 ;
input VAR4;
input VAR6;
input VAR3 ;
input VAR8 ;
input VAR5 ;
VAR1 VAR7 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR9 ,
VAR2 ,
VAR4
);
output VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2.behavioral.v | 1,401 | module MODULE1 (
VAR6,
VAR5,
VAR2
);
output VAR6;
input VAR5;
input VAR2;
supply1 VAR9;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR10 ;
wire VAR1;
xnor VAR4 (VAR1, VAR5, VAR2 );
buf VAR3 (VAR6 , VAR1 );
endmodule | apache-2.0 |
Daeno/DCLabExp3 | exp3_recorder.v | 10,230 | module MODULE1(
VAR56,
VAR89,
VAR39,
VAR12,
VAR9,
VAR61,
VAR18,
VAR19,
VAR6,
VAR87,
VAR81,
VAR66,
VAR64,
VAR43,
VAR57,
VAR73,
VAR33,
VAR67,
VAR23,
VAR78,
VAR45,
VAR54,
VAR76,
VAR25,
VAR84,
VAR40,
VAR30,
VAR50,
VAR29,
VAR32,
VAR94,
VAR52,
VAR44,
VAR82,
VAR70,
VAR42,
VAR51
);
input VAR56;
input VAR89;
input VAR39;
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3.symbol.v | 1,322 | module MODULE1 (
input VAR6,
output VAR4
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_gt_es.v | 29,824 | module MODULE1 (
VAR11,
VAR80,
VAR106,
VAR24,
VAR109,
VAR52,
VAR84,
VAR86,
VAR22,
VAR57,
VAR16,
VAR97,
VAR102,
VAR41,
VAR54,
VAR14,
VAR89,
VAR88,
VAR78,
VAR30,
VAR4,
VAR79,
VAR113,
VAR65,
VAR110,
VAR15,
VAR8,
VAR69,
VAR12,
VAR38,
VAR100,
VAR114,
VAR10,
VAR70,
VAR26,
VAR20);
parameter integer VAR120 = 0;
localparam [11:... | lgpl-3.0 |
jrward/qdbreakout | rtl/display_logic.v | 2,948 | module MODULE1( input VAR33,
input [9:0] VAR16,
input [9:0] VAR14,
input [9:0] VAR7,
input [9:0] VAR9,
input [5:0] VAR21,
input [3:0] VAR1,
input VAR25,
input VAR15,
input VAR17,
output reg VAR12,
output reg VAR18,
output reg [2:0] VAR34 );
reg [2:0] VAR24;
reg [3:0] VAR32;
reg VAR5;
always @ (VAR16, VAR14, VAR7, VAR9,... | gpl-2.0 |
lfmunoz/vhdl | ip_blocks/sip_check_data/async_fifo_align_64in_out/async_fifo_align_64in_out_stub.v | 1,468 | module MODULE1(clk, rst, din, VAR4, VAR2, dout, VAR3, VAR1, valid)
;
input clk;
input rst;
input [63:0]din;
input VAR4;
input VAR2;
output [63:0]dout;
output VAR3;
output VAR1;
output valid;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o.symbol.v | 1,367 | module MODULE1 (
input VAR3,
input VAR1,
input VAR7,
input VAR2,
output VAR4
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
chimeh/stopwatch_verilog | src/time_cnt.v | 3,803 | module MODULE1(
input VAR10, input VAR14, input VAR5, output [3:0] VAR13, output [3:0] VAR26, output [3:0] VAR7, output [3:0] VAR16, output [3:0] VAR20, output [3:0] VAR18);
reg [3:0] VAR24;
reg [3:0] VAR6;
reg [3:0] VAR22;
reg [3:0] VAR12;
reg [3:0] VAR1;
reg [3:0] VAR9;
wire VAR11;
assign VAR11 = 1; wire enable, VAR2... | unlicense |
monotone-RK/FACE | IEICE-Trans/4-way/src/ip_dram/dram_mig.v | 56,250 | module MODULE1 #
(
parameter VAR313 = 3,
parameter VAR196 = 1,
parameter VAR25 = 10,
parameter VAR126 = 1,
parameter VAR134 = 1,
parameter VAR61 = 1,
parameter VAR74 = 5,
parameter VAR167 = 6,
parameter VAR262 = 8,
parameter VAR81 = 8,
parameter VAR125 = 64,
parameter VAR15 = 8,
parameter VAR38 = 3,
parameter VAR49 = 8... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/TimeCounter.v | 3,793 | module MODULE1
(
parameter VAR9 = 32 ,
parameter VAR10 = 100000000
)
(
VAR13 ,
VAR6 ,
VAR3 ,
VAR11 ,
VAR2 ,
VAR4 ,
VAR12
);
input VAR13 ;
input VAR6 ;
input VAR3 ;
input [VAR9 - 1:0] VAR11 ;
input VAR2 ;
input VAR4 ;
output [VAR9 - 1:0] VAR12 ;
reg [VAR9 - 1:0] VAR1 ;
reg [VAR9 - 1:0] VAR8 ;
reg [VAR9 - 1:0] VAR7 ;
reg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai.pp.blackbox.v | 1,435 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR8 ,
VAR3,
VAR10,
VAR9 ,
VAR1
);
output VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR8 ;
input VAR3;
input VAR10;
input VAR9 ;
input VAR1 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_current_monitor/axi_mc_current_monitor.v | 13,959 | module MODULE1 (
input VAR62,
output VAR166,
input VAR21,
output VAR60,
input VAR13,
output VAR45,
output VAR64,
output VAR101,
input VAR46,
input VAR121,
output [15:0] VAR29,
output [15:0] VAR66,
output [15:0] VAR111,
output VAR108,
input VAR157,
input VAR23,
input VAR44,
input [31:0] VAR50,
output VAR134,
input VAR89... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.behavioral.v | 1,267 | module MODULE1( VAR3, VAR2, VAR6, VAR1 );
input VAR1, VAR3, VAR6;
output VAR2;
VAR5 VAR7(.VAR3(VAR3),.VAR2(VAR2),.VAR6(VAR6),.VAR1(VAR1));
VAR5 VAR4(.VAR3(VAR3),.VAR2(VAR2),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/thinpad_top.v | 5,842 | module MODULE1(
VAR7,
VAR56,
VAR76,
VAR50,
VAR63,
VAR52,
VAR9,
VAR65,
VAR33,
VAR79,
VAR4,
VAR24,
VAR2,
VAR57,
VAR78,
VAR17,
VAR36,
VAR23,
VAR22,
VAR47,
VAR27,
VAR61,
VAR15,
VAR20,
VAR82,
VAR54,
VAR28,
VAR84,
VAR85,
VAR44,
VAR68,
VAR58,
VAR11,
VAR41,
VAR95,
VAR31,
VAR14,
VAR77,
VAR12,
VAR83,
VAR49,
VAR66,
VAR38,
VAR72,
... | unlicense |
hrshishym/DriveTFT18 | DriveTFT18.srcs/sources_1/DriveTFT18.v | 2,087 | module MODULE1(
input wire clk,
input wire VAR38,
output wire VAR12,
output wire VAR2,
output wire VAR18,
output wire VAR9,
inout wire VAR32,
output wire VAR27,
output wire [6:0] VAR36
);
wire [24:0] VAR6;
wire [31:0] VAR21;
wire VAR37 = VAR6[24];
wire [1:0] VAR4 = VAR6[23:22];
wire [3:0] VAR5 = VAR6[21:18];
wire [17:0... | mit |
cr88192/bgbtech_bjx1core | smalltst/compdec/ModTxtMem.v | 3,012 | module MODULE1(VAR6, reset,
VAR28, VAR14,
VAR13, VAR29,
VAR18, VAR23, VAR25, VAR2, VAR7);
input VAR6;
input reset;
input[13:0] VAR28;
output[31:0] VAR14;
input[15:0] VAR13;
output[63:0] VAR29;
input[31:0] VAR18;
inout[31:0] VAR23;
input VAR25;
input VAR2;
output VAR7;
reg VAR11; reg[31:0] VAR12; wire VAR21;
assign VAR7... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/verilog/convolve_kernel.v | 22,985 | module MODULE1 (
VAR68,
VAR137,
VAR80,
VAR117,
VAR138,
VAR90,
VAR136,
VAR60,
VAR19,
VAR65,
VAR49,
VAR169,
VAR171,
VAR156,
VAR154,
VAR77,
VAR172,
VAR131,
VAR161,
VAR111,
VAR99,
VAR67,
VAR41,
VAR9,
VAR34,
VAR28,
VAR129,
VAR170,
VAR108,
VAR56,
VAR159,
VAR173,
VAR5,
VAR39,
VAR95,
VAR6,
VAR102,
VAR16,
VAR74,
VAR153,
interru... | mit |
DeadWitcher/amber-de0-nano | hw/vlog/amber25/a25_multiply.v | 7,543 | module MODULE1 (
input VAR21,
input VAR6,
input [31:0] VAR20, input [31:0] VAR15, input [1:0] VAR7,
input VAR9,
output [31:0] VAR16,
output [1:0] VAR17, output reg VAR2 = 'd0 );
wire enable;
wire VAR25;
wire [33:0] VAR8;
wire [33:0] VAR1;
wire [33:0] sum;
wire [33:0] VAR14;
reg [5:0] VAR22 = 'd0;
reg [5:0] VAR5;
reg [6... | lgpl-2.1 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9361/axi_ad9361_rx_channel.v | 8,372 | module MODULE1 (
VAR48,
VAR33,
VAR25,
VAR43,
VAR38,
VAR55,
VAR60,
VAR75,
VAR81,
VAR14,
VAR77,
VAR89,
VAR94,
VAR99,
VAR12,
VAR51,
VAR72,
VAR49,
VAR26,
VAR31,
VAR42,
VAR62,
VAR34,
VAR90,
VAR73);
parameter VAR21 = 0;
parameter VAR65 = 0;
parameter VAR61 = 0;
input VAR48;
input VAR33;
input VAR25;
input [11:0] VAR43;
input... | gpl-3.0 |
jeffkub/n64-cart-reader | old/hdl/cic/cpu_rom.v | 7,304 | module MODULE1 (VAR101, VAR103, VAR62, VAR108, VAR19);
input wire [7:0] VAR101;
input wire VAR103;
input wire VAR62;
input wire VAR108;
output wire [15:0] VAR19;
wire VAR99;
wire VAR21;
VAR14 VAR29 (.VAR141(VAR99));
VAR122 VAR96 (.VAR141(VAR21));
VAR39 VAR130 (.VAR93(VAR21), ... | mit |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/start_for_Mat2AXIkbM.v | 3,003 | module MODULE2 (
clk,
VAR6,
VAR17,
VAR10,
VAR19);
parameter VAR24 = 32'd1;
parameter VAR25 = 32'd2;
parameter VAR22 = 32'd4;
input clk;
input [VAR24-1:0] VAR6;
input VAR17;
input [VAR25-1:0] VAR10;
output [VAR24-1:0] VAR19;
reg[VAR24-1:0] VAR15 [0:VAR22-1];
integer VAR9;
always @ (posedge clk)
begin
if (VAR17)
begin
fo... | mit |
GustavoOS/ARMAria | src/ControlUnit/SpecReg.v | 1,458 | module MODULE1(
input VAR14, reset, enable,
input [3:0] VAR12,
output VAR1, VAR11, VAR4, VAR9, VAR15,
input VAR10, VAR6, VAR16, VAR5,
input VAR3, VAR8, VAR13,
output reg VAR2
);
reg [4:0] VAR7;
assign {VAR1, VAR11, VAR4, VAR9, VAR15} = VAR7;
begin | mit |
revaldinho/opc | opc5/opc5system/ram_2k_16.v | 1,036 | module MODULE1 ( input [15:0] din, output [15:0] dout, input[10:0] address, input VAR14, input clk, input VAR4);
wire en = !VAR4;
wire VAR3 = !VAR14;
VAR10 VAR11
(
.VAR9(VAR3),
.VAR12(en),
.VAR13(),
.VAR7(clk),
.VAR6(address),
.VAR1(din[7:0]),
.VAR8(1'b0),
.VAR5(dout[7:0]),
.VAR2()
);
VAR10 VAR15
(
.VAR9(VAR3),
.VAR12(... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbp/sky130_fd_sc_lp__sdfbbp.behavioral.pp.v | 3,364 | module MODULE1 (
VAR7 ,
VAR18 ,
VAR26 ,
VAR19 ,
VAR5 ,
VAR35 ,
VAR2 ,
VAR23,
VAR13 ,
VAR27 ,
VAR20 ,
VAR4
);
output VAR7 ;
output VAR18 ;
input VAR26 ;
input VAR19 ;
input VAR5 ;
input VAR35 ;
input VAR2 ;
input VAR23;
input VAR13 ;
input VAR27 ;
input VAR20 ;
input VAR4 ;
wire VAR15 ;
wire VAR36 ;
wire VAR28 ;
reg VAR... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/softusb/rtl/softusb_sie.v | 3,733 | module MODULE1(
input VAR33,
input VAR40,
input VAR8,
input VAR38,
input [5:0] VAR22,
input [7:0] VAR13,
output reg [7:0] VAR20,
output VAR25,
output VAR11,
input VAR21,
inout VAR39,
inout VAR2,
output VAR24,
output VAR19,
input VAR17,
inout VAR23,
inout VAR41
);
wire [1:0] VAR36;
wire [1:0] VAR10;
wire VAR1;
wire VAR3... | lgpl-3.0 |
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