repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/CS_bak/synthesis/submodules/hps_sdram_p0_reset_sync.v | 1,927 | module MODULE1(
VAR4,
clk,
VAR1
);
parameter VAR7 = 4;
parameter VAR5 = 1;
input VAR4;
input clk;
output [VAR5-1:0] VAR1;
reg [VAR7+VAR5-2:0] VAR6 ;
generate
genvar VAR2;
for (VAR2=0; VAR2<VAR7+VAR5-1; VAR2=VAR2+1)
begin: VAR3
always @(posedge clk or negedge VAR4)
begin
if (~VAR4)
VAR6[VAR2] <= 1'b0;
end
else
begin
if ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr.symbol.v | 1,410 | module MODULE1 (
input VAR6,
output VAR2
);
supply1 VAR7 ;
supply0 VAR5 ;
supply1 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_uart.v | 2,468 | module MODULE1
(
input clk,
input VAR13,
input rst,
input [68:0] VAR12,
output [68:0] VAR29,
output VAR34,
output VAR38,
output VAR19,
input VAR37
);
parameter VAR16 = 0;
parameter VAR2 = 6'd62;
wire VAR3;
wire wr;
wire [3:0] VAR30;
wire [23:0] addr;
wire [31:0] VAR4;
wire [31:0] VAR20;
VAR18 #(.VAR16(VAR16), .VAR9(24'... | mit |
julioamerico/prj_crc_ip | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_defaultslavesm.v | 2,102 | module MODULE1
(
input VAR1,
input VAR3,
input VAR5,
output reg VAR9,
output reg VAR2
);
localparam VAR4 = 1'b0;
localparam VAR7 = 1'b1;
reg VAR8;
reg VAR6;
always @ ( * )
begin
VAR9 = 1'b1;
VAR2 = 1'b0;
case ( VAR6 )
VAR4:
begin
if ( VAR5 )
begin
VAR9 = 1'b0;
VAR2 = 1'b1;
VAR8 = VAR7;
end
else
VAR8 = VAR4;
end
VAR7:
b... | gpl-3.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,573 | module MODULE1 (
clk,
reset,
VAR15,
VAR5,
VAR9,
VAR10,
VAR11,
VAR7
);
parameter VAR6 = 1;
parameter VAR8 = 8;
parameter VAR2 = 1;
localparam VAR1 = VAR6 * VAR8;
input clk;
input reset;
output VAR15;
input VAR5;
input [VAR1-1:0] VAR9;
input VAR10;
output VAR11;
output [VAR1-1:0] VAR7;
reg VAR14;
reg VAR4;
reg [VAR1-1:0]... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.behavioral.pp.v | 3,372 | module MODULE1( VAR3, VAR7, VAR10, VAR1, VAR4, VAR11, VAR2, VAR9 );
input VAR4, VAR11, VAR1, VAR10, VAR7;
inout VAR2, VAR9;
output VAR3;
VAR5 VAR8(.VAR3(VAR3),.VAR7(VAR7),.VAR10(VAR10),.VAR1(VAR1),.VAR4(VAR4),.VAR11(VAR11),.VAR2(VAR2),.VAR9(VAR9));
VAR5 VAR6(.VAR3(VAR3),.VAR7(VAR7),.VAR10(VAR10),.VAR1(VAR1),.VAR4(VAR4)... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/atlys/rtl/verilog/dvi_gen/synchro.v | 3,798 | module MODULE1
parameter VAR4 = "VAR6"
)
(
input wire async,
input wire clk,
output wire sync
);
wire VAR8;
generate
if (VAR4 == "VAR9")
begin : VAR5
VAR3 VAR14 (.VAR1(VAR8),.VAR2(async),.VAR11(clk),.VAR13(1'b0));
VAR3 VAR7 (.VAR1(sync),.VAR2(VAR8),.VAR11(clk),.VAR13(1'b0));
end
else
begin : VAR10
VAR12 VAR14 (.VAR1(VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2/sky130_fd_sc_ls__nand2.symbol.v | 1,266 | module MODULE1 (
input VAR5,
input VAR2,
output VAR1
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
queq/just-stuff | pov/TopFixed/Convierte.v | 1,889 | module MODULE1(
input [3:0]VAR2,
output reg [6:0]VAR1
);
always @(VAR2)begin
case(VAR2)
7'b0000000: VAR1=7'b0000001; 7'b0000001: VAR1=7'b1001111; 7'b0000010: VAR1=7'b0010010; 7'b0000011: VAR1=7'b0000110; 7'b0000100: VAR1=7'b1001100; 7'b0000101: VAR1=7'b0100100; 7'b0000110: VAR1=7'b0100000; 7'b0000111: VAR1=7'b0001111; ... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_snoop.v | 11,116 | module MODULE1
parameter VAR5=10, parameter VAR17=5, parameter VAR15=32, parameter VAR27=2**VAR17,
parameter VAR10=6,
parameter VAR22=0
)
(
input clk,
input VAR21,
input VAR46,
input [VAR15-1:0] VAR14, input VAR1,
input VAR42,
input [VAR15-1:0] VAR13, input [VAR10-1:0] VAR12,
input VAR9,
input VAR4, output VAR24,
outpu... | mit |
bargei/NoC264 | NoC264_3x3/mkInputVCQueues.v | 19,033 | module MODULE1(VAR19,
VAR31,
VAR6,
VAR30,
VAR43,
VAR47,
VAR16,
VAR53,
VAR68,
VAR41);
input VAR19;
input VAR31;
input VAR6;
input [69 : 0] VAR30;
input VAR43;
input VAR47;
input VAR16;
output [69 : 0] VAR53;
output [1 : 0] VAR68;
output [1 : 0] VAR41;
wire [69 : 0] VAR53;
wire [1 : 0] VAR68, VAR41;
wire [2 : 0] VAR18,
V... | mit |
martinmiranda14/Digitales | Lab_6/new/show_one_char2.v | 7,759 | module MODULE1(
input clk,
input rst,
input [10:0]VAR20,
input [10:0]VAR42,
input [7:0] VAR5,
output VAR10,
output reg VAR19
);
localparam VAR39 = 3; localparam VAR34 = 'd1; parameter VAR35 = 11'd70;
parameter VAR31 = 11'd150;
localparam VAR41 = 8'd5;
localparam VAR30 = 8'd8;
localparam VAR25 = 1; localparam VAR33 = 1;... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_negate.v | 1,235 | module MODULE1
parameter VAR2=32
)
(
input [VAR2-1:0] VAR1,
output [VAR2-1:0] VAR3
);
assign VAR3 = { ~VAR1[VAR2-1], VAR1[VAR2-2:0] };
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_lvc_wpad/sky130_fd_io__top_power_lvc_wpad.symbol.v | 1,746 | module MODULE1 (
inout VAR5 ,
inout VAR17,
inout VAR4
);
supply0 VAR9;
supply0 VAR12;
supply1 VAR15 ;
supply1 VAR6 ;
supply1 VAR19 ;
supply0 VAR11 ;
supply1 VAR8 ;
supply1 VAR2 ;
supply1 VAR13 ;
supply1 VAR16 ;
supply1 VAR3 ;
supply1 VAR1 ;
supply1 VAR18 ;
supply0 VAR14 ;
supply0 VAR7 ;
supply0 VAR20 ;
supply0 VAR10 ;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv_1.v | 2,036 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR2,
VAR8,
VAR7 ,
VAR1
);
output VAR3 ;
input VAR6 ;
input VAR2;
input VAR8;
input VAR7 ;
input VAR1 ;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3,
VAR6
);
output VAR3;
input VAR6;
supply1 VAR2;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111oi/sky130_fd_sc_ls__a2111oi.pp.blackbox.v | 1,435 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR1 ,
VAR10,
VAR2,
VAR5 ,
VAR9
);
output VAR7 ;
input VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR10;
input VAR2;
input VAR5 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbn/sky130_fd_sc_lp__dfbbn.behavioral.v | 2,779 | module MODULE1 (
VAR25 ,
VAR30 ,
VAR24 ,
VAR17 ,
VAR3 ,
VAR8
);
output VAR25 ;
output VAR30 ;
input VAR24 ;
input VAR17 ;
input VAR3 ;
input VAR8;
supply1 VAR27;
supply0 VAR4;
supply1 VAR26 ;
supply0 VAR28 ;
wire VAR11 ;
wire VAR21 ;
wire VAR13 ;
wire VAR29 ;
wire VAR5 ;
wire VAR6;
wire VAR14 ;
reg VAR19 ;
wire VAR23 ;... | apache-2.0 |
mwswartwout/EECS318 | hw3/problem3/processor.v | 6,320 | module MODULE1(VAR1);
input VAR1;
reg [31:0] memory [4095:0]; reg [11:0] register [4:0];
reg [23:0] VAR3;
reg [11:0] VAR8, VAR9;
reg signed [11:0] VAR7;
reg [4:0] VAR2;
reg VAR4;
integer VAR6, VAR5, VAR10; | mit |
alexforencich/verilog-wishbone | rtl/wb_arbiter_2.v | 5,624 | module MODULE1 #
(
parameter VAR6 = 32, parameter VAR13 = 32, parameter VAR34 = (VAR6/8), parameter VAR18 = 0, parameter VAR20 = 1 )
(
input wire clk,
input wire rst,
input wire [VAR13-1:0] VAR44, input wire [VAR6-1:0] VAR16, output wire [VAR6-1:0] VAR25, input wire VAR42, input wire [VAR34-1:0] VAR4, input wire VAR2, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32a/sky130_fd_sc_hs__o32a.functional.pp.v | 2,089 | module MODULE1 (
VAR1,
VAR14,
VAR6 ,
VAR5 ,
VAR9 ,
VAR8 ,
VAR18 ,
VAR12
);
input VAR1;
input VAR14;
output VAR6 ;
input VAR5 ;
input VAR9 ;
input VAR8 ;
input VAR18 ;
input VAR12 ;
wire VAR18 VAR10 ;
wire VAR18 VAR15 ;
wire VAR2 ;
wire VAR3;
or VAR16 (VAR10 , VAR9, VAR5, VAR8 );
or VAR13 (VAR15 , VAR12, VAR18 );
and VA... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/Sgf_Multiplication.v | 8,594 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR20,
input wire [VAR26-1:0] VAR12,
input wire [VAR26-1:0] VAR36,
output wire [2*VAR26-1:0] VAR37
);
wire [VAR26/2+1:0] VAR19;
wire [VAR26/2+1:0] VAR33;
wire [2*(VAR26/2)-1:0] VAR27;
wire [2*(VAR26/2+1)-1:0] VAR8;
wire [2*(VAR26/2+2)-1:0] VAR1;
wire [2*(VAR26... | gpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_onchip_memory2_0.v | 3,119 | module MODULE1 (
address,
VAR7,
VAR19,
clk,
VAR24,
reset,
VAR1,
write,
VAR30,
VAR8
)
;
parameter VAR15 = "MODULE1.VAR10";
output [ 31: 0] VAR8;
input [ 9: 0] address;
input [ 3: 0] VAR7;
input VAR19;
input clk;
input VAR24;
input reset;
input VAR1;
input write;
input [ 31: 0] VAR30;
wire VAR16;
wire [ 31: 0] VAR8;
wire... | mit |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/infrastructure.v | 7,342 | module MODULE1 (
VAR5,
VAR15,
VAR19,
VAR9,
VAR26,
VAR22,
VAR16,
VAR48,
VAR18,
VAR37,
VAR7,
VAR41,
VAR31,
VAR35
);
input VAR5;
input VAR15;
input VAR26;
input [143:0] VAR19;
input VAR9;
output [4:0]VAR22;
output VAR16;
output VAR48;
output VAR18;
output VAR37;
output VAR7;
output VAR35;
output [7:0] VAR41;
output [7:0] ... | lgpl-3.0 |
AbhishekShah212/School_Projects | ELEN232/pset4/Problem4FinalCircuit.v | 3,382 | module MODULE1(
input [7:0] VAR40,
input [7:0] VAR27,
output VAR6,
output VAR7,
output VAR13
);
wire VAR15, VAR43, VAR10; wire VAR14, VAR16, VAR24;
wire VAR37, VAR23, VAR29;
wire VAR8, VAR17, VAR35;
wire VAR26, VAR31, VAR2;
wire VAR11, VAR42, VAR20;
wire VAR39, VAR32, VAR9;
VAR38 VAR3(
.VAR19(VAR40[0]),
.VAR41(VAR27[0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd.functional.pp.v | 1,208 | module MODULE1 (
VAR4,
VAR3,
VAR2 ,
VAR1
);
input VAR4;
input VAR3;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RegTwoN.v | 2,370 | module MODULE1(VAR6, VAR2, VAR4, VAR5, VAR1, VAR9, VAR8);
parameter VAR7 = 1;
parameter VAR11 = {VAR7 {1'b0}} ;
input VAR6;
input VAR2;
input VAR1, VAR8;
input [VAR7 - 1 : 0] VAR5;
input [VAR7 - 1 : 0] VAR9;
output [VAR7 - 1 : 0] VAR4;
reg [VAR7 - 1 : 0] VAR4;
always@(posedge VAR6)
begin
if (VAR2 == VAR10)
VAR4 <= VAR3... | mit |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | lfsr.v | 3,872 | module MODULE1
wire VAR12;
VAR10 #( .VAR15(VAR15) ) VAR5 ( .VAR17(VAR17) , .VAR12 (VAR12 ) );
VAR3 #(
.VAR8 (VAR15 ), .VAR11("VAR16"), .VAR9 (VAR2 ) ) VAR14 (
.VAR7 (clk), .enable (VAR4), .VAR6(VAR12 ), .VAR1 (rst), .VAR13 (VAR17) );
endmodule | bsd-3-clause |
fredmorcos/attic | snippets/verilog/fibfast.v | 1,840 | module MODULE1 (clk, VAR14, VAR4, VAR2, VAR9);
parameter VAR1 = 32;
input [VAR1-1:0] VAR14;
input clk, VAR4;
output [VAR1-1:0] VAR2;
output VAR9;
parameter VAR11 = 3'b000;
parameter VAR16 = 3'b001;
parameter VAR3 = 3'b010;
parameter VAR7 = 3'b011;
parameter VAR8 = 3'b100;
reg [2:0] state, VAR10;
reg [VAR1-1:0] VAR5;
re... | isc |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_12.behavioral.pp.v | 1,241 | module MODULE1( VAR6, VAR5, VAR8, VAR3, VAR7 );
input VAR6, VAR5;
inout VAR3, VAR7;
output VAR8;
VAR2 VAR1(.VAR6(VAR6),.VAR5(VAR5),.VAR8(VAR8),.VAR3(VAR3),.VAR7(VAR7));
VAR2 VAR4(.VAR6(VAR6),.VAR5(VAR5),.VAR8(VAR8),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
ptracton/pmodacl2 | soc/gpio/gpio_regs.v | 4,188 | module MODULE1 (
VAR6, VAR19, VAR14, interrupt,
clk, reset, VAR13, VAR18, VAR4, VAR10,
VAR8
) ;
parameter VAR11 = 8'h00;
input clk;
input reset;
input [7:0] VAR13;
input [7:0] VAR18;
output [7:0] VAR6;
input VAR4;
input VAR10;
output [7:0] VAR19;
output [7:0] VAR14;
input [7:0] VAR8;
output interrupt;
reg interrupt = 0... | mit |
aj-michael/Digital-Systems | Lab6-Part2/ipcore_dir/SystemClockUnit.v | 5,628 | module MODULE1
( input VAR11,
output VAR48,
output VAR28
);
VAR23 VAR17
(.VAR14 (VAR43),
.VAR26 (VAR11));
wire VAR18;
wire VAR21;
wire [7:0] VAR15;
wire VAR10;
wire VAR32;
wire VAR7;
VAR37
.VAR13 (20),
.VAR1 (13),
.VAR3 ("VAR49"),
.VAR36 (10.0),
.VAR24 ("VAR4"),
.VAR27 ("1X"),
.VAR44 ("VAR39"),
.VAR16 (0),
.VAR40 ("VAR... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/ACA_II_N32_Q16_syn.v | 13,732 | module MODULE1 ( VAR137, VAR189, VAR415 );
input [31:0] VAR137;
input [31:0] VAR189;
output [32:0] VAR415;
wire VAR232, VAR333, VAR422, VAR350, VAR13, VAR153, VAR80, VAR266, VAR145, VAR438, VAR455, VAR118, VAR55, VAR370, VAR212,
VAR309, VAR394, VAR421, VAR167, VAR107, VAR458, VAR181, VAR10, VAR2, VAR361, VAR404, VAR411... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/arWCIS2A4LM.v | 3,380 | module MODULE1 (
input VAR39,
input VAR43,
input [2:0] VAR35, input [0:0] VAR7, input [3:0] VAR32,
input [31:0] VAR41, input [31:0] VAR20,
output [1:0] VAR45,
output [31:0] VAR12,
output [0:0] VAR50,
output [0:0] VAR10,
input [0:0] VAR31,
output VAR46, input VAR11,
output [31:0] VAR40, output [2:0] VAR21,
output VAR3, ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrc/sky130_fd_sc_hd__lpflow_isobufsrc.pp.symbol.v | 1,393 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR1,
input VAR6 ,
input VAR4 ,
input VAR7 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/diode/sky130_fd_sc_lp__diode.behavioral.pp.v | 1,200 | module MODULE1 (
VAR2,
VAR5 ,
VAR3 ,
VAR4 ,
VAR1
);
input VAR2;
input VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/clkgen/clkgen.v | 6,273 | module MODULE1
(
VAR41, VAR27,
VAR22,
VAR12,
VAR39,
VAR16,
VAR35,
VAR33,
VAR49,
VAR40
);
input VAR41,VAR27;
output VAR12;
output VAR22;
input VAR39;
output VAR16;
output VAR35;
output VAR33;
output VAR49;
input VAR40;
wire VAR14;
wire VAR18;
assign VAR18 = VAR40;
assign VAR14 = ~VAR18;
assign VAR16 = VAR39;
wire VAR15;... | mit |
P3Stor/P3Stor | pcie/core/pcie_128_if.v | 25,340 | module MODULE1 #(
parameter VAR29 = 100
)(
input VAR202,
input VAR77,
output [6:0] VAR58,
output [127:0] VAR223,
output VAR61,
output VAR230,
output VAR25,
output VAR97,
output [1:0] VAR143,
output VAR138,
output VAR79,
input VAR204,
input VAR183,
output [5:0] VAR16,
output VAR41,
output VAR27,
input [127:0] VAR35,
inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o.functional.v | 1,406 | module MODULE1 (
VAR7 ,
VAR5,
VAR9,
VAR6
);
output VAR7 ;
input VAR5;
input VAR9;
input VAR6;
wire VAR3 ;
wire VAR8;
and VAR1 (VAR3 , VAR5, VAR9 );
or VAR4 (VAR8, VAR3, VAR6 );
buf VAR2 (VAR7 , VAR8 );
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/ppu/rgb_vga_generator.v | 7,622 | module MODULE1 #(
parameter VAR2 = 100
)(
input clk, input rst,
output [9:0] VAR5,
output [9:0] VAR32,
output VAR1,
output VAR10,
output [2:0] VAR9, output [2:0] VAR21, output [1:0] VAR12,
input [5:0] VAR24,
output [9:0] VAR7, output [9:0] VAR11, output [9:0] VAR29, output reg VAR33, output VAR25 );
localparam VAR31 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ba/sky130_fd_sc_hd__o21ba.behavioral.pp.v | 2,037 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR6 ,
VAR15,
VAR14,
VAR12,
VAR7 ,
VAR13
);
output VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR15;
input VAR14;
input VAR12;
input VAR7 ;
input VAR13 ;
wire VAR9 ;
wire VAR11 ;
wire VAR5;
nor VAR16 (VAR9 , VAR1, VAR6 );
nor VAR8 (VAR11 , VAR15, VAR9 );
VAR2 VAR4 (VAR5, VAR11, VAR14, VAR12);... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/ip/ip_3/synth/bd_350b_slot_0_w_0.v | 4,558 | module MODULE1 (
VAR42,
VAR48,
dout
);
input wire [0 : 0] VAR42;
input wire [0 : 0] VAR48;
output wire [1 : 0] dout;
VAR12 #(
.VAR40(1),
.VAR20(1),
.VAR22(1),
.VAR67(1),
.VAR15(1),
.VAR68(1),
.VAR2(1),
.VAR16(1),
.VAR21(1),
.VAR26(1),
.VAR6(1),
.VAR34(1),
.VAR60(1),
.VAR50(1),
.VAR57(1),
.VAR52(1),
.VAR61(1),
.VAR41(1)... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_port_lookup/cam_router/src/eth_parser.v | 6,321 | module MODULE1
parameter VAR12 = 8,
parameter VAR36 = VAR5(VAR12)
)
( input [VAR32-1:0] VAR27,
output VAR21,
output VAR11,
output VAR20,
output VAR14,
output [VAR36-1:0] VAR30,
input VAR9,
output VAR17,
input VAR19,
input VAR22,
input VAR1,
input [47:0] VAR15, input [47:0] VAR4, input [47:0] VAR37, input [47:0] VAR24,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/decap/sky130_fd_sc_hdll__decap_6.v | 1,886 | module MODULE1 (
VAR1,
VAR5,
VAR4 ,
VAR6
);
input VAR1;
input VAR5;
input VAR4 ;
input VAR6 ;
VAR2 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 ();
supply1 VAR1;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR6 ;
VAR2 VAR3 ();
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fetch/wrap_ref_luma.v | 2,228 | module MODULE1 (
clk ,
VAR15 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR5 ,
VAR9 ,
VAR12
);
input [1-1:0] clk ; input [1-1:0] VAR15 ;
input [1-1:0] VAR6 ; input [7-1:0] VAR11 ; input [96*VAR10-1:0] VAR1 ;
input [1-1:0] VAR5 ; input [7-1:0] VAR9 ; output [96*VAR10-1:0] VAR12 ;
wire [7-1:0] VAR4;
assign VAR4 = (VAR6) ? VAR11 : VAR9;
VAR... | gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v | 26,458 | module MODULE1 #
(
parameter VAR11 = "none",
parameter integer VAR49 = 1,
parameter integer VAR30 = 32,
parameter integer VAR57 = 32,
parameter integer VAR157 = 0,
parameter integer VAR161 = 1,
parameter integer VAR78 = 1,
parameter integer VAR43 = 1,
parameter integer VAR126 = 1,
parameter integer VAR153 = 1,
paramete... | gpl-3.0 |
keith-epidev/VHDL-lib | top/lab_7/part_2/ip/clk_adc/clk_adc_stub.v | 1,196 | module MODULE1(VAR4, VAR2, VAR1, VAR3)
;
input VAR4;
input VAR2;
output VAR1;
output VAR3;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3/sky130_fd_sc_hdll__and3.functional.pp.v | 1,828 | module MODULE1 (
VAR2 ,
VAR11 ,
VAR8 ,
VAR12 ,
VAR6,
VAR7,
VAR1 ,
VAR4
);
output VAR2 ;
input VAR11 ;
input VAR8 ;
input VAR12 ;
input VAR6;
input VAR7;
input VAR1 ;
input VAR4 ;
wire VAR10 ;
wire VAR9;
and VAR3 (VAR10 , VAR12, VAR11, VAR8 );
VAR13 VAR14 (VAR9, VAR10, VAR6, VAR7);
buf VAR5 (VAR2 , VAR9 );
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/etx_arbiter.v | 5,695 | module MODULE1 (
VAR26, VAR27, VAR16, VAR31, VAR19,
VAR22, VAR32, VAR30, VAR13, VAR20,
VAR23, reset, VAR25, VAR18,
VAR37, VAR10, VAR34,
VAR8, VAR17, VAR36,
VAR15, VAR11, VAR21,
VAR29, VAR35, VAR4,
VAR14, VAR5, VAR24,
VAR7, VAR2, VAR33,
VAR38, VAR3, VAR1, VAR6
);
input VAR23;
input reset;
input VAR25;
input VAR18;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2b/sky130_fd_sc_ms__and2b.behavioral.v | 1,452 | module MODULE1 (
VAR12 ,
VAR2,
VAR7
);
output VAR12 ;
input VAR2;
input VAR7 ;
supply1 VAR1;
supply0 VAR11;
supply1 VAR9 ;
supply0 VAR10 ;
wire VAR4 ;
wire VAR5;
not VAR8 (VAR4 , VAR2 );
and VAR6 (VAR5, VAR4, VAR7 );
buf VAR3 (VAR12 , VAR5 );
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128.v | 13,760 | module MODULE1(
clk,
rst,
din,
VAR211,
VAR242,
dout,
VAR360,
VAR68,
VAR229,
VAR289
);
input clk;
input rst;
input [127 : 0] din;
input VAR211;
input VAR242;
output [127 : 0] dout;
output VAR360;
output VAR68;
output VAR229;
output VAR289;
VAR351 #(
.VAR231(0),
.VAR274(0),
.VAR387(0),
.VAR83(0),
.VAR149(0),
.VAR415(0),
... | gpl-2.0 |
efabless/openlane | designs/y_huff/src/y_huff.v | 68,051 | module MODULE1(clk, rst, enable,
VAR247, VAR403, VAR408, VAR194, VAR326, VAR377, VAR16, VAR375, VAR265, VAR100, VAR435, VAR63, VAR382, VAR127, VAR347, VAR311,
VAR108, VAR243, VAR155, VAR252, VAR363, VAR161, VAR11, VAR88, VAR114, VAR6, VAR343, VAR30, VAR414, VAR349, VAR32, VAR237,
VAR211, VAR389, VAR41, VAR438, VAR353, ... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v | 2,297 | module MODULE1(
VAR9,
VAR19,
VAR8,
VAR18,
req,
VAR21,
VAR6,
VAR15,
VAR10,
VAR4,
VAR7
);
input VAR9, VAR19;
output VAR8, VAR18;
input VAR7, VAR4;
input [VAR12-1:0] VAR10, VAR15;
input req, VAR21;
input [VAR16-1:0] VAR6;
reg [VAR5-1:0] VAR20 = 0, VAR2 = 0;
reg [VAR14-1:0] VAR1 [0:VAR17-1]; wire VAR8, VAR18;
assign VAR18 ... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/calib_top.v | 37,673 | module MODULE1 #
(
parameter VAR194 = 100,
parameter VAR44 = 2, parameter VAR196 = 3333, parameter VAR134 = 3, parameter VAR136 = "VAR87", parameter VAR183 = 64, parameter VAR110 = 4,
parameter VAR17 = 3,
parameter VAR111
= 144'h000000000000000000000000000000000000,
parameter [7:0] VAR37 = 8'b00000000,
parameter VAR5 =... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2oi/sky130_fd_sc_hd__a2bb2oi.blackbox.v | 1,463 | module MODULE1 (
VAR7 ,
VAR8,
VAR3,
VAR9 ,
VAR1
);
output VAR7 ;
input VAR8;
input VAR3;
input VAR9 ;
input VAR1 ;
supply1 VAR5;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_hps_0.v | 30,534 | module MODULE1 #(
parameter VAR114 = 3,
parameter VAR14 = 2
) (
output wire VAR170, input wire VAR154, input wire VAR85, input wire VAR171, input wire [27:0] VAR180, input wire VAR88, input wire [7:0] VAR80, input wire [31:0] VAR132, input wire [3:0] VAR139, input wire [2:0] VAR111, input wire [1:0] VAR40, input wire [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4/sky130_fd_sc_hd__or4.symbol.v | 1,282 | module MODULE1 (
input VAR9,
input VAR2,
input VAR8,
input VAR5,
output VAR1
);
supply1 VAR3;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/fmlarb/fmlarb_dack.v | 1,765 | module MODULE1(
input VAR5,
input VAR2,
input VAR3,
input VAR1,
input VAR6,
output VAR8,
output reg ack
);
wire read = VAR1 & ~VAR6;
wire write = VAR1 & VAR6;
reg VAR9;
reg VAR10;
reg VAR11;
always @(posedge VAR5) begin
if(VAR2) begin
VAR9 <= 1'b0;
VAR10 <= 1'b0;
VAR11 <= 1'b0;
end else begin
VAR9 <= read;
VAR10 <= VAR... | lgpl-3.0 |
skyfex/svo-raycaster | raycaster2/raycast_core_master.v | 4,513 | module MODULE1
(
clk, rst,
VAR7, VAR39,
VAR27, VAR28,
VAR25,
VAR17, VAR42,
VAR19,
VAR5,
VAR35,
VAR32,
VAR33
);
parameter VAR24 = 2;
parameter VAR41 = 1;
input clk;
input rst;
output reg [31:0] VAR7;
input [31:0] VAR39;
output reg VAR27;
output VAR28;
input VAR25;
input VAR17;
input VAR42;
input [31:0] VAR19;
input [2:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv.behavioral.pp.v | 1,792 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR4,
VAR5,
VAR12 ,
VAR6
);
output VAR11 ;
input VAR3 ;
input VAR4;
input VAR5;
input VAR12 ;
input VAR6 ;
wire VAR9 ;
wire VAR2;
not VAR7 (VAR9 , VAR3 );
VAR10 VAR8 (VAR2, VAR9, VAR4, VAR5);
buf VAR1 (VAR11 , VAR2 );
endmodule | apache-2.0 |
lbl-cal/StanfordNoC | router/src/clib/c_rr_arbiter.v | 5,494 | module MODULE1
(clk, reset, VAR17, VAR23, VAR45, VAR25, VAR26);
parameter VAR38 = 32;
parameter VAR44 = 1;
parameter VAR3 = 1;
localparam VAR54 = VAR16(VAR38);
parameter VAR30 = VAR8;
input clk;
input reset;
input VAR17;
input [0:VAR44*VAR38-1] VAR23;
output [0:VAR44*VAR38-1] VAR45;
wire [0:VAR44*VAR38-1] VAR45;
output... | bsd-2-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/swrvr_dlib.v | 6,605 | module MODULE3 (dout, VAR21, VAR15, sel) ;
parameter VAR4 = 1;
output [VAR4-1:0] dout;
input [VAR4-1:0] VAR21;
input [VAR4-1:0] VAR15;
input sel;
reg [VAR4-1:0] dout ;
always @ (sel or VAR21 or VAR15)
begin
case (sel)
1'b1: dout = VAR15 ;
1'b0: dout = VAR21;
default:
begin
if (VAR21 == VAR15) begin
dout = VAR21;
end
el... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_2.v | 2,271 | module MODULE1 (
VAR7 ,
VAR6,
VAR3,
VAR9 ,
VAR5 ,
VAR4,
VAR2
);
output VAR7 ;
input VAR6;
input VAR3;
input VAR9 ;
input VAR5 ;
input VAR4;
input VAR2;
VAR8 VAR1 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR7 ,
VAR6,
VAR3,
VAR9 ,
VAR5
);
ou... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/iface/ip/export/export_master.v | 1,793 | module MODULE1 (
clk,
reset,
address,
read,
VAR13,
VAR3,
write,
VAR17,
VAR12,
VAR14,
VAR8,
VAR5,
VAR15,
VAR18,
VAR1,
VAR19,
VAR9,
VAR2,
VAR7,
VAR6,
VAR22,
VAR24,
interrupt,
VAR23
);
parameter VAR21 = 4;
parameter VAR16 = 32;
parameter VAR4 = 32;
parameter VAR11 = 1;
localparam VAR10 = VAR21 * 8;
localparam VAR20 = VAR1... | mit |
wgml/sysrek | fsm2/fsm2.v | 1,600 | module MODULE1(
input clk,
input rst,
input VAR5,
output [7:0] VAR10,
output VAR2
);
localparam VAR6 = 2'b00;
localparam VAR8 = 2'b01;
localparam VAR9 = 2'b10;
reg [1:0] state = VAR6;
reg [7:0] VAR3 = 8'b00000000;
reg VAR4 = 1'b0;
reg [2:0] VAR1;
reg [1:0] VAR7 = 2'b11;
always @(posedge clk)
begin
if(rst)
begin
VAR3 = ... | gpl-2.0 |
betaEncoder/PSoC_WS2812Bdriver | Lticker.cydsn/WS2812driver/WS2812driver.v | 16,028 | module MODULE1 (
output VAR80,
output VAR20,
output VAR57,
input VAR89
);
localparam VAR25 = 2'd0;
localparam VAR73 = 2'd1;
localparam VAR2 = 2'd2;
localparam VAR47 = 2'd3;
reg VAR66;
reg [1:0] VAR31;
reg VAR58;
reg VAR8;
wire VAR52;
wire VAR33;
localparam VAR53 = 3'd0;
localparam VAR38 = 3'd1;
localparam VAR44 = 3'd2;... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/niosII_system/submodules/niosII_system_sdram_0.v | 23,937 | module MODULE1 (
clk,
rd,
VAR68,
wr,
VAR10,
VAR16,
VAR49,
VAR42,
VAR55,
VAR43
)
;
output VAR16;
output VAR49;
output VAR42;
output VAR55;
output [ 40: 0] VAR43;
input clk;
input rd;
input VAR68;
input wr;
input [ 40: 0] VAR10;
wire VAR16;
wire VAR49;
wire VAR42;
reg [ 1: 0] VAR50;
reg [ 40: 0] VAR21;
reg [ 40: 0] VAR63... | gpl-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/system_mig_7series_0_0.v | 10,467 | module MODULE1 (
inout [15:0] VAR26,
inout [1:0] VAR9,
inout [1:0] VAR12,
output [13:0] VAR47,
output [2:0] VAR60,
output VAR62,
output VAR14,
output VAR63,
output VAR37,
output [0:0] VAR44,
output [0:0] VAR57,
output [0:0] VAR39,
output [0:0] VAR41,
output [1:0] VAR58,
output [0:0] VAR3,
input VAR24,
input VAR4,
outpu... | apache-2.0 |
lbl-cal/StanfordNoC | router/src/clib/c_regfile.v | 7,542 | module MODULE1
(clk, VAR9, VAR6, VAR5, VAR7, VAR14,
VAR15);
parameter VAR2 = 8;
parameter VAR19 = 64;
parameter VAR13 = 1;
parameter VAR12 = 1;
parameter VAR20 = VAR8;
localparam VAR18 = VAR10(VAR2);
input clk;
input VAR9;
input [0:VAR13-1] VAR6;
input [0:VAR13*VAR18-1] VAR5;
input [0:VAR13*VAR19-1] VAR7;
input [0:VAR1... | bsd-2-clause |
SymbiFlow/yosys | techlibs/gowin/arith_map.v | 2,086 | module MODULE1(
module 80gw1nalu(VAR3, VAR4, VAR30, VAR5, VAR1, VAR25, VAR10);
parameter VAR7 = 0;
parameter VAR8 = 0;
parameter VAR6 = 1;
parameter VAR29 = 1;
parameter VAR14 = 1;
input [VAR6-1:0] VAR3;
input [VAR29-1:0] VAR4;
output [VAR14-1:0] VAR1, VAR25;
input VAR30, VAR5;
output [VAR14-1:0] VAR10;
wire VAR20 = VA... | isc |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_xnor.v | 1,588 | if (VAR9 && (VAR8==VAR7)) \
begin: VAR17 \
VAR19 VAR18 (.VAR2(VAR6),.VAR1(VAR11),.VAR15); \
end
module MODULE1 #(parameter VAR13(VAR8)
, parameter VAR9=0
)
(input [VAR8-1:0] VAR6
, input [VAR8-1:0] VAR11
, output [VAR8-1:0] VAR15
);
begin :VAR3
end
VAR4 assert(VAR9==0) else ("## %VAR20 VAR12 VAR10 VAR14 VAR16 VAR5 VAR1... | bsd-3-clause |
dries007/Basys3 | VGA/VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v | 3,978 | module MODULE1
(
input VAR5,
output VAR4,
input reset,
output VAR1
);
VAR3 VAR2
(
.VAR5(VAR5),
.VAR4(VAR4),
.reset(reset),
.VAR1(VAR1)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3b/sky130_fd_sc_hs__nand3b.pp.symbol.v | 1,280 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR3 ,
output VAR5 ,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_8.behavioral.pp.v | 1,236 | module MODULE1( VAR1, VAR4, VAR6, VAR7, VAR8 );
input VAR1, VAR4;
inout VAR7, VAR8;
output VAR6;
VAR3 VAR5(.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6),.VAR7(VAR7),.VAR8(VAR8));
VAR3 VAR2(.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6),.VAR7(VAR7),.VAR8(VAR8)); | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/small_rom.v | 6,659 | module MODULE1 (
address,
VAR42,
VAR5);
parameter VAR21 = ""; parameter VAR50 = "VAR6=VAR1";
parameter VAR12 = "VAR51";
input [11:0] address;
input VAR42;
output [7:0] VAR5;
tri1 VAR42;
wire [7:0] VAR26;
wire [7:0] VAR5 = VAR26[7:0];
VAR28 VAR22 (
.VAR30 (address),
.VAR18 (VAR42),
.VAR7 (VAR26),
.VAR45 (1'b0),
.VAR4 (1... | gpl-3.0 |
vad-rulezz/megabot | minsoc/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v | 9,961 | module MODULE2 (
VAR15, VAR87,
VAR63, VAR89, VAR34, VAR18, VAR58, VAR60,
VAR85, VAR25, VAR42
);
parameter VAR44 = 13; localparam VAR38 = 11; localparam VAR84 = (1<<(VAR44-VAR38));
input VAR15;
input VAR87;
input [31:0] VAR63;
output [31:0] VAR89;
input [31:0] VAR34;
input [3:0] VAR18;
input VAR58;
input VAR60;
input VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.v | 2,309 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR1,
VAR7 ,
VAR4 ,
VAR2 ,
VAR6
);
output VAR9 ;
input VAR8 ;
input VAR1;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
VAR5 VAR3 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR9 ,
VAR8 ,
VAR1
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.blackbox.v | 1,455 | module MODULE1 (
VAR5 ,
VAR11 ,
VAR10 ,
VAR2 ,
VAR4 ,
VAR9 ,
VAR3
);
output VAR5 ;
output VAR11 ;
input VAR10 ;
input VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR3;
supply1 VAR6;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/openmsp430/omsp_wakeup_cell.v | 4,153 | module MODULE1 (
VAR3,
VAR14, VAR8, VAR13, VAR7, VAR4 );
output VAR3;
input VAR14; input VAR8; input VAR13; input VAR7; input VAR4;
wire VAR5;
VAR1 VAR2 (
.VAR8 (VAR8),
.VAR9 (VAR13),
.VAR11 (VAR7),
.VAR10 (VAR5)
);
wire VAR6;
VAR1 VAR12 (
.VAR8 (VAR8),
.VAR9 (VAR14),
.VAR11 (VAR4),
.VAR10 (VAR6)
);
wire VAR5 = VAR7;
w... | bsd-3-clause |
KestrelComputer/kestrel | cores/S16X4/rtl/verilog/S16X4.v | 6,237 | module MODULE1(
input VAR40,
input VAR31,
output [15:1] VAR42,
output VAR21,
output VAR18,
output VAR3,
output [1:0] VAR19,
output VAR45,
output VAR15,
output [15:0] VAR29,
input VAR5,
input [15:0] VAR26
);
reg [15:1] VAR16;
reg VAR35;
reg VAR39;
reg [1:0] sel;
reg VAR30;
reg VAR2;
reg [15:0] VAR17;
assign VAR42 = VAR1... | mpl-2.0 |
ThotIP/async_fifo | src/vlog/sync_r2w.v | 1,242 | module MODULE1
parameter VAR6 = 4
)(
input wire VAR3,
input wire VAR1,
input wire [VAR6:0] VAR4,
output reg [VAR6:0] VAR2
);
reg [VAR6:0] VAR5;
always @(posedge VAR3 or negedge VAR1) begin
if (!VAR1)
{VAR2,VAR5} <= 0;
end
else
{VAR2,VAR5} <= {VAR5,VAR4};
end
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp1/toplevel/usrp_std/usrp_std.v | 12,605 | module MODULE1
(output VAR195,
input VAR83,
input VAR23,
input VAR97,
inout VAR72,
input VAR204,
input VAR108,
output VAR80,
output VAR10,
input wire [11:0] VAR53,
input wire [11:0] VAR130,
input wire [11:0] VAR76,
input wire [11:0] VAR11,
output wire [13:0] VAR146,
output wire [13:0] VAR87,
output wire VAR170,
output ... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/6223c44b21ae4a4d/zqynq_lab_1_design_axi_gpio_1_1_stub.v | 2,391 | module MODULE1(VAR18, VAR13, VAR10,
VAR6, VAR17, VAR14, VAR1, VAR7, VAR12,
VAR15, VAR11, VAR16, VAR4, VAR20, VAR2,
VAR8, VAR3, VAR9, VAR5, VAR19, VAR21)
;
input VAR18;
input VAR13;
input [8:0]VAR10;
input VAR6;
output VAR17;
input [31:0]VAR14;
input [3:0]VAR1;
input VAR7;
output VAR12;
output [1:0]VAR15;
output VAR11;
... | mit |
HackLinux/CPU-Design | cpu/EX.v | 4,701 | module MODULE1(VAR11,
VAR14, VAR21, VAR20, VAR16, VAR9,
VAR6, VAR12, VAR8,
VAR24, VAR15, VAR13, VAR29,
VAR19, VAR22, VAR17, VAR25
);
input VAR11;
input [31:0] VAR14;
input signed [31:0] VAR21, VAR20;
input [4:0] VAR16;
input [31:0] VAR9;
inout [31:0] VAR15;
input [63:0] VAR17, VAR25;
output [31:0] VAR24;
output [4:0] V... | bsd-2-clause |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/pmodOLEDrgb_v1_0/hdl/PmodOLEDrgb_v1_0.v | 9,682 | module MODULE1 #
(
parameter integer VAR92 = 32,
parameter integer VAR166 = 7,
parameter integer VAR41 = 32,
parameter integer VAR108 = 9
)
(
input wire VAR51,
input wire VAR95,
output wire VAR146,
output wire VAR113,
input wire VAR33,
output wire VAR47,
output wire VAR88,
input wire VAR22,
output wire VAR34,
output wi... | bsd-3-clause |
meteorcloudy/CPU_verilog | IP_ROM.v | 3,674 | module MODULE1(VAR2,VAR3
);
input [31:0] VAR2;
output [31:0] VAR3;
wire [31:0] VAR1 [0:63];
/*
assign VAR1[6'h00]=32'h20230000; assign VAR1[6'h01]=32'h20430000; assign VAR1[6'h02]=32'h14420001; assign VAR1[6'h03]=32'hffffffff;
assign VAR1[6'h04]=32'hffffffff; assign VAR1[6'h05]=32'h1c210080; assign VAR1[6'h06]=32'hffff... | mit |
apotocnik/redpitaya_guide | projects/2_knight_rider/knight_rider.v | 1,391 | module MODULE1(
input clk,
output [7:0] VAR4
);
parameter VAR1 = 10'b1100000000;
parameter VAR6 = 1;
reg [9:0] VAR3 = VAR1; reg [3:0] VAR2 = VAR6*8; reg VAR5 = VAR6;
always @ (posedge clk) begin
if (VAR5 == 0) begin
VAR3 <= VAR3 << 1; end else begin
VAR3 <= VAR3 >> 1; end
VAR2 <= VAR2 + 1;
end
always @ (VAR2) begin if ... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/tart_spi/bench/capture/signal_stagger.v | 6,056 | module MODULE1
parameter VAR22 = VAR4-1,
parameter VAR5 = 12, parameter VAR12 = 4, parameter VAR30 = VAR12-1, parameter VAR25 = 0, parameter VAR2 = VAR5>>1, parameter VAR13 = VAR5-1,
parameter VAR29 = VAR12+1, parameter VAR24 = VAR29-1, parameter VAR3 = 0, parameter VAR11 = VAR5>>1, parameter VAR17 = VAR5-1,
parameter ... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_1.functional.v | 1,436 | module MODULE1( VAR7, VAR15, VAR14, VAR3, VAR9 );
input VAR15, VAR3, VAR9, VAR7;
output VAR14;
wire VAR4;
not VAR1( VAR4, VAR15 );
wire VAR8;
not VAR16( VAR8, VAR3 );
wire VAR12;
not VAR2( VAR12, VAR9 );
wire VAR11;
and VAR10( VAR11, VAR4, VAR8, VAR12 );
wire VAR13;
not VAR5( VAR13, VAR7 );
or VAR6( VAR14, VAR11, VAR13... | apache-2.0 |
bluespec/Flute | builds/RV32ACDFIMSU_Flute_verilator/Verilog_RTL/mkCSR_MIP.v | 9,941 | module MODULE1(VAR52,
VAR56,
VAR46,
VAR54,
VAR40,
VAR15,
VAR6,
VAR31,
VAR53,
VAR21,
VAR8,
VAR66,
VAR11,
VAR7,
VAR28,
VAR23,
VAR4);
input VAR52;
input VAR56;
input VAR46;
output [31 : 0] VAR54;
input [27 : 0] VAR40;
input [31 : 0] VAR15;
input VAR6;
output [31 : 0] VAR31;
output [31 : 0] VAR53;
input [27 : 0] VAR21;
inp... | apache-2.0 |
sh-chris110/chris | FPGA/chris.final/Qsys/soc_design/synthesis/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1500971289 : 255;
endmodule | gpl-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_pipe_reset.v | 22,146 | module MODULE1 #
(
parameter VAR30 = "VAR6", parameter VAR13 = "VAR34",
parameter VAR66 = "VAR27", parameter VAR35 = "VAR71", parameter VAR29 = "VAR6", parameter VAR72 = 1, parameter VAR67 = 6'd63, parameter VAR68 = 1
)
(
input VAR69,
input VAR3,
input VAR48,
input VAR4,
input [VAR72-1:0] VAR33,
input [VAR72-1:0] VAR78... | mit |
eda-globetrotter/PicenoDecoders | viterbi/cencoder.v | 1,442 | module MODULE1 (output [1:0] VAR4, input VAR1, input clk, input reset);
reg [1:0] VAR4;
reg VAR2, VAR3;
always @ (posedge clk)
begin
if (reset)
begin
VAR2 <= 1'b0;
end
else
begin
VAR2 <= VAR1;
end
end
always @ (posedge clk)
begin
if (reset)
begin
VAR3 <= 1'b0;
end
else
begin
VAR3 <= VAR2;
end
end
always @ (VAR2 or VAR3... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/verilog/feedforward_mul_7ns_32s_39_3.v | 1,441 | module MODULE1(clk, VAR16, VAR12, VAR3, VAR10);
input clk;
input VAR16;
input[7 - 1 : 0] VAR12; input[32 - 1 : 0] VAR3; output[39 - 1 : 0] VAR10;
reg [7 - 1 : 0] VAR9;
reg signed [32 - 1 : 0] VAR6;
wire signed [39 - 1 : 0] VAR15;
reg signed [39 - 1 : 0] VAR14;
assign VAR10 = VAR14;
assign VAR15 = ({1'b0, VAR9}) * VAR6;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3b/sky130_fd_sc_hs__and3b.behavioral.v | 1,882 | module MODULE1 (
VAR13 ,
VAR5 ,
VAR2 ,
VAR3 ,
VAR10,
VAR1
);
output VAR13 ;
input VAR5 ;
input VAR2 ;
input VAR3 ;
input VAR10;
input VAR1;
wire VAR7 ;
wire VAR6 ;
wire VAR14;
not VAR11 (VAR7 , VAR5 );
and VAR12 (VAR6 , VAR3, VAR7, VAR2 );
VAR4 VAR9 (VAR14, VAR6, VAR10, VAR1);
buf VAR8 (VAR13 , VAR14 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi_4.v | 2,352 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR2 ,
VAR9 ,
VAR3 ,
VAR6,
VAR11,
VAR5 ,
VAR8
);
output VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR9 ;
input VAR3 ;
input VAR6;
input VAR11;
input VAR5 ;
input VAR8 ;
VAR10 VAR1 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_2.v | 2,361 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR11 ,
VAR1 ,
VAR2 ,
VAR3,
VAR7,
VAR6 ,
VAR8
);
output VAR5 ;
input VAR4 ;
input VAR11 ;
input VAR1 ;
input VAR2 ;
input VAR3;
input VAR7;
input VAR6 ;
input VAR8 ;
VAR10 VAR9 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR... | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/DecOp4_XE_0.v | 15,142 | module MODULE1(
VAR74,
VAR53,
VAR68,
VAR47,
VAR20,
VAR82
);
input[31:0] VAR74;
output[6:0] VAR53;
output[6:0] VAR68;
output[6:0] VAR47;
output[31:0] VAR20;
output[7:0] VAR82;
reg[6:0] VAR63;
reg[6:0] VAR85;
reg[6:0] VAR153; reg[31:0] VAR51; reg[7:0] VAR93;
assign VAR53 = VAR63;
assign VAR68 = VAR85;
assign VAR47 = VAR1... | mit |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_i2c.v | 18,555 | module MODULE1 (
VAR79, VAR33, VAR64, VAR39, VAR66,
VAR30, VAR25, VAR62, VAR69, VAR83, VAR28, VAR56, VAR54, VAR48, VAR75, VAR11, VAR16 );
output [5:0] VAR79; output [15:0] VAR33; output VAR64; output VAR39; output VAR66;
input VAR30; input [15:0] VAR25; input [6:0] VAR62; input [6:0] VAR69; input VAR83; input VAR28; in... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o_2.v | 2,469 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR1 ,
VAR12 ,
VAR10,
VAR2,
VAR11 ,
VAR6
);
output VAR9 ;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR12 ;
input VAR10;
input VAR2;
input VAR11 ;
input VAR6 ;
VAR8 VAR7 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR10(... | apache-2.0 |
mistryalok/Zedboard | learning/training/Microsystem/les6/ip_repo/myip_1.0/hdl/myip_v1_0.v | 6,527 | module MODULE1 #
(
parameter integer VAR45 = 32,
parameter integer VAR53 = 4,
parameter integer VAR34 = 1,
parameter integer VAR38 = 32,
parameter integer VAR51 = 6,
parameter integer VAR114 = 0,
parameter integer VAR80 = 0,
parameter integer VAR93 = 0,
parameter integer VAR96 = 0,
parameter integer VAR18 = 0
)
(
input... | gpl-3.0 |
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