repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
lkesteloot/alice | alice4/fpga/Alice4-DE0/Vga_control.v | 4,357 | module MODULE1(
input [3:0] VAR16,
input [3:0] VAR1,
input [3:0] VAR19,
output [9:0] VAR18, output [9:0] VAR14, output [21:0] VAR28,
output VAR27,
output reg VAR15, output [3:0] VAR22,
output [3:0] VAR11,
output [3:0] VAR2,
output reg VAR24, output reg VAR20, output VAR17, output VAR30, input VAR9,
input VAR8
);
reg [1... | apache-2.0 |
domahony/ButtonCount | LED.v | 1,087 | module MODULE1 (input clk, input enable, input [3:0] VAR3, input [2:0] VAR4, output reg[7:0] VAR2, output reg[7:0] VAR1);
always @(posedge clk)
begin
if (enable)
begin
case (VAR4)
3'd0: begin VAR2 <= 8'b11111110; end
3'd1: begin VAR2 <= 8'b11111101; end
3'd2: begin VAR2 <= 8'b11111011; end
3'd3: begin VAR2 <= 8'b111101... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_1.behavioral.pp.v | 1,328 | module MODULE1( VAR7, VAR9, VAR3, VAR6, VAR5, VAR1 );
input VAR6, VAR3, VAR7;
inout VAR5, VAR1;
output VAR9;
VAR8 VAR2(.VAR7(VAR7),.VAR9(VAR9),.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1));
VAR8 VAR4(.VAR7(VAR7),.VAR9(VAR9),.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp_clkgn.v | 34,724 | module MODULE1(
VAR40, VAR7, VAR12,
VAR104, VAR44, VAR80,
VAR5, VAR51, VAR156,
VAR143, VAR151, VAR178, VAR96,
VAR160, VAR165, VAR19, VAR8,
VAR197, VAR112, VAR182, VAR168,
VAR53, VAR174, VAR170, VAR64,
VAR127, VAR181, VAR74, VAR27, VAR124,
VAR217, VAR154, VAR21, VAR175,
VAR162, VAR71, VAR38, VAR67,
VAR183, VAR173, VAR97... | gpl-2.0 |
monotone-RK/FACE | MCSoC-15/16-way_4-parallel/src/vivado_ip_dram/phy/mig_7series_v2_3_poc_top.v | 13,638 | module MODULE1 #
(parameter VAR11 = 10,
parameter VAR57 = 95,
parameter VAR30 = "VAR39",
parameter VAR45 = 100,
parameter VAR41 = 0,
parameter VAR12 = 0,
parameter VAR6 = 8,
parameter VAR44 = 128,
parameter VAR43 = 7,
parameter VAR21 =112)
(
VAR5, VAR15, VAR46, VAR18, VAR49,
VAR51, VAR40, VAR34,
VAR38, rst, VAR13, VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufbuf/sky130_fd_sc_hd__bufbuf.behavioral.v | 1,341 | module MODULE1 (
VAR7,
VAR4
);
output VAR7;
input VAR4;
supply1 VAR1;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR6 ;
wire VAR2;
buf VAR5 (VAR2, VAR4 );
buf VAR9 (VAR7 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xor2/sky130_fd_sc_hvl__xor2.behavioral.v | 1,385 | module MODULE1 (
VAR3,
VAR4,
VAR10
);
output VAR3;
input VAR4;
input VAR10;
supply1 VAR8;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR6 ;
wire VAR7;
xor VAR2 (VAR7, VAR10, VAR4 );
buf VAR1 (VAR3 , VAR7 );
endmodule | apache-2.0 |
jotego/jt51 | hdl/jt51_exprom.v | 3,336 | module MODULE1
(
input [4:0] addr,
input clk,
input VAR3,
output reg [44:0] VAR2
);
reg [44:0] VAR1[31:0];
begin | gpl-3.0 |
LSaldyt/qnp | output/vs/opt_var25_multi.v | 44,263 | module MODULE1(VAR5, VAR13, VAR22, VAR17, VAR6, VAR3, VAR18, VAR20, VAR15, VAR23, VAR10, VAR25, VAR24, VAR9, VAR7, VAR1, VAR8, VAR2, VAR14, VAR4, VAR19, VAR21, VAR11, VAR16, VAR12, valid);
wire 0000;
wire 0001;
wire 0002;
wire 0003;
wire 0004;
wire 0005;
wire 0006;
wire 0007;
wire 0008;
wire 0009;
wire 0010;
wire 0011;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha_4.v | 2,184 | module MODULE2 (
VAR10,
VAR2 ,
VAR8 ,
VAR3 ,
VAR1,
VAR6,
VAR7 ,
VAR9
);
output VAR10;
output VAR2 ;
input VAR8 ;
input VAR3 ;
input VAR1;
input VAR6;
input VAR7 ;
input VAR9 ;
VAR5 VAR4 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE2... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.functional.v | 1,778 | module MODULE1( VAR21, VAR14, VAR1, VAR7, VAR18 );
input VAR18, VAR7, VAR14, VAR21;
output VAR1;
wire VAR12;
not VAR16( VAR12, VAR18 );
wire VAR8;
not VAR13( VAR8, VAR14 );
wire VAR9;
and VAR3( VAR9, VAR12, VAR8 );
wire VAR11;
not VAR15( VAR11, VAR21 );
wire VAR2;
and VAR6( VAR2, VAR12, VAR11 );
wire VAR20;
not VAR5( V... | apache-2.0 |
mlarouche/sd2snes | verilog/sd2snes/main.v | 21,457 | module MODULE1(
input VAR150,
input [23:0] VAR72,
input VAR122,
input VAR157,
input VAR222,
inout [7:0] VAR67,
input VAR288,
input VAR248,
output VAR280,
output VAR31,
output VAR139,
input VAR51,
input [7:0] VAR112,
input VAR334,
input VAR168,
inout [15:0] VAR213,
output [22:0] VAR255,
output VAR57,
output VAR239,
outp... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat_32.v | 6,884 | module MODULE1(
enable,
VAR33,
VAR9,
VAR23,
VAR19,
VAR10,
VAR7,
VAR39,
VAR5,
VAR24,
VAR11,
VAR13,
VAR35,
VAR29,
VAR38,
VAR22,
VAR32,
VAR17,
VAR8,
VAR30,
VAR31,
VAR34,
VAR16,
VAR21,
VAR3,
VAR36,
VAR4,
VAR1,
VAR28,
VAR14,
VAR20,
VAR12,
VAR2,
VAR26,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7,
VAR27,
VAR25,
o10,
o11,
o12,
o13,
o14,
o1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a.behavioral.pp.v | 2,074 | module MODULE1 (
VAR1 ,
VAR14 ,
VAR13 ,
VAR15 ,
VAR10 ,
VAR16 ,
VAR18,
VAR11,
VAR4 ,
VAR6
);
output VAR1 ;
input VAR14 ;
input VAR13 ;
input VAR15 ;
input VAR10 ;
input VAR16 ;
input VAR18;
input VAR11;
input VAR4 ;
input VAR6 ;
wire VAR8 ;
wire VAR3 ;
wire VAR17;
or VAR7 (VAR8 , VAR13, VAR14 );
and VAR9 (VAR3 , VAR15,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b_4.v | 2,270 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR3 ,
VAR9 ,
VAR6,
VAR7,
VAR4 ,
VAR5
);
output VAR10 ;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR6;
input VAR7;
input VAR4 ;
input VAR5 ;
VAR8 VAR1 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_frame_gen.v | 4,745 | module MODULE1
(
VAR8,
VAR4,
VAR1,
VAR7,
VAR6,
VAR3
);
output [0:63] VAR8;
output VAR4;
input VAR1;
input VAR7;
input VAR6;
input VAR3;
reg VAR4;
reg [0:15] VAR5;
wire VAR9;
assign VAR9 = VAR6 || !VAR3;
always @(posedge VAR7)
if(VAR9)
begin
VAR5 <= VAR2 16'hABCD; VAR4 <= VAR2 1'b1;
end
else if(!VAR1)
begin
VAR5 <= VAR2... | gpl-3.0 |
bqlabs/toolchain-icestorm | build-data/yosys/share/ice40/brams_map.v | 7,980 | module \VAR11 (
output [15:0] VAR20,
input VAR13, VAR3, VAR18,
input [10:0] VAR30,
input VAR4, VAR23, VAR50,
input [10:0] VAR7,
input [15:0] VAR12, VAR27
);
parameter integer VAR29 = 0;
parameter integer VAR59 = 0;
parameter [0:0] VAR22 = 0;
parameter [0:0] VAR16 = 0;
parameter [255:0] VAR58 = 256'h00000000000000000000... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_binari_sao_offset.v | 12,881 | module MODULE1(
VAR40 ,
VAR41 ,
VAR43 ,
VAR6 ,
VAR31 ,
VAR28 ,
VAR19 ,
VAR18 ,
VAR2 ,
VAR44 ,
VAR29
);
input [19:0] VAR40 ;
input [ 1:0] VAR41 ;
input VAR43 ;
output [10:0] VAR6 ;
output [10:0] VAR31 ;
output [10:0] VAR28 ;
output [10:0] VAR19 ;
output [10:0] VAR18 ;
output [10:0] VAR2 ;
output [10:0] VAR44 ;
output [1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.pp.blackbox.v | 1,547 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR7,
VAR3 ,
VAR4 ,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR5 ;
input VAR7;
input VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o31ai/sky130_fd_sc_hdll__o31ai_1.v | 2,351 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR10 ,
VAR6,
VAR5,
VAR8 ,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR10 ;
input VAR6;
input VAR5;
input VAR8 ;
input VAR4 ;
VAR7 VAR11 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/db/ip/nios_system/submodules/nios_system_sram_data.v | 3,644 | module MODULE1 (
address,
VAR9,
clk,
VAR11,
VAR5,
VAR3,
VAR4,
VAR6
)
;
inout [ 15: 0] VAR4;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR11;
input VAR5;
input [ 31: 0] VAR3;
wire [ 15: 0] VAR4;
wire VAR10;
reg [ 15: 0] VAR7;
wire [ 15: 0] VAR2;
reg [ 15: 0] VAR12;
wire [ 15: 0] VAR1;
reg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4b/sky130_fd_sc_hs__or4b_1.v | 2,164 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR4 ,
VAR6 ,
VAR9 ,
VAR2,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR9 ;
input VAR2;
input VAR5;
VAR3 VAR1 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR8 ,
VAR7 ,
VAR4 ,
VAR6 ,
VAR9... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_8.behavioral.v | 1,101 | module MODULE1( VAR4, VAR1 );
input VAR4;
output VAR1;
VAR2 VAR3(.VAR4(VAR4),.VAR1(VAR1));
VAR2 VAR5(.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
kielfriedt/ece472 | lab5/control_pipeline.v | 2,831 | module MODULE1(VAR13, VAR15, VAR4, VAR1, VAR10, VAR7, VAR14, VAR9, VAR6, VAR8);
input [5:0] VAR13;
output VAR15, VAR4, VAR1, VAR10, VAR7, VAR14, VAR9, VAR8;
output [1:0] VAR6;
reg VAR15, VAR4, VAR1, VAR10, VAR7, VAR14, VAR9, VAR8;
reg [1:0] VAR6;
parameter VAR2 = 6'd0;
parameter VAR3 = 6'd35;
parameter VAR12 = 6'd43;
p... | gpl-3.0 |
AbhishekShah212/School_Projects | ELEN232/pset3/Problem1.v | 1,128 | module MODULE1(
input VAR4,
input VAR2,
input VAR5,
input VAR3,
output reg VAR6,
output reg VAR1
);
always @ (VAR4 or VAR2 or VAR5 or VAR3)
begin
if (!((VAR4 & VAR5) ^ (VAR2 & VAR3)) == 1) VAR6 = 1;
end
else if ((~VAR5) & (VAR2 | VAR3) & VAR5 ^ !( VAR2 & VAR3) == 1)
VAR6 = 1;
else
VAR6 = 0;
if ( !(VAR4 & ~VAR5) == 1 ) ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_pwrgood_pp_p/sky130_fd_sc_hdll__udp_pwrgood_pp_p.symbol.v | 1,293 | module MODULE1 (
input VAR1 ,
output VAR3,
input VAR2
);
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/old/hdl/elink-gold/synchronizer.v | 1,612 | module MODULE1 #(parameter VAR2=32) (
out,
in, clk, reset
);
input [VAR2-1:0] in;
input clk;
input reset;
output [VAR2-1:0] out;
reg [VAR2-1:0] VAR3;
reg [VAR2-1:0] VAR1;
reg [VAR2-1:0] out;
always @ (posedge clk or posedge reset)
if(reset)
begin
VAR3[VAR2-1:0] <= {(VAR2){1'b0}};
VAR1[VAR2-1:0] <= {(VAR2){1'b0}};
out[V... | gpl-3.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_LCD/picoblze/kcuart_rx.v | 17,411 | module MODULE1
(VAR31,
VAR66,
VAR12,
VAR28,
clk);
input VAR31;
output [7:0] VAR66;
output VAR12;
input VAR28;
input clk;
wire VAR8 ;
wire VAR50 ;
wire [7:0] VAR81 ;
wire [7:0] VAR13 ;
wire VAR4 ;
wire VAR77 ;
wire VAR44 ;
wire VAR32 ;
wire VAR35 ;
wire VAR73 ;
wire VAR76 ;
wire VAR11 ;
wire [8:0] VAR14 ;
wire [8:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.functional.v | 2,185 | module MODULE1 (
VAR11 ,
VAR1 ,
VAR7 ,
VAR12 ,
VAR3 ,
VAR10 ,
VAR16 ,
VAR17
);
input VAR11 ;
input VAR1 ;
output VAR7 ;
input VAR12 ;
input VAR3 ;
input VAR10 ;
input VAR16 ;
input VAR17;
wire VAR8 ;
wire VAR6 ;
wire VAR19 ;
wire VAR18;
not VAR9 (VAR6 , VAR17 );
not VAR2 (VAR19 , VAR12 );
VAR4 VAR13 (VAR18, VAR3, VAR10... | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/gpio/gpio_sbus.v | 1,564 | module MODULE1 #(
parameter VAR6 = 16'h0000,
parameter VAR7 = 16'h0000,
parameter VAR22 = 16,
parameter VAR2 = 8,
parameter VAR15 = 0,
parameter VAR11 = 0
) (
input wire VAR8,
input wire VAR10,
input wire [VAR22-1:0] VAR12,
input wire [7:0] VAR21,
output wire [7:0] VAR5,
input wire VAR14,
input wire VAR9,
inout wire [V... | bsd-3-clause |
sundw2014/sdr-transmiter | software/AD9708_FPGA/prnf5ccc_bb.v | 4,914 | module MODULE1 (
address,
VAR1,
VAR2);
input [15:0] address;
input VAR1;
output [7:0] VAR2;
tri1 VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp.pp.blackbox.v | 1,278 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR6 ,
VAR4,
VAR3 ,
VAR2
);
input VAR5 ;
input VAR1 ;
output VAR6 ;
input VAR4;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_gtp_pipe_rate.v | 16,237 | module MODULE1 #
(
parameter VAR13 = "VAR51", parameter VAR38 = 4'd15
)
(
input VAR46,
input VAR17,
input [ 1:0] VAR53,
input VAR54,
input VAR47,
input VAR31,
input VAR20,
input VAR37,
input VAR11,
output VAR21,
output VAR49,
output VAR5,
output [ 2:0] VAR27,
output VAR3,
output VAR22,
output VAR12,
output [ 4:0] VAR14... | gpl-3.0 |
Xilinx/PYNQ | boards/ip/boolean_generator_1.1/src/boolean_fsm.v | 1,784 | module MODULE1(
input clk,
input VAR4,
input [(2**VAR8)-1:0] VAR3,
output reg VAR6,
output reg VAR2,
output reg VAR7
);
parameter VAR8 = 5;
reg [(2**VAR8)-1:0] VAR5;
reg [VAR8-1:0] VAR9 = {VAR8{1'b0}};
wire VAR1;
assign VAR1 = (VAR9 == (2**VAR8-1)) ? 1'b1 : 1'b0;
always @(posedge clk)
VAR7 <= VAR1;
always @(posedge clk... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtn/sky130_fd_sc_ms__dfrtn.functional.pp.v | 2,024 | module MODULE1 (
VAR10 ,
VAR15 ,
VAR6 ,
VAR1,
VAR3 ,
VAR9 ,
VAR13 ,
VAR4
);
output VAR10 ;
input VAR15 ;
input VAR6 ;
input VAR1;
input VAR3 ;
input VAR9 ;
input VAR13 ;
input VAR4 ;
wire VAR7 ;
wire VAR16 ;
wire VAR5;
not VAR14 (VAR16 , VAR1 );
not VAR8 (VAR5, VAR15 );
VAR12 VAR2 VAR11 (VAR7 , VAR6, VAR5, VAR16, , VAR... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_nonsynth_cache_axe_tracer.v | 1,514 | module MODULE1
import VAR23::*;
, parameter VAR18(VAR12)
, parameter VAR18(VAR5)
, parameter VAR24=VAR19(VAR12,VAR9,VAR5)
)
(
input VAR2
, input VAR21
, input VAR20
, input VAR17 VAR4
, input [VAR12-1:0] VAR11
, input [VAR24-1:0] VAR22
, input [VAR9-1:0] VAR25
);
VAR6 VAR15;
assign VAR15 = VAR22;
localparam VAR8 = "VAR... | bsd-3-clause |
ashwith/hdlroot | lib/buffers/circular_buff.v | 2,607 | module MODULE1(
input VAR5,
input VAR1,
input VAR10,
input [VAR14 - 1 : 0] VAR17,
input VAR12,
output [VAR14 - 1 : 0] VAR18,
output VAR8,
output VAR6
);
parameter VAR14 = 8;
parameter VAR19 = 8;
parameter VAR16 = 3;
reg [VAR16 : 0] VAR11;
reg [VAR16 - 1 : 0] VAR15;
reg [VAR16 - 1 : 0] VAR3;
reg VAR7;
memory VAR4(
.VAR5... | gpl-3.0 |
ultraembedded/riscv | top_cache_axi/src_v/dcache_core_tag_ram.v | 3,019 | module MODULE1
(
input VAR10
,input VAR2
,input [ 7:0] VAR9
,input VAR11
,input VAR7
,input [ 7:0] VAR4
,input [ 20:0] VAR1
,input VAR6
,output [ 20:0] VAR5
);
reg [20:0] VAR8 [255:0] ;
reg [20:0] VAR3;
always @ (posedge VAR11)
begin
if (VAR6)
VAR8[VAR4] = VAR1;
VAR3 = VAR8[VAR9];
end
assign VAR5 = VAR3;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1.v | 2,339 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR4 ,
VAR3 ,
VAR1,
VAR2 ,
VAR6
);
output VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR3 ;
input VAR1;
input VAR2 ;
input VAR6 ;
VAR5 VAR8 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7,
VAR9
);
output VAR7;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.pp.blackbox.v | 1,545 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR3,
VAR1 ,
VAR2 ,
VAR4
);
output VAR5 ;
input VAR6 ;
input VAR3;
input VAR1 ;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
gabesk/xmascard | hdl/serial.v | 9,946 | module MODULE3(
input VAR20,
input MODULE6,
output MODULE4,
output [7:0] VAR28,
output [71:0] VAR33,
output VAR29,
output [1:0] VAR18, output [71:0] VAR35
);
wire VAR6, VAR1, VAR12, VAR3;
wire [7:0] VAR15;
wire [7:0] VAR25;
wire VAR39;
MODULE1 MODULE2(VAR20, VAR39);
MODULE4 MODULE3(.clk(VAR20),
.VAR39(VAR39),
.VAR8(VAR... | gpl-3.0 |
hanyazou/vivado-ws | playpen/null_filter/null_filter.srcs/sources_1/new/null_filter.v | 1,120 | module MODULE1(
VAR6,
VAR4,
VAR9,
VAR7,
VAR10,
VAR5,
VAR3,
VAR8,
VAR1,
VAR2
);
input [23:0] VAR6;
input VAR4;
input VAR9;
input VAR7;
input VAR10;
output [23:0] VAR5;
output VAR3;
output VAR8;
output VAR1;
output VAR2;
assign VAR5 = VAR6;
assign VAR8 = VAR9;
assign VAR3 = VAR4;
assign VAR1 = VAR7;
assign VAR2 = VAR10;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv.functional.v | 1,259 | module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
wire VAR2;
not VAR1 (VAR2, VAR3 );
buf VAR4 (VAR5 , VAR2 );
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/NTNU FPU/low-cost-fpu-src/fpu_control_unit.v | 36,156 | module MODULE1(VAR127, VAR161, VAR118, VAR146,
VAR81, VAR108, VAR156, VAR49, VAR106, VAR184, VAR186,
VAR84, VAR137, VAR123,
VAR1, VAR31,
VAR28, VAR37,
VAR68, VAR113, VAR145,
VAR64,
VAR125, VAR175, VAR100, VAR40,
VAR132, VAR70,
VAR102, VAR140, VAR177, VAR141,
VAR147, VAR152, VAR12,
VAR5,
VAR67,
VAR119,
VAR11, VAR179, VA... | gpl-3.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/altera_avalon_st_jtag_interface.v | 7,788 | module MODULE1 #(
parameter VAR61 = 0, parameter VAR49 = 0,
parameter VAR44 = 0,
parameter VAR25 = -1,
parameter VAR31 = 0,
parameter VAR22 = 0, parameter VAR66 = 50000 ) (
input wire VAR53,
input wire VAR10,
input wire VAR37,
output wire VAR63,
input wire VAR48,
input wire VAR33,
input wire VAR14,
input wire VAR42,
in... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211ai/sky130_fd_sc_hs__o211ai_1.v | 2,234 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR5 ,
VAR3 ,
VAR8 ,
VAR1,
VAR7
);
output VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR3 ;
input VAR8 ;
input VAR1;
input VAR7;
VAR9 VAR6 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR2 ,
VAR4,
VAR5,
VAR3,
VAR8
);... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_intp2_8.v | 5,201 | module MODULE1 (
clk,
VAR26,
VAR2,
VAR18,
VAR30,
VAR31,
VAR3,
VAR15,
VAR23,
VAR5);
input clk;
input [15:0] VAR26;
output [15:0] VAR2;
output [15:0] VAR18;
output [15:0] VAR30;
output [15:0] VAR31;
output [15:0] VAR3;
output [15:0] VAR15;
output [15:0] VAR23;
output [15:0] VAR5;
reg [15:0] VAR4 = 'd0;
reg [15:0] VAR17 =... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v | 18,247 | module MODULE1 (
input wire VAR87, input wire VAR88, input wire [29:0] VAR43, output wire VAR55, input wire [4:0] VAR27, input wire [31:0] VAR40, input wire VAR77, output wire [255:0] VAR35, output wire VAR76, input wire VAR6, input wire [255:0] VAR56, input wire VAR10, output wire [24:0] VAR45, output wire VAR31, outp... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_port_lookup/cam_router/src/dest_ip_filter.v | 8,854 | module MODULE1
parameter VAR50 = VAR6,
parameter VAR26 = VAR17(VAR50)
)
( input [VAR84-1:0] VAR63,
output VAR20,
output VAR54,
input VAR2,
input VAR57,
input VAR67,
input [VAR26-1:0] VAR7, input VAR13, output [31:0] VAR79, output VAR37,
input [VAR26-1:0] VAR68,
input VAR83,
input [31:0] VAR66, output VAR51,
input reset... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1.pp.blackbox.v | 1,344 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR2,
VAR6,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp.blackbox.v | 1,327 | module MODULE1 (
VAR3,
VAR4 ,
VAR6 ,
VAR2
);
input VAR3;
input VAR4 ;
input VAR6 ;
output VAR2 ;
supply1 VAR5;
supply0 VAR1;
endmodule | apache-2.0 |
klaNath/synth1 | synth1.v | 2,674 | module MODULE1(
input wire clk,
input wire VAR29,
input wire VAR6,
input wire VAR4,
input wire VAR8,
output wire VAR43,
output wire VAR15,
input wire [3:0] VAR9);
reg VAR40, VAR12;
wire VAR52, VAR33, VAR23, VAR17, VAR5, VAR51, VAR16, VAR46;
wire [20:0] VAR42;
wire [15:0] VAR50;
wire [31:0] VAR36, VAR14;
wire [7:0] VAR3... | lgpl-3.0 |
efabless/openlane | designs/xtea/src/xtea.v | 8,736 | module MODULE1(VAR30, reset, VAR34, VAR10, VAR13, VAR1, VAR11, VAR29, VAR33);
parameter VAR9 = 8'd0, VAR16 = 8'd1, VAR26 = 8'd2, VAR6 = 8'd3, VAR5 = 8'd4, VAR8 = 8'd5, VAR27 = 8'd6, VAR22 = 8'd7, VAR19 = 8'd8, VAR31 = 8'd9, VAR18 = 8'd10,
VAR4 = 8'd11, VAR35 = 8'd12, VAR20 = 8'd13, VAR7 = 8'd14, VAR17 = 8'd15, VAR21 = ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfstp/sky130_fd_sc_hd__sdfstp.pp.blackbox.v | 1,434 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3 ,
VAR10 ,
VAR9 ,
VAR8,
VAR1 ,
VAR5 ,
VAR7 ,
VAR6
);
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR10 ;
input VAR9 ;
input VAR8;
input VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR6 ;
endmodule | apache-2.0 |
asicguy/gplgpu | stim/fast_mem_tasks.v | 19,157 | module MODULE1;
task VAR59;
input [31:0] VAR13; input [31:0] VAR35;
input [31:0] VAR25;
reg [31:0] VAR28;
begin
for (VAR28 = VAR13; VAR28 < (VAR13+VAR35); VAR28 = VAR28 + 1) begin
VAR62.VAR48.VAR42[{VAR28, 2'b00}] = VAR25[7:0];
VAR62.VAR48.VAR42[{VAR28, 2'b01}] = VAR25[15:8];
VAR62.VAR48.VAR42[{VAR28, 2'b10}] = VAR25[2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai.blackbox.v | 1,381 | module MODULE1 (
VAR10 ,
VAR1,
VAR6,
VAR4,
VAR3,
VAR2
);
output VAR10 ;
input VAR1;
input VAR6;
input VAR4;
input VAR3;
input VAR2;
supply1 VAR8;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
boylansr/Prop_Muse | P1V/P8X32A_Emulation/P8X32A_BeMicroCV/cog.v | 13,989 | module MODULE1
(
input VAR89,
input VAR32, input VAR40,
input VAR22,
input VAR36, input [27:0] VAR60,
input VAR23,
input VAR27, output VAR103,
output VAR67,
output VAR73,
output [1:0] VAR42,
output [15:0] VAR91,
output [31:0] VAR66,
input [31:0] VAR88,
input VAR87,
input VAR55,
input [31:0] VAR12,
input [7:0] VAR54, ou... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/4-way/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_bank_mach.v | 31,504 | module MODULE1 #
(
parameter VAR89 = 100,
parameter VAR140 = "VAR75",
parameter VAR41 = "1T",
parameter VAR63 = 3,
parameter VAR10 = 2,
parameter VAR95 = "8",
parameter VAR147 = 12,
parameter VAR194 = 4,
parameter VAR139 = 5,
parameter VAR19 = 5,
parameter VAR83 = 8,
parameter VAR176 = "VAR90",
parameter VAR154 = "VAR7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb.pp.symbol.v | 1,336 | module MODULE1 (
input VAR3 ,
input VAR5 ,
input VAR7 ,
input VAR4 ,
output VAR6 ,
input VAR8 ,
input VAR2,
input VAR9,
input VAR1
);
endmodule | apache-2.0 |
thurday/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX_OneDataChannel.v | 4,069 | module MODULE1(
input VAR9,
input VAR5,
input [7:0] VAR7,
output reg VAR6,
output reg [7:0] VAR1
);
reg [1:0] VAR10;
localparam VAR3 = 2'b00;
localparam VAR4 = 2'b01;
localparam VAR8 = 2'b10;
reg [7:0] VAR2;
reg [4:0] counter;
always@(posedge VAR9) VAR2[7:0] <= VAR7[7:0];
always@(posedge VAR9) begin
if (VAR5) begin
cou... | bsd-2-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_ddr_downstream.v | 8,589 | module MODULE1
,parameter VAR31 = 8
,parameter VAR30 = 1
,parameter VAR16 = 6
,parameter VAR18 = 3
,parameter VAR7 = 0
,parameter VAR2 = 0
,parameter VAR13 = 0
,parameter VAR3 = 0
,parameter VAR8 = 0
,localparam VAR28 = VAR31*2 + VAR7
,localparam VAR21 = VAR51/(VAR28*VAR30)
,localparam VAR10 = VAR31+1
)
( input VAR5
,i... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbn/sky130_fd_sc_ls__dfbbn.behavioral.v | 2,779 | module MODULE1 (
VAR19 ,
VAR14 ,
VAR26 ,
VAR3 ,
VAR27 ,
VAR23
);
output VAR19 ;
output VAR14 ;
input VAR26 ;
input VAR3 ;
input VAR27 ;
input VAR23;
supply1 VAR2;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR17 ;
wire VAR18 ;
wire VAR20 ;
wire VAR4 ;
wire VAR1 ;
wire VAR21 ;
wire VAR15;
wire VAR12 ;
reg VAR13 ;
wire VAR11 ;... | apache-2.0 |
julioamerico/prj_crc_ip | src/SoC/hdl/crc_datapath.v | 6,525 | module MODULE1
(
output [31:0] VAR48,
output [ 1:0] VAR4,
output [ 7:0] VAR21,
output [31:0] VAR20,
output [31:0] VAR23,
input [31:0] VAR38, input [ 1:0] VAR29, input VAR72,
input VAR59,
input VAR57,
input VAR41,
input VAR5,
input VAR65,
input VAR71,
input VAR27,
input VAR25,
input VAR61,
input [1:0] VAR22,
input [1:0]... | gpl-3.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_iic_0_0/system_axi_iic_0_0_stub.v | 2,429 | module MODULE1(VAR1, VAR15, VAR9,
VAR11, VAR4, VAR7, VAR25, VAR24, VAR10,
VAR14, VAR6, VAR26, VAR22, VAR18, VAR16,
VAR17, VAR3, VAR27, VAR13, VAR2, VAR23, VAR19, VAR21, VAR12,
VAR20, VAR5, VAR8)
;
input VAR1;
input VAR15;
output VAR9;
input [8:0]VAR11;
input VAR4;
output VAR7;
input [31:0]VAR25;
input [3:0]VAR24;
input... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/ip_top/infrastructure.v | 13,844 | module MODULE1 #
(
parameter VAR18 = 100, parameter VAR8 = 3000, parameter VAR28 = 2, parameter VAR29 = "VAR6", parameter VAR30 = "VAR25", parameter VAR1 = 2, parameter VAR21 = 1, parameter VAR3 = 2, parameter VAR15 = 1
)
(
input VAR23, input VAR17, input VAR10, output VAR26, output clk, output VAR11, output VAR27, inp... | lgpl-3.0 |
moizumi99/brainf__k_CPU | hdl/brainfuck.v | 14,136 | module MODULE1
(
input clk, rst, input VAR41, output [VAR47-1:0] VAR55,
output VAR21,
input [31:0] VAR3,
input VAR46, output reg [VAR69-1:0] VAR65,
output reg [VAR40-1:0] VAR9,
output reg VAR88,
output reg VAR74,
input VAR93, input [VAR40-1:0] VAR75,
output reg VAR61,
output reg VAR8,
input VAR1 );
localparam VAR54 = 8... | unlicense |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/mpuc707.v | 5,052 | module MODULE1 ( VAR20,VAR13 ,VAR21, VAR1,VAR18,VAR17 ,VAR10 ,VAR19 );
input VAR20 ;
wire VAR20 ;
input VAR13 ; wire VAR13 ;
input VAR21; input VAR1 ; wire VAR1 ;
input [VAR5-1:0] VAR18 ;
wire signed [VAR5-1:0] VAR18 ;
input [VAR5-1:0] VAR17 ;
wire signed [VAR5-1:0] VAR17 ;
output [VAR5-1:0] VAR10 ;
reg [VAR5-1:0] VAR1... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/config_switch32.v | 11,163 | module MODULE1 (
VAR12,
VAR42,
VAR22,
VAR30,
VAR1,
VAR37,
VAR33,
VAR7,
VAR4,
VAR38);
parameter VAR47 = 10;
parameter VAR43 = 20;
parameter VAR39 = "VAR9";
input VAR12;
input VAR42;
input VAR22;
input [VAR43-1:0] VAR30;
input [VAR47-1:0] VAR1;
input [VAR47-1:0] VAR37;
input [VAR47-1:0] VAR33;
input VAR7;
output reg [VAR... | mit |
Digilent/vivado-library | ip/MotorFeedback_1.0/hdl/posCounter.v | 2,813 | module MODULE1 (
input wire clk,
output reg [15:0] VAR3, output reg [15:0] VAR2, input wire VAR6, input wire [1:0] VAR1, input wire VAR4, input wire [15:0] VAR5 );
reg VAR7; | mit |
omicronns/studies-sys-rek | de1-soc-proc/src/de1_soc_proc.v | 2,588 | module MODULE1(
input VAR6,
input VAR1,
input VAR11,
input VAR19,
inout [35:0] VAR18,
output [6:0] VAR5,
output [6:0] VAR12,
output [6:0] VAR20,
output [6:0] VAR13,
output [6:0] VAR16,
output [6:0] VAR3,
input [3:0] VAR4,
output [9:0] VAR9,
input [9:0] VAR17
);
reg VAR10 = 1;
integer VAR14 = 0;
assign VAR9[8] = VAR10;
... | mit |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/soc_system_led_pio.v | 2,182 | module MODULE1 (
address,
VAR5,
clk,
VAR8,
VAR2,
VAR9,
VAR4,
VAR7
)
;
output [ 9: 0] VAR4;
output [ 31: 0] VAR7;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR8;
input VAR2;
input [ 31: 0] VAR9;
wire VAR6;
reg [ 9: 0] VAR1;
wire [ 9: 0] VAR4;
wire [ 9: 0] VAR3;
wire [ 31: 0] VAR7;
assign VAR6 = 1;
assign VAR3 ... | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p.functional.pp.v | 1,742 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR6,
VAR10 ,
VAR2 ,
VAR11 ,
VAR8
);
output VAR9 ;
input VAR4 ;
input VAR6;
input VAR10 ;
input VAR2 ;
input VAR11 ;
input VAR8 ;
wire VAR5;
or VAR7 (VAR5, VAR4, VAR6 );
VAR3 VAR1 (VAR9 , VAR5, VAR10, VAR2);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v | 2,384 | module MODULE1 #(parameter VAR26(VAR6 )
,parameter VAR26(VAR7 )
,parameter VAR24 = VAR20(VAR6)
,parameter VAR37 = VAR7>>3
)
(input VAR40
,input VAR16
,input VAR12
,input VAR35
,input [VAR24-1:0] VAR11
,input [VAR7-1:0] VAR36
,input [VAR37-1:0] VAR28
,output [VAR7-1:0] VAR41
);
if ((VAR6 == 1024) & (VAR7 == 32))
begin :... | bsd-3-clause |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_SRAM_SS_210930.v | 73,272 | module MODULE1 (VAR3, VAR11, VAR15, VAR8);
output VAR3;
input VAR11, VAR15, VAR8;
reg VAR4;
wire VAR2, VAR7;
wire VAR1, VAR10, VAR5;
wire VAR14;
not (VAR1, VAR2);
not (VAR5, VAR15);
VAR13 (VAR14, VAR7, VAR1, VAR5);
VAR9 (VAR10, VAR4, VAR7, VAR1, VAR5, VAR14);
buf (VAR3, VAR10);
wire VAR6, VAR16, VAR12;
and (VAR6, VAR11... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_1.v | 2,135 | module MODULE2 (
VAR1,
VAR4,
VAR7 ,
VAR3 ,
VAR8,
VAR5
);
output VAR1;
input VAR4;
input VAR7 ;
input VAR3 ;
input VAR8;
input VAR5;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR1,
VAR4,
VAR7 ,
VAR3
);
output VAR1;
input VAR4;
input VAR7 ;
inpu... | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/arrmul.v | 57,236 | module MODULE1 (VAR7,VAR12,VAR15,VAR6,VAR8);
output [0:127] VAR8;
input [0:127] VAR7;
input [0:127] VAR12;
input [0:1] VAR15;
input [0:4] VAR6;
integer VAR34;
integer VAR31;
reg [0:127] VAR8;
reg [0:127] VAR35;
reg [0:15] VAR2;
reg [0:15] VAR29;
reg [0:7] VAR25;
reg [0:15] VAR3;
reg [0:15] VAR5;
reg [0:15] VAR17;
reg [... | mit |
ychaim/FPGA-Litecoin-Miner | ICARUS-LX150/xilinx_pll.v | 3,017 | module MODULE1 # (parameter VAR39 = 25 )
(VAR18,
VAR53,
VAR57,
VAR41,
VAR51,
VAR29);
input VAR18;
output VAR53;
output VAR57;
output VAR41;
output VAR51;
output VAR29;
wire VAR7;
wire VAR40;
wire VAR33;
wire VAR35;
wire VAR31;
wire VAR49;
assign VAR49 = 0;
assign VAR53 = VAR40;
assign VAR57 = VAR7;
VAR5 VAR4 (.VAR3(VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtp/sky130_fd_sc_lp__dlrtp.functional.v | 1,701 | module MODULE1 (
VAR4 ,
VAR3,
VAR10 ,
VAR11
);
output VAR4 ;
input VAR3;
input VAR10 ;
input VAR11 ;
wire VAR8;
wire VAR2;
not VAR5 (VAR8 , VAR3 );
VAR1 VAR7 VAR6 (VAR2 , VAR10, VAR11, VAR8 );
buf VAR9 (VAR4 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b.behavioral.v | 1,536 | module MODULE1 (
VAR14 ,
VAR7,
VAR6 ,
VAR1 ,
VAR13
);
output VAR14 ;
input VAR7;
input VAR6 ;
input VAR1 ;
input VAR13 ;
supply1 VAR2;
supply0 VAR5;
supply1 VAR12 ;
supply0 VAR11 ;
wire VAR9 ;
wire VAR8;
not VAR4 (VAR9 , VAR7 );
nand VAR3 (VAR8, VAR13, VAR1, VAR6, VAR9);
buf VAR10 (VAR14 , VAR8 );
endmodule | apache-2.0 |
thinkoco/de1_soc_opencl | de10_nano_sharedonly_hdmi/ip/altsource_probe/hps_reset_bb.v | 3,139 | module MODULE1 (
VAR1,
VAR3,
VAR2);
input VAR1;
input VAR3;
output [2:0] VAR2;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.functional.pp.v | 1,410 | module MODULE1( VAR15, VAR11, VAR19, VAR20, VAR14, VAR6, VAR13, VAR9, VAR18 );
input VAR13, VAR6, VAR15, VAR19, VAR11, VAR14;
inout VAR9, VAR18;
output VAR20;
wire VAR10;
not VAR3( VAR10, VAR11 );
wire VAR21;
not VAR8( VAR21, VAR14 );
wire VAR22;
and VAR12( VAR22, VAR10, VAR21, VAR13 );
wire VAR1;
and VAR4( VAR1, VAR21... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.behavioral.v | 1,767 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR2
);
output VAR1 ;
input VAR11 ;
input VAR2;
supply1 VAR4 ;
supply0 VAR5 ;
supply1 VAR13;
supply1 VAR3 ;
supply0 VAR8 ;
wire VAR6 ;
wire VAR10;
not VAR9 (VAR6 , VAR2 );
and VAR12 (VAR10, VAR2, VAR11 );
buf VAR7 (VAR1 , VAR10 );
endmodule | apache-2.0 |
Sponk/mips86 | src/alu/ArithmeticLogicUnit.v | 1,782 | module MODULE1
(input wire [VAR5-1:0] VAR3,
input wire [VAR5-1:0] VAR2,
input wire [3:0] VAR16,
input wire clk,
input wire reset,
output wire [VAR5-1:0] out,
output wire VAR6
);
reg VAR4;
wire VAR13;
wire [VAR5-1:0] VAR10;
reg [VAR5-1:0] VAR12;
reg [VAR5-1:0] VAR8;
reg VAR7;
reg [VAR5-1:0] VAR15;
assign out = VAR15;
as... | gpl-3.0 |
DreamSourceLab/DSLogic-hdl | src/ipcore_dir/asyncfifo.v | 13,971 | module MODULE1(
VAR413,
VAR141,
VAR367,
VAR258,
din,
VAR323,
VAR51,
dout,
VAR269,
VAR202,
VAR296,
VAR264
);
input VAR413;
input VAR141;
input VAR367;
input VAR258;
input [15 : 0] din;
input VAR323;
input VAR51;
output [15 : 0] dout;
output VAR269;
output VAR202;
output VAR296;
output VAR264;
VAR84 #(
.VAR21(0),
.VAR403... | gpl-2.0 |
bluespec/Flute | builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkSoC_Map.v | 7,922 | module MODULE1(VAR22,
VAR8,
VAR18,
VAR15,
VAR19,
VAR28,
VAR21,
VAR5,
VAR12,
VAR20,
VAR9,
VAR25,
VAR1,
VAR13,
VAR2,
VAR16,
VAR11,
VAR10,
VAR29,
VAR26,
VAR24,
VAR27,
VAR6,
VAR23,
VAR3,
VAR4,
VAR14,
VAR17,
VAR7);
input VAR22;
input VAR8;
output [63 : 0] VAR18;
output [63 : 0] VAR15;
output [63 : 0] VAR19;
output [63 : 0] ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp_1.v | 2,703 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR4 ,
VAR9 ,
VAR5 ,
VAR12 ,
VAR6,
VAR13 ,
VAR1 ,
VAR2 ,
VAR3
);
output VAR7 ;
output VAR11 ;
input VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR12 ;
input VAR6;
input VAR13 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
VAR10 VAR8 (
.VAR7(VAR7),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR... | apache-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_if.v | 5,572 | module MODULE1(
clk, rst,
VAR15, VAR9, VAR5, VAR20, VAR17,
VAR13, VAR23, VAR18, VAR4,
VAR12, VAR22, VAR8, VAR2,
VAR16, VAR1, VAR19
);
input clk;
input rst;
input [31:0] VAR15;
input VAR9;
input VAR5;
input [31:0] VAR20;
input [3:0] VAR17;
input VAR13;
output [31:0] VAR23;
output [31:0] VAR18;
input VAR4;
output VAR12;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb.blackbox.v | 1,330 | module MODULE1 (
VAR5 ,
VAR4,
VAR7,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR4;
input VAR7;
input VAR1 ;
input VAR3 ;
supply1 VAR2;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_design_smp_hps_hps_io.v | 3,683 | module MODULE1 (
output wire [14:0] VAR5, output wire [2:0] VAR19, output wire VAR15, output wire VAR14, output wire VAR17, output wire VAR8, output wire VAR10, output wire VAR16, output wire VAR22, output wire VAR9, inout wire [31:0] VAR18, inout wire [3:0] VAR3, inout wire [3:0] VAR21, output wire VAR20, output wire ... | gpl-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/2-instruction_decode/instruction_decode.v | 7,419 | module MODULE1
parameter VAR75=32, parameter VAR54=5 )
(
input wire clk,
input wire reset,
input wire VAR11, input wire [VAR75-1:0] VAR66,
input wire VAR13,
input wire VAR108,
input wire [VAR75-1:0] VAR22,
input wire [VAR54-1:0] VAR31, input wire [VAR75-1:0] VAR105, input wire [VAR75-1:0] VAR81,
input wire [VAR75-1:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfstp/sky130_fd_sc_ms__sdfstp.functional.v | 1,938 | module MODULE1 (
VAR16 ,
VAR3 ,
VAR4 ,
VAR6 ,
VAR7 ,
VAR15
);
output VAR16 ;
input VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR15;
wire VAR11 ;
wire VAR5 ;
wire VAR12;
not VAR1 (VAR5 , VAR15 );
VAR14 VAR9 (VAR12, VAR4, VAR6, VAR7 );
VAR8 VAR13 VAR10 (VAR11 , VAR12, VAR3, VAR5);
buf VAR2 (VAR16 , VAR11 );
end... | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_led_pio.v | 2,194 | module MODULE1 (
address,
VAR9,
clk,
VAR7,
VAR2,
VAR1,
VAR8,
VAR4
)
;
output [ 9: 0] VAR8;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR7;
input VAR2;
input [ 31: 0] VAR1;
wire VAR6;
reg [ 9: 0] VAR5;
wire [ 9: 0] VAR8;
wire [ 9: 0] VAR3;
wire [ 31: 0] VAR4;
assign VAR6 = 1;
assign VAR3 ... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/meiko/ff_primitives.v | 5,688 | module MODULE7(VAR15, VAR14, clk);
output VAR15;
input VAR14, clk;
reg VAR15;
always @(posedge (clk)) begin
VAR15 <= VAR14;
end
endmodule
module MODULE2(VAR15, VAR14, clk, VAR12);
output VAR15;
input VAR14, clk, VAR12;
reg VAR15;
always @(posedge clk or posedge VAR12) begin
if (VAR12)
VAR15 <= 1'b0;
end
else
VAR15 <= V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2_4.v | 2,187 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR10,
VAR4,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR10;
input VAR4;
input VAR6 ;
input VAR1 ;
VAR2 VAR7 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_rf.v | 8,860 | module MODULE1(
clk, rst,
VAR44, VAR52, VAR25, VAR45, VAR63, VAR18, VAR51, VAR11,
VAR43, VAR31, VAR35, VAR26, VAR30, VAR46, VAR49,
VAR53, VAR17, VAR3, VAR14, VAR39, VAR4
);
parameter VAR9 = VAR5;
parameter VAR28 = VAR41;
input clk;
input rst;
input VAR44;
output VAR52;
input VAR25;
input VAR45;
input [VAR28-1:0] VAR63;... | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_ResetCatchAndSync_2.v | 2,269 | module MODULE1(
input VAR14,
input reset,
input VAR2,
output VAR1
);
wire VAR3;
wire VAR7;
wire [19:0] VAR13;
wire [19:0] VAR16;
wire VAR17;
wire [18:0] VAR8;
wire [19:0] VAR5;
wire VAR9;
wire VAR15;
VAR4 VAR10 (
.VAR14(VAR3),
.reset(VAR7),
.VAR12(VAR13),
.VAR6(VAR16),
.VAR11(VAR17)
);
assign VAR1 = VAR2 ? reset : VAR1... | apache-2.0 |
sergev/vak-opensource | hardware/basys3/buttons-and-leds/top.v | 1,313 | module MODULE1 (
input clk,
input VAR4, input VAR2,
input VAR3,
input VAR8,
input VAR10,
input [15:0] VAR6,
output reg [15:0] VAR5,
output reg [6:0] VAR11, output reg VAR1, output reg [3:0] VAR7 );
VAR9 VAR11 = 7'b1111111;
VAR9 VAR7 = 4'b0000;
VAR9 VAR1 = 0;
always @(VAR6) begin VAR5 <= VAR6;
end
always @(VAR4 or VAR2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b.symbol.v | 1,313 | module MODULE1 (
input VAR1,
input VAR6 ,
input VAR3 ,
output VAR5
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21bai/sky130_fd_sc_ls__o21bai.behavioral.pp.v | 2,174 | module MODULE1 (
VAR18 ,
VAR16 ,
VAR17 ,
VAR15,
VAR5,
VAR1,
VAR14 ,
VAR7
);
output VAR18 ;
input VAR16 ;
input VAR17 ;
input VAR15;
input VAR5;
input VAR1;
input VAR14 ;
input VAR7 ;
wire VAR6 ;
wire VAR13 ;
wire VAR9 ;
wire VAR10;
not VAR4 (VAR6 , VAR15 );
or VAR8 (VAR13 , VAR17, VAR16 );
nand VAR2 (VAR9 , VAR6, VAR13... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_pu_binari_mv.v | 18,209 | module MODULE1(
VAR32 ,
VAR33 ,
VAR54 ,
VAR7 ,
VAR2 ,
VAR35 ,
VAR58 ,
VAR29 ,
VAR27 ,
VAR38 ,
VAR17 ,
VAR30 ,
VAR47 ,
VAR21 ,
VAR39 ,
VAR20 ,
VAR61
);
input [2:0] VAR32 ;
input [2*VAR23-1:0] VAR33 ;
output [10:0] VAR54 ;
output [10:0] VAR7 ;
output [10:0] VAR2 ;
output [10:0] VAR35 ;
output [10:0] VAR58 ;
output [10:0]... | gpl-3.0 |
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