repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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fanatid/gost28147-89 | rtl/gost89_cfb.v | 2,722 | module MODULE2(
input clk,
input reset,
input VAR6,
input VAR13,
input [511:0] VAR5,
input [255:0] VAR4,
input [63:0] in,
output reg [63:0] out,
output reg VAR8
);
reg [63:0] VAR12;
reg [63:0] VAR2;
wire [63:0] VAR9;
wire VAR7, VAR1, VAR11;
assign VAR1 = !reset && VAR13;
assign VAR7 = VAR1;
VAR3
VAR10(clk, VAR7, VAR1, ... | bsd-3-clause |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_operandmuxes.v | 6,543 | module MODULE1(
clk, rst,
VAR7, VAR16, VAR8, VAR19, VAR13, VAR14,
VAR4, VAR6, VAR10, VAR17, VAR12, VAR9
);
parameter VAR15 = VAR1;
input clk;
input rst;
input VAR7;
input VAR16;
input [VAR15-1:0] VAR8;
input [VAR15-1:0] VAR19;
input [VAR15-1:0] VAR13;
input [VAR15-1:0] VAR14;
input [VAR15-1:0] VAR4;
input [VAR5-1:0] VA... | apache-2.0 |
drichmond/riffa | fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/hdl/VC709_Gen2x8If128_CLK.v | 39,146 | module MODULE1
parameter VAR73 = 8,
parameter VAR45 = 128,
parameter VAR231 = 256,
parameter VAR222 = 6
)
(output [(VAR73 - 1) : 0] VAR135,
output [(VAR73 - 1) : 0] VAR51,
input [(VAR73 - 1) : 0] VAR190,
input [(VAR73 - 1) : 0] VAR105,
output [7:0] VAR34,
input VAR240,
input VAR95,
input VAR194
);
wire VAR153;
wire VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o.pp.blackbox.v | 1,389 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR7 ,
VAR2 ,
VAR4 ,
VAR1,
VAR8,
VAR6 ,
VAR5
);
output VAR9 ;
input VAR3 ;
input VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR1;
input VAR8;
input VAR6 ;
input VAR5 ;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_load_store_unit.v | 31,667 | module MODULE1 (
VAR128,
VAR62,
VAR63,
VAR84,
VAR74,
VAR158,
VAR7,
VAR78,
VAR163,
VAR153,
VAR131,
VAR69,
VAR14,
VAR35,
VAR68,
VAR109,
VAR157,
VAR83,
VAR92,
VAR4,
VAR70,
VAR166,
VAR86,
VAR9,
VAR47,
VAR148,
VAR12,
VAR5,
VAR150,
VAR164,
VAR37,
VAR28,
VAR143,
VAR29,
VAR97,
VAR23,
VAR59,
VAR27,
VAR80,
VAR66,
VAR100,
VAR132,... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9152/axi_ad9152_channel.v | 21,634 | module MODULE1 (
VAR53,
VAR60,
VAR37,
VAR79,
VAR22,
VAR41,
VAR5,
VAR77,
VAR17,
VAR63,
VAR8,
VAR12,
VAR14,
VAR51,
VAR29,
VAR43,
VAR16);
parameter VAR87 = 32'h0;
parameter VAR70 = 0;
input VAR53;
input VAR60;
output VAR37;
output [63:0] VAR79;
input [63:0] VAR22;
input VAR41;
input VAR5;
input VAR77;
input VAR17;
input V... | gpl-3.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/ClockInvToBool.v | 1,678 | module MODULE1(
input VAR12,
input VAR5,
output VAR11);
VAR9#(.VAR4(1'b0)) VAR2 (.VAR7(VAR11), .VAR6(VAR5), .VAR10(1'b1), .VAR8(VAR12), .VAR3(1'b0), .VAR1(1'b0));
endmodule | gpl-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/phy_clock_io.v | 4,869 | module MODULE1 #
(
parameter VAR4 = 100, parameter VAR2 = 2, parameter VAR5 = "VAR6", parameter VAR10 = "VAR7", parameter VAR3 = 300.0, parameter VAR8 = "VAR13" )
(
input VAR11, input clk, input rst, output [VAR2-1:0] VAR15, output [VAR2-1:0] VAR14 );
generate
genvar VAR9;
for (VAR9 = 0; VAR9 < VAR2; VAR9 = VAR9 + 1) b... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkbuf/sky130_fd_sc_hd__clkbuf.pp.blackbox.v | 1,249 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR1,
VAR5,
VAR3 ,
VAR2
);
output VAR6 ;
input VAR4 ;
input VAR1;
input VAR5;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2_ctrl_module/ddr2_ctrl_output.v | 6,052 | module MODULE1(
VAR14,
VAR43,
VAR27,
VAR29,
VAR24,
VAR15,
VAR13,
VAR28,
VAR16,
VAR34,
VAR23,
VAR12,
VAR40
);
input VAR14;
input VAR43;
input [31:0] VAR27;
input VAR29;
input VAR24;
input VAR15;
output[127:0] VAR13;
input VAR28;
output[6:0] VAR16;
output VAR34;
input[6:0] VAR23;
input VAR12;
output VAR40;
wire[127:0] VA... | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/rxc_engine_classic.v | 37,507 | module MODULE2
parameter VAR71 = 128,
parameter VAR23 = 10
)
(
input VAR155,
input VAR63,
input [VAR71-1:0] VAR25,
input VAR60,
input VAR73,
input [VAR179-1:0] VAR84,
input VAR45,
input [VAR179-1:0] VAR140,
input [VAR168-1:0] VAR67,
output [VAR71-1:0] VAR105,
output VAR177,
output [(VAR71/32)-1:0] VAR125,
output VAR95,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211o/sky130_fd_sc_ls__a211o.pp.symbol.v | 1,372 | module MODULE1 (
input VAR3 ,
input VAR5 ,
input VAR8 ,
input VAR1 ,
output VAR2 ,
input VAR7 ,
input VAR4,
input VAR6,
input VAR9
);
endmodule | apache-2.0 |
Triple-Z/COExperiment_Repo | Project_Assignment/datapath/CoProcessor0RF.v | 1,308 | module MODULE1(clk, din, VAR1, VAR10, sel, dout, VAR14, VAR4, VAR15);
input clk;
input [1:0] VAR1;
input [4:0] VAR10;
input [2:0] sel;
input [31:0] din;
input [31:0] VAR15;
input [31:0] VAR14;
output [31:0] dout;
output reg [31:0] VAR4;
reg [31:0] VAR5 [0:31];
wire [5:0] VAR2;
wire [5:0] VAR9;
wire [4:0] VAR12;
assign ... | mit |
fabugo/witnesses-of-jhon | fpga/quartus/db/my_altpll_altpll.v | 4,061 | module MODULE1
(
clk,
VAR2) ;
output [4:0] clk;
input [1:0] VAR2;
tri0 [1:0] VAR2;
wire [4:0] VAR14;
wire VAR24;
VAR42 VAR6
(
.VAR15(),
.clk(VAR14),
.VAR25(),
.VAR36(VAR24),
.VAR10(VAR24),
.VAR2(VAR2),
.VAR28(),
.VAR41(),
.VAR35(),
.VAR29(),
.VAR11(),
.VAR18()
,
.VAR19(1'b0),
.VAR8(1'b0),
.VAR39(1'b0),
.VAR20(1'b1),
.V... | gpl-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Position/Top_BackBox.v | 1,254 | module MODULE1(
input clk,
input rst,
input [15:0] VAR19,
input [15:0] VAR2,
input [15:0] VAR12,
input [31:0]VAR11,
input enable,
input [7:0]VAR24,
input VAR10,
input VAR16,
input [31:0]VAR1,
output VAR6,
output [31:0]VAR15,
output [31:0]VAR23,
output [31:0]VAR3
);
wire [7:0] address;
wire [15:0] ref;
wire [31:0] VAR9;... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_VGA_Controller.v | 9,846 | module MODULE1 (
clk,
reset,
VAR25,
VAR15,
VAR5,
VAR46,
valid,
ready,
VAR56,
VAR30,
VAR36,
VAR42,
VAR29,
VAR50,
VAR4,
VAR26
);
parameter VAR41 = 9;
parameter VAR3 = 29;
parameter VAR12 = 29;
parameter VAR20 = 20;
parameter VAR57 = 19;
parameter VAR45 = 10;
parameter VAR27 = 9;
parameter VAR39 = 0;
parameter VAR14 = 640... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv.pp.blackbox.v | 1,251 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR4,
VAR3,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrbp/sky130_fd_sc_hs__dfrbp.behavioral.pp.v | 2,295 | module MODULE1 (
VAR20 ,
VAR1 ,
VAR11 ,
VAR4 ,
VAR13 ,
VAR6 ,
VAR15
);
input VAR20 ;
input VAR1 ;
output VAR11 ;
output VAR4 ;
input VAR13 ;
input VAR6 ;
input VAR15;
wire VAR17 ;
wire VAR2 ;
reg VAR10 ;
wire VAR12 ;
wire VAR14;
wire VAR21 ;
wire VAR19 ;
wire VAR3 ;
wire VAR7 ;
not VAR8 (VAR2 , VAR14 );
VAR9 VAR18 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0n/sky130_fd_sc_lp__iso0n.functional.v | 1,193 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR3;
and VAR4 (VAR2 , VAR1, VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41a/sky130_fd_sc_ls__o41a.behavioral.pp.v | 2,047 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR15 ,
VAR9 ,
VAR5 ,
VAR16 ,
VAR10,
VAR11,
VAR7 ,
VAR4
);
output VAR6 ;
input VAR8 ;
input VAR15 ;
input VAR9 ;
input VAR5 ;
input VAR16 ;
input VAR10;
input VAR11;
input VAR7 ;
input VAR4 ;
wire VAR17 ;
wire VAR13 ;
wire VAR14;
or VAR3 (VAR17 , VAR5, VAR9, VAR15, VAR8 );
and VAR18 (VAR1... | apache-2.0 |
dries007/Basys3 | VGA/VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v | 6,514 | module MODULE1
( input VAR17,
output VAR15,
input reset,
output VAR52
);
VAR77 VAR54
(.VAR42 (VAR14),
.VAR78 (VAR17));
wire [15:0] VAR18;
wire VAR11;
wire VAR56;
wire VAR46;
wire VAR51;
wire VAR64;
wire VAR43;
wire VAR20;
wire VAR1;
wire VAR62;
wire VAR26;
wire VAR24;
wire VAR47;
wire VAR49;
wire VAR10;
wire VAR13;
wir... | mit |
glennchid/font5-firmware | src/verilog/synthesis/monitor_readback.v | 3,724 | module MODULE1(
clk,
rst,
VAR10,
VAR2,
VAR19,
VAR7,
VAR4,
VAR13,
VAR18,
VAR14,
VAR27,
VAR24,
VAR21,
VAR15,
VAR9,
VAR5,
VAR11,
VAR8,
VAR6,
VAR1,
VAR23,
VAR16
);
parameter VAR22 = 15;
input clk;
input rst;
input VAR10;
input VAR7;
output reg VAR2;
output [6:0] VAR19;
output reg VAR4;
input [6:0] VAR13;
input [6:0] VAR18;... | gpl-3.0 |
velizarefremov/MIPS | Part 2/Verilog Code/Post-Synthesis/aluparam_synthesis.v | 19,537 | module MODULE2 (
VAR129, VAR33, sel, VAR124, VAR101
);
input [15 : 0] VAR129;
input [15 : 0] VAR33;
input [3 : 0] sel;
output [15 : 0] VAR124;
output [15 : 0] VAR101;
wire VAR191;
wire VAR166;
wire VAR54;
wire VAR58;
wire VAR86;
wire VAR128;
wire VAR148;
wire VAR43;
wire VAR65;
wire VAR19;
wire VAR177;
wire VAR136;
wir... | gpl-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/rp2a03.v | 5,423 | module MODULE1
(
input VAR1, input VAR47,
input VAR12, input [ 7:0] din, input VAR52, input VAR46, output [ 7:0] dout, output [15:0] VAR2, output VAR15, output VAR51,
input [7:0] VAR19, input [7:0] VAR10, input [ 3:0] VAR3, output VAR40,
input [ 3:0] VAR32, input [ 7:0] VAR43, input VAR21, output [ 7:0] VAR30 );
wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp.pp.symbol.v | 1,351 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR1,
input VAR6 ,
input VAR4 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.functional.pp.v | 2,122 | module MODULE1 (
VAR13 ,
VAR5 ,
VAR7 ,
VAR14 ,
VAR12 ,
VAR20 ,
VAR16,
VAR2,
VAR15 ,
VAR18
);
output VAR13 ;
input VAR5 ;
input VAR7 ;
input VAR14 ;
input VAR12 ;
input VAR20 ;
input VAR16;
input VAR2;
input VAR15 ;
input VAR18 ;
wire VAR19 ;
wire VAR10;
wire VAR6 ;
VAR17 VAR1 (VAR10, VAR6, VAR12, VAR20 );
VAR17 VAR8 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4bb/sky130_fd_sc_hs__or4bb_1.v | 2,187 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR9 ,
VAR1 ,
VAR3 ,
VAR8,
VAR6
);
output VAR4 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
input VAR3 ;
input VAR8;
input VAR6;
VAR5 VAR2 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR4 ,
VAR7 ,
VAR9 ,
VAR1,
VAR3
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.functional.pp.v | 1,404 | module MODULE1( VAR8, VAR11, VAR9, VAR1, VAR12, VAR2, VAR5 );
input VAR12, VAR1, VAR9, VAR8;
inout VAR2, VAR5;
output VAR11;
wire VAR14;
not VAR7( VAR14, VAR12 );
wire VAR4;
not VAR6( VAR4, VAR1 );
wire VAR15;
not VAR10( VAR15, VAR9 );
wire VAR16;
not VAR3( VAR16, VAR8 );
and VAR13( VAR11, VAR14, VAR4, VAR15, VAR16 );
... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/8-way_8-parallel/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_round_robin_arb.v | 7,553 | module MODULE1
parameter VAR16 = 100,
parameter VAR18 = 3
)
(
VAR14, VAR19,
clk, rst, req, VAR20, VAR17, VAR9
);
input clk;
input rst;
input [VAR18-1:0] req;
wire [VAR18-1:0] VAR12;
reg [VAR18*2-1:0] VAR2;
always @(VAR12)
VAR2 = {VAR12, VAR12};
reg [VAR18*2-1:0] VAR10;
always @(req) VAR10 = {req, req};
reg [VAR18-1:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a_1.v | 2,444 | module MODULE1 (
VAR4 ,
VAR10 ,
VAR1 ,
VAR3 ,
VAR8 ,
VAR11 ,
VAR12,
VAR6,
VAR9 ,
VAR5
);
output VAR4 ;
input VAR10 ;
input VAR1 ;
input VAR3 ;
input VAR8 ;
input VAR11 ;
input VAR12;
input VAR6;
input VAR9 ;
input VAR5 ;
VAR7 VAR2 (
.VAR4(VAR4),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR1... | apache-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/sync_debouncer_10ms.v | 2,960 | module MODULE1 (
VAR4,
VAR7, rst, VAR5 );
output VAR4;
input VAR7; input rst; input VAR5;
reg [1:0] VAR3;
always @(posedge VAR7 or posedge rst)
if (rst) VAR3 <= 2'b00;
else VAR3 <= {VAR3[0], VAR5};
wire VAR2 = VAR3[1];
reg [18:0] VAR1;
always @(posedge VAR7 or posedge rst)
if (rst) VAR1 <= 19'h00000;
else if(VAR4==VAR2... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.v | 2,334 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR2 ,
VAR4 ,
VAR6 ,
VAR9,
VAR10,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR6 ;
input VAR9;
input VAR10;
input VAR1 ;
input VAR3 ;
VAR8 VAR11 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9467/axi_ad9467_pnmon.v | 7,071 | module MODULE1 (
VAR5,
VAR1,
VAR15,
VAR7,
VAR2);
input VAR5;
input [15:0] VAR1;
output VAR15;
output VAR7;
input [ 3:0] VAR2;
reg VAR3 = 'd0;
reg [31:0] VAR14 = 'd0;
reg [31:0] VAR9 = 'd0;
wire [31:0] VAR11;
function [31:0] VAR13;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21]... | gpl-3.0 |
balanx/laotzu | RTL/asyn_fifo_controller.v | 3,892 | module MODULE1 #(
parameter VAR34 = 1, parameter VAR4 = 6,
parameter [VAR4:0] VAR9 = 44 ) (
input VAR28 ,
input VAR21 ,
input VAR5 ,
output VAR30 ,
output VAR11 ,
output [VAR4:0] VAR17 ,
input VAR33 ,
input VAR6 ,
input VAR37 ,
output VAR27 ,
output VAR2 ,
output [VAR4:0] VAR10 ,
output [VAR4-1:0] VAR32 ,
output VAR16 ... | apache-2.0 |
yyang29/MIPS | design/mips_regFile.v | 1,762 | module MODULE1 (
clk,
VAR17,
VAR14,
VAR10,
VAR16,
VAR12,
VAR8,
VAR7,
VAR13,
VAR22
);
input clk;
input VAR17;
input VAR7;
input [4:0] VAR14;
input [4:0] VAR10;
output [31:0] VAR13;
output [31:0] VAR22;
input VAR16;
input [4:0] VAR12;
input [31:0] VAR8;
reg [31:0] VAR6[31:0];
integer VAR5;
always @(posedge clk) begin
if ... | gpl-2.0 |
ZiCog/xoro | rtl/AsyncReceiver.v | 6,294 | module MODULE1 (
input [7:0] VAR17,
output [7:0] VAR31,
input VAR27,
input VAR2,
output VAR5,
output VAR34,
input clk,
input reset);
wire [7:0] VAR8;
wire [4:0] VAR32;
wire [4:0] VAR20;
wire [7:0] VAR3;
wire VAR29;
reg [4:0] head;
reg [4:0] VAR28;
reg VAR37;
reg VAR30;
reg VAR13;
reg VAR36;
reg VAR16;
reg VAR15;
reg [7... | mit |
horia141/bachelor-thesis | prj/applications/ViewImage/ViewImage.v | 2,245 | module MODULE1(VAR22,VAR33,reset,VAR40,VAR17,VAR2,VAR29,VAR48);
input wire VAR22;
input wire VAR33;
input wire reset;
output wire VAR40;
output wire VAR17;
output wire VAR2;
output wire VAR29;
output wire VAR48;
wire [7:0] VAR49;
wire [11:0] VAR14;
wire [7:0] VAR9;
wire [19:0] VAR42;
wire [4095:0] VAR3;
wire [7:0] VAR3... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_cmos2_pad.v | 2,447 | module MODULE1(VAR25 ,VAR12 ,VAR23 ,VAR27 ,VAR21, VAR6 );
output VAR23 ;
input VAR25 ;
input VAR12 ;
input VAR21 ;
inout VAR27 ;
input VAR6 ;
supply1 VAR1 ;
supply0 VAR22 ;
wire VAR5 ;
wire VAR4 ;
wire VAR20 ;
wire VAR8 ;
wire VAR26 ;
wire VAR11 ;
VAR17 VAR15 (
.VAR5 (VAR5 ),
.VAR23 (VAR23 ),
.VAR10 (VAR22 ),
.VAR2 (VA... | gpl-2.0 |
kyzhai/NUNY | src/hardware/four_new2_bb.v | 5,018 | module MODULE1 (
address,
VAR2,
VAR1);
input [9:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
duttondj/LEDDimmer | SourceFiles/dimmer.v | 4,440 |
reg [3:0] VAR2; reg VAR9; reg VAR3; reg [4:0] VAR13; reg [4:0] VAR8; reg [17:0] VAR11; reg [25:0] VAR12; reg [25:0] VAR10;
always @(negedge VAR7 or negedge VAR6) begin
if (VAR7 == 0) begin
VAR3 <= 1;
end
else if (VAR6 == 0) begin
VAR3 <= 1;
end
else begin
VAR3 <= 0;
end
end
always @(VAR12 or VAR10) begin
if (!VAR7 &&... | mit |
ellisgl/Driver-YL-3 | yl3.v | 12,966 | module MODULE1(
input VAR2, input VAR18, input [63:0] VAR52, input VAR7,
output VAR56, output VAR21, output VAR11, output VAR28 );
localparam VAR4 = 2'b00; localparam VAR43 = 2'b01; localparam VAR32 = 2'b10;
reg [7:0] VAR30 [0:7]; reg [3:0] VAR36; reg [7:0] VAR24; reg [7:0] VAR40; reg [15:0] VAR51; reg [3:0] VAR42; reg... | bsd-3-clause |
hcabrera-/lancetfish | RTL/processing_element/des_engine/rtl/des_key_generator.v | 4,291 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR10,
input wire VAR11,
input wire VAR3,
input wire [0:55] VAR9,
output wire [0:47] VAR4
);
reg [0:27] VAR6;
reg [0:27] VAR12;
wire [0:27] VAR5;
wire [0:27] VAR8;
assign VAR5 = (VAR11) ? VAR2 : VAR9[28:55];
assign VAR8 = (VAR11) ? VAR1 : VAR9[0:27];
always ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp.behavioral.v | 1,760 | module MODULE1 (
VAR11 ,
VAR13,
VAR7
);
output VAR11 ;
input VAR13;
input VAR7 ;
supply1 VAR10;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR3 ;
wire VAR1 ;
reg VAR4 ;
wire VAR6 ;
wire VAR2;
wire VAR15 ;
VAR12 VAR9 (VAR1 , VAR6, VAR2, VAR4, VAR10, VAR5);
assign VAR15 = ( VAR10 === 1'b1 );
buf VAR14 (VAR11 , VAR1 );
endmodul... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v | 40,363 | module MODULE1 #(
parameter VAR227 = "VAR150",
parameter integer VAR248 = 0,
parameter integer VAR116 = 0,
parameter integer VAR251 = 0,
parameter integer VAR22 = 4,
parameter integer VAR256 = 32,
parameter integer VAR266 = 32,
parameter integer VAR9 = 1,
parameter integer VAR137 = 1,
parameter integer VAR59 = 0,
param... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/111e5b5bdee7fef3/ip_design_axi_gpio_0_0_stub.v | 2,378 | module MODULE1(VAR1, VAR2, VAR7,
VAR12, VAR10, VAR18, VAR22, VAR20, VAR3,
VAR19, VAR5, VAR13, VAR15, VAR17, VAR6,
VAR21, VAR4, VAR9, VAR11, VAR16, VAR8, VAR14)
;
input VAR1;
input VAR2;
input [8:0]VAR7;
input VAR12;
output VAR10;
input [31:0]VAR18;
input [3:0]VAR22;
input VAR20;
output VAR3;
output [1:0]VAR19;
output V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3/sky130_fd_sc_lp__and3_lp.v | 2,172 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR1 ,
VAR8 ,
VAR3,
VAR5,
VAR4 ,
VAR9
);
output VAR7 ;
input VAR10 ;
input VAR1 ;
input VAR8 ;
input VAR3;
input VAR5;
input VAR4 ;
input VAR9 ;
VAR6 VAR2 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_rx.v | 4,968 | module MODULE1 # (
parameter VAR35 = 128
)
(
input VAR10,
input VAR27,
input [VAR35-1:0] VAR32,
input [(VAR35/8)-1:0] VAR7,
input VAR5,
input VAR23,
output VAR34,
input [21:0] VAR31,
output VAR3,
output VAR33,
output VAR4,
output VAR25,
output [VAR35-1:0] VAR38,
output [7:0] VAR21,
output VAR29,
output VAR2,
output [VA... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/megafunctions/async_fifo_512x36_to_72_progfull_500_bb.v | 6,524 | module MODULE1 (
VAR4,
VAR1,
VAR5,
VAR2,
VAR7,
VAR9,
VAR10,
VAR8,
VAR3,
VAR6);
input VAR4;
input [35:0] VAR1;
input VAR5;
input VAR2;
input VAR7;
input VAR9;
output [71:0] VAR10;
output VAR8;
output VAR3;
output [8:0] VAR6;
tri0 VAR4;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2.behavioral.v | 1,200 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
lynxis/lpc_sniffer | mem2serial.v | 2,313 | module MODULE1 #(parameter VAR8 = 8)
(
output reg VAR10,
input [47:0] VAR7,
input VAR9, input reset, input VAR6,
input VAR4,
output reg [7:0] VAR12,
output reg VAR13);
parameter VAR1 = 0, VAR5 = 1, VAR14 = 2,
VAR2 = 3, VAR11 = 4;
reg [2:0] state;
reg [7:0] VAR3;
reg [47:0] VAR15;
always @(negedge reset or negedge VAR6)... | gpl-3.0 |
subailong/miaow | src/verilog/rtl/lsu/PS_flops_ex_mem_lsu.v | 1,316 | module MODULE1(
VAR13,
VAR9,
VAR17,
VAR7,
VAR15,
VAR24,
VAR22,
VAR20,
VAR14,
VAR18,
VAR19,
VAR1,
VAR21,
VAR16,
clk,
rst
);
input [8191:0] VAR13;
input [3:0] VAR9;
input [3:0] VAR17;
input [2047:0] VAR7;
input [6:0] VAR15;
input [63:0] VAR24;
input VAR22;
output [8191:0] VAR20;
output [3:0] VAR14;
output [3:0] VAR18;
ou... | bsd-3-clause |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_axi_basic_tx_pipeline.v | 22,376 | module MODULE1 #(
parameter VAR44 = 128, parameter VAR30 = "VAR45", parameter VAR47 = 1,
parameter VAR27 = (VAR44 == 128) ? 2 : 1, parameter VAR46 = VAR44 / 8 ) (
input [VAR44-1:0] VAR56, input VAR29, output VAR1, input [VAR46-1:0] VAR40, input VAR51, input [3:0] VAR8,
output [VAR44-1:0] VAR33, output VAR23, output VAR... | gpl-2.0 |
drichmond/riffa | fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/hdl/VC709_Gen1x8If64_CLK.v | 39,128 | module MODULE1
parameter VAR120 = 8,
parameter VAR19 = 64,
parameter VAR230 = 256,
parameter VAR112 = 6)
(output [(VAR120 - 1) : 0] VAR124,
output [(VAR120 - 1) : 0] VAR208,
input [(VAR120 - 1) : 0] VAR12,
input [(VAR120 - 1) : 0] VAR194,
output [7:0] VAR89,
input VAR94,
input VAR81,
input VAR235);
wire VAR165;
wire VA... | bsd-3-clause |
Nrpickle/ECE272 | Lab4_SmartTekbotRemote/Section4_Verilog.v | 1,135 | module MODULE3(
input VAR13,
input VAR12,
input VAR11,
input VAR24,
input VAR31,
output VAR32,
output VAR19,
output VAR34,
output VAR30
);
wire VAR21;
wire VAR3;
wire VAR1;
wire VAR33;
wire VAR9;
wire VAR20;
wire VAR28;
wire VAR26;
supply0 VAR10;
assign VAR26 = VAR24 & VAR31;
MODULE1 VAR15(.VAR13(VAR13), .VAR7(VAR21));... | mit |
aap/pdp6 | verilog/iobus_1_connect.v | 1,515 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR25,
input wire VAR6,
input wire VAR5,
input wire VAR2,
input wire VAR10,
input wire VAR20,
input wire VAR12,
input wire VAR27,
input wire VAR23,
input wire [3:9] VAR4,
input wire [0:35] VAR16,
output wire [1:7] VAR21,
output wire [0:35] VAR14,
output wire ... | mit |
vvk/sysrek | skin_color_segm/bounding_box.v | 3,426 | module MODULE1 #
(
parameter [9:0] VAR9 = 720,
parameter [9:0] VAR3 = 576
)
(
input clk,
input VAR15,
input rst,
input VAR11,
input VAR10,
input VAR16,
input VAR22,
output [9:0] VAR8,
output [9:0] VAR20,
output [9:0] VAR5,
output [9:0] VAR12,
output [9:0] VAR4,
output [9:0] VAR18,
output VAR13
);
reg [9:0] VAR30 = 0;
r... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.behavioral.v | 1,188 | module MODULE1( VAR5, VAR3, VAR4 );
input VAR4, VAR5;
output VAR3;
VAR6 VAR2(.VAR5(VAR5),.VAR3(VAR3),.VAR4(VAR4));
VAR6 VAR1(.VAR5(VAR5),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
sh-chris110/chris | FPGA/atlas_linux_ghrd/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v | 6,164 | module MODULE1 #(
parameter VAR24 = 66,
parameter VAR20 = 0,
parameter VAR2 = 66,
parameter VAR18 = 0,
parameter VAR1 = 0,
parameter VAR4 = 0,
parameter VAR23 = 1,
parameter VAR8 = 1,
parameter VAR25 = 0,
parameter VAR21 = 66,
parameter VAR17 = 0,
parameter VAR7 = 1,
parameter VAR3 = 0,
parameter VAR13 = 1,
parameter V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi.pp.blackbox.v | 1,391 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR3 ,
VAR5 ,
VAR9 ,
VAR7,
VAR4,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR8 ;
input VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR7;
input VAR4;
input VAR6 ;
input VAR2 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/a79f7727e74fe6ae/zynq_design_1_axi_bram_ctrl_0_bram_0_stub.v | 1,733 | module MODULE1(VAR7, VAR8, VAR9, VAR3, VAR14, VAR13, VAR12, VAR1, VAR4, VAR2,
VAR5, VAR6, VAR10, VAR11)
;
input VAR7;
input VAR8;
input VAR9;
input [3:0]VAR3;
input [31:0]VAR14;
input [31:0]VAR13;
output [31:0]VAR12;
input VAR1;
input VAR4;
input VAR2;
input [3:0]VAR5;
input [31:0]VAR6;
input [31:0]VAR10;
output [31:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ha/sky130_fd_sc_hs__ha.pp.blackbox.v | 1,223 | module MODULE1 (
VAR2,
VAR3 ,
VAR4 ,
VAR5 ,
VAR6,
VAR1
);
output VAR2;
output VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR6;
input VAR1;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.functional.pp.v | 1,611 | module MODULE1( VAR18, VAR6, VAR8, VAR12, VAR10, VAR2, VAR4 );
input VAR8, VAR6, VAR12, VAR10;
inout VAR2, VAR4;
output VAR18;
wire VAR1;
not VAR17( VAR1, VAR8 );
wire VAR5;
not VAR14( VAR5, VAR12 );
wire VAR7;
not VAR20( VAR7, VAR10 );
wire VAR11;
and VAR16( VAR11, VAR1, VAR5, VAR7 );
wire VAR15;
not VAR9( VAR15, VAR6... | apache-2.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/io/src/util.v | 2,646 | module MODULE2(
input VAR6,
input VAR2,
input VAR14,
output VAR16
);
reg VAR1;
reg VAR8;
always @(posedge VAR6)
begin
if (VAR14 == 1'b1)
begin
VAR8 <= 1'b0;
VAR1 <= 1'b0;
end
else
begin
if (VAR2 == VAR8)
begin
VAR8 <= ~VAR8;
VAR1 <= 1'b1;
end
else if (VAR1 == 1'b1)
begin
VAR1 <= 1'b0;
end
end
end
assign VAR16 = VAR1;
e... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2b/sky130_fd_sc_hs__and2b.functional.v | 1,822 | module MODULE1 (
VAR1,
VAR13,
VAR8 ,
VAR5 ,
VAR7
);
input VAR1;
input VAR13;
output VAR8 ;
input VAR5 ;
input VAR7 ;
wire VAR8 VAR3 ;
wire VAR9 ;
wire VAR6;
not VAR11 (VAR3 , VAR5 );
and VAR12 (VAR9 , VAR3, VAR7 );
VAR10 VAR4 (VAR6, VAR9, VAR1, VAR13);
buf VAR2 (VAR8 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2.functional.pp.v | 1,832 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR5,
VAR9,
VAR12 ,
VAR2
);
output VAR3 ;
input VAR11 ;
input VAR5;
input VAR9;
input VAR12 ;
input VAR2 ;
wire VAR7 ;
wire VAR10;
buf VAR8 (VAR7 , VAR11 );
VAR6 VAR4 (VAR10, VAR7, VAR5, VAR9);
buf VAR1 (VAR3 , VAR10 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2.behavioral.pp.v | 9,064 | module MODULE1( VAR50, VAR51, VAR71, VAR16, VAR26, VAR13, VAR47 );
input VAR50, VAR51, VAR16, VAR71;
inout VAR13, VAR47;
output VAR26;
reg VAR20;
VAR36 VAR53(.VAR50(VAR50),.VAR51(VAR51),.VAR71(VAR71),.VAR16(VAR16),.VAR26(VAR26),.VAR13(VAR13),.VAR47(VAR47),.VAR20(VAR20));
VAR36 VAR46(.VAR50(VAR50),.VAR51(VAR51),.VAR71(V... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/arb_mux.v | 17,638 | module MODULE1 #
(
parameter VAR53 = 100,
parameter VAR19 = "1T",
parameter VAR83 = 11,
parameter VAR66 = 3,
parameter VAR90 = "8",
parameter VAR79 = 4,
parameter VAR49 = 31,
parameter VAR77 = 8,
parameter VAR33 = "VAR6",
parameter VAR56 = "VAR61",
parameter VAR92 = "VAR61",
parameter VAR35 = 4,
parameter VAR8 = 2, par... | mit |
sstallion/apple-idun | cpld/clk_div.v | 1,710 | module MODULE1(input reset,
input VAR2,
output reg VAR3);
reg [2:0] VAR1;
always @(posedge VAR2) begin
if (!reset) begin
VAR3 <= 1'b0;
VAR1 <= 3'b111;
end
else if (VAR1 == 5) begin
VAR3 <= ~VAR3;
VAR1 <= 0;
end
else begin
VAR1 <= VAR1 + 1;
end
end
endmodule | bsd-2-clause |
ZiCog/P8X32A_Emulation | P8X32A_DE2_115/hub_mem.v | 3,072 | module MODULE1
(
input VAR6,
input VAR20,
input VAR11,
input [3:0] VAR3,
input [13:0] VAR19,
input [31:0] VAR17,
output [31:0] VAR5
);
reg [7:0] VAR15 [8191:0];
reg [7:0] VAR14 [8191:0];
reg [7:0] VAR2 [8191:0];
reg [7:0] VAR10 [8191:0];
reg [7:0] VAR13;
reg [7:0] VAR16;
reg [7:0] VAR9;
reg [7:0] VAR4;
always @(posedge... | gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab02/lab02/Code/HexTo8SEG.v | 2,760 | module MODULE1(input [31:0] VAR23, input [7:0] VAR31,
input [7:0] VAR21,
input VAR20,
output[63:0] VAR27
);
MODULE2 VAR11(VAR23[31:28],VAR21[7],VAR31[7],VAR20,VAR27[7:0]);
MODULE2 VAR1(VAR23[27:24],VAR21[6],VAR31[6],VAR20,VAR27[15:8]);
MODULE2 VAR12(VAR23[23:20],VAR21[5],VAR31[5],VAR20,VAR27[23:16]);
MODULE2 VAR4(VAR23... | gpl-3.0 |
toomij/DE2Labs | Lab2/lab2_part3.v | 1,210 | module MODULE1 (VAR4, VAR3, VAR10);
input [17:0] VAR4;
output [8:0] VAR10, VAR3;
assign VAR10[8:0] = VAR4[8:0];
wire VAR8, VAR11, VAR5;
MODULE2 VAR12 (VAR4[0], VAR4[4], VAR4[8], VAR3[0], VAR8);
MODULE2 VAR13 (VAR4[1], VAR4[5], VAR8, VAR3[1], VAR11);
MODULE2 VAR7 (VAR4[2], VAR4[6], VAR11, VAR3[2], VAR5);
MODULE2 VAR6 (V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4b/sky130_fd_sc_ls__or4b_2.v | 2,291 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR8 ,
VAR3 ,
VAR2 ,
VAR9,
VAR10,
VAR1 ,
VAR11
);
output VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
input VAR9;
input VAR10;
input VAR1 ;
input VAR11 ;
VAR5 VAR7 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1),
.VA... | apache-2.0 |
jotego/jt12 | hdl/jt12_sh24.v | 1,994 | module MODULE1 #(parameter VAR22=5 )
(
input clk,
input VAR9 ,
input [VAR22-1:0] din,
output reg [VAR22-1:0] VAR6,
output reg [VAR22-1:0] VAR23,
output reg [VAR22-1:0] VAR12,
output reg [VAR22-1:0] VAR18,
output reg [VAR22-1:0] VAR17,
output reg [VAR22-1:0] VAR10,
output reg [VAR22-1:0] VAR5,
output reg [VAR22-1:0] VAR... | gpl-3.0 |
efabless/openlane | designs/jpeg_encoder/src/jpeg.v | 85,496 | module MODULE1(
clk,
VAR264,
VAR159,
din,
VAR262,
VAR229,
VAR307,
VAR218,
VAR69,
VAR188,
VAR219,
VAR306,
VAR257
);
parameter VAR28 = 11;
parameter VAR163 = 8;
input VAR219;
input VAR306;
output VAR257;
input clk; input VAR264;
input VAR159; input [VAR163-1:0] din;
input [7:0] VAR262;
output [ 5:0] VAR229;
output [ 3:0]... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/src_axi_mm.v | 6,243 | module MODULE1 (
input VAR8,
input VAR42,
input VAR56,
output VAR29,
input [31:VAR36] VAR45,
input [VAR43-1:0] VAR32,
input enable,
output VAR4,
input VAR13,
input VAR3,
output VAR7,
output VAR71,
input VAR46,
output [1:0] VAR22,
input [VAR24-1:0] VAR23,
output [VAR24-1:0] VAR40,
output [VAR24-1:0] VAR37,
output [VAR24... | gpl-3.0 |
DreamSourceLab/DSLogic-hdl | src/sample.v | 12,052 | module MODULE1(
input VAR92,
input VAR87,
input VAR78,
input VAR9,
output VAR47,
input VAR75,
input VAR33,
input VAR24,
input VAR70,
input VAR83,
input VAR76,
input VAR21,
input VAR46,
input VAR74,
input VAR99,
input VAR44,
input [23:0] VAR18,
input VAR50,
output VAR100,
input [15:0] VAR68,
output [15:0] VAR59,
output ... | gpl-2.0 |
Kipsora/MIPS-CPU | source/machine/cpu/mips.v | 15,178 | module MODULE1(
input wire VAR155,
input wire reset,
input wire[VAR93] VAR133,
input wire[VAR93] VAR179,
output wire[VAR113] VAR44,
output wire VAR42,
output wire VAR192,
output wire[VAR39] VAR77,
output wire[VAR113] VAR78,
output wire[VAR93] VAR100,
output wire VAR49
);
wire[VAR113] VAR104;
wire[VAR113] VAR94;
wire[VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2.functional.v | 1,104 | module MODULE1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr.symbol.v | 1,410 | module MODULE1 (
input VAR4,
output VAR7
);
supply1 VAR6 ;
supply0 VAR1 ;
supply1 VAR3;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp.behavioral.v | 2,780 | module MODULE1 (
VAR16 ,
VAR30 ,
VAR4 ,
VAR21 ,
VAR7 ,
VAR12 ,
VAR23
);
output VAR16 ;
output VAR30 ;
input VAR4 ;
input VAR21 ;
input VAR7 ;
input VAR12 ;
input VAR23;
supply1 VAR11;
supply0 VAR13;
supply1 VAR27 ;
supply0 VAR15 ;
wire VAR31 ;
wire VAR5 ;
wire VAR24 ;
reg VAR29 ;
wire VAR8 ;
wire VAR1 ;
wire VAR25 ;
wi... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp.functional.pp.v | 1,825 | module MODULE1 (
VAR12 ,
VAR15 ,
VAR8 ,
VAR1,
VAR14 ,
VAR10 ,
VAR7 ,
VAR9
);
output VAR12 ;
input VAR15 ;
input VAR8 ;
input VAR1;
input VAR14 ;
input VAR10 ;
input VAR7 ;
input VAR9 ;
wire VAR3;
wire VAR4 ;
not VAR2 (VAR4 , VAR1 );
VAR5 VAR11 VAR6 (VAR3 , VAR8, VAR15, VAR4, , VAR14, VAR10);
buf VAR13 (VAR12 , VAR3 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2.pp.symbol.v | 1,324 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/BIOSROM.v | 1,318 | module MODULE1(
input VAR13, input VAR4,
input [15:0] VAR12,
output [15:0] VAR1,
input [19:1] VAR6,
input VAR8,
input VAR3,
input VAR5,
input VAR14,
input [ 1:0] VAR10,
output reg VAR9
);
wire VAR7 = VAR5 & VAR14;
always @(posedge VAR13) VAR9 <= VAR7;
reg [15:0] VAR2[0:127]; VAR16
wire [ 6:0] VAR15 = VAR6[7:1];
wire [1... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_itcm_ctrl.v | 22,485 | module MODULE1(
output VAR169,
input VAR56,
input VAR52, output VAR60, input [VAR15-1:0] VAR97, input VAR120, input [VAR133-1:0] VAR186,
input [VAR45-1:0] VAR124,
output VAR157, input VAR191, output VAR90, output [VAR133-1:0] VAR53,
output VAR10,
input VAR121, output VAR46, input [VAR15-1:0] VAR111, input VAR194, input... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufinv/sky130_fd_sc_lp__bufinv.behavioral.v | 1,355 | module MODULE1 (
VAR6,
VAR9
);
output VAR6;
input VAR9;
supply1 VAR7;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
wire VAR2;
not VAR8 (VAR2, VAR9 );
buf VAR5 (VAR6 , VAR2 );
endmodule | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T25-uart-rx/rxleds.v | 1,908 | module MODULE1(input wire clk, input wire VAR4, output reg [3:0] VAR5, output wire VAR9);
localparam VAR6 = VAR2;
wire VAR10;
wire [7:0] VAR3;
reg VAR8 = 0;
always @(posedge clk)
VAR8 <= 1;
VAR7 #(VAR6)
VAR1 (.clk(clk), .VAR8(VAR8), .VAR4(VAR4), .VAR10(VAR10), .VAR3(VAR3) );
always @(posedge clk)
if (VAR10 == 1'b1)
VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2/sky130_fd_sc_ls__or2_4.v | 2,075 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR8 ,
VAR4,
VAR3,
VAR6 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR8 ;
input VAR4;
input VAR3;
input VAR6 ;
input VAR5 ;
VAR9 VAR7 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR1,
VAR2,
VAR8
);
output VAR1;
... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_aon_top.v | 18,954 | module MODULE1 #(
parameter VAR80 = 2
)(
input VAR82,
output VAR58,
input [32-1:0] VAR247,
input VAR78,
input [32-1:0] VAR73,
output VAR136,
input VAR85,
output [32-1:0] VAR40,
input VAR212,
output VAR218,
output VAR223,
output VAR242,
output VAR98,
output VAR222,
input VAR188,
output VAR5,
output VAR269,
output VAR168... | apache-2.0 |
mda-ut/AquaTux | fpga/fpga_hw/top_level/SONAR/ShiftRegisterWEnableFourteenAsyncMuxedInput.v | 3,052 | module MODULE1(clk, VAR27, enable, select, VAR24, VAR19);
input clk;
input VAR27;
input enable;
input select;
input [13:0] VAR24;
output [13:0] VAR19;
wire [13:1]VAR12;
VAR32 VAR13(.VAR17(VAR24[1]), .VAR36(VAR19[0]), .sel(select), .VAR2(VAR12[1]) );
VAR32 VAR8(.VAR17(VAR24[2]), .VAR36(VAR19[1]), .sel(select), .VAR2(VAR... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/db/ip/tracking_camera_system/submodules/tracking_camera_system_switch.v | 1,974 | module MODULE1 (
address,
clk,
VAR3,
VAR4,
VAR2
)
;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input clk;
input VAR3;
input VAR4;
wire VAR6;
wire VAR1;
wire VAR5;
reg [ 31: 0] VAR2;
assign VAR6 = 1;
assign VAR5 = {1 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR4)
begin
if (VAR4 == 0)
VAR2 <= 0;
end
el... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/16-way_2-tree/src/top.v | 20,716 | module MODULE1 #(parameter VAR171 = 1, parameter VAR186 = 8,
parameter VAR79 = 128,
parameter VAR174 = 256,
parameter VAR21 = 6)
(output [(VAR186 - 1) : 0] VAR80,
output [(VAR186 - 1) : 0] VAR106,
input [(VAR186 - 1) : 0] VAR121,
input [(VAR186 - 1) : 0] VAR59,
output [3:0] VAR52,
input VAR214,
input VAR17,
input VAR5,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15.functional.v | 1,343 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
wire VAR3;
buf VAR5 (VAR3, VAR2 );
buf VAR1 (VAR4 , VAR3 );
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_reset_controller_171/synth/altera_reset_synchronizer.v | 3,468 | module MODULE1
parameter VAR6 = 1,
parameter VAR2 = 2
)
(
input VAR5 ,
input clk,
output VAR4
);
reg [VAR2-1:0] VAR1;
reg VAR3;
generate if (VAR6) begin
always @(posedge clk or posedge VAR5) begin
if (VAR5) begin
VAR1 <= {VAR2{1'b1}};
VAR3 <= 1'b1;
end
else begin
VAR1[VAR2-2:0] <= VAR1[VAR2-1:1];
VAR1[VAR2-1] <= 0;
VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_1.behavioral.pp.v | 1,316 | module MODULE1( VAR8, VAR7, VAR2, VAR6, VAR5, VAR1 );
input VAR8, VAR2, VAR7;
inout VAR5, VAR1;
output VAR6;
VAR3 VAR4(.VAR8(VAR8),.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1));
VAR3 VAR9(.VAR8(VAR8),.VAR7(VAR7),.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp_2.v | 2,128 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR8 ,
VAR4,
VAR7,
VAR3 ,
VAR5
);
output VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR4;
input VAR7;
input VAR3 ;
input VAR5 ;
VAR9 VAR1 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR2 ,
VAR6,
VAR8
);
output VAR2 ... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp1/inband_lib/channel_demux.v | 1,919 | module MODULE1
input VAR4,
input reset,
input VAR5,
output reg [VAR10:0] VAR9,
output reg [31:0] VAR17,
output reg [VAR10:0] VAR7 );
reg [2:0]VAR8;
reg [4:0]VAR11 ;
reg [6:0]VAR15 ;
parameter VAR3 = 3'd0;
parameter VAR1 = 3'd1;
parameter VAR2 = 3'd2;
parameter VAR13 = 3'd3;
wire [4:0] VAR14;
assign VAR14 = (VAR12[VAR16... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2.pp.blackbox.v | 1,291 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR7 ,
VAR3,
VAR4,
VAR1 ,
VAR6
);
output VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbn/sky130_fd_sc_hd__sdfbbn_1.v | 2,825 | module MODULE2 (
VAR10 ,
VAR6 ,
VAR3 ,
VAR12 ,
VAR1 ,
VAR7 ,
VAR14 ,
VAR8,
VAR11 ,
VAR13 ,
VAR2 ,
VAR9
);
output VAR10 ;
output VAR6 ;
input VAR3 ;
input VAR12 ;
input VAR1 ;
input VAR7 ;
input VAR14 ;
input VAR8;
input VAR11 ;
input VAR13 ;
input VAR2 ;
input VAR9 ;
VAR5 VAR4 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),... | apache-2.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_led.v | 2,184 | module MODULE1 (
address,
VAR3,
clk,
VAR4,
VAR9,
VAR7,
VAR5,
VAR6
)
;
output [ 7: 0] VAR5;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR4;
input VAR9;
input [ 31: 0] VAR7;
wire VAR8;
reg [ 7: 0] VAR1;
wire [ 7: 0] VAR5;
wire [ 7: 0] VAR2;
wire [ 31: 0] VAR6;
assign VAR8 = 1;
assign VAR2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2b/sky130_fd_sc_ls__or2b_4.v | 2,127 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR4 ,
VAR2,
VAR5,
VAR7 ,
VAR8
);
output VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR2;
input VAR5;
input VAR7 ;
input VAR8 ;
VAR9 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR6 ,
VAR1 ,
VAR4
);
output VAR6... | apache-2.0 |
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