repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
xuwenyihust/MapReduce_NoC | RTL/node_noc.v | 5,242 | module MODULE1(clk, rst, VAR3, VAR30, VAR6, VAR22, VAR20);
parameter VAR4 = 4'b0000;
parameter VAR29 = 4'b1111;
parameter VAR17 = 4'b0001;
parameter VAR5 = 4'b0010;
parameter VAR35 = 4'b0011;
parameter VAR21 = 10;
input clk;
input rst;
input [31:0] VAR3;
input VAR30;
input VAR6;
output reg [31:0] VAR22;
output reg VAR2... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_fast_cfg_init_cntr.v | 3,132 | module MODULE1 #(
parameter VAR4 = 8,
parameter VAR3 = 8'hA5,
parameter VAR1 = 1
) (
input clk,
input rst,
output reg [VAR4-1:0] VAR2
);
always @(posedge clk) begin
if(rst) begin
end else begin
if(VAR2 != VAR3) begin
end
end
end
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi.pp.blackbox.v | 1,306 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR5 ,
VAR3 ,
VAR4,
VAR6
);
output VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR6;
endmodule | apache-2.0 |
carstenbru/fpga-log | spartanmc/hardware/pwm/src/spmc_pwm.v | 4,872 | module MODULE1 #(
parameter VAR14 = 2, parameter VAR15 = 10'h0) (
input wire VAR35, input wire [17:0] VAR26, output wire [17:0] VAR4, input wire [9:0] VAR33, input wire VAR1, input wire VAR13,
input wire reset,
output wire [VAR14-1:0] VAR38
);
parameter VAR34 = 32;
parameter VAR39 = 2'b00;
parameter VAR12 = 2'b01;
para... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31o/sky130_fd_sc_hdll__a31o.pp.blackbox.v | 1,391 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR5 ,
VAR6 ,
VAR9 ,
VAR2,
VAR4,
VAR8 ,
VAR7
);
output VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR9 ;
input VAR2;
input VAR4;
input VAR8 ;
input VAR7 ;
endmodule | apache-2.0 |
m-labs/milkymist | cores/softusb/rtl/softusb_timer.v | 1,265 | module MODULE1(
input VAR3,
input VAR5,
input VAR4,
input [5:0] VAR1,
output reg [7:0] VAR2
);
reg [31:0] counter;
always @(posedge VAR3) begin
if(VAR5) begin
counter <= 32'd0;
VAR2 <= 8'd0;
end else begin
VAR2 <= 8'd0;
case(VAR1)
6'h20: VAR2 <= counter[7:0];
6'h21: VAR2 <= counter[15:8];
6'h22: VAR2 <= counter[23:16];... | lgpl-3.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_iodelay2.v | 1,710 | module MODULE1 #(
parameter VAR23 = 30
) (
input [1:0] VAR10,
output [1:0] VAR12,
input [1:0] VAR13,
output [1:0] VAR14,
input [1:0] VAR17,
output [1:0] VAR18,
input VAR3,
input VAR7,
input VAR4,
input VAR6,
input VAR9,
input VAR2,
input VAR16
);
VAR11 #(
.VAR22("VAR5"),
.VAR15("VAR20"),
.VAR8("VAR19"),
.VAR23(VAR23)
)... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbn/sky130_fd_sc_ms__dlxbn.blackbox.v | 1,339 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR1 ,
VAR2
);
output VAR7 ;
output VAR4 ;
input VAR1 ;
input VAR2;
supply1 VAR8;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.functional.v | 1,778 | module MODULE1( VAR13, VAR16, VAR4, VAR18, VAR22 );
input VAR18, VAR22, VAR16, VAR13;
output VAR4;
wire VAR15;
not VAR11( VAR15, VAR18 );
wire VAR14;
not VAR6( VAR14, VAR16 );
wire VAR21;
and VAR19( VAR21, VAR15, VAR14 );
wire VAR5;
not VAR10( VAR5, VAR13 );
wire VAR8;
and VAR7( VAR8, VAR15, VAR5 );
wire VAR3;
not VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha.functional.pp.v | 2,194 | module MODULE1 (
VAR18,
VAR7 ,
VAR2 ,
VAR14 ,
VAR19,
VAR5,
VAR3 ,
VAR1
);
output VAR18;
output VAR7 ;
input VAR2 ;
input VAR14 ;
input VAR19;
input VAR5;
input VAR3 ;
input VAR1 ;
wire VAR4 ;
wire VAR16;
wire VAR11 ;
wire VAR17 ;
and VAR13 (VAR4 , VAR2, VAR14 );
VAR10 VAR6 (VAR16, VAR4, VAR19, VAR5);
buf VAR12 (VAR18 ,... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/ipcore_dir/rx_fifo_blank.v | 2,960 | module MODULE1(
rst,
VAR7,
VAR5,
din,
VAR6,
VAR1,
dout,
VAR2,
VAR4,
VAR3
);
input rst;
input VAR7;
input VAR5;
input [7 : 0] din;
input VAR6;
input VAR1;
output [63 : 0] dout;
output VAR2;
output VAR4;
output [7 : 0] VAR3;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbn/sky130_fd_sc_hs__dfbbn.symbol.v | 1,449 | module MODULE1 (
input VAR8 ,
output VAR1 ,
output VAR6 ,
input VAR7,
input VAR4 ,
input VAR3
);
supply1 VAR2;
supply0 VAR5;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.functional.pp.v | 1,583 | module MODULE1( VAR3, VAR16, VAR9, VAR1, VAR5, VAR2 );
input VAR16, VAR3, VAR9;
inout VAR5, VAR2;
output VAR1;
wire VAR15;
and VAR12( VAR15, VAR16, VAR3, VAR9 );
wire VAR4;
not VAR21( VAR4, VAR3 );
wire VAR7;
not VAR6( VAR7, VAR9 );
wire VAR19;
and VAR13( VAR19, VAR4, VAR7, VAR16 );
wire VAR17;
not VAR10( VAR17, VAR16 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i_1.v | 2,214 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR1 ,
VAR10 ,
VAR4,
VAR3,
VAR7 ,
VAR9
);
output VAR8 ;
input VAR2 ;
input VAR1 ;
input VAR10 ;
input VAR4;
input VAR3;
input VAR7 ;
input VAR9 ;
VAR6 VAR5 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb_4.v | 2,323 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR4 ,
VAR11 ,
VAR10 ,
VAR2,
VAR7,
VAR6 ,
VAR9
);
output VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR11 ;
input VAR10 ;
input VAR2;
input VAR7;
input VAR6 ;
input VAR9 ;
VAR1 VAR8 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.... | apache-2.0 |
SymbiFlow/prjxray | experiments/clbpips/top.v | 1,863 | module MODULE2(input clk, VAR22, VAR27, output do);
localparam integer VAR13 = 10;
localparam integer VAR29 = 10;
reg [VAR13-1:0] din;
wire [VAR29-1:0] dout;
reg [VAR13-1:0] VAR12;
reg [VAR29-1:0] VAR17;
always @(posedge clk) begin
VAR12 <= {VAR12, VAR27};
VAR17 <= {VAR17, VAR12[VAR13-1]};
if (VAR22) begin
din <= VAR12... | isc |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_charSent.v | 2,273 | module MODULE1 (
address,
VAR3,
clk,
VAR7,
VAR2,
VAR8,
VAR5,
VAR4
)
;
output VAR5;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR7;
input VAR2;
input [ 31: 0] VAR8;
wire VAR1;
reg VAR9;
wire VAR5;
wire VAR6;
wire [ 31: 0] VAR4;
assign VAR1 = 1;
assign VAR6 = {1 {(address == 0)}} & VAR9;
a... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor3/sky130_fd_sc_ls__xor3.pp.blackbox.v | 1,322 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR1 ,
VAR8 ,
VAR4,
VAR6,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR8 ;
input VAR4;
input VAR6;
input VAR7 ;
input VAR3 ;
endmodule | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_data_fifo.v | 10,755 | module MODULE1(
parameter VAR1 = 128,
parameter VAR40 = 1,
parameter VAR11 = 1,
parameter VAR16 = 256 )
(
input VAR41,
input VAR32,
input [VAR1-1:0] VAR60,
input VAR35,
input VAR66,
input [(VAR1/32)-1:0] VAR7,
input [(VAR1/32)-1:0] VAR55,
output VAR18,
input [(VAR1/32)-1:0] VAR30,
output [VAR1-1:0] VAR24,
output VAR51,... | bsd-3-clause |
marshmellow42/proxmark3 | fpga/hi_iso14443a.v | 19,749 | module MODULE1(
VAR37,
VAR44, VAR31, VAR23, VAR55, VAR5, VAR38,
VAR59, VAR53,
VAR11, VAR46, VAR14, VAR4,
VAR18,
VAR54
);
input VAR37;
output VAR44, VAR31, VAR23, VAR55, VAR5, VAR38;
input [7:0] VAR59;
output VAR53;
input VAR14;
output VAR11, VAR46, VAR4;
output VAR18;
input [2:0] VAR54;
wire VAR53 = VAR37;
reg VAR50;
r... | gpl-2.0 |
yunqu/PYNQ | boards/ip/gclk_generator_1.0/hdl/gclk_generator_v1_0_S_AXI.v | 14,937 | module MODULE1 #
(
parameter integer VAR15 = 16,
parameter integer VAR14 = 32,
parameter integer VAR10 = 4
)
(
input wire VAR26,
output wire [2:0] VAR55,
input wire VAR4,
input wire VAR31,
input wire [VAR10-1 : 0] VAR54,
input wire [2 : 0] VAR21,
input wire VAR29,
output wire VAR45,
input wire [VAR14-1 : 0] VAR33,
inpu... | bsd-3-clause |
csturton/wirepatch | system/hardware/cores/arbiter/arbiter_dbus.v | 37,253 | module MODULE1
(
VAR1,
VAR26,
VAR48,
VAR25,
VAR86,
VAR8,
VAR82,
VAR37,
VAR19,
VAR47,
VAR53,
VAR77,
VAR70,
VAR36,
VAR91,
VAR66,
VAR71,
VAR49,
VAR78,
VAR112,
VAR85,
VAR92,
VAR33,
VAR59,
VAR114,
VAR121,
VAR31,
VAR98,
VAR57,
VAR124,
VAR106,
VAR79,
VAR15,
VAR83,
VAR100,
VAR27,
VAR95,
VAR58,
VAR61,
VAR68,
VAR20,
VAR69,
VAR16... | mit |
emeb/iceRadio | FPGA/rxadc_2/verilog/src/rxadc_2.v | 7,507 | module MODULE1 #(
parameter VAR47 = 10,
VAR23 = 26,
VAR101 = 16
)
(
input VAR71,
input VAR31,
output VAR57,
input VAR96,
input VAR41,
output VAR52,
input VAR90,
input [9:0] VAR39,
output VAR55,
output VAR93,
output VAR46,
output VAR82,
input VAR97,
output VAR11,
output VAR106,
output VAR8,
output wire VAR27,
output wir... | mit |
leviathanch/qtflow | tech/osu050/osu05_stdcells.v | 23,882 | module MODULE1 (VAR2, VAR1, VAR3);
input VAR2 ;
input VAR1 ;
output VAR3 ;
and (VAR3, VAR2, VAR1); | lgpl-3.0 |
peteasa/oh | src/elink/hdl/etx_io.v | 5,859 | module MODULE1 (
VAR11, VAR8, VAR54, VAR64, VAR69,
VAR25, VAR52, VAR15,
VAR48, VAR10, VAR53, VAR3, VAR59,
VAR44, VAR12, VAR19, VAR27
);
parameter VAR20 = "VAR33";
parameter VAR32 = 104;
parameter VAR50 = 0; input VAR48; input VAR10; input VAR53;
output VAR11, VAR8; output VAR54, VAR64; output [7:0] VAR69, VAR25; input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill_diode/sky130_fd_sc_hs__fill_diode.pp.blackbox.v | 1,204 | module MODULE1 (
VAR3,
VAR2,
VAR1 ,
VAR4
);
input VAR3;
input VAR2;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_poc_edge_store.v | 4,856 | module MODULE1 #
(parameter VAR16 = 100,
parameter VAR17 = 7,
parameter VAR20 = 112)
(
VAR8, VAR21, VAR6, VAR22,
clk, VAR10, VAR5, VAR18, VAR19, VAR14, VAR2
);
input clk;
input VAR10;
input VAR5;
input VAR18;
input VAR19;
input [VAR17-1:0] VAR14;
input [VAR17-1:0] VAR2;
wire [VAR17:0] VAR12 = VAR2 > VAR14 ? VAR14 + VAR... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/01BLUETOOTH/Version_02/02 verilog/Prueba1/transmision.v | 1,364 | module MODULE1 (input enable,
input wire [7:0] dout,
output VAR2,
output reg VAR5,
input wire VAR1,
output reg VAR3);
parameter VAR4 = 8; | gpl-3.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v2_0_round_robin_arb.v | 7,553 | module MODULE1
parameter VAR20 = 100,
parameter VAR17 = 3
)
(
VAR7, VAR8,
clk, rst, req, VAR4, VAR5, VAR13
);
input clk;
input rst;
input [VAR17-1:0] req;
wire [VAR17-1:0] VAR9;
reg [VAR17*2-1:0] VAR2;
always @(VAR9)
VAR2 = {VAR9, VAR9};
reg [VAR17*2-1:0] VAR10;
always @(req) VAR10 = {req, req};
reg [VAR17-1:0] VAR18 =... | bsd-2-clause |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/packetparse.v | 9,723 | module MODULE1(reset, VAR1, VAR10, VAR6, VAR19, VAR28,
VAR4, VAR16, VAR9,
VAR8, VAR21, VAR29,
VAR3, VAR13 );
input reset, VAR1, VAR10;
input [8:0] VAR6;
input [15:0] VAR4;
input [15:0] VAR16;
output VAR9;
output [3:0] VAR19;
output [2:0] VAR28;
output [1:0] VAR8;
output [7:0] VAR21;
output [7:0] VAR29;
output VAR3, VAR... | gpl-3.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/verilog/axi_vdma_v6_2_axis_dwidth_converter_v1_0_axisc_downsizer.v | 14,210 | module MODULE1 #
(
parameter VAR6 = "VAR33",
parameter integer VAR7 = 96,
parameter integer VAR75 = 32,
parameter integer VAR48 = 1,
parameter integer VAR4 = 1,
parameter integer VAR64 = 3,
parameter integer VAR62 = 1,
parameter [31:0] VAR1 = 32'hFF ,
parameter integer VAR9 = 3 )
(
input wire VAR23,
input wire VAR73,
i... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrtp/sky130_fd_sc_hvl__dfrtp.blackbox.v | 1,341 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR4;
supply1 VAR6;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4bb/sky130_fd_sc_hdll__nor4bb.functional.pp.v | 2,018 | module MODULE1 (
VAR2 ,
VAR16 ,
VAR13 ,
VAR11 ,
VAR12 ,
VAR5,
VAR17,
VAR4 ,
VAR1
);
output VAR2 ;
input VAR16 ;
input VAR13 ;
input VAR11 ;
input VAR12 ;
input VAR5;
input VAR17;
input VAR4 ;
input VAR1 ;
wire VAR10 ;
wire VAR8 ;
wire VAR9;
nor VAR7 (VAR10 , VAR16, VAR13 );
and VAR15 (VAR8 , VAR10, VAR11, VAR12 );
VAR1... | apache-2.0 |
liqimai/Assignment1-Calculator | Integer-Arithmetic/AdderAndSuuber64/Adder64.v | 1,230 | module MODULE1(
input [63:0] VAR26,
input [63:0] VAR13,
input VAR18,
output [3:0] VAR25,
output [3:0] VAR3,
output [63:0] sum,
output VAR16,
output VAR1,
output VAR6,
output VAR11,
output VAR21
);
wire[15:0] VAR24,VAR12;
wire[4:0] VAR17;
wire[3:0] VAR20,VAR23,VAR14,VAR9,VAR4;
VAR7 VAR7(VAR24,VAR12,VAR25,VAR3);
VAR15 VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21boi/sky130_fd_sc_ls__a21boi.behavioral.pp.v | 2,172 | module MODULE1 (
VAR1 ,
VAR17 ,
VAR10 ,
VAR15,
VAR14,
VAR12,
VAR6 ,
VAR7
);
output VAR1 ;
input VAR17 ;
input VAR10 ;
input VAR15;
input VAR14;
input VAR12;
input VAR6 ;
input VAR7 ;
wire VAR5 ;
wire VAR9 ;
wire VAR8 ;
wire VAR13;
not VAR3 (VAR5 , VAR15 );
and VAR18 (VAR9 , VAR17, VAR10 );
nor VAR2 (VAR8 , VAR5, VAR9 )... | apache-2.0 |
klaNath/synth1 | pwm_out.v | 1,454 | module MODULE1(
input wire clk,
input wire VAR3,
output reg VAR2,
input wire VAR6,
input wire [31:0] VAR5,
output wire VAR9,
output wire VAR1);
reg VAR4;
reg [11:0] VAR11;
reg [31:0] VAR8, VAR10;
always @(posedge clk, negedge VAR3)
begin
if(!VAR3)
begin
VAR11 <= 0;
VAR2 <= 0;
VAR8 <= 0;
VAR10 <= 0;
VAR4 <= 0;
end
else
... | lgpl-3.0 |
alan4186/Hardware-CNN | DE2_115_CAMERA/v/I2C_CCD_Config.v | 8,209 | module MODULE1 ( VAR9,
VAR24,
VAR6,
VAR40,
VAR27,
VAR33,
VAR16
);
input VAR9;
input VAR24;
input VAR6;
output VAR33;
inout VAR16;
reg [15:0] VAR26;
reg [31:0] VAR23;
reg VAR43;
reg VAR44;
wire VAR30;
wire VAR5;
reg [23:0] VAR14;
reg [5:0] VAR25;
reg [3:0] VAR20;
input VAR40;
input VAR27;
parameter VAR45 = 16'h07c0;
par... | mit |
migajv/mips_pipeline | verilog/arbiter.v | 1,405 | module MODULE1
(
input [VAR2-1:0] req,
input enable,
input clk,
input rst,
output reg [VAR2-1:0] VAR6,
output VAR5
);
parameter VAR9 = VAR3(VAR2);
logic [VAR9-1:0] VAR4;
logic [2*VAR2-1:0] VAR10;
logic [VAR2-1:0] VAR7;
logic [2*VAR2-1:0] VAR1;
logic [VAR2-1:0] VAR8;
assign VAR10 = {req,req} >> VAR4;
assign VAR7 = VAR10... | gpl-3.0 |
P3Stor/P3Stor | DDR3/phy/phy_dqs_iob.v | 13,358 | module MODULE1 #
(
parameter VAR40 = 100, parameter VAR29 = "VAR132", parameter VAR159 = 300.0, parameter VAR122 = "VAR62", parameter VAR53 = "VAR57", parameter VAR21 = "VAR107" )
(
input VAR119, input clk, input VAR138, input VAR133, input rst, input VAR3, input [4:0] VAR98, input [3:0] VAR104, input [3:0] VAR68, inpu... | gpl-2.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_mem2reg.v | 11,247 | module MODULE1(addr, VAR1, VAR25, VAR9);
parameter VAR22 = VAR12;
input [1:0] addr;
input [VAR10-1:0] VAR1;
input [VAR22-1:0] VAR25;
output [VAR22-1:0] VAR9;
reg [7:0] VAR14;
reg [7:0] VAR8;
reg [7:0] VAR23;
reg [7:0] VAR28;
reg [VAR22-1:0] VAR18;
reg [3:0] VAR7, VAR3,
VAR15, VAR5;
assign VAR9 = {VAR14, VAR8, VAR23, VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32oi/sky130_fd_sc_hs__a32oi_1.v | 2,356 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR4 ,
VAR8 ,
VAR5,
VAR1
);
output VAR9 ;
input VAR2 ;
input VAR6 ;
input VAR7 ;
input VAR4 ;
input VAR8 ;
input VAR5;
input VAR1;
VAR3 VAR10 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE1 ... | apache-2.0 |
linuxbest/lzs | pcores/comp_unit_v1_00_a/hdl/verilog/crc.v | 8,182 | module MODULE1 (
VAR1,
clk, VAR2, VAR7, VAR4
);
input clk;
input VAR2;
input [31:0] VAR7;
input VAR4;
output [31:0] VAR1;
reg VAR5;
wire [31:0] VAR3;
wire [31:0] VAR6;
reg [31:0] VAR1;
always @(posedge clk)
begin
if(VAR2)
VAR1 <= 32'h52325032;
end
else if(VAR4)
begin
VAR1 <= VAR3;
end
end
assign VAR6 = VAR7 ^ VAR1 ;
as... | gpl-2.0 |
sabertazimi/hust-lab | verilog/labs/lab2/src/_8_to_3_priority_encoder.v | 1,284 | module MODULE1(
module 8to3priorityencoder(
input [7:0] VAR10,
input VAR3,
output reg [2:0] VAR13,
output reg VAR7,
output reg VAR2
);
always @(VAR10 or VAR3) begin
case ({VAR3, VAR10})
9'VAR1: {VAR13, VAR2, VAR7} = 5'b11111;
9'b011111111: {VAR13, VAR2, VAR7} = 5'b11110;
9'VAR9: {VAR13, VAR2, VAR7} = 5'b00001;
9'VAR6: ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbn/sky130_fd_sc_lp__dfbbn.functional.pp.v | 2,454 | module MODULE1 (
VAR24 ,
VAR17 ,
VAR15 ,
VAR7 ,
VAR9 ,
VAR22,
VAR5 ,
VAR20 ,
VAR19 ,
VAR16
);
output VAR24 ;
output VAR17 ;
input VAR15 ;
input VAR7 ;
input VAR9 ;
input VAR22;
input VAR5 ;
input VAR20 ;
input VAR19 ;
input VAR16 ;
wire VAR14 ;
wire VAR12 ;
wire VAR18 ;
wire VAR6 ;
wire VAR4 ;
wire VAR10;
wire VAR2 ;
n... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a.symbol.v | 1,331 | module MODULE1 (
input VAR1,
input VAR6,
input VAR7,
input VAR4,
output VAR3
);
supply1 VAR5;
supply0 VAR2;
endmodule | apache-2.0 |
elegabriel/myzju | junior1/CA/LAB/lab5/code/cpu_ctl.v | 2,955 | module MODULE1(VAR8,VAR18,VAR38,VAR36,VAR26,VAR13,VAR30,VAR28,VAR6,VAR3,VAR31,VAR11,VAR10,VAR20,VAR33
);
input wire [5:0] VAR8, VAR18;
input wire VAR38;
output wire VAR36,VAR26,VAR13,VAR30,VAR28,VAR6,VAR3,VAR31,VAR11,VAR10,VAR20;
output wire [4:0] VAR33;
wire VAR34, VAR14, VAR29, VAR37, VAR4; wire VAR23, VAR1, VAR7, VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxbp/sky130_fd_sc_ms__dfxbp.functional.v | 1,578 | module MODULE1 (
VAR1 ,
VAR2,
VAR4,
VAR7
);
output VAR1 ;
output VAR2;
input VAR4;
input VAR7 ;
wire VAR10;
VAR3 VAR9 VAR5 (VAR10 , VAR7, VAR4 );
buf VAR8 (VAR1 , VAR10 );
not VAR6 (VAR2 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn_0.v | 2,150 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR4,
VAR8,
VAR5,
VAR3 ,
VAR9
);
output VAR1 ;
input VAR7 ;
input VAR4;
input VAR8;
input VAR5;
input VAR3 ;
input VAR9 ;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR1 ,
VAR7 ,
VAR4
);
output VAR1 ;... | apache-2.0 |
lvd2/zxevo | fpga/base_trdemu/trunk/video/video_top.v | 8,875 | module MODULE1(
input wire clk,
output wire [ 1:0] VAR32,
output wire [ 1:0] VAR85,
output wire [ 1:0] VAR28,
output wire VAR26,
output wire VAR48,
output wire VAR71,
input wire [ 3:0] VAR87,
input wire [ 1:0] VAR86,
input wire [ 2:0] VAR80,
input wire VAR70,
input wire VAR4,
input wire [ 1:0] VAR29,
input wire VAR73,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ba/sky130_fd_sc_hdll__o21ba.behavioral.pp.v | 2,057 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR13 ,
VAR1,
VAR7,
VAR11,
VAR15 ,
VAR4
);
output VAR8 ;
input VAR2 ;
input VAR13 ;
input VAR1;
input VAR7;
input VAR11;
input VAR15 ;
input VAR4 ;
wire VAR12 ;
wire VAR9 ;
wire VAR3;
nor VAR16 (VAR12 , VAR2, VAR13 );
nor VAR10 (VAR9 , VAR1, VAR12 );
VAR14 VAR5 (VAR3, VAR9, VAR7, VAR11);
... | apache-2.0 |
alanachtenberg/CSCE-350 | Lab6/lab6_5dec.v | 1,467 | module MODULE1(VAR10, VAR1);
output [7:0]VAR10; reg [7:0]VAR10;
input [2:0] VAR1;
always @ (VAR1)
case (VAR1)
3'b000: VAR10=8'b00000001;
3'b001: VAR10=8'b00000010;
3'b010: VAR10=8'b00000100;
3'b011: VAR10=8'b00001000;
3'b100: VAR10=8'b00010000;
3'b101: VAR10=8'b00100000;
3'b110: VAR10=8'b01000000;
3'b111: VAR10=8'b1000... | gpl-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/NormaliseProdMultDescale.v | 2,555 | module MODULE1(
input [32:0] VAR13,
input [49:0] VAR11,
input [7:0] VAR17,
input VAR4,
input [31:0] VAR16,
input VAR5,
input VAR3,
output reg VAR8,
output reg [32:0] VAR18,
output reg [49:0] VAR7,
output reg [7:0] VAR9,
output reg VAR2,
output reg [31:0] VAR12
);
parameter VAR10 = 1'b0,
VAR6 = 1'b1;
wire VAR15;
wire [7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp.behavioral.v | 2,130 | module MODULE1 (
VAR16 ,
VAR5 ,
VAR21 ,
VAR18
);
output VAR16 ;
input VAR5 ;
input VAR21 ;
input VAR18;
supply1 VAR14;
supply0 VAR6;
supply1 VAR13 ;
supply0 VAR11 ;
wire VAR9 ;
wire VAR8 ;
reg VAR19 ;
wire VAR10 ;
wire VAR2;
wire VAR1 ;
wire VAR4 ;
wire VAR20 ;
wire VAR3 ;
not VAR17 (VAR8 , VAR2 );
VAR12 VAR7 (VAR9 , V... | apache-2.0 |
red0bear/AES128 | rtl/key_expander.v | 4,985 | module MODULE1
(
output [127:0] VAR21,
output [ 31:0] VAR17,
input [ 31:0] VAR5,
input [127:0] VAR15,
input [ 3:0] VAR13,
input VAR14,
input VAR7
);
localparam integer VAR4 = 32;
localparam integer VAR6 = 4;
localparam integer VAR26 = 8;
localparam integer VAR18 = 10;
wire [VAR4 - 1 : 0] VAR9 [0 : VAR6 - 1];
wire [ VAR... | lgpl-3.0 |
tuura/workcraft | ci/substitution-rules/vme-tm.workcraft.v | 2,632 | module MODULE1 (VAR23, VAR67, VAR40, VAR22, VAR20, VAR19);
input VAR22, VAR20, VAR19;
output VAR23, VAR67, VAR40;
wire VAR34, VAR44, VAR58, VAR38, VAR59, VAR52, VAR29, VAR15, VAR46, VAR31, VAR57, VAR2, VAR43, VAR6, VAR17, VAR51, VAR28, VAR63;
VAR39 VAR50 (.VAR30(VAR34), .VAR41(VAR28), .VAR42(VAR19), .VAR1(VAR22));
VAR1... | mit |
fallen/milkymist-mmu | cores/ac97/rtl/ac97_framer.v | 4,835 | module MODULE1(
input VAR10,
input VAR17,
input VAR4,
output VAR13,
output reg VAR7,
output reg VAR15,
input en,
output reg VAR16,
input VAR1,
input [19:0] addr,
input VAR2,
input [19:0] VAR11,
input VAR8,
input [19:0] VAR12,
input VAR3,
input [19:0] VAR5
);
reg [7:0] VAR14;
reg VAR18;
always @(*) begin
case(VAR14)
8'd... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.v | 2,377 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR9 ,
VAR7 ,
VAR5,
VAR10 ,
VAR4 ,
VAR1 ,
VAR3
);
output VAR8 ;
output VAR6 ;
input VAR9 ;
input VAR7 ;
input VAR5;
input VAR10 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
VAR2 VAR11 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.behavioral.v | 1,336 | module MODULE1( VAR4, VAR1, VAR6, VAR3, VAR7 );
input VAR7, VAR3, VAR1, VAR4;
output VAR6;
VAR5 VAR8(.VAR4(VAR4),.VAR1(VAR1),.VAR6(VAR6),.VAR3(VAR3),.VAR7(VAR7));
VAR5 VAR2(.VAR4(VAR4),.VAR1(VAR1),.VAR6(VAR6),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/soc_system_onchip_memory2_0.v | 3,158 | module MODULE1 (
address,
VAR5,
VAR4,
clk,
VAR34,
VAR30,
reset,
VAR15,
write,
VAR35,
VAR9
)
;
parameter VAR27 = "MODULE1.VAR23";
output [ 63: 0] VAR9;
input [ 12: 0] address;
input [ 7: 0] VAR5;
input VAR4;
input clk;
input VAR34;
input VAR30;
input reset;
input VAR15;
input write;
input [ 63: 0] VAR35;
wire VAR24;
wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbn/sky130_fd_sc_hd__sdfbbn.pp.blackbox.v | 1,558 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR11 ,
VAR12 ,
VAR3 ,
VAR5 ,
VAR8 ,
VAR4,
VAR10 ,
VAR7 ,
VAR9 ,
VAR1
);
output VAR2 ;
output VAR6 ;
input VAR11 ;
input VAR12 ;
input VAR3 ;
input VAR5 ;
input VAR8 ;
input VAR4;
input VAR10 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
endmodule | apache-2.0 |
efabless/openlane | designs/aes/src/aes.v | 83,434 | module MODULE1(
input wire clk,
input wire VAR70,
input wire VAR198,
input wire VAR13,
input wire [7 : 0] address,
input wire [31 : 0] VAR92,
output wire [31 : 0] VAR176
);
localparam VAR16 = 8'h00;
localparam VAR221 = 8'h01;
localparam VAR210 = 8'h02;
localparam VAR123 = 8'h08;
localparam VAR145 = 0;
localparam VAR189... | apache-2.0 |
vvk/sysrek | rgb2hsv/src/rx_nok/decode_nok.v | 11,378 | module MODULE1 # (
parameter VAR8 = "VAR12"
)
(
input wire reset, input wire VAR17, input wire VAR62, input wire VAR35, input wire VAR41, input wire VAR49, input wire VAR5, input wire VAR29, input wire VAR14, input wire VAR46, input wire VAR19, input wire VAR55, input wire VAR39,
output wire VAR31, output wire VAR43, o... | gpl-2.0 |
neale/MachX02 | Voltmeter/TopModel.v | 1,711 | module MODULE1 (
input [7:0] VAR3,
input VAR8,
output VAR30,
output [6:0] VAR15,
output [2:0] VAR12,
output VAR22,
output VAR20,
output VAR31
);
integer VAR23;
wire clk;
wire VAR19;
reg [3:0] VAR17;
reg [3:0] VAR9;
reg [3:0] VAR2;
reg [3:0] VAR18;
wire [3:0] VAR16;
always@(*) begin
VAR23 = VAR3; VAR18 = (((VAR23 * 5000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2.pp.blackbox.v | 1,260 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR6 ,
VAR1,
VAR3,
VAR5 ,
VAR2
);
output VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR3;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_s6_x1_125/source/pcie_brams_s6.v | 8,155 | module MODULE1 #(
parameter VAR15 = 0,
parameter VAR13 = 1,
parameter VAR14 = 1,
parameter VAR6 = 1
) (
input VAR4,
input VAR10,
input VAR11,
input [11:0] VAR16,
input [35:0] VAR3,
input VAR9,
input VAR1,
input [11:0] VAR12,
output [35:0] VAR8
);
localparam VAR5 = (VAR14 > 1) ? 1 : 0;
localparam [6:0] VAR7 = ((VAR15 ==... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tap/sky130_fd_sc_ms__tap.pp.symbol.v | 1,217 | module MODULE1 (
input VAR1 ,
input VAR4,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_dmmu_tlb.v | 8,666 | module MODULE1(
clk, rst,
VAR15, VAR12, VAR21, VAR43, VAR33, VAR19, VAR57, VAR25, VAR16,
VAR18, VAR58, VAR10,
VAR7, VAR6, VAR23, VAR13, VAR48
);
parameter VAR32 = VAR17;
parameter VAR9 = VAR17;
input clk;
input rst;
input VAR15;
input [VAR9-1:0] VAR12;
output VAR21;
output [31:VAR56] VAR43;
output VAR33;
output VAR19;
... | gpl-3.0 |
mshaklunov/mips_onemore | rtl/mips_fifosync.v | 1,653 | module MODULE1 #(parameter VAR6= 8,
parameter VAR5= 4)
(
input clk,
input rst,
input VAR9,
input[VAR6-1:0] VAR11,
input VAR7,
output[VAR6-1:0] VAR14,
output VAR13,
output VAR3
);
localparam VAR2= 1<<VAR5;
reg[VAR6-1:0] VAR12[VAR2-1:0];
reg[VAR5:0] VAR8;
reg[VAR5:0] VAR10;
assign VAR14= VAR12[VAR10[VAR5-1:0]];
assign VA... | mit |
open-power/snap | actions/hdl_helloworld/hw/hdl/axi_lite_slave.v | 11,962 | module MODULE1 #(
parameter VAR37 = 32,
parameter VAR65 = 32
)(
input clk ,
input VAR31 ,
output reg VAR27 ,
input [VAR65 - 1:0] VAR2 ,
input [02:0] VAR38 ,
input VAR53 ,
output reg VAR25 ,
input [VAR37 - 1:0] VAR24 ,
input [(VAR37/8) - 1:0] VAR47 ,
input VAR12 ,
output [01:0] VAR4 ,
output reg VAR56 ,
input VAR58 ,
ou... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221oi/sky130_fd_sc_hs__a221oi.pp.symbol.v | 1,376 | module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR4 ,
input VAR6 ,
input VAR7 ,
output VAR3 ,
input VAR8,
input VAR5
);
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_spi/rtl/wb_spi.v | 12,817 | module MODULE1 #(
parameter VAR10 = 8
)(
input clk,
input rst,
input VAR25,
input VAR47,
input VAR13,
input [31:0] VAR49,
input [31:0] VAR36,
output reg [31:0] VAR35,
output reg VAR43,
output reg VAR63,
output [31:0] VAR23, output VAR58, output VAR37, input VAR19 );
localparam VAR18 = 2 ** VAR10;
localparam VAR70 = VAR... | mit |
hoglet67/opc | system/avnet_microboard/wrapper.v | 2,526 | module MODULE1
(
input VAR56,
output VAR46,
output [0:0] VAR8,
inout VAR26,
inout VAR44,
inout VAR3,
inout VAR24,
input VAR39,
input VAR17,
input VAR14,
input VAR34,
input VAR4,
output [3:0] VAR51,
input VAR31,
output VAR20,
inout VAR47,
input VAR25,
output [12:0] VAR30,
output [1:0] VAR57,
inout [15:0] VAR12,
output V... | gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_fifo.v | 4,625 | module MODULE1 #
(
parameter VAR15 = "VAR20",
parameter integer VAR6 = 5, parameter integer VAR8 = 64, parameter VAR16 = "lut" )
(
input wire VAR13, input wire VAR17, input wire [VAR8-1:0] VAR12, input wire VAR23, output wire VAR9, output wire [VAR8-1:0] VAR11, output wire VAR24, input wire VAR1 );
VAR5 #(
.VAR15(VAR15... | gpl-3.0 |
jhol/butterflylogic | rtl/trigger.v | 6,996 | module MODULE1 #(
parameter integer VAR2 = 32
)(
input wire clk,
input wire rst,
input wire [3:0] VAR22, input wire [3:0] VAR20, input wire [3:0] VAR11, input wire [31:0] VAR18, input wire VAR19,
input wire VAR6,
input wire VAR7,
input wire [VAR2-1:0] VAR13, output reg VAR9, output wire VAR25 );
reg [1:0] VAR4 = 2'b00;... | gpl-2.0 |
Murailab-arch/magukara | cores/sfifo/rtl/sfifo.v | 2,801 | module MODULE1 (
clk , rst , VAR10 , VAR26 , din , VAR24 , VAR11 , dout , VAR9 , VAR14 , VAR2 );
parameter VAR6 = 8;
parameter VAR20 = 8;
parameter VAR25 = (1 << VAR20);
input clk ;
input rst ;
input VAR10 ;
input VAR26 ;
input VAR24 ;
input VAR11 ;
input [VAR6-1:0] din ;
output VAR14 ;
output VAR9 ;
output [VAR6-1:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211ai/sky130_fd_sc_ms__o211ai.pp.symbol.v | 1,380 | module MODULE1 (
input VAR9 ,
input VAR3 ,
input VAR2 ,
input VAR7 ,
output VAR6 ,
input VAR4 ,
input VAR5,
input VAR8,
input VAR1
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_in.v | 11,436 | module MODULE1 (
VAR26,
VAR6,
VAR15,
VAR36,
VAR25,
VAR31,
VAR4,
VAR42,
VAR9,
VAR40,
VAR18,
VAR21,
VAR37,
VAR43,
VAR57,
VAR59,
VAR14,
VAR2,
VAR28,
VAR58,
VAR1,
VAR17,
VAR5,
VAR44,
VAR52,
VAR13,
VAR20,
VAR23,
VAR12,
VAR19,
VAR41,
VAR55,
VAR54,
VAR56,
VAR38,
VAR53,
VAR35,
VAR33,
VAR46,
VAR29,
VAR7,
VAR47,
VAR11,
VAR16,
VA... | gpl-2.0 |
kramble/FPGA-Litecoin-Miner | experimental/CM1/pwm_fade.v | 1,596 | module MODULE1 (clk, VAR8, VAR5);
input VAR8;
input clk;
output VAR5;
parameter VAR4 = 8;
parameter VAR2 = 1;
parameter VAR3 = 1;
reg [VAR4-1:0] VAR1;
always @(posedge clk) VAR1 = VAR1 + 1;
reg [VAR7-1:0] VAR9 = 0;
always @(posedge clk)
if (VAR8) VAR9 = 0 - 1;
else if (|VAR9) VAR9 = VAR9 - 1;
wire [VAR4-1:0] VAR6;
assi... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_idma.v | 21,065 | module MODULE1( clk, rst,
VAR3, VAR44, VAR56,
VAR16, VAR10, VAR31,
VAR43, VAR53,
VAR20, VAR35,
VAR68, VAR71,
VAR17,
VAR70, VAR47, VAR60,
VAR61, VAR72, VAR37, VAR5, VAR40, VAR59
);
parameter VAR1 = 14;
input clk, rst;
input [7:0] VAR3;
input VAR44;
input VAR56;
output VAR16;
output [7:0] VAR10;
input VAR31;
input VAR43;... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_28.v | 21,057 | module MODULE2 (
clk,
reset,
VAR160,
VAR75,
VAR73,
VAR38,
VAR61
);
parameter VAR52 = 18;
parameter VAR54 = 28;
parameter VAR78 = 14;
localparam VAR60 = 34;
input clk;
input reset;
input VAR160;
input VAR75;
input [VAR52-1:0] VAR73; output VAR38;
output [VAR52-1:0] VAR61;
localparam VAR151 = 18; localparam VAR66 = 36; l... | mit |
lokisz/openzcore | pippo-riscv/rtl/verilog/pippo_div_uu.v | 3,109 | module MODULE1(
clk, VAR19,
VAR1, VAR14, VAR16, VAR7,
VAR9, VAR2
);
parameter VAR11 = 64;
parameter VAR3 = VAR11 /2;
input clk;
input VAR19;
input [VAR11 -1:0] VAR1; input [VAR3 -1:0] VAR14; output [VAR3 -1:0] VAR16; output [VAR3 -1:0] VAR7; output VAR9;
output VAR2;
reg [VAR3-1:0] VAR16;
reg [VAR3-1:0] VAR7;
reg VAR9;... | gpl-2.0 |
stpr18/verilog-processor | register.v | 1,680 | module MODULE3 #(parameter VAR5 = 16, parameter VAR4 = {VAR5{1'VAR2}}) (input clk, input [VAR5-1:0] VAR9, output reg [VAR5-1:0] VAR3, input [1:0] VAR6);
VAR1 VAR3 <= VAR4;
always @(clk) begin
case (VAR6)
2'b01 : begin
VAR3[VAR5/2-1 : 0] <= VAR9[VAR5/2-1 : 0];
end
2'b10 : begin
VAR3[VAR5-1 : VAR5/2] <= VAR9[VAR5-1 : VAR... | unlicense |
olofk/wb_streamer | rtl/verilog/wb_stream_writer_cfg.v | 2,056 | module MODULE1
parameter VAR20 = 32)
(
input VAR9,
input VAR4,
input [4:0] VAR16,
input [VAR20-1:0] VAR21,
input [VAR20/8-1:0] VAR15,
input VAR19 ,
input VAR12,
input VAR17,
input [2:0] VAR7,
input [1:0] VAR3,
output [VAR20-1:0] VAR8,
output reg VAR2,
output VAR10,
output reg irq,
input VAR6,
output reg enable,
input [... | lgpl-3.0 |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab09/mem_beh.v | 4,675 | module MODULE1(addr,VAR1,VAR2, VAR6, VAR5, clk);
parameter VAR4 = 4096;
input clk;
input [31:0] addr, VAR1;
output [31:0] VAR2;
reg [31:0] VAR2;
input VAR6, VAR5;
reg [31:0] memory[VAR4-1:0];
integer VAR3; | mit |
Microsoft/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_OSERDES.v | 4,029 | module MODULE1(VAR17, VAR32, VAR16, VAR5, VAR20, VAR22);
output VAR17;
input VAR32, VAR16;
input [7:0] VAR5;
input VAR20, VAR22;
wire VAR1, VAR11;
VAR14 VAR2 (
.VAR17(VAR17), .VAR9(), .VAR34(), .VAR4(), .VAR32(VAR32), .VAR16(VAR16), .VAR8(VAR5[7]), .VAR24(VAR5[6]), .VAR6(VAR5[5]), .VAR23(VAR5[4]), .VAR25(VAR5[3]), .VAR... | bsd-2-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4SharedKES_0_0/synth/OpenSSD2_Tiger4SharedKES_0_0.v | 10,903 | module MODULE1 (
VAR36,
VAR16,
VAR5,
VAR12,
VAR40,
VAR34,
VAR48,
VAR9,
VAR15,
VAR20,
VAR32,
VAR45,
VAR31,
VAR29,
VAR7,
VAR10,
VAR39,
VAR13,
VAR33,
VAR26,
VAR19,
VAR38,
VAR24,
VAR2,
VAR17,
VAR8,
VAR46,
VAR11,
VAR41,
VAR43,
VAR28,
VAR23,
VAR21,
VAR3,
VAR30,
VAR35,
VAR49,
VAR6,
VAR47,
VAR44,
VAR25,
VAR22
);
input wire VAR... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | R_SEQ_bb.v | 5,069 | module MODULE1 (
address,
VAR2,
VAR1);
input [7:0] address;
input VAR2;
output [127:0] VAR1;
endmodule | mit |
jameshegarty/rigel | platform/camera/vsrc/vfifo64x1024.v | 13,773 | module MODULE1(
rst,
VAR130,
VAR118,
din,
VAR268,
VAR88,
dout,
VAR250,
VAR368,
VAR50
);
input rst;
input VAR130;
input VAR118;
input [63 : 0] din;
input VAR268;
input VAR88;
output [63 : 0] dout;
output VAR250;
output VAR368;
output [10 : 0] VAR50;
VAR323 #(
.VAR245(0),
.VAR34(0),
.VAR205(0),
.VAR71(0),
.VAR122(0),
.VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.behavioral.v | 8,879 | module MODULE1( VAR25, VAR49, VAR81, VAR42, VAR26 );
input VAR25, VAR49, VAR42, VAR81;
output VAR26;
reg VAR69;
VAR72 VAR57(.VAR25(VAR25),.VAR49(VAR49),.VAR81(VAR81),.VAR42(VAR42),.VAR26(VAR26),.VAR69(VAR69));
VAR72 VAR62(.VAR25(VAR25),.VAR49(VAR49),.VAR81(VAR81),.VAR42(VAR42),.VAR26(VAR26),.VAR69(VAR69));
not VAR9(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4/sky130_fd_sc_hs__or4_2.v | 2,104 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR9 ,
VAR2 ,
VAR8 ,
VAR4,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR9 ;
input VAR2 ;
input VAR8 ;
input VAR4;
input VAR7;
VAR6 VAR3 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR5,
VAR1,
VAR9,
VAR2,
VAR8
);
... | apache-2.0 |
rkrajnc/minimig-de1 | rtl/minimig/Beamcounter.v | 11,295 | module MODULE1
(
input clk, input reset, input VAR15, input VAR20, input VAR34, input VAR27, input [15:0] VAR14, output reg [15:0] VAR16, input [8:1] VAR47, output reg [8:0] VAR26, output reg [10:0] VAR22, output reg VAR39, output reg VAR11, output VAR5, output reg VAR7, output VAR3, output VAR21, output VAR37, output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3b/sky130_fd_sc_ls__and3b.functional.v | 1,381 | module MODULE1 (
VAR6 ,
VAR3,
VAR9 ,
VAR8
);
output VAR6 ;
input VAR3;
input VAR9 ;
input VAR8 ;
wire VAR5 ;
wire VAR2;
not VAR7 (VAR5 , VAR3 );
and VAR4 (VAR2, VAR8, VAR5, VAR9 );
buf VAR1 (VAR6 , VAR2 );
endmodule | apache-2.0 |
chenm001/connectal | verilog/altera/BRAM1BE.v | 4,336 | module MODULE1(VAR14,
VAR13,
VAR1,
VAR6,
VAR15,
VAR12
);
parameter VAR7 = 0;
parameter VAR4 = 1;
parameter VAR8 = 1;
parameter VAR9 = 1;
parameter VAR3 = 1;
parameter VAR2 = 1;
input VAR14;
input VAR13;
input [VAR3-1:0] VAR1;
input [VAR4-1:0] VAR6;
input [VAR8-1:0] VAR15;
output [VAR8-1:0] VAR12;
reg [VAR8-1:0] VAR5[0:... | mit |
HarmonInstruments/verilog | primitives/iddr_wrap.v | 1,172 | module MODULE1(input VAR6, input VAR14, output[1:0] VAR15);
VAR16 #(.VAR10("VAR8"), .VAR21("VAR11")) VAR18
(.VAR22(VAR15[0]), .VAR1(VAR15[1]),
.VAR17(VAR6),
.VAR20(1'b1),
.VAR2(VAR14),
.VAR3(1'b0), .VAR19(1'b0));
VAR5 #(.VAR9("VAR4"), .VAR21("VAR11")) VAR13
(.VAR7(VAR15[0]), .VAR22(VAR15[1]),
.VAR4(VAR6), .VAR12(~VAR6)... | gpl-3.0 |
ncos/Xilinx-Verilog | INTERFACES/src/ARINC429/dectohexstr.v | 2,458 | module MODULE2(
input [23:0] in,
output [127:0] out
);
assign out[127:48] = " ";
MODULE1 MODULE3
(
.in(in[7:0]),
.out(out[15:0])
);
MODULE1 MODULE2
(
.in(in[15:8]),
.out(out[31:16])
);
MODULE1 MODULE1
(
.in(in[23:16]),
.out(out[47:32])
);
endmodule
module MODULE1(
input [7:0] in,
output [15:0] out
);
wire[3:0] VAR8;
wi... | mit |
scalable-networks/ext | uhd/fpga/usrp2/models/xlnx_glbl.v | 1,560 | module MODULE1
(
VAR1,
VAR2
);
output VAR1;
output VAR2;
assign VAR1 = 0;
assign VAR2 = 0;
endmodule | gpl-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_qpll_reset.v | 14,387 | module MODULE1 #
(
parameter VAR43 = "VAR20", parameter VAR46 = "VAR45", parameter VAR21 = 1, parameter VAR16 = 1
)
(
input VAR33,
input VAR42,
input VAR7,
input [VAR21-1:0] VAR13,
input [(VAR21-1)>>2:0]VAR40,
input [(VAR21-1)>>2:0]VAR15,
input [ 1:0] VAR50,
input [VAR21-1:0] VAR23,
input [VAR21-1:0] VAR37,
output VAR2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/conb/sky130_fd_sc_ls__conb.symbol.v | 1,270 | module MODULE1 (
output VAR6,
output VAR3
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
chiralhat/fpga-pulses-ice | ECP5/pulses.v | 12,942 | module MODULE1(
input clk, input VAR37, input reset, input [31:0] VAR26, input [15:0] VAR30, input [15:0] VAR8, input [15:0] VAR36, input [15:0] VAR28,
input [15:0] VAR35,
input [15:0] VAR9,
input [15:0] VAR50,
input [7:0] VAR21, input [15:0] VAR33, input [6:0] VAR13,
input [6:0] VAR43,
input [7:0] VAR23, input [7:0] V... | bsd-3-clause |
sh-chris110/chris | FPGA/atlas_linux_ghrd/ip/altsource_probe/hps_reset.v | 4,169 | module MODULE1 (
VAR7,
VAR2,
VAR24);
input VAR7;
input VAR2;
output [2:0] VAR24;
wire [2:0] VAR4;
wire [2:0] VAR24 = VAR4[2:0];
VAR13 VAR8 (
.VAR7 (VAR7),
.VAR2 (VAR2),
.VAR24 (VAR4)
,
.VAR11 (),
.VAR20 (),
.VAR10 (),
.VAR16 (),
.VAR27 (),
.VAR30 (),
.VAR15 (),
.VAR5 (),
.VAR17 (),
.VAR28 (),
.VAR22 (),
.VAR21 (),
.VAR... | gpl-2.0 |
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