repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.v | 2,821 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR13 ,
VAR9 ,
VAR14 ,
VAR12 ,
VAR10 ,
VAR1,
VAR4 ,
VAR3 ,
VAR5 ,
VAR11
);
output VAR8 ;
output VAR2 ;
input VAR13 ;
input VAR9 ;
input VAR14 ;
input VAR12 ;
input VAR10 ;
input VAR1;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR11 ;
VAR6 VAR7 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR13(VAR13),... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v | 12,634 | module MODULE1 #
(
parameter VAR46 = 100,
parameter VAR2 = "VAR47",
parameter VAR22 = "VAR31",
parameter VAR44 = 4,
parameter VAR38 = 2,
parameter VAR54 = 2
)
(
VAR29, VAR18, VAR66, VAR39,
VAR13, VAR35, VAR3,
VAR63, VAR11, VAR12, VAR69, VAR76,
VAR45, VAR21, VAR33, VAR65,
clk, rst, VAR6, VAR34, VAR8, VAR10,
VAR19, VAR32... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/decap/sky130_fd_sc_hdll__decap_12.v | 1,892 | module MODULE2 (
VAR3,
VAR2,
VAR5 ,
VAR4
);
input VAR3;
input VAR2;
input VAR5 ;
input VAR4 ;
VAR6 VAR1 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE2 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
VAR6 VAR1 ();
endmodule | apache-2.0 |
bgelb/digilite_zl | rtl/zl_fifo_2.v | 1,700 | module MODULE1 #
(
parameter VAR7 = 0
)
(
input clk,
input VAR10,
input VAR4,
output VAR1,
input [VAR7-1:0] VAR8,
output VAR3,
input VAR2,
output [VAR7-1:0] VAR6
);
reg [VAR7-1:0] VAR11 [0:1];
reg [1:0] VAR5;
wire VAR12;
wire VAR9;
assign VAR12 = (VAR5 == 2'b00);
assign VAR9 = (VAR5 == 2'b10);
assign VAR3 = (!VAR12);
a... | bsd-2-clause |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/synth/design_1_xbar_0.v | 14,589 | module MODULE1 (
VAR71,
VAR112,
VAR40,
VAR96,
VAR9,
VAR64,
VAR82,
VAR107,
VAR49,
VAR30,
VAR118,
VAR15,
VAR46,
VAR5,
VAR67,
VAR111,
VAR76,
VAR6,
VAR10,
VAR90,
VAR33,
VAR110,
VAR126,
VAR117,
VAR70,
VAR56,
VAR92,
VAR106,
VAR120,
VAR63,
VAR66,
VAR45,
VAR72,
VAR18,
VAR81,
VAR132,
VAR127,
VAR77,
VAR61,
VAR69
);
input wire VA... | mit |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/db/ip/tracking_camera_system/submodules/tracking_camera_system_nios2_qsys_0_jtag_debug_module_wrapper.v | 11,172 | module MODULE1 (
VAR25,
VAR15,
clk,
VAR54,
VAR58,
VAR39,
VAR45,
VAR52,
VAR21,
VAR11,
VAR13,
VAR2,
VAR37,
VAR4,
VAR9,
VAR29,
VAR41,
VAR44,
VAR19,
VAR36,
VAR18,
VAR35,
VAR14,
VAR49,
VAR7,
VAR40,
VAR10,
VAR23,
VAR55,
VAR57,
VAR38,
VAR8,
VAR46,
VAR56,
VAR27,
VAR48
)
;
output [ 37: 0] VAR18;
output VAR35;
output VAR14;
outp... | gpl-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ddr3_source/ddr3_driver.v | 16,144 | module MODULE1 #(
parameter VAR59 = 3, parameter VAR88 = 2, parameter VAR45 = 2, parameter VAR60 = 1, parameter VAR32 = 2, parameter VAR61 = 8, parameter VAR3 = 64, parameter VAR18 = 8,
parameter VAR34 = 2, parameter VAR93 = 15, parameter VAR14 = 29,
parameter VAR24 = 64,
parameter VAR17 = 2,
parameter VAR63 = 2
parame... | gpl-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/Flash_Controller.v | 7,914 | module MODULE1(
input VAR28,
input [21:0] VAR15,
input [15:0] VAR41,
input [3:0] VAR23,
input VAR29,
input VAR25,
input VAR35,
output reg[15:0]VAR6,
output VAR5,
output reg VAR31,
output reg VAR50,
output reg[21:0] VAR62,
inout [15:0] VAR9,
output VAR8,
output VAR36,
output VAR56,
output VAR34
);
reg [21:0] VAR32,VAR18... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi.symbol.v | 1,418 | module MODULE1 (
input VAR3,
input VAR4,
input VAR6,
input VAR10,
input VAR8,
input VAR11,
output VAR1
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/store_pkt.v | 11,074 | module MODULE1
parameter VAR41 = 64,
parameter VAR62=VAR41/8,
parameter VAR47 = 5,
parameter VAR31 = 13,
parameter VAR34 = 11,
parameter VAR36 = VAR34-VAR2(VAR62),
parameter VAR53 = 6,
parameter VAR10 = VAR2(VAR47)
)
( VAR45,
VAR42,
VAR19,
VAR32,
VAR48,
VAR35,
VAR12,
VAR3,
VAR20,
VAR23,
VAR17,
VAR30,
VAR6,
VAR58,
VAR28... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_byp.v | 26,853 | module MODULE1
(
VAR145, VAR173, VAR11, VAR24,
VAR166, VAR108, VAR191,
VAR43, VAR192, VAR194,
VAR140, VAR141, VAR59,
VAR101, VAR38, VAR99,
VAR89, VAR125, VAR112,
VAR188, VAR42,
VAR71, VAR149, VAR119, VAR35, VAR171,
VAR132, VAR137,
VAR5, VAR182,
VAR25, VAR131,
VAR57, VAR19,
VAR189, VAR67,
VAR73, VAR113,
VAR88, VAR68,
VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a_m.v | 2,319 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR1 ,
VAR11 ,
VAR7,
VAR10,
VAR8 ,
VAR4
);
output VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR1 ;
input VAR11 ;
input VAR7;
input VAR10;
input VAR8 ;
input VAR4 ;
VAR9 VAR3 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.... | apache-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_frequency_analyzer_synch_0_0/synth/image_processing_2d_design_frequency_analyzer_synch_0_0.v | 3,674 | module MODULE1 (
VAR1,
reset,
enable,
VAR5,
VAR7,
VAR6,
VAR8
);
input wire VAR1;
input wire reset;
input wire enable;
output wire VAR5;
output wire VAR7;
output wire VAR6;
output wire VAR8;
VAR9 #(
.VAR2(100000000),
.VAR3(2000)
) VAR4 (
.VAR1(VAR1),
.reset(reset),
.enable(enable),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),... | gpl-2.0 |
unihd-cag/openhmc | rtl/hmc_controller/register_file/openhmc_rf.v | 21,650 | module MODULE1 #(
parameter VAR23 = 8,
parameter VAR54 = 1,
parameter VAR59 = 8,
parameter VAR58= 8,
parameter VAR77 = 64,
parameter VAR10 = 0,
parameter VAR38 = 0,
parameter VAR55 = 0
) (
input wire clk,
input wire VAR16,
input wire [VAR38-1:0] address,
output reg VAR48,
output reg VAR22,
input wire VAR21,
output reg[... | lgpl-3.0 |
manu3193/GatoTDD | Registro_Juego.v | 2,435 | module MODULE1(
clk,
VAR7,
VAR41,
VAR4,
VAR13,
VAR36,
VAR10,
VAR1,
VAR8,
VAR40,
VAR21,
VAR5,
VAR25,
VAR37,
VAR48,
VAR20,
VAR38,
VAR16,
VAR27,
VAR23,
VAR15,
VAR35,
VAR6,
VAR12,
VAR44,
VAR33,
VAR14,
VAR42,
VAR17
);
input clk,VAR7;
input VAR41, VAR4, VAR13, VAR36, VAR10, VAR1, VAR8, VAR40, VAR21;
input [1:0] VAR5, VAR25, ... | mit |
rossmacarthur/verilog-utilities | sevensegment/SS_Control.v | 1,425 | module MODULE1 #(VAR2 = 4) (
input clk, input rst,
input [VAR2*4-1:0] VAR6, output [VAR2-1:0] VAR5, output [6:0] VAR4 );
reg [6:0] VAR8 [VAR2-1:0];
reg [VAR3(VAR2)+1:0] VAR1;
assign VAR5 = ~reset ? ~(1'b1 << VAR1) : ~1'b0;
assign VAR4 = VAR8[VAR1];
always @(posedge clk) VAR1 <= (VAR1 == VAR2-1) ? 1'b0 : VAR1 + 1'b1;
ge... | mit |
mrehkopf/sd2snes | verilog/sd2snes_cx4/dcm.v | 2,984 | module MODULE1 (
input VAR37,
output VAR2,
output VAR21,
input VAR35,
output[7:0] VAR24
);
VAR18 #(
.VAR40("VAR31"), .VAR30(2.0), .VAR1(3), .VAR36(10), .VAR12("VAR13"), .VAR16(41.667), .VAR9("VAR20"), .VAR6("VAR20"), .VAR32("VAR17"), .VAR3("VAR38"), .VAR15("VAR38"), .VAR39("VAR11"), .VAR41(16'hFFFF), .VAR10(0), .VAR5("... | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/phy_dq_iob.v | 23,027 | module MODULE1 #
(
parameter VAR142 = 100, parameter VAR122 = 5, parameter VAR154 = "VAR47", parameter VAR135 = "VAR102", parameter VAR100 = 300.0, parameter VAR69 = "VAR23", parameter VAR15 = "VAR102", parameter VAR83 = "VAR162" )
(
input VAR99,
input clk,
input rst,
input VAR125,
input VAR173,
input VAR71,
input [4:0... | mit |
TheMadSocrates/vercpu-project | rtl/core/controller_unit.v | 3,613 | module MODULE1(
input wire [ 7 : 0] VAR29,
input wire [VAR30 - 1 : 0] VAR7,
input wire clk,
input wire VAR51,
output wire [1 : 0] VAR41,
output wire VAR52,
output wire VAR22,
output wire VAR20,
output wire [1 : 0] VAR39,
output wire VAR48,
output wire VAR8,
output wire [ 1 : 0] VAR12,
output wire VAR43,
output wire VAR... | gpl-3.0 |
brandonpelfrey/ice40-nes | src/mod_clock_master.v | 1,232 | module MODULE1(
input VAR3,
output VAR12,
output VAR13
);
VAR10 #(
.VAR7("VAR9"),
.VAR18("VAR5"),
.VAR1(7'b1000010),
.VAR14(3'b101),
.VAR11(4'b0000),
.VAR16(3'b001)
) VAR17 (
.VAR8(VAR3),
.VAR2(VAR12),
.VAR15(1'b1),
.VAR4(1'b0)
);
VAR10 #(
.VAR7("VAR9"),
.VAR11(4'b0000), .VAR1(7'b0110110), .VAR14(3'b010), .VAR16(3'b001... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211oi/sky130_fd_sc_hs__a211oi.blackbox.v | 1,332 | module MODULE1 (
VAR3 ,
VAR4,
VAR7,
VAR5,
VAR6
);
output VAR3 ;
input VAR4;
input VAR7;
input VAR5;
input VAR6;
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb_2.v | 2,350 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR11 ,
VAR5 ,
VAR7 ,
VAR6,
VAR3,
VAR9 ,
VAR2
);
output VAR8 ;
input VAR1 ;
input VAR11 ;
input VAR5 ;
input VAR7 ;
input VAR6;
input VAR3;
input VAR9 ;
input VAR2 ;
VAR4 VAR10 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR... | apache-2.0 |
kyzhai/NUNY | src/hardware/ninjasymbol_bb.v | 5,046 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
Alejandro88/unal_digital01 | rom_ram_logic_array/223473--223480/ram_memory.v | 1,276 | module MODULE1 # (parameter VAR1=4, VAR2=4)
(input clk,
input VAR5,
input [VAR1-1:0] VAR4,
input [VAR2-1:0] din,
output [VAR1-1:0]dout);
reg [VAR2-1:0] VAR3 [VAR1-1:0];
always @ (posedge clk)
if (VAR5) VAR3 [VAR4] <= din;
assign dout = VAR3[VAR4];
endmodule | gpl-2.0 |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_vc_alloc_sep_if.v | 21,884 | module MODULE1
(clk, reset, VAR80, VAR89, VAR69, VAR91,
VAR60, VAR25, VAR16, VAR74, VAR77);
parameter VAR40 = 2;
parameter VAR84 = 2;
localparam VAR54 = VAR40 * VAR84;
parameter VAR42 = 1;
localparam VAR41 = VAR54 * VAR42;
parameter VAR58 = 5;
localparam VAR49 = VAR87(VAR58);
parameter VAR30 = VAR21;
parameter VAR94 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2/sky130_fd_sc_hd__or2.functional.v | 1,244 | module MODULE1 (
VAR1,
VAR6,
VAR4
);
output VAR1;
input VAR6;
input VAR4;
wire VAR5;
or VAR3 (VAR5, VAR4, VAR6 );
buf VAR2 (VAR1 , VAR5 );
endmodule | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | generador_caracteres_v2.v | 9,040 | module MODULE1
(
input wire clk,
input wire [3:0] VAR11, VAR12, VAR24, VAR25, VAR48, VAR15,VAR18, VAR16, VAR19, VAR51, VAR13, VAR26,VAR35, VAR34, VAR23, VAR32, VAR44, VAR27,input wire VAR45,input wire VAR6,input wire [1:0] VAR17,input wire [1:0] VAR28,input wire [9:0] VAR8, VAR33,output wire VAR10, output wire VAR37, o... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9739a/axi_ad9739a.v | 8,888 | module MODULE1 (
VAR59,
VAR40,
VAR117,
VAR98,
VAR50,
VAR15,
VAR27,
VAR68,
VAR112,
VAR11,
VAR70,
VAR24,
VAR28,
VAR61,
VAR81,
VAR113,
VAR105,
VAR66,
VAR74,
VAR55,
VAR58,
VAR6,
VAR10,
VAR44,
VAR110,
VAR34,
VAR118,
VAR103,
VAR63,
VAR99,
VAR45,
VAR41,
VAR56);
parameter VAR2 = 0;
parameter VAR16 = 0;
parameter VAR5 = 1;
para... | gpl-3.0 |
jmahler/EECE344-Digital_System_Design | lab01/lattice-grey_code_counter/main.v | 1,203 | module MODULE1(VAR2, VAR6, VAR4, clk );
input VAR2 ;
output VAR6 ;
output wire [7:0] VAR4 ;
output clk ;
reg [22:0]VAR7 ;
VAR1 VAR9 (.VAR1(VAR2));
VAR10 VAR5 (.VAR11(VAR6)) ;
VAR3 VAR8(clk, VAR4);
always @(posedge VAR6 or negedge VAR2)
begin
if (~VAR2)
VAR7 <= 32'h0000 ;
end
else
VAR7 <= VAR7 + 1 ;
end
assign clk = VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o.blackbox.v | 1,425 | module MODULE1 (
VAR10 ,
VAR7,
VAR1,
VAR6,
VAR5,
VAR4
);
output VAR10 ;
input VAR7;
input VAR1;
input VAR6;
input VAR5;
input VAR4;
supply1 VAR3;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/alu_x_pipelined.v | 8,164 | module MODULE1(
input [31:0] VAR92,
input [31:0] VAR30,
input [31:0] VAR78,
input [1:0] VAR33,
input VAR14,
input VAR31,
input [7:0] VAR85,
input reset,
input VAR23,
output [31:0] VAR61,
output [1:0] VAR63,
output VAR55,
output VAR37,
output [7:0] VAR34
);
wire [1:0] VAR98,VAR6,VAR29,VAR19,VAR35,VAR8,VAR5;
wire [32:0] ... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/cpu_dma_queue_main.v | 13,176 | module MODULE1
parameter VAR64 = 64,
parameter VAR47=VAR64/8,
parameter VAR16 = VAR3,
parameter VAR12 = VAR16/8,
parameter VAR56 = 125000
)
(
output [VAR64-1:0] VAR58,
output [VAR47-1:0] VAR85,
output VAR41,
input VAR5,
input [VAR64-1:0] VAR52,
input [VAR47-1:0] VAR27,
input VAR70,
output VAR31,
output reg VAR84,
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbn/sky130_fd_sc_ms__dfbbn.symbol.v | 1,485 | module MODULE1 (
input VAR3 ,
output VAR10 ,
output VAR1 ,
input VAR7,
input VAR6 ,
input VAR5
);
supply1 VAR8;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
P3Stor/P3Stor | pcie/app/pcie_2_0_ep.v | 17,610 | module MODULE1 #(
parameter VAR87 = "VAR15"
)
(
output [7:0] VAR36,
output [7:0] VAR42,
input [7:0] VAR123,
input [7:0] VAR41,
output VAR136,
input VAR79,
input VAR69,
output VAR92,
output [127:0] VAR128,
input VAR116,
input VAR81,
output VAR30,
input [127:0] VAR51,
input VAR29,
input VAR119,
output VAR145,
output [127... | gpl-2.0 |
Marcoslz22/Tercer_Proyecto | list_ch09_03_kb_code.v | 1,249 | module MODULE1
(
input wire clk, reset,VAR7,
input wire [7:0] VAR3,
output reg VAR6
);
localparam VAR4 = 8'hf0;
localparam
VAR5 = 1'b0,
VAR1 = 1'b1;
reg VAR8, VAR2;
always @(posedge clk, posedge reset)
if (reset)
VAR8 <= VAR5;
else
VAR8 <= VAR2;
always @*
begin
VAR6 = 1'b0;
VAR2 = VAR8;
case (VAR8)
VAR5: if (VAR7==1'b1... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/Deco_Round_Mult.v | 1,344 | module MODULE1(
input wire [1:0] VAR1,
input wire VAR5, input wire VAR2, output reg VAR3 );
wire VAR4;
always @*
case ({VAR2,VAR5,VAR1})
4'b0101: VAR3 <= 1'b0;
4'b1101: VAR3 <= 1'b1;
4'b0110: VAR3 <= 1'b1;
4'b1110: VAR3 <= 1'b0;
default: VAR3 <= 1'b0; endcase
endmodule | gpl-3.0 |
mamijaz/RISC-V | src/riscv_instruction_cache/INSTRUCTION_CACHE.v | 19,913 | module MODULE1 #(
parameter VAR61 = 32 ,
parameter VAR10 = 32 ,
parameter VAR62 = 64*1024 ,
parameter VAR13 = 4 ,
parameter VAR32 = 16 ,
parameter VAR39 = 1'b1 ,
parameter VAR24 = 1'b0 ,
localparam VAR27 = VAR32 * VAR13 ,
localparam VAR69 = VAR27 * 8 ,
localparam VAR18 = VAR62 / (2 * VAR27) ,
localparam VAR4 = VAR14(VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor2/sky130_fd_sc_hs__xnor2.pp.blackbox.v | 1,248 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR5 ,
VAR4,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR4;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3.functional.v | 1,291 | module MODULE1 (
VAR6,
VAR3,
VAR4,
VAR7
);
output VAR6;
input VAR3;
input VAR4;
input VAR7;
wire VAR1;
nand VAR2 (VAR1, VAR4, VAR3, VAR7 );
buf VAR5 (VAR6 , VAR1 );
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_hdr_fifo.v | 7,751 | module MODULE1(
parameter VAR36 = 128,
parameter VAR26 = 1,
parameter VAR35 = 1,
parameter VAR45 = "VAR30"
)
(
input VAR9,
input VAR38,
input VAR33,
input [(VAR36)-1:0] VAR43,
input [VAR54-1:0] VAR32,
input [VAR10-1:0] VAR55,
input [VAR24-1:0] VAR1,
input VAR42,
output VAR11,
output VAR48,
output [(VAR36)-1:0] VAR18,
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv_8.v | 1,995 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR5,
VAR1,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR8 ;
input VAR5;
input VAR1;
input VAR7 ;
input VAR3 ;
VAR4 VAR6 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR2,
VAR8
);
output VAR2;
input VAR8;
supply1 VAR5;
supply0 VAR1;... | apache-2.0 |
tinkercnc/spi-fpga-driver | pluto_spi_servo_firmware/spi_servo_rspi-opendrain.v | 8,633 | module MODULE1(in, out);
input in;
output out;
assign out = in ? 1'VAR19 : 1'b0;
endmodule
module MODULE2(clk, VAR45, VAR36, VAR39, VAR29, VAR57, VAR3, VAR4, VAR63, VAR62, VAR60, VAR50, VAR15, VAR17, dout, din);
parameter VAR51=14;
input clk;
input VAR45, VAR29, VAR36, VAR4;
output VAR39, VAR3, VAR63;
output VAR57;
out... | gpl-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC/FSM.v | 8,734 | module MODULE1(
input [31:0] VAR1, input [31:0] VAR27, input [31:0] VAR11, input [31:0] VAR20, input [31:0] VAR22,
input [31:0] VAR26,
input [31:0] VAR8,
input [31:0] VAR25,
input [31:0] VAR14,
input [31:0] VAR2,
input [31:0] VAR13, input [31:0] VAR7, input [31:0] VAR23, input [1:0] VAR31, input VAR24, input VAR28,
inp... | apache-2.0 |
dvanmali/Superscalar_Pipeline_Processor | execute.v | 2,081 | module MODULE1(clk, VAR66,VAR39, VAR34,VAR45, VAR22,VAR23, VAR50,VAR35,VAR2,VAR13,VAR4,VAR62,VAR65,VAR60,VAR30,VAR57,VAR20,VAR41,
VAR67,VAR63,VAR29,VAR19,VAR52,VAR24,VAR25,VAR17,VAR58,VAR46,VAR42,VAR49,VAR38,VAR61,
VAR59,VAR32,VAR36,VAR15,VAR7,VAR9);
input clk, VAR29,VAR19, VAR25,VAR17, VAR66,VAR39, VAR52,VAR24;
input ... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/top_mdio/mdio_mdc.v | 6,072 | module MODULE1(
input reset,
input clk,
output VAR25, inout VAR10,
input VAR29, input [1:0] VAR28, input [4:0] VAR30, input [4:0] VAR17, input [15:0] VAR20,
output VAR3, output reg [15:0] VAR6,
output VAR27
);
wire VAR19;assign VAR19 = ((state==VAR15)&&(VAR16 == 1'b0));
wire VAR23;assign VAR23 = ( (!VAR3) || VAR19 || V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22o/sky130_fd_sc_lp__a22o.behavioral.v | 1,607 | module MODULE1 (
VAR14 ,
VAR13,
VAR6,
VAR15,
VAR1
);
output VAR14 ;
input VAR13;
input VAR6;
input VAR15;
input VAR1;
supply1 VAR11;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR9 ;
wire VAR3 ;
wire VAR12 ;
wire VAR5;
and VAR7 (VAR3 , VAR15, VAR1 );
and VAR16 (VAR12 , VAR13, VAR6 );
or VAR10 (VAR5, VAR12, VAR3);
buf VAR8 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3/sky130_fd_sc_ls__and3_1.v | 2,164 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR6 ,
VAR10 ,
VAR7,
VAR1,
VAR3 ,
VAR8
);
output VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR10 ;
input VAR7;
input VAR1;
input VAR3 ;
input VAR8 ;
VAR9 VAR4 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
asicguy/gplgpu | hdl/de/ded_funshf.v | 6,646 | module MODULE1
(
input VAR18,
output reg [(VAR20<<3)-1:0] VAR17, output [VAR20-1:0] VAR9 );
reg [(VAR20<<4)-1:0] VAR21; reg [31:0] VAR5;
reg [4:0] VAR13;
wire [1:0] VAR11;
wire [1:0] VAR25;
wire [3:0] VAR26;
wire [127:0] VAR22;
wire [135:0] VAR15;
wire [151:0] VAR1;
wire [183:0] VAR3;
wire [VAR20-1:0] VAR16;
wire [VAR2... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | wwp/alu.v | 173,729 | module MODULE1(VAR5,VAR8,VAR3,VAR6,VAR4,VAR1);
output [0:127] VAR1;
input [0:127] VAR5;
input [0:127] VAR8;
input [0:2] VAR3;
input [0:1] VAR6;
input [0:4] VAR4;
parameter VAR7 = 1'b0;
parameter VAR2 = 1'b1;
reg [0:127] VAR1;
always @(VAR5 or VAR8 or VAR3 or VAR6 or VAR4)
begin
case(VAR4)
begin
case(VAR3)
case(VAR6)
be... | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_fbmult.v | 4,836 | module MODULE1
(VAR6, VAR3, VAR26, VAR1);
parameter VAR31 = 32;
parameter VAR9 = 1;
input [0:VAR31-1] VAR6;
input VAR3;
input [0:VAR31-1] VAR26;
output [0:VAR31-1] VAR1;
wire [0:VAR31-1] VAR1;
wire [0:VAR31-1] VAR32;
wire [0:VAR31*VAR31-1] VAR17;
generate
if(VAR31 == 1)
begin
assign VAR32 = VAR3 ^ VAR26;
assign VAR17 =... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_qpram.v | 1,510 | module MODULE1 #(
parameter VAR17 = 11,
parameter VAR9 = 8
) (
input VAR20,
input [VAR17-1:0] VAR18,
output [VAR9-1:0] VAR8,
input [VAR17-1:0] VAR4,
output [VAR9-1:0] VAR1,
input [VAR17-1:0] VAR16,
output [VAR9-1:0] VAR15,
input [VAR17-1:0] VAR11,
output [VAR9-1:0] VAR5,
input VAR6,
input [VAR17-1:0] VAR19,
input [VAR9... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.v | 2,119 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR1,
VAR2,
VAR5 ,
VAR6
);
output VAR7 ;
input VAR4 ;
input VAR1;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR8 VAR3 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7,
VAR4
);
output VAR7;
input VAR4;
supply1 VAR1;
supply0 VAR2;... | apache-2.0 |
bgamari/timetag-fpga | timetag.v | 2,915 | module MODULE1(
VAR22,
VAR11, VAR27, VAR44,
VAR58, VAR9,
VAR56, VAR29, VAR48, VAR12,
clk,
VAR54,
VAR18
);
input VAR22;
input clk;
input VAR58;
input [7:0] VAR9;
output VAR56;
output [7:0] VAR29;
input VAR48;
output VAR12;
output VAR11;
output [7:0] VAR27;
input VAR44;
input [3:0] VAR54;
output [3:0] VAR18;
wire [15:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2b/sky130_fd_sc_hs__nand2b_4.v | 2,020 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR7 ,
VAR5,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR7 ;
input VAR5;
input VAR3;
VAR2 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR4 ,
VAR1,
VAR7
);
output VAR4 ;
input VAR1;
input VAR7 ;
supply1 VAR5;
supply0 VAR3;
VAR2 VAR6 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22a/sky130_fd_sc_hdll__o22a.functional.pp.v | 2,178 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR8 ,
VAR16 ,
VAR2 ,
VAR12,
VAR14,
VAR5 ,
VAR10
);
output VAR1 ;
input VAR4 ;
input VAR8 ;
input VAR16 ;
input VAR2 ;
input VAR12;
input VAR14;
input VAR5 ;
input VAR10 ;
wire VAR15 ;
wire VAR3 ;
wire VAR18 ;
wire VAR6;
or VAR19 (VAR15 , VAR8, VAR4 );
or VAR17 (VAR3 , VAR2, VAR16 );
and ... | apache-2.0 |
liqimai/ZPC | PersonalComputer/Memory.v | 1,954 | module MODULE1(
input clk,
input[14:0] VAR4,
input[14:0] VAR33,
input VAR27,
input[31:0] VAR12,
input VAR13, input VAR16,
output[31:0] VAR23,
output[15:0] VAR25
);
wire VAR31,VAR24;
wire[13:0] VAR32,VAR18,VAR9,VAR26;
wire[15:0] VAR28,VAR15,VAR10,VAR14;
wire[15:0] VAR6,VAR7;
assign VAR31 = VAR27 & ( ~VAR16 | ~VAR4[0] );... | gpl-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_arb_mux.v | 9,398 | module MODULE1 #
(
parameter VAR25 = 4,
parameter VAR43 = 8,
parameter VAR1 = (VAR43>8),
parameter VAR33 = (VAR43/8),
parameter VAR50 = 0,
parameter VAR11 = 8,
parameter VAR21 = 0,
parameter VAR6 = 8,
parameter VAR51 = 1,
parameter VAR10 = 1,
parameter VAR35 = 0,
parameter VAR74 = 1
)
(
input wire clk,
input wire rst,
... | mit |
CatherineH/QubitekkCC | TDH/src/DE0Nano/verilog/counterselect.v | 4,221 | module MODULE1 (
VAR11,
VAR12,
VAR8,
VAR1,
sel,
VAR10);
input [20:0] VAR11;
input [20:0] VAR12;
input [20:0] VAR8;
input [20:0] VAR1;
input [1:0] sel;
output [20:0] VAR10;
wire [20:0] VAR3;
wire [20:0] VAR4 = VAR1[20:0];
wire [20:0] VAR15 = VAR8[20:0];
wire [20:0] VAR9 = VAR12[20:0];
wire [20:0] VAR13 = VAR11[20:0];
wi... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361_tx_dds.v | 6,932 | module MODULE1 (
VAR13,
VAR28,
VAR31,
VAR24,
VAR22,
VAR29,
VAR21,
VAR35,
VAR16,
VAR11,
VAR30,
VAR3,
VAR19,
VAR15,
VAR26);
parameter VAR14 = 0;
input VAR13;
input VAR28;
output [15:0] VAR31;
input VAR24;
input VAR22;
input VAR29;
input VAR21;
input [15:0] VAR35;
input [15:0] VAR16;
input [15:0] VAR11;
input [ 3:0] VAR30... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp.symbol.v | 1,413 | module MODULE1 (
input VAR4 ,
output VAR9 ,
output VAR3 ,
input VAR1,
input VAR6
);
supply1 VAR8;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
fallen/milkymist-mmu | cores/softusb/rtl/softusb_rx.v | 6,414 | module MODULE1(
input VAR24,
input VAR22,
input VAR36,
input VAR37,
input VAR18,
output reg [7:0] VAR16,
output reg VAR28,
output reg VAR3,
output reg VAR31,
input VAR13
);
wire VAR29 = VAR36 ^ VAR13;
wire VAR39 = ~VAR37 & ~VAR18;
wire VAR14;
reg [2:0] VAR17;
reg [2:0] VAR21;
always @(posedge VAR24) begin
if(VAR22)
VAR... | lgpl-3.0 |
cynngah/virtualsynthesizer | keyboard.v | 1,792 | module MODULE1(VAR6, VAR9, VAR4, reset, read, VAR3, VAR11);
input VAR6;
input VAR9;
input VAR4; input reset;
input read;
output VAR3;
output [7:0] VAR11;
reg VAR8;
reg [7:0] VAR11;
reg VAR3;
reg VAR12;
reg VAR7;
reg [3:0] VAR1;
reg [8:0] VAR2;
reg [7:0] VAR10;
reg VAR5;
always @ (posedge VAR8 or posedge read)
if (read ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0p/sky130_fd_sc_lp__inputiso0p.blackbox.v | 1,352 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR5
);
output VAR3 ;
input VAR7 ;
input VAR5;
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
linuxbest/lzs | pcores/comp_unit_v1_00_a/hdl/verilog/copy.v | 2,305 | module MODULE1(
VAR23, VAR2, VAR12, VAR24, VAR7,
VAR20, VAR18, VAR1, VAR16, VAR9, VAR3,
VAR14, VAR15, VAR8,
VAR17
);
input VAR20;
input VAR18;
input VAR1;
input [23:0] VAR16;
output VAR23;
input [63:0] VAR9;
input VAR3;
input VAR14;
input VAR15;
output VAR2;
output [63:0] VAR12;
output VAR24;
input VAR8;
input VAR17;
o... | gpl-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | src/frequency_analyzer_synch.v | 2,912 | module MODULE1 #
(
parameter integer VAR9 = 100000000,
parameter integer VAR4 = 2000
)
(
input wire VAR2,
input wire reset,
input wire enable,
output reg VAR7,
output reg VAR10,
output reg VAR3,
output reg VAR8
);
localparam integer VAR5 = VAR9 / VAR4;
localparam integer VAR1 = 40;
integer VAR6;
always @(posedge VAR2)
... | gpl-2.0 |
tinkercnc/spi-fpga-driver | pluto_spi_stepper_firmware/spi_main-opendrain.v | 7,137 | module MODULE2(in, out);
input in;
output out;
assign out = in ? 1'VAR6 : 1'b0;
endmodule
module MODULE1(clk, VAR35, VAR44, VAR19, VAR28, VAR48, VAR23, VAR51, VAR29, dout, din, VAR54, VAR27);
parameter VAR60=10;
parameter VAR33=11;
parameter VAR25=4;
input clk;
input VAR35, VAR28, VAR44, VAR48;
output VAR19, VAR29 = 1'... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o.pp.symbol.v | 1,367 | module MODULE1 (
input VAR7 ,
input VAR8 ,
input VAR5 ,
input VAR3 ,
input VAR2 ,
output VAR6 ,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
freecores/ca_prng | src/rtl/ca_prng.v | 32,917 | module MODULE1(
input wire clk,
input wire VAR1,
input wire [31 : 0] VAR15,
input wire VAR5,
input wire VAR11,
input wire [7 : 0] VAR4,
input wire VAR6,
output wire [31 : 0] VAR12
);
parameter [7 : 0] VAR9 = 8'b00011110;
reg [31 : 0] VAR3;
reg [31 : 0] VAR2;
reg VAR7;
reg [7 : 0] VAR14;
reg [31 : 0] VAR8;
assign VAR12 ... | bsd-2-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_nor3.v | 1,633 | if (VAR2 && (VAR19==VAR11)) \
begin: VAR9 \
VAR21 VAR6 (.VAR15(VAR13),.VAR5(VAR3),.VAR10(VAR14),.VAR17); \
end
module MODULE1 #(parameter VAR4(VAR19)
, parameter VAR2=0
)
(input [VAR19-1:0] VAR13
, input [VAR19-1:0] VAR3
, input [VAR19-1:0] VAR14
, output [VAR19-1:0] VAR17
);
begin :VAR16
end
VAR7 assert(VAR2==0) else ... | bsd-3-clause |
windelbouwman/ppci-mirror | tools/fatfs/spi.v | 2,403 | module MODULE1 #(
parameter integer VAR14 = 0,
parameter integer VAR22 = 32
) (
input clk,
input VAR18,
input VAR5,
input VAR13,
input [ 7:0] VAR6,
input [31:0] VAR15,
output reg [31:0] VAR11,
output reg VAR19,
output [VAR22-1:0] VAR1,
output VAR7,
input VAR17,
output VAR9
);
wire VAR10;
reg VAR24, VAR21;
reg [VAR22-1:... | bsd-2-clause |
krmarien/Proxmark | fpga/relay_encode.v | 3,887 | module MODULE1(
clk,
reset,
VAR6,
VAR7,
VAR9
);
input clk, reset, VAR6, VAR7;
output VAR9;
reg [0:0] VAR9 = 1'b0;
reg [7:0] VAR4 = 8'b0;
reg [7:0] VAR8 = 8'b0;
reg [6:0] VAR2 = 7'b0;
reg [2:0] VAR1 = 3'b0;
reg [0:0] VAR3 = 1'b0;
reg [0:0] VAR5 = 1'b0;
reg [3:0] counter = 4'b0;
always @(posedge clk)
begin
counter = coun... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_pmod_fmeter/util_pmod_fmeter_core.v | 3,486 | module MODULE1 (
VAR5,
reset,
VAR3,
VAR1);
input VAR5;
input reset;
input VAR3;
output [31:0] VAR1;
reg [31:0] VAR1 = 'h0;
reg [31:0] VAR4 = 'h0;
reg [ 2:0] VAR6 = 'h0;
wire VAR2;
assign VAR2 = ~VAR6[2] & VAR6[1];
always @(posedge VAR5) begin
VAR6[0] <= VAR3;
VAR6[2:1] <= VAR6[1:0];
end
always @(posedge VAR5) begin
if ... | gpl-3.0 |
laanwj/yosys-ice-experiments | pmodoled2/pmodoled2.v | 3,421 | module MODULE1(input clk,
output VAR1, input VAR29,
input VAR3,
output VAR32, output VAR30, output VAR19, output VAR27,
output VAR7,
output VAR9,
output VAR38,
output VAR23,
output VAR14,
output VAR8,
output VAR39,
);
localparam VAR33 = 12;
reg VAR20, VAR28;
wire [7:0] VAR37;
wire [7:0] VAR17 = 0;
wire VAR4 = 0;
wire V... | mit |
MeshSr/onetswitch45 | ons45-gsg-2-gt_ibert/vivado/onets_7045_gt_ibert/sources/onetswitch_top.v | 2,177 | module MODULE1
(
output [(4*VAR13)-1:0] VAR14,
output [(4*VAR13)-1:0] VAR18,
input [(4*VAR13)-1:0] VAR25,
input [(4*VAR13)-1:0] VAR19,
input [VAR2-1:0] VAR7,
input [VAR2-1:0] VAR12,
input [VAR2-1:0] VAR26,
input [VAR2-1:0] VAR11
);
wire [VAR13-1:0] VAR10;
wire [VAR13-1:0] VAR20;
wire [VAR2-1:0] VAR4;
wire [VAR2-1:0] VA... | lgpl-2.1 |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_mem_intfc.v | 40,945 | module MODULE1 #
(
parameter VAR119 = 100,
parameter VAR161 = 64,
parameter VAR199 = "1T",
parameter VAR38 = "0", parameter VAR241 = 3, parameter VAR195 = 2, parameter VAR24 = "8", parameter VAR233 = "VAR133", parameter VAR288 = "VAR200", parameter VAR184 = 1, parameter VAR92 = 4'hc,
parameter VAR210 = 4'hf,
parameter ... | mit |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/COUNTER/COUNTER.v | 4,425 | module MODULE1 (
VAR9,
VAR3,
VAR20,
VAR23);
input VAR9;
input VAR3;
input VAR20;
output [13:0] VAR23;
wire [13:0] VAR1;
wire [13:0] VAR23 = VAR1[13:0];
VAR10 VAR21 (
.VAR9 (VAR9),
.VAR3 (VAR3),
.VAR20 (VAR20),
.VAR23 (VAR1),
.VAR25 (1'b0),
.VAR22 (1'b0),
.VAR5 (1'b1),
.VAR11 (1'b1),
.VAR24 (),
.VAR2 ({14{1'b0}}),
.VAR8... | gpl-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_ln1px_double_s5.v | 1,326 | module MODULE1 (
enable, VAR1,
VAR2,
VAR9,
VAR5);
input enable, VAR1;
input VAR2;
input [63:0] VAR9;
output [63:0] VAR5;
wire [63:0] VAR3;
wire [63:0] VAR5 = VAR3[63:0];
VAR4 VAR10 ( .clk(VAR2),
.VAR8(1'b0),
.en(enable),
.VAR6(VAR9),
.VAR7(VAR3));
endmodule | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/phy_wrcal.v | 40,300 | module MODULE1 #
(
parameter VAR29 = 100, parameter VAR22 = 2, parameter VAR114 = 64, parameter VAR15 = 3, parameter VAR34 = 8, parameter VAR65 = 8, parameter VAR18 = "VAR12" )
(
input clk,
input rst,
input VAR101,
input VAR93,
input VAR78,
input VAR58,
output VAR72,
output reg VAR74,
output reg VAR17,
output reg VAR12... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_scm.v | 12,878 | module MODULE1 (
VAR50, VAR7, VAR30,
VAR57, VAR46, VAR24,
VAR2, VAR47, VAR55, VAR19,
VAR23, VAR33, VAR21, VAR48,
VAR35, VAR37, VAR12,
VAR32, VAR51, VAR31
) ;
parameter VAR27 = 32 ;
input [44:15] VAR2 ; input [44:15] VAR47 ; input [14:0] VAR55 ; input VAR19 ;
input VAR23 ; input [1:0] VAR33 ; input [7:0] VAR21;
input [2... | gpl-2.0 |
cpulabs/gci-std-display | rtl/gci_std_display.v | 6,478 | module MODULE1(
input wire VAR64,
input wire VAR21,
input wire VAR40,
output wire VAR24,
input wire VAR9,
input wire [31:0] VAR19, input wire [31:0] VAR52,
output wire VAR46,
input wire VAR2,
output wire [31:0] VAR45,
output wire VAR44,
input wire VAR1,
output wire [23:0] VAR59,
input wire VAR47,
input wire VAR38,
outp... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill.blackbox.v | 1,166 | module MODULE1 ();
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
ChrisPVille/RL02 | FPGA/ipcore_dir/commandAndWriteFIFO.v | 13,736 | module MODULE1(
clk,
VAR171,
din,
VAR277,
VAR1,
dout,
VAR417,
VAR382,
VAR241
);
input clk;
input VAR171;
input [15 : 0] din;
input VAR277;
input VAR1;
output [15 : 0] dout;
output VAR417;
output VAR382;
output VAR241;
VAR223 #(
.VAR342(0),
.VAR100(0),
.VAR378(0),
.VAR59(0),
.VAR299(0),
.VAR228(0),
.VAR278(0),
.VAR183(3... | gpl-3.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_gate_bits.v | 2,475 | module MODULE1
(select, VAR3, VAR5);
parameter VAR4 = 1;
parameter VAR7 = 32;
parameter VAR6 = VAR8;
input [0:VAR4-1] select;
input [0:VAR4*VAR7-1] VAR3;
output [0:VAR4*VAR7-1] VAR5;
wire [0:VAR4*VAR7-1] VAR5;
generate
genvar VAR9;
for(VAR9 = 0; VAR9 < VAR4; VAR9 = VAR9 + 1)
begin:VAR10
VAR1
.VAR7(VAR7),
.VAR6(VAR6))
V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22o/sky130_fd_sc_lp__a22o.functional.v | 1,511 | module MODULE1 (
VAR4 ,
VAR11,
VAR10,
VAR3,
VAR1
);
output VAR4 ;
input VAR11;
input VAR10;
input VAR3;
input VAR1;
wire VAR12 ;
wire VAR5 ;
wire VAR8;
and VAR9 (VAR12 , VAR3, VAR1 );
and VAR7 (VAR5 , VAR11, VAR10 );
or VAR6 (VAR8, VAR5, VAR12);
buf VAR2 (VAR4 , VAR8 );
endmodule | apache-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_mult_cell.v | 8,003 | module MODULE1 (
VAR16,
VAR25,
VAR17,
clk,
VAR35,
VAR14,
VAR26,
VAR41
)
;
output [ 31: 0] VAR14;
output [ 31: 0] VAR26;
output [ 31: 0] VAR41;
input [ 31: 0] VAR16;
input [ 31: 0] VAR25;
input VAR17;
input clk;
input VAR35;
wire [ 31: 0] VAR14;
wire [ 31: 0] VAR26;
wire [ 31: 0] VAR41;
wire VAR9;
wire [ 31: 0] VAR42;
w... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_gclk_inv_r90_256x.v | 1,308 | module MODULE1 (
VAR1,
VAR2 );
output VAR1;
input VAR2;
assign VAR1 = ~( VAR2 );
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.v | 2,119 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR4,
VAR2,
VAR5 ,
VAR6
);
output VAR7 ;
input VAR8 ;
input VAR4;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR1 VAR3 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7,
VAR8
);
output VAR7;
input VAR8;
supply1 VAR4;
supply0 VAR2;... | apache-2.0 |
8l/beri | cherilibs/trunk/peripherals/i2c/i2c_master_bit_ctrl.v | 21,382 | module MODULE1 (
input clk, input rst, input VAR40, input VAR4,
input [15:0] VAR13,
input [ 3:0] VAR10, output reg VAR27, output reg VAR9, output reg VAR15,
input din,
output reg dout,
input VAR53, output VAR6, output reg VAR17, input VAR42, output VAR37, output reg VAR26 );
reg [ 1:0] VAR47, VAR46; reg [ 2:0] VAR29, V... | apache-2.0 |
bluespec/Flute | builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCSR_MIE.v | 5,900 | module MODULE1(VAR38,
VAR11,
VAR34,
VAR10,
VAR24,
VAR35,
VAR4,
VAR33,
VAR1,
VAR25,
VAR32,
VAR8,
VAR18);
input VAR38;
input VAR11;
input VAR34;
output [31 : 0] VAR10;
input [27 : 0] VAR24;
input [31 : 0] VAR35;
input VAR4;
output [31 : 0] VAR33;
output [31 : 0] VAR1;
input [27 : 0] VAR25;
input [31 : 0] VAR32;
input VAR... | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/altera_jtag_streaming.v | 26,246 | module MODULE1 #(
parameter VAR64 = 0,
parameter VAR29 = 0,
parameter VAR31 = 0,
parameter VAR108 = -1
) (
input wire VAR113,
input wire VAR55,
output reg VAR119,
input wire [2:0] VAR23,
input wire VAR28,
input wire VAR70,
input wire VAR114,
input wire VAR94,
output wire [7:0] VAR87,
output wire VAR81,
input wire [7:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlclkp/sky130_fd_sc_hvl__dlclkp.functional.pp.v | 1,947 | module MODULE1 (
VAR8,
VAR3,
VAR4 ,
VAR16,
VAR1,
VAR10 ,
VAR6
);
output VAR8;
input VAR3;
input VAR4 ;
input VAR16;
input VAR1;
input VAR10 ;
input VAR6 ;
wire VAR9 ;
wire VAR5 ;
wire VAR14;
not VAR7 (VAR5 , VAR4 );
VAR12 VAR13 (VAR9 , VAR3, VAR5, , VAR16, VAR1);
and VAR11 (VAR14, VAR9, VAR4 );
VAR15 VAR2 (VAR8 , VAR14... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9643_v6_00_a/hdl/verilog/axi_ad9643_channel.v | 6,971 | module MODULE1 (
VAR20,
VAR60,
VAR62,
VAR18,
VAR40,
VAR46,
VAR59,
VAR64,
VAR65,
VAR71,
VAR42,
VAR50,
VAR32,
VAR41,
VAR37,
VAR80,
VAR58,
VAR53,
VAR67);
parameter VAR79 = 0;
parameter VAR75 = 0;
input VAR20;
input VAR60;
input [13:0] VAR62;
input VAR18;
output [15:0] VAR40;
input [15:0] VAR46;
output [15:0] VAR59;
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfstp/sky130_fd_sc_lp__dfstp_1.v | 2,273 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR5 ,
VAR9,
VAR6 ,
VAR4 ,
VAR8 ,
VAR7
);
output VAR3 ;
input VAR10 ;
input VAR5 ;
input VAR9;
input VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR7 ;
VAR1 VAR2 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODU... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_128.v | 1,550 | module MODULE2 (
VAR9,
VAR6
);
input [31:0] VAR9;
output [31:0]
VAR6;
wire [31:0]
VAR4,
VAR11,
VAR1,
VAR12,
VAR10,
VAR15,
VAR5,
VAR3,
VAR13,
VAR7;
assign VAR4 = VAR9;
assign VAR5 = VAR10 - VAR15;
assign VAR10 = VAR12 - VAR4;
assign VAR12 = VAR4 << 7;
assign VAR13 = VAR3 - VAR5;
assign VAR3 = VAR5 << 7;
assign VAR15 = V... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v | 3,914 | module MODULE1(VAR16, VAR14, VAR8,
VAR32, VAR18, VAR31, VAR42, VAR46, VAR11,
VAR33, VAR36, VAR28, VAR3, VAR22, VAR45,
VAR19, VAR26, VAR2, VAR25, VAR15, VAR6,
VAR13, VAR29, VAR1, VAR21, VAR40, VAR38,
VAR20, VAR43, VAR17, VAR35, VAR39, VAR7, VAR41,
VAR37, VAR23, VAR10, VAR9, VAR30, VAR34, VAR5,
VAR27, VAR47, VAR44, VAR24... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp_4.v | 2,128 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR4 ,
VAR9,
VAR5,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR9;
input VAR5;
input VAR2 ;
input VAR7 ;
VAR8 VAR1 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3 ,
VAR6,
VAR4
);
output VAR3 ... | apache-2.0 |
zeruniverse/pipelined_CPU | .v source code/cpu_top.v | 2,523 | module MODULE1(
input wire VAR71,rst,clk,
input wire [1:0] VAR47,
input wire [4:0] VAR62,
output wire VAR38,
output wire [5:0] VAR68,
output wire [3:0] VAR57,
output wire [7:0] VAR64
);
wire VAR50;
wire VAR5;
wire VAR12;
wire [31:0] VAR9;
reg [15:0] VAR81,VAR11=0;
wire [7:0] VAR83;
wire [31:0] VAR14;
wire [31:0] VAR21;... | gpl-3.0 |
hoglet67/CoPro6502 | src/m32632/DATENPFAD.v | 10,515 | module MODULE1( VAR74, VAR92, VAR79, VAR140, VAR33, VAR38, VAR58, VAR76, VAR148, VAR3, VAR81, VAR61, VAR29,
VAR158, VAR40, VAR108, VAR23, VAR157, VAR156, VAR94, VAR21, VAR102, VAR133, VAR151, VAR67,
VAR4, VAR5, VAR129, VAR98, VAR116, VAR25, VAR89, VAR15, VAR114, VAR1, VAR26, VAR18, VAR78,
VAR46, VAR57, VAR155, VAR22, V... | gpl-3.0 |
aquaxis/synverll | lib/sdiv/aq_div31x31.v | 8,001 | module MODULE1(
input VAR53,
input VAR28,
input [30:0] VAR48,
input [30:0] VAR10,
output [30:0] VAR27,
output [30:0] VAR41
);
reg [62:0] VAR52;
reg [62:0] VAR20;
reg [62:0] VAR4;
reg [62:0] VAR29;
reg [62:0] VAR42;
reg [62:0] VAR2;
reg [62:0] VAR19;
reg [62:0] VAR63;
reg [62:0] VAR47;
reg [62:0] VAR18;
reg [62:0] VAR14... | mit |
Beck-Sisyphus/EE471 | Lab4/sourceCode/CPUcontrol.v | 1,552 | module MODULE1 (clk, rst, VAR27, VAR7, VAR6, VAR33, VAR30, VAR17, VAR23, VAR2, VAR10, VAR22, VAR18, VAR8, VAR14, VAR28);
input clk, rst, VAR27, VAR7;
input [31:0] VAR6;
input [6:0] VAR33;
output VAR30, VAR17, VAR23, VAR2, VAR10, VAR22;
output [4:0] VAR18, VAR8, VAR14;
output [31:0] VAR28;
wire [31:0] VAR4, VAR19;
wire ... | mit |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.