repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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ShepardSiegel/ocpi | libsrc/hdl/ocpi/fpgaTop_n210.v | 3,989 | module MODULE1(
input wire VAR12, input wire VAR50, input wire VAR17,
output wire [5:1] VAR48, output wire [31:0] VAR43,
input wire VAR16, output wire VAR22,
output wire VAR7,
output wire [7:0] VAR55,
output wire VAR37,
output wire VAR42,
input wire VAR36,
input wire [7:0] VAR45,
input wire VAR35,
input wire VAR13,
inp... | lgpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_gray_cols_V.v | 2,983 | module MODULE1 (
clk,
VAR16,
VAR21,
VAR13,
VAR9);
parameter VAR2 = 32'd12;
parameter VAR8 = 32'd2;
parameter VAR3 = 32'd3;
input clk;
input [VAR2-1:0] VAR16;
input VAR21;
input [VAR8-1:0] VAR13;
output [VAR2-1:0] VAR9;
reg[VAR2-1:0] VAR18 [0:VAR3-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR21)
begin
for (VAR... | gpl-3.0 |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/ISP1362_IF.v | 2,540 | module MODULE1( VAR23,
VAR1,
VAR19,
VAR16,
VAR21,
VAR24,
VAR6,
VAR25,
VAR15,
VAR7,
VAR27,
VAR20,
VAR8,
VAR14,
VAR5,
VAR13,
VAR18,
VAR3,
VAR11,
VAR10,
VAR4,
VAR22,
VAR12,
VAR26,
VAR9,
VAR17
);
input [15:0] VAR23;
input VAR19;
input VAR16;
input VAR21;
input VAR24;
input VAR6;
input VAR25;
output [15:0] VAR1;
output VAR1... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/packet_buffer_bypass.v | 3,782 | module MODULE1(
input clk,
input reset,
output [239:0] VAR59,
input [63:0] VAR44,
input [23:0] VAR17,
input VAR4,
output reg VAR30,
input VAR2,
output reg VAR54,
output reg [63:0] VAR25,
output reg [23:0] VAR45,
output reg VAR32,
output reg VAR46,
input VAR6,
output reg [1:0] VAR16,
output reg VAR38,
output reg VAR33,
... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/megafunctions/net2pci_dma_512x32_bb.v | 6,305 | module MODULE1 (
VAR8,
VAR10,
VAR7,
VAR5,
VAR9,
VAR3,
VAR6,
VAR11,
VAR4,
VAR2,
VAR1);
input VAR8;
input VAR10;
input [31:0] VAR7;
input VAR5;
input VAR9;
output VAR3;
output VAR6;
output VAR11;
output VAR4;
output [31:0] VAR2;
output [8:0] VAR1;
endmodule | mit |
secworks/fltfpga | src/rtl/fltfpga.v | 4,781 | module MODULE1(
input wire clk,
input wire VAR14,
output wire VAR11,
input wire VAR16,
output wire VAR18,
input wire VAR13,
output wire [23 : 0] VAR9,
output wire VAR15,
output wire VAR12,
output wire VAR1,
output wire VAR19,
output wire VAR4,
input wire VAR8,
output wire VAR17,
input wire VAR3,
output wire VAR2,
outpu... | bsd-2-clause |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/RMON/RMON_dpram.v | 1,292 | module MODULE1(
VAR14 ,
VAR13 ,
VAR19,
VAR18,
VAR10,
VAR17,
VAR9,
VAR7
);
input VAR14 ;
input VAR13 ;
input [5:0] VAR19;
input [31:0] VAR18;
output [31:0] VAR10;
input VAR17;
input [5:0] VAR9;
output [31:0] VAR7;
wire VAR6;
wire VAR4;
assign VAR6=VAR13;
assign VAR4=VAR13;
VAR23 #(32,6,"VAR20") VAR11(
.VAR21 (VAR18 ),
.... | apache-2.0 |
kDaniu/miaow | src/verilog/rtl/issue/inflight_instr_counter.v | 2,031 | module MODULE1
(
VAR21, VAR10,
clk, rst, VAR6, VAR17, VAR8,
VAR12
);
input clk,rst, VAR6,
VAR17, VAR8,
VAR12;
output VAR21, VAR10;
wire VAR13;
wire [3:0] MODULE1;
wire [1:0] VAR3;
wire [2:0] VAR2;
wire [3:0] VAR11;
wire [3:0] VAR15;
VAR20 VAR4
(
VAR3[0],
VAR3[1],
VAR6,
VAR17,
VAR8
);
VAR18 #(3) VAR7
(
.VAR16({{2{1'b0}}... | bsd-3-clause |
nickdesaulniers/Omicron | reg_block.v | 1,394 | module MODULE1(
input [2:0] VAR4,
input [2:0] VAR2,
input [2:0] VAR7,
input [15:0] VAR6,
input VAR1,
input VAR9,
output [15:0] VAR3,
output [15:0] VAR5
);
reg [15:0] VAR8 [7:0];
assign VAR3 = VAR8[VAR4];
assign VAR5 = VAR8[VAR2];
always@(posedge VAR1) begin
if(VAR9) begin
VAR8[3'b0] <= 16'b0;
if(VAR7 != 3'b0) begin
VAR... | gpl-3.0 |
edgd1er/M1S1_INFO | S1_AEO/TP2/ipcore_dir/timer.v | 5,761 | module MODULE1
( input VAR9,
output VAR19,
output VAR43
);
VAR26 VAR27
(.VAR48 (VAR40),
.VAR2 (VAR9));
wire VAR28;
wire VAR1;
wire [7:0] VAR6;
wire VAR30;
wire VAR11;
VAR23
.VAR15 (1),
.VAR25 (4),
.VAR49 ("VAR31"),
.VAR17 (10.0),
.VAR47 ("VAR13"),
.VAR45 ("1X"),
.VAR21 ("VAR8"),
.VAR18 (0),
.VAR4 ("VAR31"))
VAR20
(.VAR... | gpl-2.0 |
thinkoco/de1_soc_opencl | de10_nano_sharedonly_hdmi/ip/debounce/debounce.v | 2,532 | module MODULE1 (
clk,
VAR4,
VAR6,
VAR1
);
parameter VAR12 = 32; parameter VAR9 = "VAR2"; parameter VAR10 = 50000; parameter VAR7 = 16;
input wire clk;
input wire VAR4;
input wire [VAR12-1:0] VAR6;
output wire [VAR12-1:0] VAR1;
reg [VAR7-1:0] counter [0:VAR12-1];
wire VAR3 [0:VAR12-1];
wire VAR11 [0:VAR12-1];
genvar VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2b/sky130_fd_sc_ms__and2b.pp.symbol.v | 1,290 | module MODULE1 (
input VAR1 ,
input VAR5 ,
output VAR6 ,
input VAR7 ,
input VAR2,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
megari/sd2snes | verilog/sd2snes/address.v | 9,760 | module MODULE1(
input VAR3,
input [7:0] VAR12, input [2:0] VAR33, input [23:0] VAR13, input [7:0] VAR32, input VAR35, output [23:0] VAR22, output VAR34, output VAR10, output VAR23, output VAR1, input [23:0] VAR36,
input [23:0] VAR9,
output VAR14,
output VAR42,
output VAR20,
output VAR16,
input [14:0] VAR27,
output VAR3... | gpl-2.0 |
karatekid/ultrasonic-fountain | hardware/src/message_printer.v | 1,696 | module MODULE1 (
input clk,
input rst,
output [7:0] VAR20,
output reg VAR4,
input VAR18,
input [7:0] VAR21,
input VAR17
);
localparam VAR5 = 2;
localparam VAR3 = 0,
VAR19 = 1,
VAR13 = 2,
VAR8 = 3;
localparam VAR12 = 2;
reg [VAR5-1:0] VAR14, VAR2;
reg [3:0] VAR10, VAR7;
reg [7:0] VAR16, VAR15;
wire [7:0] VAR6;
VAR9 VAR9... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18.functional.pp.v | 1,832 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR11,
VAR6,
VAR3 ,
VAR4
);
output VAR7 ;
input VAR9 ;
input VAR11;
input VAR6;
input VAR3 ;
input VAR4 ;
wire VAR12 ;
wire VAR2;
buf VAR1 (VAR12 , VAR9 );
VAR8 VAR10 (VAR2, VAR12, VAR11, VAR6);
buf VAR5 (VAR7 , VAR2 );
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_5/ab882192/src/ScrambleEncoder.v | 8,986 | module MODULE1
(
parameter VAR46 = 32 ,
parameter VAR5 = 32 ,
parameter VAR3 = 16 ,
parameter VAR52 = 3
)
(
VAR39 ,
VAR24 ,
VAR18 ,
VAR36 ,
VAR25 ,
VAR42 ,
VAR32 ,
VAR29 ,
VAR19 ,
VAR48 ,
VAR47 ,
VAR21 ,
VAR16 ,
VAR12 ,
VAR55 ,
VAR31 ,
VAR14 ,
VAR38 ,
VAR13 ,
VAR15 ,
VAR8 ,
VAR20 ,
VAR49 ,
VAR37
);
input VAR39 ;
input ... | gpl-3.0 |
benjaminfjones/fpga-led-counter | src/mojo_top.v | 1,124 | module MODULE1(
input clk,
input VAR14,
input VAR9,
output[7:0]VAR7,
output VAR1,
input VAR3,
input VAR15,
input VAR5,
output [3:0] VAR18,
input VAR8, output VAR17, input VAR2 );
wire rst = ~VAR14;
assign VAR1 = 1'VAR11;
assign VAR17 = 1'VAR11;
assign VAR18 = 4'VAR16;
genvar VAR4;
generate
for (VAR4 = 0; VAR4 < 8; VAR4... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf.behavioral.v | 1,345 | module MODULE1 (
VAR6,
VAR8
);
output VAR6;
input VAR8;
supply1 VAR7;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR2 ;
wire VAR1;
buf VAR3 (VAR1, VAR8 );
buf VAR9 (VAR6 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp.behavioral.pp.v | 2,935 | module MODULE1 (
VAR14 ,
VAR10 ,
VAR11 ,
VAR29 ,
VAR23 ,
VAR15 ,
VAR4 ,
VAR27 ,
VAR20
);
input VAR14 ;
input VAR10 ;
output VAR11 ;
output VAR29 ;
input VAR23 ;
input VAR15 ;
input VAR4 ;
input VAR27 ;
input VAR20;
wire VAR9 ;
wire VAR18 ;
wire VAR25 ;
reg VAR13 ;
wire VAR17 ;
wire VAR28 ;
wire VAR12 ;
wire VAR2;
wire ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxbp/sky130_fd_sc_ls__edfxbp.functional.pp.v | 2,082 | module MODULE1 (
VAR15 ,
VAR8 ,
VAR16 ,
VAR7 ,
VAR14 ,
VAR4,
VAR11,
VAR3 ,
VAR5
);
output VAR15 ;
output VAR8 ;
input VAR16 ;
input VAR7 ;
input VAR14 ;
input VAR4;
input VAR11;
input VAR3 ;
input VAR5 ;
wire VAR10 ;
wire VAR9;
VAR13 VAR2 (VAR9, VAR10, VAR7, VAR14 );
VAR17 VAR6 VAR18 (VAR10 , VAR9, VAR16, , VAR4, VAR11... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p.symbol.v | 1,393 | module MODULE1 (
input VAR2 ,
output VAR7 ,
input VAR5
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
patrick-samy/ace | data/path.v | 3,591 | module MODULE1();
wire[31:0] VAR62;
wire[31:0] VAR29;
wire[31:0] VAR27;
wire[31:0] VAR34;
wire[31:0] VAR59;
wire VAR60;
VAR38 VAR35(VAR26, VAR50);
VAR14 VAR25(VAR50, VAR43);
VAR4 VAR1(VAR43,
VAR26,
VAR28);
VAR21 VAR37(VAR28,
VAR58,
VAR47,
VAR3,
VAR33,
VAR40,
VAR15,
VAR8,
VAR49,
VAR55,
VAR57);
VAR44 VAR11(VAR3,
VAR15,
V... | mit |
combinatorylogic/soc | backends/c2/hw/blackice2/delay.v | 1,774 | module MODULE1(input clk,
input rst,
input VAR21,
input [7:0] VAR35,
input VAR18,
output reg [7:0] VAR15,
output VAR6,
output VAR31);
reg [8:0] VAR19,VAR11,VAR11,VAR8,VAR12,VAR3,VAR9,VAR14,VAR25,VAR5;
wire [8:0] VAR26,VAR17,VAR30,VAR34,VAR33,VAR29,VAR20,VAR23,VAR4,VAR32;
wire VAR16,VAR22,VAR24,VAR1,VAR27,VAR7,VAR2,VAR1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_4.behavioral.v | 2,113 | module MODULE1( VAR9, VAR8, VAR2 );
input VAR9, VAR8;
output VAR2;
reg VAR5;
VAR1 VAR6(.VAR9(VAR9),.VAR8(VAR8),.VAR2(VAR2),.VAR5(VAR5));
VAR1 VAR3(.VAR9(VAR9),.VAR8(VAR8),.VAR2(VAR2),.VAR5(VAR5));
not VAR7(VAR4,VAR8);
buf VAR10(VAR11,VAR8); | apache-2.0 |
shipinsworks/BeD | rtl/memory_8bit.v | 1,609 | module MODULE1 #(
parameter integer VAR1 = 32,
parameter integer VAR10 = 512 )(
input wire clk,
input wire [VAR1-1:0] VAR9,
input wire [7:0] VAR2,
input wire VAR7,
input wire VAR5,
input wire [VAR1-1:0] VAR12,
output wire [7:0] VAR13
);
function integer VAR6;
input integer addr;
begin
addr = addr - 1;
for (VAR6=0; addr... | mit |
peteasa/parallella-fpga | AdiHDLLib/library/axi_hdmi_tx/axi_hdmi_tx_es.v | 5,079 | module MODULE1 (
VAR8,
VAR9,
VAR15,
VAR4,
VAR2);
parameter VAR14 = 32;
localparam VAR5 = VAR14/8;
input VAR8;
input VAR9;
input VAR15;
input [(VAR14-1):0] VAR4;
output [(VAR14-1):0] VAR2;
reg VAR16 = 'd0;
reg [(VAR14-1):0] VAR10 = 'd0;
reg VAR6 = 'd0;
reg [(VAR14-1):0] VAR1 = 'd0;
reg VAR11 = 'd0;
reg [(VAR14-1):0] VAR... | lgpl-3.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_sub_inputs.v | 2,304 | module MODULE1 (
address,
VAR4,
clk,
VAR6,
VAR8,
VAR7,
VAR9,
VAR5
)
;
output [ 8: 0] VAR9;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input VAR4;
input clk;
input VAR6;
input VAR8;
input [ 31: 0] VAR7;
wire VAR3;
reg [ 8: 0] VAR2;
wire [ 8: 0] VAR9;
wire [ 8: 0] VAR1;
wire [ 31: 0] VAR5;
assign VAR3 = 1;
assign VAR1 ... | gpl-3.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/sfa_2x2_v1_0/sfa_5to1_mux.v | 2,511 | module MODULE1
(
output reg VAR7 ,
input wire VAR11 ,
input wire [31 : 0] VAR18 ,
output reg VAR9 ,
input wire VAR2 ,
input wire [31 : 0] VAR12 ,
output reg VAR17 ,
input wire VAR10 ,
input wire [31 : 0] VAR15 ,
output reg VAR14 ,
input wire VAR5 ,
input wire [31 : 0] VAR6 ,
output reg VAR8 ,
input wire VAR13 ,
input w... | bsd-3-clause |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_except.v | 20,409 | module MODULE1(
clk, rst,
VAR102, VAR35, VAR79, VAR26, VAR46, VAR20, VAR92,
VAR111, VAR58, VAR98, VAR69, VAR14, VAR93,
VAR39, VAR22, VAR6, VAR81, VAR101, VAR16,
VAR71, VAR44, VAR64, VAR50, VAR48, VAR91, VAR37,
VAR36, VAR5, VAR57,
VAR9, VAR68, VAR86, VAR74, VAR99, VAR18, VAR52, VAR90, VAR45, VAR3,
VAR65, VAR19, VAR89, V... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/ip_dram/clocking/mig_7series_v2_3_infrastructure.v | 29,640 | module MODULE1 #
(
parameter VAR37 = "VAR65", parameter VAR51 = 100, parameter VAR42 = 3000, parameter VAR8 = 2, parameter VAR53 = "VAR13",
parameter VAR63 = "VAR65",
parameter VAR1 = 4, parameter VAR55 = 1, parameter VAR16 = 45.0, parameter VAR54 = 16, parameter VAR69 = 4, parameter VAR18 = 64, parameter VAR47 = 16, p... | mit |
The-OpenROAD-Project/asap7 | asap7sc7p5t_27/Verilog/asap7sc7p5t_SEQ_LVT_TT_201020.v | 73,237 | module MODULE1 (VAR8, VAR1, VAR19, VAR5, VAR20);
output VAR8;
input VAR1, VAR19, VAR5, VAR20;
reg VAR7;
wire VAR12, VAR10, VAR25, VAR17;
wire VAR28, VAR21, VAR27;
not (VAR28, VAR12);
VAR6 (VAR27, VAR17, VAR28, VAR25, VAR10);
VAR22 (VAR21, VAR7, VAR17, VAR28, VAR25, VAR10, VAR27);
buf (VAR8, VAR21);
wire VAR16, VAR2, VA... | bsd-3-clause |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/niosII_system/submodules/niosII_system_pixel_out_buffer.v | 7,233 | module MODULE1 (
clk,
reset,
address,
VAR3,
read,
write,
VAR14,
VAR2,
VAR8,
VAR1,
VAR4,
VAR15,
VAR6,
VAR9,
VAR12,
VAR10
);
input clk;
input reset;
input [17: 0] address;
input [ 1: 0] VAR3;
input read;
input write;
input [15: 0] VAR14;
inout [15: 0] VAR2;
output reg [15: 0] VAR8;
output reg VAR1;
output reg [17: 0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxtp/sky130_fd_sc_ls__sdfxtp.blackbox.v | 1,344 | module MODULE1 (
VAR7 ,
VAR8,
VAR9 ,
VAR6,
VAR1
);
output VAR7 ;
input VAR8;
input VAR9 ;
input VAR6;
input VAR1;
supply1 VAR2;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a_lp.v | 2,452 | module MODULE1 (
VAR2 ,
VAR11 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR3 ,
VAR6,
VAR12,
VAR8 ,
VAR7
);
output VAR2 ;
input VAR11 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR3 ;
input VAR6;
input VAR12;
input VAR8 ;
input VAR7 ;
VAR9 VAR4 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6... | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/verilog/feedforward_ST_WandB.v | 1,457 | module MODULE1 (VAR4, VAR2, VAR1, VAR9, VAR7, clk);
parameter VAR6 = 32;
parameter VAR5 = 13;
parameter VAR3 = 5040;
input[VAR5-1:0] VAR4;
input VAR2;
input[VAR6-1:0] VAR1;
input VAR9;
output reg[VAR6-1:0] VAR7;
input clk;
reg [VAR6-1:0] VAR8[VAR3-1:0];
begin
begin
begin
end | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/serdes/serdes_tx.v | 5,509 | module MODULE1
(input clk,
input rst,
output VAR1,
output reg [15:0] VAR5,
output reg VAR43,
output reg VAR33,
input [31:0] VAR22,
input [3:0] VAR20,
output VAR4,
input VAR3,
input VAR55,
input VAR9,
input VAR15,
output VAR45,
output [15:0] VAR14,
output VAR34,
output VAR26,
output [31:0] VAR51
);
localparam VAR50 = 8'... | gpl-2.0 |
GustavoOS/ARMAria | src/ARMAria.v | 4,142 | module MODULE1
parameter VAR97 = 32,
parameter VAR53 = 16,
parameter VAR84 = 5,
parameter VAR23 = 16,
parameter VAR33 = 7*8,
parameter VAR68 = 12
)(
input VAR8, VAR66, VAR19,
input VAR29, VAR90,
input [(VAR23 - 1) : 0] VAR26,
output [(VAR23 - 1) : 0] VAR4,
output [(VAR84 - 1) : 0] VAR36,
output [(VAR33 - 1) : 0] VAR87,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o.symbol.v | 1,394 | module MODULE1 (
input VAR4,
input VAR7,
input VAR5,
input VAR3,
input VAR2,
output VAR10
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3.pp.symbol.v | 1,274 | module MODULE1 (
input VAR3 ,
input VAR8 ,
input VAR1 ,
output VAR4 ,
input VAR6 ,
input VAR7,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
Lan-Hekary/ARM | single_cycle.v | 1,566 | module MODULE3(input clk,input enable,output VAR22,output reg VAR6,VAR12);
reg [32:0] VAR15 = 0;
reg VAR18=0;
reg VAR17=0;
reg VAR1=0;
reg reset=0;
wire VAR13,VAR10;
MODULE1 MODULE1(VAR18,reset,VAR13,VAR10);
always @(negedge enable,posedge VAR1)begin
if(VAR1)
VAR17=0;
end
else begin
if(!enable)
VAR17=1;
end
else
VAR17=... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric.functional.pp.v | 1,962 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR11 ,
VAR9 ,
VAR1,
VAR8 ,
VAR13
);
output VAR4 ;
input VAR6 ;
input VAR11 ;
input VAR9 ;
input VAR1;
input VAR8 ;
input VAR13 ;
wire VAR3;
wire VAR10 ;
VAR12 VAR5 (VAR3, VAR6, VAR1, VAR9 );
buf VAR7 (VAR10 , VAR3 );
VAR12 VAR2 (VAR4 , VAR10, VAR11, VAR9);
endmodule | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | core/core_mem_wb.v | 1,762 | module MODULE1( clk,
rst,
VAR10,
VAR11,
VAR4,
VAR9,
VAR2,
VAR8,
VAR7,
VAR3,
VAR6,
VAR5,
VAR1
);
input clk;
input rst;
input VAR10;
input VAR11;
input [31:0] VAR4;
input [31:0] VAR9;
input VAR2;
input [4:0] VAR8;
output VAR7;
output VAR3;
output [31:0] VAR6;
output [31:0] VAR5;
output [4:0] VAR1;
reg VAR7;
reg VAR3;
reg... | apache-2.0 |
elegabriel/myzju | junior1/CA/LAB/lab6/lab6_gxl_3120102146/code/top.v | 9,669 | module MODULE1(VAR65, VAR95, VAR119, VAR156, VAR64, VAR155,VAR70,
VAR129, VAR51, VAR114, VAR46
);
input wire VAR65;
input wire [3:0] VAR95;
input wire VAR119,VAR156,VAR155,VAR64;
output wire VAR129, VAR51, VAR114;
output wire [3:0] VAR46;
output wire [7:0] VAR70;
wire VAR18;
wire rst;
reg VAR73,VAR67;
wire VAR101,VAR74... | gpl-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/infrastructure_iobs.v | 12,682 | module MODULE1 (
VAR8,
VAR38,
VAR30,
VAR70,
VAR40,
VAR87,
VAR62,
VAR23,
VAR60,
VAR65,
VAR90,
VAR80,
VAR97,
VAR7,
VAR33,
VAR54,
VAR98,
VAR5,
VAR78,
VAR100,
VAR14,
VAR77,
VAR95,
VAR9,
VAR94
);
input VAR8;
input VAR38;
input VAR30;
input VAR70;
input [7:0] VAR87;
input [7:0] VAR62;
output VAR40;
output VAR65;
output VAR90... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32o/sky130_fd_sc_ms__a32o.pp.blackbox.v | 1,458 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR7 ,
VAR5 ,
VAR4 ,
VAR3 ,
VAR6,
VAR9,
VAR8 ,
VAR1
);
output VAR2 ;
input VAR10 ;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR9;
input VAR8 ;
input VAR1 ;
endmodule | apache-2.0 |
jmassucco17/full_mips | processor/SingleCycleDatapath/Processor.v | 5,598 | module MODULE1(input VAR1,
input VAR75);
wire[31:0] VAR13;
wire[31:0] VAR12;
VAR70 VAR64(
VAR1,
VAR75,
VAR13,
VAR12);
wire[31:0] VAR61;
wire[31:0] VAR38;
VAR19 VAR56(
VAR1,
VAR75,
VAR61,
VAR38);
assign VAR61 = VAR12;
wire[31:0] VAR21;
wire[31:0] VAR24;
VAR35 VAR36(VAR21,
VAR24);
assign VAR21 = VAR12;
wire[31:0] VAR32;
... | mit |
sabertazimi/hust-lab | architecture/design/fpga/src/branch_target_buffer.v | 6,274 | module MODULE1
(
input clk,
input rst,
input en,
input VAR48,
input VAR45,
input VAR5,
input [VAR44-1:0] VAR21,
input [VAR44-1:0] VAR32,
input [VAR44-1:0] VAR12,
input [VAR44-1:0] VAR25,
output [VAR1-1:0] VAR17,
output VAR9,
output [VAR44-1:0] VAR35
);
integer VAR41;
reg valid [VAR46-1:0];
reg [VAR1-1:0] VAR23 [VAR46-1... | mit |
kammce/LPCXpresso-Nexys4-Servo-Commander | ServoCommander.srcs/sources_1/imports/new/segment.v | 1,029 | module MODULE1(
input wire [9:0] in,
output reg [10:0] out,
output reg valid
);
always @(in) begin
valid = 1;
casex(in)
11'VAR5: out = 2000;
11'VAR7: out = 1800;
11'VAR6: out = 1600;
11'VAR9: out = 1400;
11'VAR4: out = 1200;
11'VAR3: out = 1000;
11'VAR1: out = 800;
11'VAR8: out = 600;
11'VAR2: out = 400;
11'b0000000001... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.behavioral.pp.v | 1,164 | module MODULE1( VAR1, VAR6, VAR3, VAR5 );
input VAR1;
inout VAR3, VAR5;
output VAR6;
VAR7 VAR4(.VAR1(VAR1),.VAR6(VAR6),.VAR3(VAR3),.VAR5(VAR5));
VAR7 VAR2(.VAR1(VAR1),.VAR6(VAR6),.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_jesd_align.v | 4,349 | module MODULE1 (
VAR11,
VAR10,
VAR1,
VAR7,
VAR8,
VAR5,
VAR3);
input VAR11;
input [ 3:0] VAR10;
input [ 3:0] VAR1;
input [ 3:0] VAR7;
input [31:0] VAR8;
output VAR5;
output [31:0] VAR3;
reg [31:0] VAR4 = 'd0;
reg [ 3:0] VAR13 = 'd0;
reg [ 3:0] VAR9 = 'd0;
reg [31:0] VAR3 = 'd0;
reg VAR5 = 'd0;
wire [ 3:0] VAR2;
wire VAR... | mit |
8l/beri | cherilibs/trunk/peripherals/i2c/i2c_master_byte_ctrl.v | 10,585 | module MODULE1 (
clk, rst, VAR8, VAR36, VAR30, VAR4, VAR40, read, write, VAR24, din,
VAR15, VAR9, dout, VAR14, VAR43, VAR25, VAR13, VAR20, VAR1, VAR7, VAR29 );
input clk; input rst; input VAR8; input VAR36;
input [15:0] VAR30;
input VAR4;
input VAR40;
input read;
input write;
input VAR24;
input [7:0] din;
output VAR15;... | apache-2.0 |
GSejas/Aproximate-Arithmetic-Operators | src_lib/addlib/GDA_St_N16_M4_P4.v | 2,789 | module MODULE1(
input [15:0] VAR7,
input [15:0] VAR45,
output [16:0] VAR3
);
wire [4:0] VAR15, VAR86, VAR97, VAR24;
wire VAR95,VAR89,VAR87,VAR69,VAR22,VAR102,VAR57,VAR42;
wire VAR23,VAR27,VAR21,VAR83,VAR92;
wire VAR52, VAR48;
wire VAR66;
and VAR51(VAR69,VAR7[3],VAR45[3]);
and VAR75(VAR87,VAR7[2],VAR45[2]);
and VAR74(VA... | apache-2.0 |
sheiksadique/USB-Uart | top_loopback.v | 1,203 | module MODULE1(
input VAR7, input VAR6, output VAR5, input VAR10, output VAR3, input VAR2, output [3:0] VAR13
);
wire VAR9;
VAR15 VAR16(
.VAR1(VAR9), .VAR5(VAR5), .VAR10(VAR10), .VAR3(VAR3), .VAR2(VAR2), .VAR13(VAR13)
);
VAR11 VAR12(
.VAR8(VAR7),
.VAR4(VAR6),
.VAR14(VAR9)
);
endmodule | gpl-2.0 |
orbancedric/DeepGate | other/Mojo Projects/Mojo-SDRAM/ipcore_dir/sdram_clk_gen.v | 5,555 | module MODULE1
( input VAR32,
output VAR25
);
VAR21 VAR4
(.VAR10 (VAR9),
.VAR46 (VAR32));
wire VAR35;
wire VAR48;
wire [7:0] VAR31;
wire VAR33;
wire VAR6;
wire VAR38;
VAR8
.VAR41 (1),
.VAR22 (2),
.VAR16 ("VAR3"),
.VAR28 (20.0),
.VAR11 ("VAR42"),
.VAR47 ("VAR42"),
.VAR24 ("VAR1"),
.VAR12 (0),
.VAR17 ("VAR3"))
VAR40
(.VA... | gpl-3.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/acl_arb2.v | 11,300 | module MODULE3
parameter string VAR15 = "VAR20", parameter integer VAR27 = 1, parameter integer VAR34 = 0,
parameter integer VAR22 = 32, parameter integer VAR6 = 4, parameter integer VAR14 = 32, parameter integer VAR16 = VAR22 / 8, parameter integer VAR33 = 1 )
(
input logic VAR8,
input logic VAR18,
VAR29 VAR5,
VAR29 V... | mit |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/read_data_fifo.v | 13,587 | module MODULE1(
rst,
VAR386,
VAR315,
din,
VAR224,
VAR167,
dout,
VAR158,
VAR267,
VAR193,
VAR181,
VAR25
);
input rst;
input VAR386;
input VAR315;
input [31 : 0] din;
input VAR224;
input VAR167;
output [255 : 0] dout;
output VAR158;
output VAR267;
output [9 : 0] VAR193;
output [12 : 0] VAR181;
output VAR25;
VAR311 #(
.VAR... | gpl-2.0 |
cliffordwolf/picorv32 | scripts/icestorm/example.v | 1,880 | module MODULE1 (
input clk,
output reg VAR17, VAR23, VAR15, VAR18, VAR3, VAR14, VAR21, VAR8
);
reg [7:0] VAR1 = 0;
wire VAR10 = &VAR1;
always @(posedge clk) begin
if (!VAR10)
VAR1 <= VAR1 + 1;
end
wire VAR2;
wire [31:0] VAR5;
wire [31:0] VAR7;
wire [3:0] VAR24;
reg VAR6;
reg [31:0] VAR11;
VAR20 #(
.VAR13(0),
.VAR22(1),... | isc |
ultraembedded/altor32 | rtl/soc/cpu_if.v | 7,793 | module MODULE1
(
input VAR33,
input VAR57,
output [31:0] VAR76,
input [31:0] VAR4,
output [3:0] VAR50,
output VAR95,
output VAR100,
output [2:0] VAR41,
input VAR65,
input VAR118,
output [31:0] VAR27,
output [31:0] VAR96,
input [31:0] VAR74,
output [3:0] VAR59,
output VAR112,
output VAR91,
output VAR21,
output [2:0] VAR... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N8_R1_P3_syn.v | 2,368 | module MODULE1 ( VAR63, VAR10, VAR27 );
input [7:0] VAR63;
input [7:0] VAR10;
output [8:0] VAR27;
wire VAR14, VAR82, VAR9, VAR5, VAR38, VAR7, VAR81, VAR44, VAR30, VAR88, VAR36, VAR69, VAR72, VAR49,
VAR22, VAR39, VAR89, VAR75, VAR86, VAR34, VAR46, VAR80, VAR64, VAR77;
VAR70 VAR71 ( .VAR1(VAR63[0]), .VAR56(VAR10[0]), .VA... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/spare/build1/prog_counter.v | 1,269 | module MODULE1 (VAR2,VAR1,rst,clk);
output [0:31] VAR2;
input [0:31] VAR1;
input clk;
input rst;
reg [0:31] VAR2;
always @(posedge clk)
begin
if(rst)
begin
VAR2<=32'd0;
end
else
begin
VAR2<=VAR1+32'd4;
end
end
endmodule | mit |
monotone-RK/FACE | MCSoC-15/16-way/ise/ipcore_dir/dram/user_design/rtl/ui/mig_7series_v1_9_ui_rd_data.v | 19,522 | module MODULE1 #
(
parameter VAR57 = 100,
parameter VAR98 = 256,
parameter VAR33 = 5,
parameter VAR17 = "VAR77",
parameter VAR51 = 2 ,
parameter VAR27 = "VAR31"
)
(
VAR75, VAR89, VAR83, VAR90,
VAR69, VAR80, VAR19, VAR52,
rst, clk, VAR20, VAR87, VAR45, VAR74,
VAR60, VAR56, VAR23
);
input rst;
input clk;
output wire VAR7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbn/sky130_fd_sc_hs__dlrbn_2.v | 2,338 | module MODULE2 (
VAR2,
VAR7 ,
VAR4 ,
VAR3 ,
VAR6 ,
VAR5 ,
VAR8
);
input VAR2;
input VAR7 ;
input VAR4 ;
output VAR3 ;
output VAR6 ;
input VAR5 ;
input VAR8 ;
VAR9 VAR1 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR2,
VAR7 ,
VAR4 ,
VAR3 ,
VAR... | apache-2.0 |
secworks/fltfpga | cpu/src/rtl/fltcpu_mem.v | 4,485 | module MODULE1(
input wire clk,
input wire VAR11,
input wire VAR8,
input wire [3 : 0] VAR10,
input wire [31 : 0] VAR3,
input wire [31 : 0] VAR9,
output wire [31 : 0] VAR12
);
localparam VAR6 = 12:
localparam VAR4 = 2**VAR6;
reg [7 : 0] VAR2 [0 : (VAR4 - 1)];
reg [7 : 0] VAR5 [0 : (VAR4 - 1)];
reg [7 : 0] VAR13 [0 : (VA... | bsd-2-clause |
takeshineshiro/fpga_linear_128 | lf.v | 10,706 | module MODULE1 (
clk,
VAR8,
VAR5,
VAR3,
VAR9,
VAR6,
VAR4,
VAR10,
VAR11,
VAR1);
input clk;
input VAR8;
input [14:0] VAR5;
input VAR3;
input VAR9;
input [1:0] VAR6;
output [30:0] VAR4;
output VAR10;
output VAR11;
output [1:0] VAR1;
VAR2 VAR7(
.clk(clk),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6),
.VA... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_axis_fifo.v | 5,876 | module MODULE1
parameter VAR39 = 33,
parameter VAR13 = 1 ,
parameter VAR28 = 1 ,
parameter VAR30 = 14,
parameter VAR40 = 16,
parameter VAR20 = 4
) (
input VAR37 ,
input VAR32 ,
input [VAR39-1:0] VAR27 ,
input [VAR39-1:0] VAR25,
input VAR35 ,
input VAR33 ,
input VAR5 ,
input VAR23 ,
output VAR17 ,
output VAR11 ,
output ... | gpl-3.0 |
moizumi99/brainf__k_CPU | hdl/dmem16_bb.v | 5,590 | module MODULE1 (
address,
VAR3,
VAR2,
VAR1,
VAR4);
input [11:0] address;
input VAR3;
input [15:0] VAR2;
input VAR1;
output [15:0] VAR4;
tri1 VAR3;
endmodule | unlicense |
HarmonInstruments/verilog | math/complex_mult.v | 1,320 | module MODULE1
(
input VAR3,
input VAR9,
input signed [24:0] VAR11, VAR8,
input signed [17:0] VAR17, VAR2,
output signed [47:0] VAR4, VAR15
);
VAR13 VAR1
(
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(1'b1),
.VAR6(VAR11),
.VAR12(VAR17),
.VAR10(VAR8),
.VAR5(VAR2),
.VAR16(VAR4)
);
VAR13 VAR14
(
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(1'b0),
... | gpl-3.0 |
sh-chris110/chris | FPGA/uCos/system/synthesis/submodules/system_mm_interconnect_0_avalon_st_adapter_003.v | 6,164 | module MODULE1 #(
parameter VAR4 = 18,
parameter VAR19 = 0,
parameter VAR11 = 18,
parameter VAR23 = 0,
parameter VAR7 = 0,
parameter VAR8 = 0,
parameter VAR12 = 1,
parameter VAR13 = 1,
parameter VAR21 = 0,
parameter VAR1 = 18,
parameter VAR18 = 0,
parameter VAR24 = 1,
parameter VAR3 = 0,
parameter VAR15 = 1,
parameter ... | gpl-2.0 |
neale/CS-program | 474-VLSI/Lab_ADC/ADC.v | 6,368 | module MODULE1 (
address,
VAR23,
VAR2);
input [10:0] address;
input VAR23;
output [11:0] VAR2;
tri1 VAR23;
wire [11:0] VAR47;
wire [11:0] VAR2 = VAR47[11:0];
VAR45 VAR11 (
.VAR8 (address),
.VAR15 (VAR23),
.VAR44 (VAR47),
.VAR30 (1'b0),
.VAR13 (1'b0),
.VAR5 (1'b1),
.VAR10 (1'b0),
.VAR38 (1'b0),
.VAR20 (1'b1),
.VAR28 (1'... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtn/sky130_fd_sc_lp__dfrtn.pp.blackbox.v | 1,401 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR8 ,
VAR3,
VAR6 ,
VAR4 ,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR7 ;
input VAR8 ;
input VAR3;
input VAR6 ;
input VAR4 ;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbp/sky130_fd_sc_hd__dlxbp.symbol.v | 1,364 | module MODULE1 (
input VAR1 ,
output VAR5 ,
output VAR6 ,
input VAR8
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fetch/wrap_ref_chroma.v | 2,232 | module MODULE1 (
clk ,
VAR3 ,
VAR13 ,
VAR5 ,
VAR4 ,
VAR12 ,
VAR15 ,
VAR7
);
input [1-1:0] clk ; input [1-1:0] VAR3 ;
input [1-1:0] VAR13 ; input [6-1:0] VAR5 ; input [48*VAR18-1:0] VAR4 ;
input [1-1:0] VAR12 ; input [6-1:0] VAR15 ; output [48*VAR18-1:0] VAR7 ;
wire [6-1:0] VAR8;
assign VAR8 = (VAR13) ? VAR5 : VAR15;
VA... | gpl-3.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/imx_cbu.v | 4,700 | module MODULE1(
clk, rst,
VAR20, VAR14, VAR15, VAR19, VAR21, VAR8, VAR22, VAR4,
VAR25, VAR11, VAR13, VAR2,
VAR6, VAR9, VAR5, VAR1, VAR16,
VAR10, VAR17, VAR7, VAR24
);
parameter VAR12 = 32;
parameter VAR18 = 32;
input clk; input rst;
input [VAR18-1:0] VAR9; input [VAR12-1:0] VAR6; input VAR5; input VAR1; input [3:0] VAR... | gpl-2.0 |
freecores/eco32 | fpga/src/dsk/ataio.v | 3,175 | module MODULE1 (clk, reset,
VAR2, VAR9, VAR13, VAR8, VAR7, VAR12,
VAR1, VAR3, VAR4, VAR10,
VAR15, VAR11, VAR14);
input clk;
input reset;
input VAR2;
input VAR9;
input [3:0] VAR13;
input [15:0] VAR8;
output reg [15:0] VAR7;
output VAR12;
inout [15:0] VAR1;
output reg [2:0] VAR3;
output reg VAR4;
output reg VAR10;
output... | bsd-2-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/butterfly_4.v | 1,829 | module MODULE1(
clk,
rst,
VAR5,
VAR2,
VAR6,
VAR4,
o0,
o1,
o2,
o3
);
input clk;
input rst;
input signed [23:0] VAR5;
input signed [23:0] VAR2;
input signed [23:0] VAR6;
input signed [23:0] VAR4;
output reg signed [24:0] o0;
output reg signed [24:0] o1;
output reg signed [24:0] o2;
output reg signed [24:0] o3;
wire signe... | gpl-3.0 |
alexforencich/verilog-ethernet | lib/axis/rtl/axis_async_fifo.v | 27,116 | module MODULE1 #
(
parameter VAR10 = 4096,
parameter VAR18 = 8,
parameter VAR34 = (VAR18>8),
parameter VAR9 = ((VAR18+7)/8),
parameter VAR21 = 1,
parameter VAR33 = 0,
parameter VAR47 = 8,
parameter VAR41 = 0,
parameter VAR25 = 8,
parameter VAR5 = 1,
parameter VAR37 = 1,
parameter VAR16 = 1,
parameter VAR13 = 0,
paramet... | mit |
lvd2/zxevo | fpga/baseconf/trunk/z80/zclock.v | 7,450 | module MODULE1(
input wire VAR23,
input wire VAR1,
input wire VAR16,
input wire [15:0] VAR24,
input wire [ 1:0] VAR17,
input wire VAR8,
input wire VAR9,
input wire [ 2:0] VAR32,
input wire VAR26,
input wire VAR35,
input wire VAR30,
input wire VAR15,
input wire VAR10,
output reg VAR31,
output reg VAR38,
output reg VAR20... | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/ipcore_dir/user_fifo.v | 13,571 | module MODULE1(
VAR52,
VAR8,
VAR251,
VAR61,
VAR201,
VAR372,
VAR250,
VAR351,
VAR333
);
input VAR52;
input VAR8;
input VAR251;
input VAR61;
output VAR201;
input [63 : 0] VAR372;
output VAR250;
input VAR351;
output [63 : 0] VAR333;
VAR399 #(
.VAR289(0),
.VAR125(0),
.VAR365(0),
.VAR159(0),
.VAR224(0),
.VAR271(0),
.VAR2(0),... | mit |
Tsung-Wei/OpenTimer | benchmark/s349/s349.v | 13,828 | module MODULE1 (
VAR279,
VAR14,
VAR393,
VAR371,
VAR171,
VAR242,
VAR183,
VAR397,
VAR67,
VAR362,
VAR225,
VAR101,
VAR300,
VAR240,
VAR195,
VAR88,
VAR77,
VAR156,
VAR1,
VAR117,
VAR10,
VAR111);
input VAR279;
input VAR14;
input VAR393;
input VAR371;
input VAR171;
input VAR242;
input VAR183;
input VAR397;
input VAR67;
input VAR... | gpl-3.0 |
sittner/lcnc-mdsio | vhdl/source/can/can_btl.v | 13,968 | module MODULE1
(
clk,
rst,
VAR9,
VAR21,
VAR31,
VAR26,
VAR17,
VAR2,
VAR39,
VAR3,
VAR30,
VAR15,
VAR18,
VAR40,
VAR28,
VAR24,
VAR16,
VAR35,
VAR10,
VAR12,
VAR7,
VAR23,
VAR8,
VAR32,
VAR29
);
parameter VAR5 = 1;
input clk;
input rst;
input VAR9;
input VAR21;
input [5:0] VAR31;
input [1:0] VAR26;
input [3:0] VAR17;
input [2:0]... | gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v | 10,418 | module MODULE1 #
(
parameter VAR3 = "none",
parameter integer VAR24 = 1,
parameter integer VAR40 = 32,
parameter integer VAR2 = 32,
parameter integer VAR12 = 0,
parameter integer VAR11 = 1,
parameter integer VAR6 = 1,
parameter integer VAR31 = 1
)
(
input wire VAR36,
input wire VAR39,
input wire VAR43,
input wire [VAR2... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_4.behavioral.pp.v | 1,784 | module MODULE1( VAR7, VAR5, VAR3, VAR1, VAR6 );
input VAR5, VAR7;
inout VAR1, VAR6;
output VAR3;
reg VAR9;
VAR13 VAR12(.VAR7(VAR7),.VAR5(VAR5),.VAR3(VAR3),.VAR1(VAR1),.VAR6(VAR6),.VAR9(VAR9));
VAR13 VAR4(.VAR7(VAR7),.VAR5(VAR5),.VAR3(VAR3),.VAR1(VAR1),.VAR6(VAR6),.VAR9(VAR9));
not VAR8(VAR2,VAR5);
buf VAR11(VAR10,VAR5)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2.behavioral.v | 1,405 | module MODULE1 (
VAR8,
VAR1
);
output VAR8;
input VAR1;
supply1 VAR6;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR7 ;
wire VAR3;
buf VAR4 (VAR3, VAR1 );
buf VAR5 (VAR8 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb_1.v | 2,350 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR4 ,
VAR10 ,
VAR11 ,
VAR3,
VAR8,
VAR6 ,
VAR7
);
output VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR10 ;
input VAR11 ;
input VAR3;
input VAR8;
input VAR6 ;
input VAR7 ;
VAR5 VAR9 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3.behavioral.v | 1,387 | module MODULE1 (
VAR11,
VAR4,
VAR1,
VAR5
);
output VAR11;
input VAR4;
input VAR1;
input VAR5;
supply1 VAR10;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR2 ;
wire VAR3;
nand VAR6 (VAR3, VAR1, VAR4, VAR5 );
buf VAR9 (VAR11 , VAR3 );
endmodule | apache-2.0 |
plindstroem/oh | elink/hdl/erx_arbiter.v | 3,953 | module MODULE1 (
VAR15, VAR18, VAR24, VAR23, VAR1,
VAR26, VAR9, VAR10, VAR27, VAR11,
VAR25, VAR19, VAR4, VAR28, VAR16,
VAR20, VAR7, VAR21, timeout, VAR18,
VAR15, VAR13
);
parameter VAR17 = 32;
parameter VAR22 = 32;
parameter VAR2 = 104;
parameter VAR5 = 12'h800; parameter VAR12 = 6;
input VAR25;
input [VAR2-1:0] VAR19;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp.blackbox.v | 1,305 | module MODULE1 (
VAR7,
VAR3 ,
VAR1,
VAR4
);
output VAR7;
input VAR3 ;
input VAR1;
input VAR4 ;
supply1 VAR6;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_phy_10g_rx_ber_mon.v | 3,228 | module MODULE1 #
(
parameter VAR3 = 2,
parameter VAR1 = 125000/6.4
)
(
input wire clk,
input wire rst,
input wire [VAR3-1:0] VAR2,
output wire VAR4
); | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_otp_top.v | 2,628 | module MODULE1(
input clk,
input VAR3,
input VAR4,
output VAR17,
input [32-1:0] VAR15,
input VAR5,
input [32-1:0] VAR9,
output VAR2,
input VAR8,
output [32-1:0] VAR1,
input VAR6,
output VAR13,
input [32-1:0] VAR12,
input VAR11,
input [32-1:0] VAR16,
output VAR10,
input VAR7,
output [32-1:0] VAR14
);
assign VAR17 = 1'b0... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/arbiter/arbiter_dbus.v | 11,522 | module MODULE1
(
VAR1,
VAR70,
VAR23,
VAR67,
VAR6,
VAR72,
VAR13,
VAR34,
VAR109,
VAR107,
VAR65,
VAR5,
VAR94,
VAR58,
VAR42,
VAR68,
VAR60,
VAR71,
VAR54,
VAR8,
VAR44,
VAR9,
VAR25,
VAR36,
VAR50,
VAR101,
VAR106,
VAR39,
VAR74,
VAR61,
VAR88,
VAR92,
VAR41,
VAR102,
VAR89,
VAR53,
VAR77,
VAR52,
VAR55,
VAR19,
VAR83,
VAR62,
VAR33,
VA... | mit |
cpulabs/mist1032isa | src/core/execute/execute_sys_reg.v | 1,380 | module MODULE1(
input wire [4:0] VAR7,
input wire [31:0] VAR5,
input wire [31:0] VAR6,
input wire [31:0] VAR10,
output wire [31:0] VAR8,
output wire VAR2,
output wire VAR1,
output wire VAR12,
output wire [31:0] VAR4
);
reg [31:0] VAR13;
always @* begin
case(VAR7)
default :
begin
VAR13 = VAR6;
end
endcase
end
assign VAR... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.behavioral.pp.v | 1,561 | module MODULE1( VAR8, VAR3, VAR2, VAR4, VAR9, VAR6 );
input VAR2, VAR3, VAR4;
inout VAR9, VAR6;
output VAR8;
VAR1 VAR7(.VAR8(VAR8),.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR9(VAR9),.VAR6(VAR6));
VAR1 VAR5(.VAR8(VAR8),.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR9(VAR9),.VAR6(VAR6)); | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/altera_mult_add_q1u2.v | 15,695 | module MODULE1
(
VAR90,
VAR219,
VAR60,
VAR277,
VAR118) ;
input VAR90;
input VAR219;
input [15:0] VAR60;
input [15:0] VAR277;
output [31:0] VAR118;
tri0 VAR90;
tri1 VAR219;
tri0 [15:0] VAR60;
tri0 [15:0] VAR277;
wire [31:0] VAR244;
VAR134 VAR238
(
.VAR90(VAR90),
.VAR263(),
.VAR219(VAR219),
.VAR60(VAR60),
.VAR277(VAR277)... | gpl-2.0 |
GLADICOS/UART | rtl/uart_tx.v | 5,764 | module MODULE1#(
parameter integer VAR18 = 12
)
(
input VAR16,
input VAR12,
input [7:0] VAR2,
input [11:0] VAR1,
input VAR13,
output VAR20,
output reg VAR10
);
localparam [11:0] VAR14 = 12'b000000000000,
VAR3 = 12'b000000000001,
VAR5 = 12'b000000000010,
VAR15 = 12'b000000000100,
VAR21 = 12'b000000001000,
VAR7 = 12'b000... | gpl-3.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/soc_system_bb.v | 5,619 | module MODULE1 (
VAR13,
VAR55,
VAR30,
VAR58,
VAR67,
VAR11,
VAR45,
VAR19,
VAR5,
VAR47,
VAR20,
VAR9,
VAR73,
VAR71,
VAR14,
VAR29,
VAR32,
VAR44,
VAR66,
VAR69,
VAR76,
VAR78,
VAR51,
VAR8,
VAR38,
VAR3,
VAR25,
VAR56,
VAR70,
VAR49,
VAR40,
VAR36,
VAR22,
VAR50,
VAR52,
VAR60,
VAR2,
VAR54,
VAR26,
VAR17,
VAR37,
VAR74,
VAR77,
VAR21,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41o/sky130_fd_sc_ls__a41o.behavioral.v | 1,558 | module MODULE1 (
VAR3 ,
VAR11,
VAR8,
VAR10,
VAR6,
VAR15
);
output VAR3 ;
input VAR11;
input VAR8;
input VAR10;
input VAR6;
input VAR15;
supply1 VAR5;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR12 ;
wire VAR4 ;
wire VAR14;
and VAR2 (VAR4 , VAR11, VAR8, VAR10, VAR6 );
or VAR9 (VAR14, VAR4, VAR15 );
buf VAR13 (VAR3 , VAR14 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp_0.v | 2,025 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR5,
VAR8,
VAR7 ,
VAR1
);
output VAR2 ;
input VAR6 ;
input VAR5;
input VAR8;
input VAR7 ;
input VAR1 ;
VAR4 VAR3 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR5;
supply0 VAR8;... | apache-2.0 |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/inferred_rom.v | 14,261 | module MODULE1(VAR5, VAR3, VAR4, VAR8, VAR9, VAR1, VAR7, VAR2);
input VAR5, VAR3;
input VAR4, VAR8;
input [8:0] VAR9, VAR1;
output reg [31:0] VAR7, VAR2;
reg [31:0] VAR6 [511:0];
always @(negedge VAR5) begin
if (VAR4) begin
VAR7 <= VAR6[VAR9];
end
end
always @(negedge VAR3) begin
if (VAR8) begin
VAR2 <= VAR6[VAR1];
end... | gpl-3.0 |
alexforencich/verilog-axis | rtl/axis_srl_fifo.v | 6,015 | module MODULE1 #
(
parameter VAR37 = 8,
parameter VAR39 = (VAR37>8),
parameter VAR50 = ((VAR37+7)/8),
parameter VAR51 = 1,
parameter VAR1 = 0,
parameter VAR18 = 8,
parameter VAR25 = 0,
parameter VAR26 = 8,
parameter VAR33 = 1,
parameter VAR32 = 1,
parameter VAR34 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR... | mit |
CospanDesign/nysa-verilog | verilog/generic/dc_fifo.v | 8,337 | module MODULE1 #(
parameter VAR13 = 32,
parameter VAR21 = 8
)(
input VAR19,
input VAR29,
input rst,
input VAR28,
input [VAR13 - 1:0] VAR15,
input write,
output VAR3,
output [VAR13 - 1: 0] VAR9,
input read,
output VAR30,
output ready
);
reg VAR18;
reg VAR8;
reg VAR26;
reg VAR25;
always @ (posedge VAR19 or posedge rst)
i... | mit |
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