repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_rxcounters.v | 8,423 | module MODULE1 (VAR18, VAR23, VAR3, VAR15, VAR35, VAR29, VAR1, VAR11,
VAR20, VAR22, VAR36, VAR26, VAR19, VAR4, VAR17, VAR14,
VAR32, VAR37, VAR21,VAR13,VAR10,VAR12, VAR2,
VAR28, VAR16, VAR31, VAR24, VAR34
);
parameter VAR27 = 1;
input VAR18;
input VAR23;
input VAR3;
input VAR35;
input [1:0] VAR29;
input VAR20;
input VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbp/sky130_fd_sc_lp__dfbbp.symbol.v | 1,467 | module MODULE1 (
input VAR8 ,
output VAR4 ,
output VAR5 ,
input VAR9,
input VAR7 ,
input VAR6
);
supply1 VAR1;
supply0 VAR10;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/edfxbp/sky130_fd_sc_lp__edfxbp.pp.symbol.v | 1,447 | module MODULE1 (
input VAR3 ,
output VAR9 ,
output VAR5 ,
input VAR8 ,
input VAR1 ,
input VAR7 ,
input VAR2,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp.behavioral.pp.v | 2,334 | module MODULE1 (
VAR16 ,
VAR21,
VAR13 ,
VAR18 ,
VAR19 ,
VAR4 ,
VAR2 ,
VAR8
);
output VAR16 ;
input VAR21;
input VAR13 ;
input VAR18 ;
input VAR19 ;
input VAR4 ;
input VAR2 ;
input VAR8 ;
wire VAR15 ;
reg VAR12 ;
wire VAR10 ;
wire VAR14 ;
wire VAR17 ;
wire VAR20;
wire VAR11 ;
wire VAR7 ;
wire VAR5 ;
wire VAR1 ;
not VAR9... | apache-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_one_db_load/solution1/impl/verilog/contact_discoverybkb.v | 1,801 | module MODULE1 (VAR8, VAR6, VAR4, VAR3, VAR10, VAR12, VAR9, VAR11, clk);
parameter VAR7 = 8;
parameter VAR5 = 13;
parameter VAR1 = 8192;
input[VAR5-1:0] VAR8;
input VAR6;
input[VAR7-1:0] VAR4;
input VAR3;
output reg[VAR7-1:0] VAR10;
input[VAR5-1:0] VAR12;
input VAR9;
output reg[VAR7-1:0] VAR11;
input clk;
reg [VAR7-1:0... | gpl-3.0 |
tvelliott/dsp_ice | firmware/fpga/src/fpga_top.v | 30,044 | module MODULE1 (
input clk,
output VAR38,
output VAR220,
output VAR10,
output VAR62,
output VAR148,
output VAR208,
output VAR156,
input VAR75,
output VAR31,
input VAR224,
input VAR49,
output VAR40,
input VAR203,
output VAR152,
output VAR216,
input VAR26,
input VAR200,
input VAR53,
input VAR240,
input VAR32,
input VAR83... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_p_src_rows_V_channel.v | 3,019 | module MODULE1 (
clk,
VAR12,
VAR27,
VAR24,
VAR13);
parameter VAR23 = 32'd12;
parameter VAR6 = 32'd2;
parameter VAR5 = 32'd3;
input clk;
input [VAR23-1:0] VAR12;
input VAR27;
input [VAR6-1:0] VAR24;
output [VAR23-1:0] VAR13;
reg[VAR23-1:0] VAR18 [0:VAR5-1];
integer VAR21;
always @ (posedge clk)
begin
if (VAR27)
begin
fo... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_wb.v | 10,015 | module MODULE1( VAR11, VAR14, rst, VAR6, VAR17, VAR7,
VAR3, VAR31, VAR27, VAR20,
VAR8, VAR22, VAR34, VAR12, VAR19, VAR2,
VAR29, VAR35, VAR13, VAR28);
input VAR11, VAR14;
input rst;
input [VAR9:0] VAR6;
input [31:0] VAR17;
output [31:0] VAR7;
output VAR3;
input VAR31;
input VAR27;
input VAR20;
output [VAR9:0] VAR8;
outp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3.symbol.v | 1,322 | module MODULE1 (
input VAR4,
output VAR6
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv.behavioral.pp.v | 1,766 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1,
VAR6,
VAR10 ,
VAR2
);
output VAR4 ;
input VAR3 ;
input VAR1;
input VAR6;
input VAR10 ;
input VAR2 ;
wire VAR7 ;
wire VAR9;
not VAR5 (VAR7 , VAR3 );
VAR11 VAR8 (VAR9, VAR7, VAR1, VAR6);
buf VAR12 (VAR4 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb.pp.blackbox.v | 1,357 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR9 ,
VAR6 ,
VAR2 ,
VAR7,
VAR1,
VAR8 ,
VAR4
);
output VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR6 ;
input VAR2 ;
input VAR7;
input VAR1;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn.pp.blackbox.v | 1,478 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR8 ,
VAR3 ,
VAR5 ,
VAR9,
VAR4 ,
VAR7 ,
VAR2 ,
VAR10
);
output VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR3 ;
input VAR5 ;
input VAR9;
input VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR10 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_3.behavioral.pp.v | 1,246 | module MODULE1( VAR2, VAR5, VAR6, VAR4, VAR1 );
input VAR2, VAR5;
inout VAR4, VAR1;
output VAR6;
VAR7 VAR3(.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1));
VAR7 VAR8(.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b_1.v | 2,189 | module MODULE2 (
VAR6 ,
VAR3 ,
VAR7 ,
VAR8,
VAR4,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR8;
input VAR4;
input VAR1 ;
input VAR2 ;
VAR9 VAR5 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6 ,
VAR3 ,
VAR7
);
output VAR6... | apache-2.0 |
ZiCog/xoro | rtl/uartTx.v | 4,133 | module MODULE2 (
input VAR9,
output VAR22,
input clk,
input VAR19);
reg VAR16;
assign VAR22 = (VAR9 && (! VAR16));
always @ (posedge clk or negedge VAR19) begin
if (!VAR19) begin
VAR16 <= 1'b0;
end else begin
VAR16 <= VAR9;
end
end
endmodule
module MODULE1 (
input wire clk,
input wire VAR19,
input wire VAR12,
output wi... | mit |
cfangmeier/VFPIX-telescope-Code | utils/apc128_pattern_generator/step_curve_short.v | 4,253 | module MODULE1
(
input clk,
input [15:0]VAR18,
output reg VAR26,
output VAR9,
output VAR13,
output VAR22,
output reg VAR16,
output VAR20,
output reg VAR12,
output reg VAR17,
output reg VAR15,
output reg VAR11,
output VAR25,
output VAR4,
output reg VAR2,
output reg VAR23,
output VAR21,
output [15:0]VAR3,
output [15:0]VA... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/source/endpoint_blk_plus_v1_14.v | 19,614 | module MODULE1 # (
parameter VAR100 = "VAR169",
parameter VAR32 = 0,
parameter VAR109 = 1,
parameter VAR168 = 1,
parameter VAR155 = 0,
parameter VAR121 = 64,
parameter VAR204 = 8,
parameter VAR149 = 4,
parameter VAR129 = 7,
parameter VAR50 = 8,
parameter VAR179 = 12,
parameter VAR95 = 32,
parameter VAR193 = 10,
paramet... | lgpl-3.0 |
CospanDesign/nysa-verilog | verilog/generic/graycounter.v | 1,162 | module MODULE1
(output reg [VAR1-1:0] VAR2,
input wire en, input wire rst,
input wire clk);
reg [VAR1-1:0] VAR4;
always @ (posedge clk)
if (rst) begin
VAR4 <= {VAR1{1'VAR3 0}} + 1; VAR2 <= {VAR1{1'VAR3 0}}; end
else if (en) begin
VAR4 <= VAR4 + 1;
VAR2 <= {VAR4[VAR1-1],
VAR4[VAR1-2:0] ^ VAR4[VAR1-1:1]};
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2.behavioral.v | 1,604 | module MODULE1 (
VAR11 ,
VAR10,
VAR3,
VAR6
);
output VAR11 ;
input VAR10;
input VAR3;
input VAR6 ;
supply1 VAR7;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR1 ;
wire VAR5;
VAR9 VAR2 (VAR5, VAR10, VAR3, VAR6 );
buf VAR12 (VAR11 , VAR5);
endmodule | apache-2.0 |
spike556/HuffmanCode | rtl model/sortnet/SortX8.v | 2,922 | module MODULE1 # (
parameter VAR27 = 18,
parameter VAR18 = 8
)(
input [VAR27-1:0] VAR9,
input [VAR27-1:0] VAR19,
input [VAR27-1:0] VAR7,
input [VAR27-1:0] VAR24,
input [VAR27-1:0] VAR23,
input [VAR27-1:0] VAR37,
input [VAR27-1:0] VAR30,
input [VAR27-1:0] VAR2,
output wire [VAR27-1:0] VAR38,
output wire [VAR27-1:0] VAR3... | gpl-3.0 |
rongcuid/lots-of-subleq-cpus | Subleq Pipelined/src/BRAM.v | 1,083 | module MODULE1(
clk, VAR8, en, addr, VAR3, VAR6
);
parameter VAR2 = 8, VAR5 = 1024, VAR1 = 10;
input wire clk;
input wire VAR8;
input wire en;
input wire [VAR2-1:0] VAR3;
output reg [VAR2-1:0] VAR6;
reg [VAR2-1:0] VAR7 [0:VAR5-1];
always @ (posedge clk) begin
if (en) begin
if (VAR8) begin
VAR7[addr] <= VAR3;
VAR6 <= VA... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_8c_v1_00_a/hdl/verilog/cf_adc_if.v | 9,015 | module MODULE1 (
VAR67,
VAR38,
VAR21,
VAR70,
VAR87,
VAR35,
VAR25,
VAR15,
VAR56,
VAR8,
VAR7,
VAR16,
VAR60,
VAR50,
VAR3,
VAR79);
input VAR67;
input VAR38;
input [ 7:0] VAR21;
input [ 7:0] VAR70;
input VAR87;
input VAR35;
output VAR25;
output VAR15;
output [63:0] VAR56;
output VAR8;
output [ 7:0] VAR7;
output [ 7:0] VAR16... | mit |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/phyIniCommand0.v | 1,133 | module MODULE1
(
input [(VAR4-1):0] VAR3,
input [(VAR1-1):0] addr,
input VAR6, clk,
output [(VAR4-1):0] VAR2
);
reg [VAR4-1:0] VAR7[2**VAR1-1:0];
reg [VAR1-1:0] VAR5;
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o.functional.pp.v | 2,231 | module MODULE1 (
VAR10 ,
VAR11,
VAR2,
VAR4 ,
VAR6 ,
VAR3,
VAR9,
VAR8 ,
VAR5
);
output VAR10 ;
input VAR11;
input VAR2;
input VAR4 ;
input VAR6 ;
input VAR3;
input VAR9;
input VAR8 ;
input VAR5 ;
wire VAR13 ;
wire VAR16 ;
wire VAR15 ;
wire VAR12;
and VAR17 (VAR13 , VAR4, VAR6 );
nor VAR18 (VAR16 , VAR11, VAR2 );
or VAR1... | apache-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/lib/xs6_addsub_n.v | 5,193 | module MODULE1 #(
parameter VAR19=32
)(
input [VAR19-1:0] VAR54,
input [VAR19-1:0] VAR14,
input VAR51,
input VAR33,
output [VAR19-1:0] VAR46,
output VAR4
);
wire [7:0] VAR10;
wire [47:0] VAR49, VAR36;
wire [47:0] out;
assign VAR10 = {VAR33, 1'd0, VAR51, 1'd0, 2'd3, 2'd3 };
assign VAR49 = {{48-VAR19{1'd0}}, VAR54};
assi... | gpl-2.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab04/lab04/Code/CPU/Regs.v | 1,167 | module MODULE1(input clk,
input rst,
input [4:0] VAR2,
input [4:0] VAR5,
input [4:0] VAR6,
input [31:0]VAR3,
input VAR4,
output [31:0] VAR8,
output [31:0] VAR7
);
reg [31:0] register [1:31]; integer VAR1;
assign VAR8 = (VAR2 == 0)? 0 : register[VAR2]; assign VAR7 = (VAR5 == 0)? 0 : register[VAR5];
always @(posedge clk ... | gpl-3.0 |
migajv/mips_pipeline | verilog/alu.v | 2,037 | module MODULE1(
input [5:0] VAR15,
input [5:0] VAR25,
input [31:0] VAR23, VAR16,
output reg [31:0] out,
output VAR7);
wire VAR9;
wire [1:0] VAR6;
wire VAR20;
wire VAR21;
wire VAR8;
wire [1:0] VAR5;
wire VAR11;
wire VAR10;
VAR24 VAR14(.VAR19(VAR6),
.VAR9 (VAR9),
.VAR20 (VAR20),
.VAR8 (VAR8),
.VAR5 (VAR5[1:0]),
.VAR21 (V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3.blackbox.v | 1,260 | module MODULE1 (
VAR7,
VAR1,
VAR4,
VAR6
);
output VAR7;
input VAR1;
input VAR4;
input VAR6;
supply1 VAR8;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.functional.pp.v | 2,018 | module MODULE1 (
VAR18,
VAR1 ,
VAR9,
VAR12 ,
VAR14,
VAR11,
VAR15 ,
VAR16
);
output VAR18;
input VAR1 ;
input VAR9;
input VAR12 ;
input VAR14;
input VAR11;
input VAR15 ;
input VAR16 ;
wire VAR7 ;
wire VAR2 ;
wire VAR6 ;
wire VAR8;
not VAR3 (VAR2 , VAR7 );
not VAR13 (VAR6 , VAR12 );
nor VAR10 (VAR8, VAR9, VAR1 );
VAR5 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp.symbol.v | 1,346 | module MODULE1 (
input VAR8 ,
input VAR5 ,
input VAR6,
output VAR1
);
supply1 VAR3;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
jameshegarty/rigel | platform/camera1x/vsrc/axi_master_read_stub.v | 1,411 | module MODULE1(
output VAR9,
output VAR8,
input VAR1,
output [31:0] VAR3,
output [1:0] VAR11,
output [3:0] VAR5,
output [1:0] VAR4,
input VAR6,
output VAR2,
input VAR10,
input [63:0] VAR12,
input [1:0] VAR7
);
assign VAR9 = 1'b0;
assign VAR8 = 1'b0;
assign VAR3 = 32'b0;
assign VAR11 = 2'b0;
assign VAR5 = 4'b0;
assign V... | mit |
zhangly/azpr_cpu | rtl/io/uart/rtl/uart_rx.v | 2,668 | module MODULE1 (
input wire clk, input wire reset,
output wire VAR4, output reg VAR8, output reg [VAR5] VAR3,
input wire VAR21 );
reg [VAR19] state; reg [VAR10] VAR1; reg [VAR23] VAR18;
assign VAR4 = (state != VAR17) ? VAR9 : VAR20;
always @(posedge clk or VAR15 reset) begin
if (reset == VAR12) begin
VAR8 <= VAR20;
VAR... | mit |
rkrajnc/minimig-mist | lib/io/generic_input.v | 1,843 | module MODULE1 #(
parameter VAR5 = 1, parameter VAR1 = 10, parameter VAR2 = 1'b0, parameter VAR7 = 0 )(
output wire [ VAR5-1:0] VAR3
);
reg [ VAR5-1:0] state = {VAR5{VAR2}};
assign VAR3 = state;
task VAR10;
input [ VAR5-1:0] VAR4;
begin
if (VAR7) );
state <= VAR2 ? VAR4 & state : VAR4 | state;
end
endtask
task VAR8;
in... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapmet1/sky130_fd_sc_ms__tapmet1.blackbox.v | 1,223 | module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_clk_edgelogic.v | 2,398 | module MODULE1(
VAR15, VAR14,
clk, VAR5, VAR11, VAR9,
VAR12, VAR7
);
input clk;
input VAR7;
input VAR5;
input VAR11;
input VAR9;
input VAR12;
output VAR15;
output VAR14;
wire VAR17 = VAR7 ? ~clk : clk;
VAR10 #(1) VAR1(
.din(VAR12),
.VAR4(VAR2),
.clk(VAR17),
.VAR6(VAR5), .VAR3(VAR15), .VAR13(VAR11));
wire VAR8 = VAR9 & ... | gpl-2.0 |
amrmorsey/Digital-Design-Project | sbox1.v | 3,551 | module MODULE1(
VAR2,
VAR3
);
input [6:1] VAR2;
output reg [4:1] VAR3;
wire [6:1] VAR1;
assign VAR1 = {VAR2[6], VAR2[1], VAR2[5 : 2]};
always @(VAR1)
begin
case (VAR1)
6'b000000: VAR3 <= 4'd14;
6'b000001: VAR3 <= 4'd4;
6'b000010: VAR3 <= 4'd13;
6'b000011: VAR3 <= 4'd1;
6'b000100: VAR3 <= 4'd2;
6'b000101: VAR3 <= 4'd15;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2_lp2.v | 2,102 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR6 ,
VAR1,
VAR9,
VAR5 ,
VAR7
);
output VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR1;
input VAR9;
input VAR5 ;
input VAR7 ;
VAR3 VAR2 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR4,
VAR8,
VAR6
);
output VAR4;
... | apache-2.0 |
Kumikomi/openreroc_accelsensor | hardware/src/MPU_accel_controller.v | 12,919 | module MODULE1(
input clk,
input reset,
output reg [15:0] VAR3, output reg [15:0] VAR19, output reg [15:0] VAR1,
output VAR52, output VAR38, output VAR47, input VAR20, output reg VAR17
);
parameter VAR25 = 0,
VAR44 = 1,
VAR11 = 2,
VAR13 = 3,
VAR31 = 4,
VAR45 = 5,
VAR33 = 6,
VAR40 = 7,
VAR12 = 8,
VAR8 = 9,
VAR21 = 10,
V... | bsd-3-clause |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_backend_frame_fifo.v | 18,582 | module MODULE1 (
VAR44, VAR37,
VAR43, VAR6,
VAR61, VAR50,
VAR48, VAR58, VAR30, VAR29, VAR38, VAR32,
VAR59,
VAR16,
VAR35, VAR42,
VAR34, VAR49 );
output [15:0] VAR44; output VAR37;
output[VAR23:0] VAR43; output VAR6;
input VAR61; input VAR50;
input [VAR25:0] VAR48; input [VAR25:0] VAR58; input [VAR26:0] VAR30; input VAR2... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn.pp.symbol.v | 1,341 | module MODULE1 (
input VAR6 ,
output VAR4 ,
input VAR1,
input VAR2 ,
input VAR3 ,
input VAR7 ,
input VAR5
);
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/DRSCFIFO_288x16_withCount.v | 2,701 | module MODULE1
(
input VAR5 ,
input VAR3 ,
input [287:0] VAR8 ,
input VAR4 ,
output VAR7 ,
output [287:0] VAR13 ,
input VAR15 ,
output VAR16 ,
output [3:0] VAR1
);
VAR9
VAR14
(
.clk (VAR5 ),
.VAR11 (VAR3 ),
.din (VAR8 ),
.VAR6 (VAR4 ),
.VAR12 (VAR7 ),
.dout (VAR13 ),
.VAR17 (VAR15 ),
.VAR10 (VAR16 ),
.VAR2 (VAR1 )
);
e... | gpl-3.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_auto_pc_0/synth/dma_loopback_auto_pc_0.v | 13,324 | module MODULE1 (
VAR20,
VAR72,
VAR23,
VAR73,
VAR87,
VAR69,
VAR100,
VAR3,
VAR107,
VAR48,
VAR95,
VAR86,
VAR105,
VAR27,
VAR114,
VAR49,
VAR47,
VAR43,
VAR18,
VAR26,
VAR113,
VAR4,
VAR68,
VAR56,
VAR108,
VAR91,
VAR67,
VAR59,
VAR2,
VAR101,
VAR14,
VAR71,
VAR7,
VAR21,
VAR83,
VAR33,
VAR53,
VAR31,
VAR98,
VAR30,
VAR62,
VAR51,
VAR96,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tap/sky130_fd_sc_lp__tap.behavioral.v | 1,152 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b.behavioral.pp.v | 1,924 | module MODULE1 (
VAR5 ,
VAR12 ,
VAR9 ,
VAR1,
VAR8,
VAR4 ,
VAR15
);
output VAR5 ;
input VAR12 ;
input VAR9 ;
input VAR1;
input VAR8;
input VAR4 ;
input VAR15 ;
wire VAR6 ;
wire VAR10 ;
wire VAR14;
not VAR7 (VAR6 , VAR9 );
or VAR2 (VAR10 , VAR6, VAR12 );
VAR13 VAR11 (VAR14, VAR10, VAR1, VAR8);
buf VAR3 (VAR5 , VAR14 );
e... | apache-2.0 |
julioamerico/prj_crc_ip | src/rtl/crc_ip.v | 2,615 | module MODULE1
(
output [31:0] VAR23,
output VAR14,
output VAR2,
input [31:0] VAR33,
input [31:0] VAR19,
input [ 2:0] VAR26,
input [ 1:0] VAR31,
input VAR1,
input VAR18,
input VAR15,
input VAR32,
input VAR20
);
wire [31:0] VAR34;
wire [31:0] VAR3;
wire [31:0] VAR8;
wire [ 7:0] VAR21;
wire VAR17;
wire VAR9;
wire [31:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi.functional.v | 1,551 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR9 ,
VAR4
);
output VAR2 ;
input VAR5 ;
input VAR9 ;
input VAR4;
wire VAR6 ;
wire VAR11 ;
wire VAR8;
not VAR7 (VAR6 , VAR4 );
and VAR10 (VAR11 , VAR5, VAR9 );
nor VAR1 (VAR8, VAR6, VAR11 );
buf VAR3 (VAR2 , VAR8 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v | 8,157 | module MODULE1 #
(
parameter VAR46 = 100,
parameter VAR4 = 33,
parameter VAR36 = 3,
parameter VAR12 = 12,
parameter VAR10 = 2,
parameter VAR15 = 16,
parameter VAR44 = 4,
parameter VAR38 = "VAR54"
)
(
VAR33, VAR37, VAR32, VAR40, VAR19, VAR7, VAR51, VAR43, VAR20,
VAR34, VAR50, VAR11,
rst, clk, VAR17, VAR25, VAR14, VAR22,... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o.behavioral.v | 1,705 | module MODULE1 (
VAR11 ,
VAR3,
VAR9,
VAR5 ,
VAR6
);
output VAR11 ;
input VAR3;
input VAR9;
input VAR5 ;
input VAR6 ;
supply1 VAR10;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR14 ;
wire VAR12 ;
wire VAR13 ;
wire VAR16;
and VAR7 (VAR12 , VAR5, VAR6 );
nor VAR1 (VAR13 , VAR3, VAR9 );
or VAR15 (VAR16, VAR13, VAR12);
buf VAR4 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15.pp.blackbox.v | 1,309 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR4,
VAR3,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s.symbol.v | 1,322 | module MODULE1 (
input VAR1,
output VAR4
);
supply1 VAR2;
supply0 VAR3;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_top.v | 14,194 | module MODULE1 (
VAR17,
VAR10,
interrupt,
VAR15,
VAR91,
VAR18,
VAR2,
VAR69,
VAR64,
VAR88,
VAR3,
VAR81,
VAR70,
VAR104,
VAR60,
VAR87,
VAR34,
VAR101,
VAR98,
VAR56,
VAR74,
VAR6,
VAR29,
VAR61,
VAR31,
VAR67,
VAR45,
VAR48,
VAR97,
VAR71,
VAR75,
VAR50,
VAR68,
VAR62,
VAR102,
VAR40,
VAR85,
VAR52,
VAR38,
VAR109,
VAR82,
VAR108,
VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o.functional.v | 2,043 | module MODULE1 (
VAR5,
VAR16,
VAR4 ,
VAR9 ,
VAR11 ,
VAR8 ,
VAR15
);
input VAR5;
input VAR16;
output VAR4 ;
input VAR9 ;
input VAR11 ;
input VAR8 ;
input VAR15 ;
wire VAR15 VAR7 ;
wire VAR15 VAR14 ;
wire VAR1 ;
wire VAR17;
and VAR3 (VAR7 , VAR8, VAR15 );
and VAR10 (VAR14 , VAR9, VAR11 );
or VAR13 (VAR1 , VAR14, VAR7 );
... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/export/export_master.v | 1,870 | module MODULE1 (
clk,
reset,
address,
read,
VAR24,
VAR13,
write,
VAR22,
VAR3,
VAR2,
VAR12,
VAR21,
VAR10,
VAR18,
VAR4,
VAR16,
VAR6,
VAR15,
VAR14,
VAR1,
VAR7,
VAR17,
interrupt,
VAR5
);
parameter VAR11 = 4;
parameter VAR19 = 32;
parameter VAR23 = 32;
parameter VAR8 = 1;
localparam VAR9 = VAR11 * 8;
localparam VAR20 = VAR1... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/float_mega/float_cmp/float_cmp.v | 16,491 | module MODULE1
(
VAR38,
VAR31,
VAR82,
VAR61,
VAR53,
VAR10) ;
output VAR38;
output VAR31;
input VAR82;
input VAR61;
input [31:0] VAR53;
input [31:0] VAR10;
tri1 VAR82;
reg VAR67;
reg VAR77;
wire VAR20;
wire VAR55;
wire VAR52;
wire VAR39;
wire VAR70;
wire VAR68;
wire VAR48;
wire VAR45;
wire VAR27;
wire VAR72;
wire VAR16;... | apache-2.0 |
eecsninja/duinocube-core | common/collision_table.v | 3,419 | module MODULE1(clk, reset,
VAR26, VAR5, VAR13,
wr, VAR23, addr, VAR14, VAR28);
input clk; input reset;
input VAR26; input [VAR9-1:0] VAR5; input [VAR21-1:0] VAR13;
input wr; input [1:0] VAR23; input [VAR9-1:0] addr; input [VAR29-1:0] VAR14; output [VAR29-1:0] VAR28;
assign VAR28 = VAR18 ? VAR33 :
(VAR1 ? VAR12[VAR10] :... | gpl-3.0 |
MeshSr/onetswitch45 | ons45-app52-ref_ofshw/vivado/onets_7045_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/output_queues.v | 10,926 | module MODULE1
parameter VAR111=VAR41/8,
parameter VAR43 = 2,
parameter VAR24 = 4,
parameter VAR80 = 8)
( output [VAR41-1:0] VAR115,
output [VAR111-1:0] VAR73,
input VAR97,
output VAR103,
output [VAR41-1:0] VAR91,
output [VAR111-1:0] VAR38,
input VAR26,
output VAR29,
output [VAR41-1:0] VAR9,
output [VAR111-1:0] VAR110,... | lgpl-2.1 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_fetchvertex.v | 5,691 | module MODULE1(
input VAR28,
input VAR7,
input VAR31,
output reg VAR16,
output [31:0] VAR30,
output [2:0] VAR48,
output VAR57,
output reg VAR49,
input VAR38,
input [31:0] VAR29,
input [6:0] VAR47,
input [6:0] VAR20,
input [28:0] VAR4,
input signed [11:0] VAR43,
input signed [11:0] VAR52,
input [10:0] VAR33,
input [10:0... | lgpl-3.0 |
cliffordwolf/picorv32 | scripts/quartus/system.v | 2,834 | module MODULE1 (
input clk,
input VAR19,
output VAR11,
output reg [7:0] VAR18,
output reg VAR6
);
parameter VAR7 = 0;
parameter VAR12 = 4096;
wire VAR9;
wire VAR13;
reg VAR3;
wire [31:0] VAR4;
wire [31:0] VAR8;
wire [3:0] VAR2;
reg [31:0] VAR14;
wire VAR5;
wire VAR20;
wire [31:0] VAR1;
wire [31:0] VAR10;
wire [3:0] VAR... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3b/sky130_fd_sc_ls__or3b.blackbox.v | 1,291 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR7 ,
VAR2
);
output VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR2;
supply1 VAR3;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
jotego/jt12 | hdl/jt12_pg_sum.v | 1,585 | module MODULE1 (
input [ 3:0] VAR6,
input [19:0] VAR5,
input VAR1,
input signed [5:0] VAR4,
input [16:0] VAR2,
output reg [19:0] VAR7,
output reg [ 9:0] VAR9
);
reg [16:0] VAR8;
reg [19:0] VAR3;
always @(*) begin
VAR8 = VAR2 + {{11{VAR4[5]}},VAR4};
VAR3 = ( VAR6==4'd0 ) ? {4'b0,VAR8[16:1]} : ({3'd0,VAR8} * VAR6);
VAR7 ... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_qp.v | 2,263 | module MODULE1(
clk ,
VAR5 ,
VAR4 ,
VAR2 ,
VAR3 ,
VAR1 ,
VAR7
);
input clk ;
input VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR1 ;
output VAR7 ;
reg VAR7 ;
wire VAR6 = !(VAR4 ||VAR2 ||VAR3 );
always@(posedge clk or negedge VAR5) begin
if(!VAR5)
VAR7 <= 1'b0 ;
end
else if(VAR6) VAR7 <= VAR1 ; else
VAR7 <= 1'b... | gpl-3.0 |
travisg/cpu | rtl/cpu/nopipeline/alu.v | 1,840 | module MODULE1(
input [3:0] VAR1,
input [31:0] VAR2,
input [31:0] VAR4,
output reg [31:0] VAR5
);
always @(VAR1 or VAR2 or VAR4)
begin
case (VAR1)
4'b0000: VAR5 = VAR2 + VAR4;
4'b0001: VAR5 = VAR2 - VAR4;
4'b0010: VAR5 = VAR4 - VAR2;
4'b0011: VAR5 = VAR2 & VAR4;
4'b0100: VAR5 = VAR2 | VAR4;
4'b0101: VAR5 = VAR2 ^ VAR4;... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_reset.v | 4,521 | module MODULE1(
VAR13,
VAR23,
VAR9,
VAR32,
VAR39,
VAR38,
VAR21,
VAR1,
VAR31,
VAR17,
VAR15,
VAR22,
VAR35,
VAR3,
VAR37,
VAR12,
VAR27,
VAR34,
VAR25,
VAR2
);
parameter VAR5 = "";
parameter VAR7 = 1;
input VAR13;
input VAR23;
input VAR9;
input VAR32;
input VAR39;
input VAR38;
input VAR21;
output VAR1;
output VAR31;
input [V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211oi/sky130_fd_sc_hs__a211oi.pp.symbol.v | 1,347 | module MODULE1 (
input VAR2 ,
input VAR4 ,
input VAR6 ,
input VAR1 ,
output VAR3 ,
input VAR7,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a222oi/sky130_fd_sc_hd__a222oi.pp.symbol.v | 1,427 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR5 ,
input VAR2 ,
input VAR3 ,
input VAR1 ,
output VAR11 ,
input VAR9 ,
input VAR10,
input VAR4,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22ai/sky130_fd_sc_ls__o22ai_1.v | 2,352 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR4 ,
VAR10 ,
VAR2 ,
VAR1,
VAR5,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR8 ;
input VAR6 ;
VAR11 VAR9 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi.symbol.v | 1,349 | module MODULE1 (
input VAR3,
input VAR1,
input VAR6,
output VAR5
);
supply1 VAR8;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
elegabriel/myzju | junior1/CA/LAB/lab1/single_cpu/alt_ctl.v | 1,474 | module MODULE1(VAR1,VAR2,VAR3
);
input [5:0] VAR1,VAR2;
output reg [4:0] VAR3;
always @*
begin
case(VAR1)
6'b001000 : begin
case(VAR2)
6'b100000 : VAR3 = 0; 6'b100010 : VAR3 = 1; 6'b100100 : VAR3 = 2; 6'b100101 : VAR3 = 3; 6'b100110 : VAR3 = 4; 6'b101010 : VAR3 = 5; 6'b000000 : VAR3 = 6; 6'b000100 : VAR3 = 7; 6'b000011... | gpl-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/i2s_out.v | 2,030 | module MODULE1(
input VAR1,
input reset,
input[15:0] VAR4,
input[15:0] VAR3,
output VAR7,
output VAR6,
output reg VAR5);
reg [3:0] VAR2;
begin
begin
begin
end
begin
begin
end
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o.blackbox.v | 1,418 | module MODULE1 (
VAR3 ,
VAR6,
VAR1,
VAR7 ,
VAR2
);
output VAR3 ;
input VAR6;
input VAR1;
input VAR7 ;
input VAR2 ;
supply1 VAR5;
supply0 VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.behavioral.pp.v | 2,036 | module MODULE1 (
VAR3 ,
VAR17 ,
VAR8 ,
VAR15 ,
VAR13 ,
VAR9,
VAR5,
VAR16 ,
VAR11
);
output VAR3 ;
input VAR17 ;
input VAR8 ;
input VAR15 ;
input VAR13 ;
input VAR9;
input VAR5;
input VAR16 ;
input VAR11 ;
wire VAR4 ;
wire VAR7 ;
wire VAR6;
or VAR12 (VAR4 , VAR8, VAR17 );
and VAR14 (VAR7 , VAR4, VAR15, VAR13 );
VAR1 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp.pp.blackbox.v | 1,420 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3 ,
VAR7 ,
VAR4 ,
VAR1 ,
VAR10,
VAR9,
VAR5 ,
VAR8
);
output VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR10;
input VAR9;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/nes_clkgen.v | 3,154 | module MODULE1 (
input clk,
input rst,
output VAR32,
output VAR45,
output VAR38
);
wire VAR52;
wire VAR61;
wire VAR5;
wire VAR28;
wire VAR48;
wire VAR9;
wire VAR44;
wire VAR50;
wire VAR6;
VAR7 #(
.VAR41 ("VAR2"),
.VAR12 ("VAR42"),
.VAR37 ("VAR58"),
.VAR19 (1),
.VAR26 (18),
.VAR14 (0.000),
.VAR54 (9),
.VAR10 (180.00),
.... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/iface/ip/Write_Master/write_burst_control.v | 12,411 | module MODULE1 (
clk,
reset,
VAR1,
VAR6,
VAR43,
VAR14,
VAR12,
ready,
valid,
VAR38,
VAR48,
VAR28,
VAR11,
VAR36,
VAR42,
VAR17,
VAR37,
VAR49,
VAR30,
VAR18,
VAR35,
VAR19,
VAR46,
VAR26
);
parameter VAR21 = 1; parameter VAR29 = 3;
parameter VAR41 = 4;
parameter VAR9 = 2;
parameter VAR22 = 32;
parameter VAR33 = 32;
parameter ... | mit |
orbancedric/DeepGate | other/Mojo Projects/Mojo-SDRAM/src/avr_interface.v | 2,141 | module MODULE1(
input clk,
input rst,
input VAR9,
output VAR10,
input VAR28,
input VAR18,
input VAR2,
output [3:0] VAR24,
output VAR4,
input VAR45,
input [3:0] VAR26,
output VAR40,
output [9:0] VAR35,
output [3:0] VAR8,
input [7:0] VAR33,
input VAR13,
output VAR11,
input VAR17,
output [7:0] VAR31,
output VAR32
);
wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi_1.v | 2,312 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR5 ,
VAR10 ,
VAR8 ,
VAR3 ,
VAR1,
VAR2
);
output VAR7 ;
input VAR9 ;
input VAR5 ;
input VAR10 ;
input VAR8 ;
input VAR3 ;
input VAR1;
input VAR2;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODUL... | apache-2.0 |
alonso193/proyecto1 | Pruebas/DMA_SD/DMA.v | 2,794 | module MODULE1(
VAR6 , reset , VAR5 , VAR8 , VAR10 , VAR2
);
input VAR6,reset,VAR5,VAR8;
output VAR10,VAR2;
wire VAR6,reset,VAR5,VAR8;
reg VAR10,VAR2;
parameter VAR1 = 3
;
parameter VAR9 = 2'b00,VAR4 = 2'b01,VAR3 = 2'b10, VAR11 = 2'b11;
reg [VAR1-1:0] state ; wire [VAR1-1:0] VAR12 ;
assign VAR12 = VAR7(state, VAR5, VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_4.behavioral.pp.v | 1,383 | module MODULE1( VAR9, VAR8, VAR7, VAR1, VAR2, VAR6, VAR10 );
input VAR1, VAR7, VAR8, VAR9;
inout VAR6, VAR10;
output VAR2;
VAR3 VAR5(.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7),.VAR1(VAR1),.VAR2(VAR2),.VAR6(VAR6),.VAR10(VAR10));
VAR3 VAR4(.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7),.VAR1(VAR1),.VAR2(VAR2),.VAR6(VAR6),.VAR10(VAR10)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i.pp.blackbox.v | 1,317 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR2,
VAR4,
VAR5 ,
VAR3
);
output VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR2;
input VAR4;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai.pp.blackbox.v | 1,393 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR5 ,
VAR7 ,
VAR1 ,
VAR9,
VAR8,
VAR2 ,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR9;
input VAR8;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
efabless/openlane | designs/jpeg_encoder/src/dct.v | 9,323 | module MODULE1(
clk,
VAR9,
rst,
VAR11,
din,
VAR1, VAR27, VAR65, VAR88, VAR75, VAR36, VAR31, VAR17,
VAR97, VAR70, VAR39, VAR94, VAR81, VAR46, VAR55, VAR50,
VAR66, VAR69, VAR34, VAR56, VAR10, VAR87, VAR63, VAR93,
VAR49, VAR62, VAR71, VAR96, VAR45, VAR15, VAR73, VAR42,
VAR38, VAR33, VAR30, VAR2, VAR78, VAR44, VAR91, VAR83... | apache-2.0 |
toomij/DE2Labs | Lab2/lab2_part5.v | 3,988 | module MODULE5 (VAR5, VAR1, VAR43, VAR45, VAR40, VAR8, VAR57, VAR60, VAR2, VAR63, VAR22);
input [17:0] VAR5;
output [8:0] VAR43, VAR1;
output [0:6] VAR45, VAR40, VAR8, VAR57, VAR60, VAR2, VAR63, VAR22;
assign VAR43[8:0] = VAR5[8:0];
assign VAR60 = 7'b1111111;
MODULE8 VAR46 (VAR5[15:12], VAR45);
MODULE8 VAR53 (VAR5[11:8... | gpl-2.0 |
mbus/mbus | mbus/verilog/no_pwr_gating_ben/mbus_ctrl_layer_wrapper.Ben.v | 3,225 | module MODULE1
(
input VAR16,
input VAR54,
input VAR4,
input VAR51,
output VAR12,
output VAR48,
input [VAR39-1:0] VAR40,
input [VAR45-1:0] VAR52,
input VAR41,
input VAR43,
input VAR31,
output VAR36,
output [VAR39:0] VAR46,
output [VAR45:0] VAR57,
output VAR2,
input VAR3,
output VAR19,
output VAR10,
output VAR38,
output... | apache-2.0 |
ayaovi/yoda | DEA/UART_Sender.v | 3,070 | module MODULE1 #(
parameter VAR3 = 5,
parameter VAR8 = 5'd29 )(
input VAR13,
input VAR5,
input [7:0]VAR16,
input VAR4,
output reg VAR1,
output reg VAR2 );
reg VAR10;
reg [ 7:0]VAR12;
reg [VAR3-1:0]VAR11;
reg [ 2:0]VAR14;
reg [1:0]VAR6;
localparam VAR9 = 2'b00;
localparam VAR17 = 2'b01;
localparam VAR15 = 2'b11;
localpa... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.v | 2,461 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR12,
VAR6,
VAR11 ,
VAR9
);
output VAR1 ;
input VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR12;
input VAR6;
input VAR11 ;
input VAR9 ;
VAR10 VAR3 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR12(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2/sky130_fd_sc_hd__and2_4.v | 2,086 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR5 ,
VAR1,
VAR8,
VAR9 ,
VAR6
);
output VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR1;
input VAR8;
input VAR9 ;
input VAR6 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR2,
VAR4,
VAR5
);
output VAR2;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.pp.blackbox.v | 1,269 | module MODULE1 (
VAR7,
VAR5,
VAR6 ,
VAR2,
VAR3,
VAR1 ,
VAR4
);
output VAR7;
input VAR5;
input VAR6 ;
input VAR2;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_2.behavioral.pp.v | 1,316 | module MODULE1( VAR9, VAR4, VAR7, VAR1, VAR8, VAR6 );
input VAR9, VAR4, VAR7;
inout VAR8, VAR6;
output VAR1;
VAR2 VAR5(.VAR9(VAR9),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR6(VAR6));
VAR2 VAR3(.VAR9(VAR9),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR6(VAR6)); | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/ball_absolute.v | 2,288 | module MODULE1(clk, reset, VAR12, VAR25, VAR13);
input clk;
input reset;
output VAR12, VAR25;
output [2:0] VAR13;
wire VAR17;
wire [8:0] VAR2;
wire [8:0] VAR20;
reg [8:0] VAR21; reg [8:0] VAR7;
reg [8:0] VAR22 = -2; reg [8:0] VAR16 = 2;
localparam VAR9 = 128; localparam VAR1 = 128;
localparam VAR19 = 4;
VAR11 VAR26(
.c... | gpl-3.0 |
olajep/oh | src/mio/hdl/mrx_protocol.v | 2,864 | module MODULE1 (
VAR10, VAR9,
VAR4, VAR12, VAR17, VAR2, VAR18, VAR6
);
parameter VAR7 = 104; parameter VAR21 = 8; parameter VAR20 = VAR14(2*VAR7/VAR21);
input VAR4; input VAR12;
input [7:0] VAR17; input VAR2;
input VAR18; input [2*VAR21-1:0] VAR6;
output VAR10; output [VAR7-1:0] VAR9;
reg [2:0] VAR19;
reg [VAR20-1:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor3/sky130_fd_sc_lp__xor3.behavioral.v | 1,406 | module MODULE1 (
VAR10,
VAR9,
VAR2,
VAR3
);
output VAR10;
input VAR9;
input VAR2;
input VAR3;
supply1 VAR8;
supply0 VAR5;
supply1 VAR11 ;
supply0 VAR7 ;
wire VAR4;
xor VAR6 (VAR4, VAR9, VAR2, VAR3 );
buf VAR1 (VAR10 , VAR4 );
endmodule | apache-2.0 |
gigglesninja/digital-system-design | Lab4/ipcore_dir/mult12x12l3.v | 8,071 | module MODULE2 (
clk, VAR5, VAR52, VAR64
);
input clk;
output [23 : 0] VAR5;
input [11 : 0] VAR52;
input [11 : 0] VAR64;
wire \VAR22/VAR8 ;
wire \VAR22/VAR36 ;
wire \VAR65/VAR66<34>VAR34 ;
wire \VAR65/VAR66<33>VAR34 ;
wire \VAR65/VAR66<32>VAR34 ;
wire \VAR65/VAR66<31>VAR34 ;
wire \VAR65/VAR66<30>VAR34 ;
wire \VAR65/VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o_2.v | 2,402 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR11 ,
VAR5 ,
VAR3 ,
VAR10 ,
VAR4 ,
VAR7,
VAR6
);
output VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR10 ;
input VAR4 ;
input VAR7;
input VAR6;
VAR8 VAR2 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
... | apache-2.0 |
joaocarlos/udlx-verilog | rtl/execute/branch_control.v | 2,421 | module MODULE1
parameter VAR10 = 32,
parameter VAR3 = 6,
parameter VAR15 = 25
)
(
input VAR11,
input VAR4,
input VAR14,
input VAR5,
input VAR12,
input [VAR3-1:0] VAR6,
input [VAR10-1:0] VAR7,
input [VAR10-1:0] VAR2,
input [VAR15-1:0] VAR13,
output VAR8,
output [VAR3-1:0] VAR17
);
wire [VAR10-1:0] VAR16;
wire [VAR10-1:0... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfstp/sky130_fd_sc_ms__sdfstp.functional.pp.v | 2,163 | module MODULE1 (
VAR14 ,
VAR10 ,
VAR16 ,
VAR19 ,
VAR11 ,
VAR2,
VAR6 ,
VAR18 ,
VAR1 ,
VAR15
);
output VAR14 ;
input VAR10 ;
input VAR16 ;
input VAR19 ;
input VAR11 ;
input VAR2;
input VAR6 ;
input VAR18 ;
input VAR1 ;
input VAR15 ;
wire VAR9 ;
wire VAR4 ;
wire VAR17;
not VAR8 (VAR4 , VAR2 );
VAR20 VAR13 (VAR17, VAR16, V... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/xcv_glbl.v | 3,292 | module MODULE1 ();
wire VAR2;
wire VAR1;
wire VAR4;
wire VAR3;
endmodule | gpl-3.0 |
masc-ucsc/cmpe220fall16 | rtl/ram_2port_fast.v | 1,717 | module MODULE1 #(parameter VAR16 = 64, VAR21=128, VAR25=0) (
input clk
,input reset
,input VAR24
,output VAR17
,input [VAR29(VAR21)-1:0] VAR14
,input [VAR16-1:0] VAR9
,input VAR33
,output VAR18
,input [VAR29(VAR21)-1:0] VAR6
,output VAR4
,input VAR12
,output [VAR16-1:0] VAR20
);
logic [VAR16-1:0] VAR2;
logic [VAR16-1:0... | apache-2.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/start_for_Loop_lotde.v | 3,003 | module MODULE2 (
clk,
VAR26,
VAR7,
VAR21,
VAR13);
parameter VAR15 = 32'd1;
parameter VAR4 = 32'd2;
parameter VAR23 = 32'd4;
input clk;
input [VAR15-1:0] VAR26;
input VAR7;
input [VAR4-1:0] VAR21;
output [VAR15-1:0] VAR13;
reg[VAR15-1:0] VAR12 [0:VAR23-1];
integer VAR1;
always @ (posedge clk)
begin
if (VAR7)
begin
for (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o_1.v | 2,469 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR11 ,
VAR4 ,
VAR12 ,
VAR7 ,
VAR3,
VAR1,
VAR8 ,
VAR5
);
output VAR2 ;
input VAR9 ;
input VAR11 ;
input VAR4 ;
input VAR12 ;
input VAR7 ;
input VAR3;
input VAR1;
input VAR8 ;
input VAR5 ;
VAR6 VAR10 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR3(... | apache-2.0 |
dries007/Basys3 | FPGA-Z/FPGA-Z.srcs/sources_1/ip/FontROM/FontROM_stub.v | 1,170 | module MODULE1(VAR1, VAR2)
;
input [13:0]VAR1;
output [0:0]VAR2;
endmodule | mit |
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