repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2/sky130_fd_sc_ms__nand2.blackbox.v | 1,239 | module MODULE1 (
VAR5,
VAR1,
VAR2
);
output VAR5;
input VAR1;
input VAR2;
supply1 VAR7;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
zhangly/azpr_cpu | rtl/cpu/rtl/mem_reg.v | 3,615 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR30] out, input wire VAR26,
input wire VAR5, input wire VAR31,
input wire [VAR1] VAR29, input wire VAR3, input wire VAR24, input wire [VAR32] VAR28, input wire [VAR21] VAR11, input wire VAR9, input wire [VAR18] VAR15,
output reg [VAR1] VAR33, output reg V... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/input_arbiter.v | 13,491 | module MODULE1
parameter VAR62 = 64,
parameter VAR45=VAR62/8,
parameter VAR37 = 2,
parameter VAR17 = 2,
parameter VAR84 = 8
)
( VAR68,
VAR47,
VAR34,
VAR57,
VAR55,
VAR85,
VAR64,
VAR6,
VAR56,
VAR7,
VAR73,
VAR89,
VAR24,
VAR36,
VAR82,
VAR27,
VAR31,
VAR22,
VAR25,
VAR54,
VAR52,
VAR39,
VAR49,
VAR88,
VAR9,
VAR75,
VAR72,
VAR35,... | apache-2.0 |
rwarmstr/Vivado_IP | xadc_data_demux/src/xadc_data_demux.v | 2,405 | module MODULE1
(
input clk,
input reset,
input [15:0] VAR2,
input VAR4,
input [4:0] VAR1,
output reg [15:0] VAR7,
output reg VAR5,
output reg [15:0] VAR6,
output reg VAR3
);
always @(posedge clk) begin
if (reset) begin
VAR7 <= 16'd0;
VAR5 <= 1'b0;
end
else
if (VAR4 && (VAR1 == 5'h10)) begin
VAR7 <= VAR2;
VAR5 <= 1'b1;
... | mit |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/submodules/hps_sdram_p0_acv_hard_memphy.v | 28,427 | module MODULE1 (
VAR71,
VAR119,
VAR116,
VAR134,
VAR211,
VAR110,
VAR221,
VAR95,
VAR130,
VAR224,
VAR122,
VAR204,
VAR92,
VAR146,
VAR156,
VAR161,
VAR157,
VAR155,
VAR188,
VAR186,
VAR180,
VAR99,
VAR239,
VAR36,
VAR50,
VAR133,
VAR69,
VAR149,
VAR138,
VAR251,
VAR79,
VAR31,
VAR94,
VAR137,
VAR1,
VAR101,
VAR170,
VAR45,
VAR32,
VAR20... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_25.v | 18,301 | module MODULE4 (
clk,
reset,
VAR99,
VAR97,
VAR124,
VAR114,
VAR14
);
parameter VAR80 = 18;
parameter VAR89 = 25;
parameter VAR15 = 13;
localparam VAR92 = 26;
input clk;
input reset;
input VAR99;
input VAR97;
input [VAR80-1:0] VAR124; output VAR114;
output [VAR80-1:0] VAR14;
localparam VAR16 = 18; localparam VAR41 = 36; ... | mit |
SiLab-Bonn/basil | basil/firmware/modules/jtag_master/jtag_master.v | 1,720 | module MODULE1 #(
parameter VAR19 = 16'h0000,
parameter VAR28 = 16'h0000,
parameter VAR7 = 16,
parameter VAR11 = 2
) (
input wire VAR22,
input wire VAR17,
input wire [VAR7-1:0] VAR16,
inout wire [7:0] VAR27,
input wire VAR14,
input wire VAR9,
input wire VAR3,
output wire VAR13, input wire VAR10, output wire VAR15, outp... | bsd-3-clause |
alanachtenberg/CSCE-350 | Project3/IdealMemory.v | 1,600 | module MODULE1 (VAR4, VAR5);
parameter VAR2 = 10;
parameter VAR1 = 1024, VAR3 = 32;
input [VAR3-1:0] VAR4;
output [VAR3-1:0] VAR5;
reg [VAR3-1:0] VAR5;
reg [VAR3-1:0] VAR6[0:VAR1-1];
always
endmodule | gpl-2.0 |
sam-falvo/remex | rtl/rx_DS_SE.v | 2,442 | module MODULE1(
input VAR3,
input VAR16,
input VAR11,
input VAR14,
output [1:0] VAR7,
output VAR1
);
wire VAR19 = VAR3 ^ VAR16;
reg VAR9, VAR4;
always @(posedge VAR11) begin
if(VAR14) begin
VAR9 <= 0;
VAR4 <= 0;
end
else begin
VAR9 <= VAR3;
VAR4 <= VAR19;
end
end
reg VAR6;
always @(posedge VAR11) begin
if(VAR14) begin
... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb.pp.symbol.v | 1,348 | module MODULE1 (
input VAR3 ,
input VAR7 ,
input VAR1 ,
input VAR9 ,
output VAR8 ,
input VAR4 ,
input VAR6,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
esonghori/TinyGarbled | circuit_synthesis/mips/ALU.v | 1,196 | module MODULE1
(
VAR1 ,
VAR5 ,
VAR4 ,
VAR8
);
input [31:0]VAR1;
input [31:0]VAR5;
input [3:0]VAR4;
output reg [31:0]VAR8;
wire signed [31:0]VAR2, bins;
assign VAR2=VAR1;
assign bins=VAR5;
wire [31:0] VAR16;
wire [31:0] VAR7;
wire VAR13;
reg VAR3;
assign VAR16 = (VAR3)?~VAR5:VAR5;
VAR12
.VAR9(32)
)
VAR12
(
.VAR15(VAR1),... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_cx4/cx4.v | 28,435 | module MODULE1(
input [7:0] VAR37,
output [7:0] VAR41,
input [12:0] VAR31,
input VAR29,
input VAR16,
input VAR55,
input VAR39,
input [7:0] VAR5,
output [23:0] VAR28,
output VAR15,
input VAR26,
output VAR44,
output [2:0] VAR34,
input VAR3
);
reg [2:0] VAR53;
parameter VAR32 = 2'b00;
parameter VAR8 = 2'b01;
parameter VAR... | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_7x_v1_8_axi_basic_rx.v | 8,258 | module MODULE1 #(
parameter VAR31 = 128, parameter VAR29 = "VAR11", parameter VAR14 = "VAR26", parameter VAR2 = "VAR26", parameter VAR17 = 1,
parameter VAR34 = (VAR31 == 128) ? 2 : 1, parameter VAR19 = VAR31 / 8 ) (
output [VAR31-1:0] VAR25, output VAR15, input VAR3, output [VAR19-1:0] VAR10, output VAR27, output [21:0... | mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_zbroji_0_0/hdl/verilog/zbroji.v | 1,092 | module MODULE1 (
VAR6,
VAR1,
VAR9,
VAR4,
VAR5,
VAR3,
VAR2
);
input VAR6;
output VAR1;
output VAR9;
output VAR4;
input [31:0] VAR5;
input [31:0] VAR3;
output [31:0] VAR2;
parameter VAR8 = 1'b1;
parameter VAR7 = 1'b0;
assign VAR1 = VAR6;
assign VAR9 = VAR8;
assign VAR4 = VAR6;
assign VAR2 = (VAR3 + VAR5);
endmodule | mit |
cbakalis/vmm_boards_firmware | sources/sources_1/xadc/mdt_xadc/xadc_read.v | 13,929 | module MODULE1
(
input VAR25,
input rst,
input VAR34,
input [4:0] VAR15,
input VAR14,
input VAR19,
input [4:0] VAR42,
input [15:0] VAR45,
input VAR9,
input VAR39,
output VAR57,
output [11:0] VAR35,
output VAR40,
output [6:0] VAR26,
output VAR51,
output VAR36,
output [15:0] VAR11,
output VAR13,
output [3:0] VAR17
);
wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtp/sky130_fd_sc_ls__dfrtp.functional.v | 1,642 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR7 ,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR7 ;
input VAR4;
wire VAR11;
wire VAR6;
not VAR9 (VAR6 , VAR4 );
VAR10 VAR3 VAR8 (VAR11 , VAR7, VAR1, VAR6 );
buf VAR5 (VAR2 , VAR11 );
endmodule | apache-2.0 |
comododragon/SHA256_FPGA | Full/Verilog/sha256_w_mem.v | 10,686 | module MODULE1(
input wire clk,
input wire VAR34,
input wire [511 : 0] VAR9,
input wire VAR23,
input wire VAR7,
output wire [31 : 0] VAR25
);
parameter VAR20 = 0;
parameter VAR5 = 1;
reg [31 : 0] VAR13 [0 : 15];
reg [31 : 0] VAR19;
reg [31 : 0] VAR38;
reg [31 : 0] VAR46;
reg [31 : 0] VAR33;
reg [31 : 0] VAR32;
reg [31 ... | mit |
bargei/NoC264 | NoC264_3x3/mkRouterOutputArbitersStatic.v | 11,922 | module MODULE1(VAR1,
VAR6,
VAR9,
VAR16,
VAR7,
VAR10,
VAR11,
VAR13,
VAR3,
VAR2,
VAR14,
VAR8,
VAR4,
VAR12,
VAR15,
VAR5,
VAR17);
input VAR1;
input VAR6;
input [4 : 0] VAR9;
output [4 : 0] VAR16;
input VAR7;
input [4 : 0] VAR10;
output [4 : 0] VAR11;
input VAR13;
input [4 : 0] VAR3;
output [4 : 0] VAR2;
input VAR14;
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o.behavioral.v | 1,502 | module MODULE1 (
VAR4 ,
VAR8,
VAR5,
VAR2
);
output VAR4 ;
input VAR8;
input VAR5;
input VAR2;
supply1 VAR11;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR9 ;
wire VAR12 ;
wire VAR1;
and VAR13 (VAR12 , VAR8, VAR5 );
or VAR6 (VAR1, VAR12, VAR2 );
buf VAR10 (VAR4 , VAR1 );
endmodule | apache-2.0 |
ptracton/Picoblaze | library/uart_pb/pb_uart.v | 4,064 | module MODULE1 (
VAR10, VAR33, interrupt,
clk, reset, VAR14, VAR8, VAR4, VAR24, VAR7
) ;
input clk;
input reset;
input VAR14;
output VAR10;
input [7:0] VAR8;
input [7:0] VAR4;
output [7:0] VAR33;
input VAR24;
input VAR7;
output interrupt;
parameter VAR25 = 8'h00;
wire VAR15; wire VAR32; wire enable; wire [15:0] VAR34; ... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v | 4,868 | module MODULE1 #
(
parameter VAR2 = 100, parameter VAR14 = 2, parameter VAR13 = "VAR6", parameter VAR3 = "VAR16", parameter VAR1 = 300.0, parameter VAR15 = "VAR10" )
(
input VAR4, input clk, input rst, output [VAR14-1:0] VAR12, output [VAR14-1:0] VAR7 );
generate
genvar VAR8;
for (VAR8 = 0; VAR8 < VAR14; VAR8 = VAR8 + ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i.pp.blackbox.v | 1,264 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR3,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR3;
input VAR2;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_delta_wrapped.v | 3,442 | module MODULE1(
clk,
rst,
VAR11,
VAR7,
VAR10,
VAR2,
out
);
parameter VAR8 = 12;
parameter VAR6 = 3;
parameter VAR8 = 32;
parameter VAR6 = 8;
input clk;
input rst;
input [VAR6-1:0] VAR11;
input [VAR6-1:0] VAR7;
input [VAR8-1:0] VAR10;
input VAR2;
output out;
wire [2:0] VAR9;
wire [2:0] VAR3;
VAR12 VAR12(.VAR8(VAR8),
.VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfsbp/sky130_fd_sc_hvl__dfsbp.functional.v | 1,747 | module MODULE1 (
VAR6 ,
VAR13 ,
VAR1 ,
VAR2 ,
VAR9
);
output VAR6 ;
output VAR13 ;
input VAR1 ;
input VAR2 ;
input VAR9;
wire VAR3;
wire VAR11 ;
not VAR12 (VAR11 , VAR9 );
VAR8 VAR4 VAR10 (VAR3 , VAR2, VAR1, VAR11 );
buf VAR5 (VAR6 , VAR3 );
not VAR7 (VAR13 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.pp.blackbox.v | 1,400 | module MODULE1 (
VAR1 ,
VAR2,
VAR5 ,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR2;
input VAR5 ;
input VAR4 ;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn.blackbox.v | 1,280 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR3 ;
input VAR6;
supply1 VAR5;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor2/sky130_fd_sc_hs__xnor2_4.v | 2,005 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR2 ,
VAR5,
VAR1
);
output VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR5;
input VAR1;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR3,
VAR2
);
output VAR7;
input VAR3;
input VAR2;
supply1 VAR5;
supply0 VAR1;
VAR6 VAR4 (
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311a/sky130_fd_sc_ms__o311a.blackbox.v | 1,373 | module MODULE1 (
VAR7 ,
VAR8,
VAR6,
VAR2,
VAR3,
VAR10
);
output VAR7 ;
input VAR8;
input VAR6;
input VAR2;
input VAR3;
input VAR10;
supply1 VAR4;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_2.functional.v | 1,664 | module MODULE1( VAR20, VAR15, VAR19, VAR7, VAR3, VAR12 );
input VAR7, VAR19, VAR20, VAR15, VAR12;
output VAR3;
wire VAR8;
not VAR5( VAR8, VAR19 );
wire VAR14;
not VAR9( VAR14, VAR20 );
wire VAR21;
and VAR18( VAR21, VAR8, VAR14 );
wire VAR17;
not VAR4( VAR17, VAR15 );
wire VAR16;
and VAR10( VAR16, VAR8, VAR17 );
wire VA... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/ip_eth_tx_64.v | 27,030 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR8,
output wire VAR17,
input wire [47:0] VAR95,
input wire [47:0] VAR26,
input wire [15:0] VAR111,
input wire [5:0] VAR62,
input wire [1:0] VAR92,
input wire [15:0] VAR2,
input wire [15:0] VAR94,
input wire [2:0] VAR81,
input wire [12:0] VAR82,
input wire [7... | mit |
scalable-networks/ext | uhd/fpga/usrp2/fifo/buffer_int2.v | 5,354 | module MODULE1
parameter VAR33 = 9)
(input clk, input rst,
input VAR1, input [7:0] VAR72, input [31:0] VAR11,
output [31:0] VAR46,
input VAR52,
input VAR62,
input VAR37,
input VAR13,
input [15:0] VAR10,
input [31:0] VAR12,
output [31:0] VAR4,
output reg VAR69,
input [35:0] VAR43,
input VAR20,
output VAR30,
output [35:0... | gpl-2.0 |
tlk-emb/SWORDS | utils/lib/xilinx.com_user_tlast_gen_1.0/tlast_gen.v | 2,152 | module MODULE1
parameter VAR3 = 8,
parameter VAR1 = 256
)
(
input VAR15,
input VAR11,
input [VAR10(VAR1):0] VAR7,
input VAR8,
output VAR14,
input [VAR3-1:0] VAR4,
output VAR9,
input VAR13,
output VAR5,
output [VAR3-1:0] VAR6
);
wire VAR2;
reg [VAR10(VAR1):0] VAR12 = 0;
assign VAR14 = VAR13;
assign VAR9 = VAR8;
assign V... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_tt.v | 9,390 | module MODULE1(
clk, rst, VAR13,
VAR16, VAR19, VAR23, VAR6, VAR17,
VAR8
);
input clk; input rst; input VAR13; input VAR16; input VAR19; input [31:0] VAR23; input [31:0] VAR6; output [31:0] VAR17; output VAR8;
reg [31:0] VAR14; else
wire [31:0] VAR14; VAR5
reg [31:0] VAR7; else
wire [31:0] VAR7; VAR5
wire VAR11; wire VA... | gpl-2.0 |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/Logica_Pong.v | 1,397 | module MODULE1(
input VAR3,
input VAR2,
input reset,
input [8:0] VAR5,
input [9:0] VAR1,
input [8:0] VAR6,
output reg VAR4,
output reg VAR7
);
begin
begin
begin
end
begin
begin
end | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_1.behavioral.v | 1,180 | module MODULE1( VAR1, VAR2, VAR6 );
input VAR1, VAR6;
output VAR2;
VAR3 VAR4(.VAR1(VAR1),.VAR2(VAR2),.VAR6(VAR6));
VAR3 VAR5(.VAR1(VAR1),.VAR2(VAR2),.VAR6(VAR6)); | apache-2.0 |
Tao-J/nexys3MIPSSoC | arbiter.v | 4,772 | module MODULE1(
VAR7, VAR19, VAR23,
VAR2, VAR34, VAR28,
VAR18, VAR21,
VAR1, VAR13,
VAR26, VAR27, VAR14, VAR4,
VAR5, VAR17, VAR15,
VAR33, VAR20, VAR24,
VAR32, VAR25, VAR31, VAR12,
VAR6, VAR22
,VAR3
);
input wire VAR26, VAR27;
input wire [31:0] VAR14;
input wire [31:0] VAR4;
input wire [3:0] VAR5;
input wire VAR17;
input... | gpl-3.0 |
VCTLabs/DE1_SOC_Linux_FB | ip/TERASIC_IRM/irda_receive_terasic.v | 9,816 | module MODULE1(
VAR23, VAR18,
VAR13, VAR20,
VAR6, VAR9 );
parameter VAR3 = 2'b00; parameter VAR1 = 2'b01; parameter VAR10 = 2'b10;
parameter VAR5 = 262143; parameter VAR4 = 230000; parameter VAR2 = 210000; parameter VAR16 = 41500; parameter VAR19 = 20000;
input VAR23; input VAR18; input VAR13; input VAR20;
output VAR6;... | epl-1.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_bae.v | 61,427 | module MODULE1(
clk ,
VAR110 ,
VAR228 ,
VAR61 ,
VAR50 ,
VAR196 ,
VAR226 ,
VAR35 ,
VAR56 ,
VAR210
);
input clk ; input VAR110 ; input VAR228 ;
input [9:0] VAR61 ; input [9:0] VAR50 ; input [9:0] VAR196 ; input [9:0] VAR226 ; output [7:0] VAR35 ; output VAR56 ; output VAR210 ;
reg VAR210 ;
wire [5:0] VAR2 ;
wire VAR127 ;... | gpl-3.0 |
MeshSr/onetswitch20 | ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/core/rx_queue.v | 16,084 | module MODULE1
parameter VAR76 = VAR41/8,
parameter VAR6 = 1,
parameter VAR58 = 'hff,
parameter VAR22 = 0,
parameter VAR44 = 32,
parameter VAR3 = VAR44/8
)
(output reg [VAR41-1:0] VAR69,
output reg [VAR76-1:0] VAR43,
output reg VAR9,
input VAR81,
input VAR48,
input [VAR44 - 1:0] VAR21,
input [VAR3 - 1:0] VAR33,
input V... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3.blackbox.v | 1,288 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
supply1 VAR2;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf.symbol.v | 1,226 | module MODULE1 (
input VAR1,
output VAR3
);
supply1 VAR2;
supply0 VAR4;
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build1/alu_andy.v | 174,363 | module MODULE1(VAR6,VAR4,VAR9,VAR8,VAR5,VAR7,VAR2);
output [0:127] VAR7;
input [0:127] VAR6;
input [0:127] VAR4;
input [0:2] VAR9;
input [0:1] VAR8;
input [0:4] VAR5;
input [15:0] VAR2;
reg [0:127] VAR7;
always @(VAR6 or VAR4 or VAR9 or VAR8 or VAR5 or VAR2)
begin
case(VAR5)
begin
case(VAR9)
case(VAR1)
begin
case(VAR4[... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtn/sky130_fd_sc_lp__dlxtn.behavioral.v | 1,884 | module MODULE1 (
VAR5 ,
VAR16 ,
VAR1
);
output VAR5 ;
input VAR16 ;
input VAR1;
supply1 VAR12;
supply0 VAR14;
supply1 VAR6 ;
supply0 VAR2 ;
wire VAR3 ;
wire VAR8 ;
wire VAR11;
wire VAR4 ;
reg VAR7 ;
VAR10 VAR15 (VAR8 , VAR4, VAR3, VAR7, VAR12, VAR14);
not VAR9 (VAR3 , VAR11 );
buf VAR13 (VAR5 , VAR8 );
endmodule | apache-2.0 |
gigglesninja/digital-system-design | Lab4/lab4dpath_part3.v | 1,514 | module MODULE1(VAR6,VAR22,VAR18,VAR15,clk);
input [9:0] VAR6,VAR22,VAR18;
input clk;
output [9:0] VAR15;
wire [11:0] VAR12, VAR17, VAR26, VAR16, VAR13, VAR4, VAR20, VAR29;
wire [23:0] VAR21, VAR19, VAR7;
reg [9:0] VAR27, VAR9, VAR3, VAR2, VAR28, VAR10;
always @(posedge clk) begin
VAR27 <= VAR6;
VAR9 <= VAR22;
VAR3 <= V... | gpl-2.0 |
hpcn-uam/hardware_packet_train | NetFPGA10G/Verilog/rater.v | 2,359 | module MODULE1(
input [31:0] VAR4,
input clk,
input reset,
output reg VAR3,
output reg [31:0]VAR2,
input VAR1
);
reg [31:0] counter;
always @(posedge clk)
begin
if(reset || VAR1)
begin
counter = 0;
VAR2 =0;
end
else
begin
if(counter == VAR4 )
begin
VAR3 =1;
counter =0;
VAR2 = VAR2 +1;
end
else if(counter > VAR4)
begin
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufbuf/sky130_fd_sc_hd__bufbuf.functional.pp.v | 1,768 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR9,
VAR3,
VAR11 ,
VAR12
);
output VAR5 ;
input VAR10 ;
input VAR9;
input VAR3;
input VAR11 ;
input VAR12 ;
wire VAR6 ;
wire VAR8;
buf VAR2 (VAR6 , VAR10 );
VAR7 VAR4 (VAR8, VAR6, VAR9, VAR3);
buf VAR1 (VAR5 , VAR8 );
endmodule | apache-2.0 |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RegTwoUN.v | 1,939 | module MODULE1(VAR6, VAR3, VAR5, VAR4, VAR8, VAR7);
parameter VAR2 = 1;
input VAR6 ;
input VAR3 ;
input VAR4 ;
input [VAR2 - 1 : 0] VAR5;
input [VAR2 - 1 : 0] VAR8;
output [VAR2 - 1 : 0] VAR7;
reg [VAR2 - 1 : 0] VAR7;
VAR7 = {((VAR2 + 1)/2){2'b10}} ;
end
always@(posedge VAR6) begin
if (VAR3)
VAR7 <= VAR1 VAR5;
end
else... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_tse_rgmii_out1.v | 5,262 | module MODULE1 (
VAR24,
VAR13,
VAR4,
VAR9,
VAR12);
input VAR24;
input VAR13;
input VAR4;
input VAR9;
output VAR12;
wire [0:0] VAR16;
wire [0:0] VAR7 = VAR16[0:0];
wire VAR12 = VAR7;
wire VAR5 = VAR13;
wire VAR15 = VAR5;
wire VAR14 = VAR4;
wire VAR21 = VAR14;
VAR10 VAR1 (
.VAR9 (VAR9),
.VAR13 (VAR15),
.VAR24 (VAR24),
.V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_1.behavioral.pp.v | 1,244 | module MODULE1( VAR6, VAR7, VAR4, VAR5, VAR8 );
input VAR6, VAR7;
inout VAR5, VAR8;
output VAR4;
VAR1 VAR2(.VAR6(VAR6),.VAR7(VAR7),.VAR4(VAR4),.VAR5(VAR5),.VAR8(VAR8));
VAR1 VAR3(.VAR6(VAR6),.VAR7(VAR7),.VAR4(VAR4),.VAR5(VAR5),.VAR8(VAR8)); | apache-2.0 |
zaqwes8811/ip-cores | spi_fsm/adv_book.v | 2,762 | module MODULE2(
output [7:0] VAR19,
input [7:0] VAR29,
input [7:0] VAR8,
input clk );
reg [15:0] VAR14;
assign VAR19 = VAR14[15:8];
always @(posedge clk) begin
VAR14 <= VAR29 * VAR8;
end
endmodule
module MODULE3(
output reg [7:0] VAR19,
output VAR22,
input [7:0] VAR29,
input [7:0] VAR8,
input clk,
input VAR16 );
reg [4... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ILC/synth/ghrd_10as066n2_ILC.v | 1,299 | module MODULE1 (
input wire [5:0] VAR10, input wire [31:0] VAR5, input wire VAR3, input wire VAR4, output wire [31:0] VAR7, input wire clk, input wire [1:0] irq, input wire VAR11 );
VAR1 #(
.VAR6 (0),
.VAR8 (100000000),
.VAR2 (2)
) VAR9 (
.VAR11 (VAR11), .clk (clk), .irq (irq), .VAR10 (VAR10), .VAR5 (VAR5), .VAR3 (VAR3... | mit |
scalable-networks/ext | uhd/fpga/usrp2/fifo/packet_generator.v | 3,045 | module MODULE1
(input clk, input reset, input VAR8,
output reg [7:0] VAR6, output VAR9, output VAR7,
input [127:0] VAR4,
output VAR1, input VAR5);
localparam VAR2 = 32'd2000;
reg [31:0] state;
reg [31:0] VAR3;
reg [31:0] VAR10;
wire VAR11 = VAR1 & VAR5 & ~(state[31:2] == 30'h3FFFFFFF);
always @(posedge clk)
if(reset | ... | gpl-2.0 |
peteasa/oh | src/xilibs/dv/PLLE2_ADV.v | 7,731 | module MODULE1 #(
parameter VAR6 = "VAR25",
parameter integer VAR38 = 5,
parameter real VAR40 = 0.000,
parameter real VAR26 = 0.000,
parameter real VAR41 = 0.000,
parameter integer VAR37 = 1,
parameter real VAR24 = 0.500,
parameter real VAR46 = 0.000,
parameter integer VAR54 = 1,
parameter real VAR3 = 0.500,
parameter ... | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/pcie_core/source/pcie_reset_delay_v6.v | 3,948 | module MODULE1 # (
parameter VAR2 = "VAR9",
parameter VAR4 = 0, parameter VAR8 = 1
)
(
input wire VAR1,
input wire VAR6,
output VAR12
);
localparam VAR11 = (VAR2 == "VAR9") ? ((VAR4 == 1) ? 20: (VAR4 == 0) ? 20 : 21) : 2;
reg [7:0] VAR5;
reg [7:0] VAR10;
reg [7:0] VAR3;
wire [23:0] VAR7;
assign VAR7 = {VAR3, VAR10, VAR... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_4.behavioral.v | 1,101 | module MODULE1( VAR2, VAR1 );
input VAR2;
output VAR1;
VAR3 VAR5(.VAR2(VAR2),.VAR1(VAR1));
VAR3 VAR4(.VAR2(VAR2),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3b/sky130_fd_sc_hd__nor3b_1.v | 2,254 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR9 ,
VAR5 ,
VAR1,
VAR4,
VAR8 ,
VAR7
);
output VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR1;
input VAR4;
input VAR8 ;
input VAR7 ;
VAR10 VAR6 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE1 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b.behavioral.v | 1,452 | module MODULE1 (
VAR1 ,
VAR8,
VAR11
);
output VAR1 ;
input VAR8;
input VAR11 ;
supply1 VAR4;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR3 ;
wire VAR12 ;
wire VAR7;
not VAR6 (VAR12 , VAR11 );
or VAR10 (VAR7, VAR12, VAR8 );
buf VAR5 (VAR1 , VAR7 );
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/wishbone/legacy/wb_prefetch.v | 7,625 | module MODULE1
parameter VAR4 = VAR21-1,
parameter VAR17 = 576, parameter VAR26 = 10,
parameter VAR14 = 1 << VAR26,
parameter VAR15 = VAR26-1,
parameter VAR7 = 24,
parameter VAR1 = 5,
parameter VAR16 = (1 << VAR1) - VAR7,
parameter VAR8 = VAR1-1,
parameter VAR24 = VAR26-VAR1,
parameter VAR25 = VAR24-1,
parameter VAR20 ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai.symbol.v | 1,358 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR1,
output VAR2
);
supply1 VAR5;
supply0 VAR4;
endmodule | apache-2.0 |
hoangt/multiported-ram | lvt_bin.v | 9,105 | module MODULE1
localparam VAR26 = VAR41(VAR35 ); localparam VAR38 = VAR41(VAR39);
wire [VAR38 -1:0] VAR36 [VAR39-1:0];
genvar VAR30;
generate
for (VAR30=0;VAR30<VAR39;VAR30=VAR30+1) begin: VAR4
assign VAR36[VAR30]=VAR30;
end
endgenerate
reg [VAR26*VAR39-1:0] VAR33; reg [ VAR39-1:0] VAR14 ; always @(posedge clk) begin
V... | bsd-3-clause |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,123 | module MODULE1 (
clk,
VAR11,
VAR1,
VAR13,
VAR10,
VAR2,
VAR26,
VAR20,
VAR21,
VAR8,
VAR9,
VAR23,
VAR19,
VAR7,
VAR3,
VAR29
)
;
output [ 37: 0] VAR2;
output VAR26;
output VAR20;
output VAR21;
output VAR8;
output VAR9;
output VAR23;
output VAR19;
output VAR7;
output VAR3;
output VAR29;
input clk;
input [ 1: 0] VAR11;
input ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_4.behavioral.v | 2,848 | module MODULE1( VAR26, VAR25, VAR22, VAR6 );
input VAR25, VAR26, VAR22;
output VAR6;
reg VAR7;
VAR9 VAR2(.VAR26(VAR26),.VAR25(VAR25),.VAR22(VAR22),.VAR6(VAR6),.VAR7(VAR7));
VAR9 VAR13(.VAR26(VAR26),.VAR25(VAR25),.VAR22(VAR22),.VAR6(VAR6),.VAR7(VAR7));
buf VAR14(VAR10,VAR22);
not VAR23(VAR24,VAR25);
and VAR18(VAR8,VAR22... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2.pp.blackbox.v | 1,263 | module MODULE1 (
VAR3,
VAR2,
VAR1 ,
VAR4
);
input VAR3;
input VAR2;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.functional.pp.v | 1,611 | module MODULE1( VAR17, VAR1, VAR10, VAR14, VAR18, VAR11 );
input VAR1, VAR17, VAR10;
inout VAR18, VAR11;
output VAR14;
wire VAR6;
not VAR4( VAR6, VAR10 );
wire VAR3;
and VAR21( VAR3, VAR6, VAR1, VAR17 );
wire VAR13;
not VAR8( VAR13, VAR17 );
wire VAR9;
and VAR19( VAR9, VAR13, VAR1, VAR10 );
wire VAR15;
not VAR2( VAR15,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o.behavioral.v | 1,567 | module MODULE1 (
VAR6 ,
VAR5,
VAR9,
VAR13,
VAR1,
VAR15
);
output VAR6 ;
input VAR5;
input VAR9;
input VAR13;
input VAR1;
input VAR15;
supply1 VAR2;
supply0 VAR3;
supply1 VAR14 ;
supply0 VAR4 ;
wire VAR11 ;
wire VAR8;
and VAR12 (VAR11 , VAR13, VAR5, VAR9 );
or VAR10 (VAR8, VAR11, VAR15, VAR1);
buf VAR7 (VAR6 , VAR8 );
e... | apache-2.0 |
drichmond/riffa | fpga/xilinx/NetFPGA/NetFPGA_Gen1x8If64/hdl/NetFPGA_Gen1x8If64.v | 25,626 | module MODULE1
parameter VAR71 = 8,
parameter VAR159 = 64,
parameter VAR115 = 256,
parameter VAR34 = 6)
(output [(VAR71 - 1) : 0] VAR156,
output [(VAR71 - 1) : 0] VAR8,
input [(VAR71 - 1) : 0] VAR202,
input [(VAR71 - 1) : 0] VAR212,
output [1:0] VAR166,
input VAR111,
input VAR151,
input VAR121);
wire VAR58;
wire VAR116... | bsd-3-clause |
nyaxt/dmix | nkmd/arch/nkmd_ddr3_mig_if.v | 5,232 | module MODULE1(
input wire clk,
input wire rst,
output wire VAR42,
output wire VAR30,
output wire [2:0] VAR14,
output wire [5:0] VAR4,
output wire [29:0] VAR17,
input wire VAR8,
input wire VAR41,
output wire VAR24,
output wire VAR27,
output wire [3:0] VAR34,
output wire [31:0] VAR39,
input wire VAR15,
input wire VAR6,
... | mit |
asicguy/gplgpu | hdl/mc_graph/mc_dlp.v | 4,926 | module MODULE1
(
input VAR2,
input VAR10,
input VAR26,
input VAR22,
input [4:0] VAR15,
input [27:0] VAR17,
input VAR3,
input VAR13,
output reg VAR23,
output reg VAR19,
output reg [4:0] VAR24,
output reg [27:0] VAR1,
output reg VAR18
);
reg [27:0] VAR16;
reg [4:0] VAR11;
reg VAR14;
reg VAR21, VAR27, VAR8;
reg VAR25;
reg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s.behavioral.pp.v | 1,868 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR7,
VAR12,
VAR8 ,
VAR2
);
output VAR9 ;
input VAR5 ;
input VAR7;
input VAR12;
input VAR8 ;
input VAR2 ;
wire VAR10 ;
wire VAR1;
buf VAR3 (VAR10 , VAR5 );
VAR4 VAR6 (VAR1, VAR10, VAR7, VAR12);
buf VAR11 (VAR9 , VAR1 );
endmodule | apache-2.0 |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/SyncFIFOLevel.v | 18,107 | module MODULE1(
VAR6,
VAR2,
VAR45,
VAR13,
VAR8,
VAR59,
VAR39,
VAR53,
VAR31,
VAR3,
VAR70,
VAR4,
VAR1,
VAR29,
VAR20
) ;
parameter VAR27 = 1 ;
parameter VAR24 = 2 ; parameter VAR21 = 1 ;
input VAR6 ;
input VAR2 ;
input VAR13 ;
input [VAR27 -1 : 0] VAR8 ;
output VAR59 ;
input VAR45 ;
input VAR39 ;
output VAR31 ;
output [VA... | apache-2.0 |
cbakalis/vmm_boards_firmware | sources/sources_1/xadc/mdt_xadc/xadc.v | 19,357 | module MODULE1 #
(
parameter VAR131 = 10'b1001011000 )
(
input VAR38,
input rst,
input VAR45,
input VAR102,
input VAR29,
input VAR109,
input VAR93,
input VAR103,
input VAR87,
input VAR95,
input VAR25,
input VAR125,
input VAR21,
input VAR84,
input VAR140,
input VAR75,
input VAR121,
input VAR12,
input VAR91,
input VAR10,... | gpl-3.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/db/ip/niosii/submodules/niosii_pio_0.v | 2,118 | module MODULE1 (
address,
VAR4,
clk,
VAR2,
VAR6,
VAR8,
VAR3,
VAR1
)
;
output [ 7: 0] VAR3;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR4;
input clk;
input VAR2;
input VAR6;
input [ 31: 0] VAR8;
wire VAR9;
reg [ 7: 0] VAR7;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR5;
wire [ 31: 0] VAR1;
assign VAR9 = 1;
assign VAR5 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hdll__udp_dff_ps_pp_pg_n.symbol.v | 1,486 | module MODULE1 (
input VAR4 ,
output VAR7 ,
input VAR2 ,
input VAR3 ,
input VAR1,
input VAR5 ,
input VAR6
);
endmodule | apache-2.0 |
8l/connectal | verilog/GenBIBUF.v | 1,358 | module MODULE1(VAR1, VAR5);
parameter VAR2 = 1;
inout [VAR2-1:0]VAR1;
inout [VAR2-1:0]VAR5;
genvar VAR3;
generate
for(VAR3 = 0; VAR3 < VAR2; VAR3 = VAR3 + 1) begin
VAR4(.VAR5(VAR5[VAR3]), .VAR1(VAR1[VAR3]));
end
endgenerate
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3.pp.blackbox.v | 1,293 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR4,
VAR5,
VAR8 ,
VAR1
);
output VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR4;
input VAR5;
input VAR8 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b.pp.symbol.v | 1,313 | module MODULE1 (
input VAR8 ,
input VAR6 ,
input VAR3 ,
output VAR1 ,
input VAR5 ,
input VAR2,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_045.v | 1,554 | module MODULE1 (
VAR6,
VAR2
);
input [31:0] VAR6;
output [31:0]
VAR2;
wire [31:0]
VAR8,
VAR10,
VAR9,
VAR5,
VAR14,
VAR13,
VAR1,
VAR4,
VAR3,
VAR7;
assign VAR8 = VAR6;
assign VAR4 = VAR8 << 1;
assign VAR5 = VAR8 << 8;
assign VAR13 = VAR8 << 5;
assign VAR9 = VAR10 - VAR8;
assign VAR10 = VAR8 << 12;
assign VAR14 = VAR9 + VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv.blackbox.v | 1,246 | module MODULE1 (
VAR2,
VAR5
);
output VAR2;
input VAR5;
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_ic_fsm.v | 9,799 | module MODULE1(
clk, rst,
VAR18, VAR12, VAR16,
VAR8, VAR10, VAR13, VAR21, VAR11,
VAR9, VAR22, VAR3, VAR23, VAR15,
VAR14, VAR7
);
input clk;
input rst;
input VAR18;
input VAR12;
input VAR16;
input VAR8;
input VAR10;
input VAR13;
input [31:0] VAR21;
output [31:0] VAR11;
output [3:0] VAR9;
output VAR22;
output VAR3;
outpu... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_oclkdelay_cal.v | 52,217 | module MODULE1 #
(
parameter VAR10 = 100,
parameter VAR50 = 2500,
parameter VAR19 = 4,
parameter VAR99 = "VAR41",
parameter VAR147 = 8,
parameter VAR105 = 3,
parameter VAR22 = 8,
parameter VAR73 = 64,
parameter VAR8 = "VAR98",
parameter VAR13 = "VAR25"
)
(
input clk,
input rst,
input VAR60,
input VAR167,
input [5:0] VA... | mit |
sharebrained/medusa | hdl/medusa_cape/ws2812.v | 3,630 | module MODULE1
(
input VAR1,
input VAR23,
output [8:0] VAR11,
input [7:0] VAR29,
input [7:0] VAR28,
input [7:0] VAR20,
output VAR3
);
parameter VAR8 = 21; parameter VAR9 = 42; parameter VAR26 = 63; parameter VAR27 = 2600;
parameter VAR12 = 0,
VAR14 = 1;
reg [1:0] state;
parameter VAR13 = 0,
VAR22 = 1,
VAR6 = 2;
wire [1... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_0/synth/pr_region_default_mm_bridge_0.v | 4,528 | module MODULE1 #(
parameter VAR30 = 32,
parameter VAR25 = 8,
parameter VAR14 = 10,
parameter VAR2 = 1,
parameter VAR19 = 1,
parameter VAR17 = 1
) (
input wire clk, input wire VAR10, input wire [VAR30-1:0] VAR7, input wire VAR3, output wire [VAR2-1:0] VAR27, output wire [VAR30-1:0] VAR26, output wire [VAR14-1:0] VAR11, ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_rst_ps7_0_100M_1/zqynq_lab_1_design_rst_ps7_0_100M_1_stub.v | 1,877 | module MODULE1(VAR1, VAR3, VAR7,
VAR10, VAR6, VAR2, VAR5, VAR9,
VAR8, VAR4)
;
input VAR1;
input VAR3;
input VAR7;
input VAR10;
input VAR6;
output VAR2;
output [0:0]VAR5;
output [0:0]VAR9;
output [0:0]VAR8;
output [0:0]VAR4;
endmodule | mit |
monotone-RK/FACE | MCSoC-15/8-way_2-parallel/src/vivado_ip_dram/controller/mig_7series_v2_3_round_robin_arb.v | 7,553 | module MODULE1
parameter VAR15 = 100,
parameter VAR2 = 3
)
(
VAR1, VAR17,
clk, rst, req, VAR12, VAR4, VAR3
);
input clk;
input rst;
input [VAR2-1:0] req;
wire [VAR2-1:0] VAR9;
reg [VAR2*2-1:0] VAR16;
always @(VAR9)
VAR16 = {VAR9, VAR9};
reg [VAR2*2-1:0] VAR5;
always @(req) VAR5 = {req, req};
reg [VAR2-1:0] VAR6 = {VAR2... | mit |
golfit/QcmMasterController | counter.v | 7,815 | module MODULE1 (clk,VAR5,VAR1);
input clk,VAR5;
output reg [13:0] VAR1;
reg [13:0] VAR8; reg [13:0] VAR9; reg [6:0] VAR4; reg VAR2; reg reset;
parameter VAR3=35795; parameter VAR10=50;
parameter VAR7=VAR6'b10; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi_2.v | 2,542 | module MODULE2 (
VAR8 ,
VAR1 ,
VAR4 ,
VAR9 ,
VAR7 ,
VAR3 ,
VAR11 ,
VAR10,
VAR2,
VAR6 ,
VAR5
);
output VAR8 ;
input VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR7 ;
input VAR3 ;
input VAR11 ;
input VAR10;
input VAR2;
input VAR6 ;
input VAR5 ;
VAR13 VAR12 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.V... | apache-2.0 |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/UART/Receptor.v | 2,128 | module MODULE1#(
parameter VAR3=8, VAR17=16 )
(
input wire clk, reset,
input wire VAR9, VAR5,
output reg VAR11,
output wire [7:0] dout
);
localparam [1:0]
VAR12 = 2'b00,
VAR2 = 2'b01,
VAR16 = 2'b10,
VAR14 = 2'b11;
reg [1:0] VAR6=0, VAR13=0;
reg [3:0] VAR15=0, VAR4=0;
reg [2:0] VAR10=0, VAR8=0;
reg [7:0] VAR1=0, VAR7=0;... | gpl-3.0 |
Kumikomi/openreroc_posturesensor | hardware/src/SPI_IF_accel.v | 4,539 | module MODULE1(
input clk,
input rst,
input [6:0] VAR21, input [7:0] VAR9, input VAR11, input VAR19, output VAR5, output VAR14, output VAR13, output VAR6, input VAR2, output [7:0] VAR4 );
reg [7:0] VAR22; reg [7:0] VAR7;
reg [11:0] counter; reg VAR1; reg VAR17; reg VAR12; reg VAR8; reg VAR20; reg [4:0] VAR10; reg [4:0]... | bsd-3-clause |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/master_control_multi.v | 3,650 | module MODULE1
( input VAR28, input VAR27,
input wire [6:0] VAR6, input wire [31:0] VAR4, input wire VAR33,
input wire VAR29,
output VAR36, output VAR17,
output wire VAR23, output wire VAR22,
output wire VAR10, output wire VAR16,
output wire VAR25,
output wire [7:0] VAR26, output wire [7:0] VAR31,
output VAR34, output ... | gpl-3.0 |
horia141/bachelor-thesis | prj/applications/PressCount/PressCount.v | 2,568 | module MODULE1(VAR34,VAR27,reset,VAR15,VAR29,VAR40,VAR33,VAR18,VAR50,VAR22,VAR19);
input wire VAR34;
input wire VAR27;
input wire reset;
input wire VAR15;
input wire VAR29;
output wire [7:0] VAR40;
output wire VAR33;
output wire VAR18;
output wire VAR50;
output wire VAR22;
output wire VAR19;
wire [7:0] VAR20;
wire [11:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2/sky130_fd_sc_hd__or2_4.v | 2,075 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR7 ,
VAR8,
VAR6,
VAR9 ,
VAR1
);
output VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR8;
input VAR6;
input VAR9 ;
input VAR1 ;
VAR3 VAR2 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR4,
VAR5,
VAR7
);
output VAR4;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o_2.v | 2,310 | module MODULE2 (
VAR10 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR3 ,
VAR7 ,
VAR6,
VAR4
);
output VAR10 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR6;
input VAR4;
VAR8 VAR9 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODUL... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x8_128/pci_express_compiler-library/altpcie_serdes_1sgx_x1_15625.v | 19,459 | module MODULE1 (
VAR9,
VAR80,
VAR17,
VAR85,
VAR45,
VAR25,
VAR4,
VAR81,
VAR46,
VAR6,
VAR23,
VAR103,
VAR100,
VAR30,
VAR101,
VAR36,
VAR5,
VAR21,
VAR2,
VAR118);
input [0:0] VAR9;
input [0:0] VAR80;
input [0:0] VAR17;
input [0:0] VAR85;
input [0:0] VAR45;
input [0:0] VAR25;
input [0:0] VAR4;
input [0:0] VAR81;
input [0:0] V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfsbp/sky130_fd_sc_ls__sdfsbp.blackbox.v | 1,455 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR4 ,
VAR3 ,
VAR10 ,
VAR11 ,
VAR2
);
output VAR9 ;
output VAR1 ;
input VAR4 ;
input VAR3 ;
input VAR10 ;
input VAR11 ;
input VAR2;
supply1 VAR7;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/wrapper/usbSlaveCyc2Wrap_usb1t11.v | 5,632 | module MODULE1(
VAR22,
VAR4,
VAR11,
VAR39,
VAR36,
VAR13,
VAR18,
VAR1,
irq,
VAR2,
VAR12,
VAR16,
VAR7,
VAR20,
VAR3,
VAR21,
VAR17,
VAR5,
VAR9
);
input VAR22;
input VAR4;
input [7:0] VAR11;
input [7:0] VAR39;
output [7:0] VAR36;
input VAR13;
input VAR18;
output VAR1;
output irq;
input VAR2;
input VAR12 ;
input VAR16 ;
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxtp/sky130_fd_sc_hs__edfxtp.behavioral.pp.v | 1,930 | module MODULE1 (
VAR11 ,
VAR13 ,
VAR6 ,
VAR7 ,
VAR16,
VAR4
);
output VAR11 ;
input VAR13 ;
input VAR6 ;
input VAR7 ;
input VAR16;
input VAR4;
wire VAR3 ;
reg VAR5 ;
wire VAR1 ;
wire VAR14 ;
wire VAR15;
wire VAR10 ;
wire VAR9 ;
VAR2 VAR8 (VAR3 , VAR1, VAR15, VAR14, VAR5, VAR16, VAR4);
assign VAR10 = ( VAR16 === 1'b1 );
... | apache-2.0 |
jncronin/jca | cpu/cselect.v | 2,492 | module MODULE1(addr, VAR5, VAR2, VAR4, VAR8, VAR3, VAR9, VAR6, VAR7, VAR1);
input [31:0] addr;
input VAR1;
output VAR5;
output VAR2;
output VAR4;
output VAR8;
output VAR3;
output VAR9;
output VAR6;
output VAR7;
reg VAR5 = 1;
reg VAR2 = 1;
reg VAR4 = 1;
reg VAR8 = 1;
reg VAR3 = 1;
reg VAR9 = 1;
reg VAR6 = 1;
reg VAR7 = ... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/multiboot_ctrl/multiboot_ctrl.v | 3,736 | module MODULE1
(
input VAR11,
input VAR23,
input VAR10,
input [31:0] VAR16
);
localparam VAR18 = 'd0,
VAR25 = 'd1,
VAR12 = 'd2;
reg [1:0] state ;
reg VAR9;
reg [31:0] VAR26;
reg VAR20;
reg [3:0] counter;
reg VAR15;
reg VAR6;
wire [31:0] VAR2;
assign VAR2 = {2'b00,1'b1,VAR16[24],VAR16[25],3'b000,VAR16[16],VAR16[17],VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.v | 2,312 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR5 ,
VAR8,
VAR2 ,
VAR7 ,
VAR9 ,
VAR1
);
output VAR10 ;
output VAR6 ;
input VAR5 ;
input VAR8;
input VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
VAR4 VAR3 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MOD... | apache-2.0 |
horia141/bachelor-thesis | prj/components/RegBank/RegBankS2.v | 4,947 | module MODULE1(VAR9,reset,VAR7,VAR5,out);
input wire VAR9;
input wire reset;
input wire [11:0] VAR7;
input wire VAR5;
output wire [7:0] out;
reg [1:0] VAR8;
reg VAR16;
reg [7:0] VAR12;
reg [7:0] VAR6;
wire [7:0] VAR24;
wire [3:0] VAR4;
wire [7:0] VAR25;
wire VAR23;
reg [256*8-1:0] VAR3;
reg [256*8-1:0] VAR13;
assign ou... | mit |
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