repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p.behavioral.pp.v | 2,075 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR5 ,
VAR7,
VAR15 ,
VAR1 ,
VAR11,
VAR16 ,
VAR6
);
output VAR3 ;
input VAR12 ;
input VAR5 ;
input VAR7;
input VAR15 ;
input VAR1 ;
input VAR11;
input VAR16 ;
input VAR6 ;
wire VAR2 ;
wire VAR4;
wire VAR9 ;
VAR17 VAR13 (VAR2 , VAR12, VAR15, VAR1 );
VAR17 VAR14 (VAR4, VAR5, VAR7, VAR1 );
o... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/diode/sky130_fd_sc_ms__diode.behavioral.v | 1,177 | module MODULE1 (
VAR2
);
input VAR2;
supply1 VAR5;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b.functional.pp.v | 2,018 | module MODULE1 (
VAR4 ,
VAR10 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR11,
VAR14,
VAR7 ,
VAR2
);
output VAR4 ;
input VAR10 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR11;
input VAR14;
input VAR7 ;
input VAR2 ;
wire VAR1 ;
wire VAR13 ;
wire VAR15;
not VAR5 (VAR1 , VAR10 );
nand VAR6 (VAR13 , VAR8, VAR9, VAR3, VAR1 );
VAR16 VAR17... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/wb_master.v | 6,108 | module MODULE1(VAR7, VAR12, VAR8, VAR30,
VAR13, VAR17, VAR1, VAR22, VAR28, VAR29, VAR27, VAR6, VAR25, VAR15);
input VAR7;
input VAR12;
input [3:0] VAR8;
output [3:0] VAR30;
input VAR13;
output [31:0] VAR17;
output VAR1;
input [31:0] VAR22;
output [31:0] VAR28;
input VAR29;
input VAR27;
output [3:0] VAR6;
output VAR25;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22a/sky130_fd_sc_hvl__o22a.functional.v | 1,515 | module MODULE1 (
VAR1 ,
VAR10,
VAR6,
VAR3,
VAR11
);
output VAR1 ;
input VAR10;
input VAR6;
input VAR3;
input VAR11;
wire VAR5 ;
wire VAR4 ;
wire VAR7;
or VAR12 (VAR5 , VAR6, VAR10 );
or VAR9 (VAR4 , VAR11, VAR3 );
and VAR8 (VAR7, VAR5, VAR4);
buf VAR2 (VAR1 , VAR7 );
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/wb_conmax/wb_conmax_rf.v | 11,883 | module MODULE1(
VAR43, VAR39,
VAR23, VAR21, VAR35, VAR1, VAR4, VAR42,
VAR13, VAR38, VAR46, VAR8,
VAR19, VAR28, VAR29, VAR17, VAR3, VAR45,
VAR33, VAR6, VAR7, VAR26,
VAR2, VAR15, VAR20, VAR16, VAR24, VAR36, VAR31, VAR22,
VAR44, VAR34, VAR41, VAR27, VAR14, VAR9, VAR12, VAR30
);
parameter [3:0] VAR32 = 4'hf;
parameter VAR3... | gpl-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/altera_up_audio_out_serializer.v | 7,591 | module MODULE1 (
clk,
reset,
VAR7,
VAR17,
VAR32,
VAR23,
VAR8,
VAR22,
VAR30,
VAR34,
VAR18,
VAR5,
VAR27
);
parameter VAR2 = 15;
input clk;
input reset;
input VAR7;
input VAR17;
input VAR32;
input VAR23;
input [VAR2: 0] VAR8;
input VAR22;
input [VAR2: 0] VAR30;
input VAR34;
output reg [ 7: 0] VAR18;
output reg [ 7: 0] VAR... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/altera/ad_xcvr_rx_rst.v | 10,035 | module MODULE1 (
VAR3,
VAR43,
VAR41,
VAR17,
VAR21,
VAR42,
VAR38,
VAR20,
VAR33,
VAR4);
parameter VAR24 = 4;
parameter VAR2 = 8;
parameter VAR18 = 8;
parameter VAR26 = 5;
parameter VAR12 = 12;
localparam VAR22 = 4'h0;
localparam VAR32 = 4'h1;
localparam VAR1 = 4'h2;
localparam VAR6 = 4'h3;
localparam VAR19 = 4'h4;
localp... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/request_generator.v | 3,740 | module MODULE1 (
input VAR2,
input VAR4,
output [VAR14-1:0] VAR11,
input [VAR14-1:0] VAR9,
input VAR12,
output reg VAR6,
input [VAR3-1:0] VAR15,
input enable,
input VAR7,
output VAR8
);
parameter VAR14 = 3;
parameter VAR3 = 17;
reg [VAR3-1:0] VAR5 = 'h00;
reg [VAR14-1:0] VAR1;
wire [VAR14-1:0] VAR13 = VAR10(VAR1);
assi... | gpl-3.0 |
maijohnson/comp3601_blue_15s2 | AudioController/duration_lut.v | 1,350 | module MODULE1 (input [3:0] VAR8, output [15:0] VAR10);
parameter
VAR1 = 16'd48000, VAR3 = 16'd24000, VAR13 = 16'd18000, VAR6 = 16'd12000, VAR4 = 16'd9000, VAR9 = 16'd6000, VAR12 = 16'd4500, VAR5 = 16'd3000, VAR7 = 16'd2000, VAR11 = 16'd1500, VAR2 = 16'd1000;
assign VAR10 = (VAR8 == 4'd1) ? VAR11 :
(VAR8 == 4'd2) ? VAR... | mit |
eSedano/vrudy | rtl/dpth_br_cnd.v | 3,345 | module MODULE1 (
input wire VAR2,
output wire VAR5,
output wire [2:0] VAR3,
output reg VAR4
);
always @(*)
begin: VAR1
case (VAR3)
3'b000:
VAR4 = 1'b1;
3'b001:
VAR4 = VAR2;
3'b010:
VAR4 = VAR5;
3'b011:
VAR4 = VAR5 | VAR2;
3'b100:
VAR4 = 1'b0;
3'b101:
VAR4 = ~VAR2;
3'b110:
VAR4 = ~VAR5;
3'b111:
VAR4 = ~(VAR5 | VAR2);
en... | mit |
SiLab-Bonn/basil | basil/firmware/modules/spi/spi_core.v | 7,199 | module MODULE1 #(
parameter VAR33 = 16,
parameter VAR31 = 16
) (
input wire VAR11,
input wire VAR82,
input wire [VAR33-1:0] VAR74,
input wire [7:0] VAR57,
input wire VAR55,
input wire VAR50,
output reg [7:0] VAR41,
input wire VAR61,
output wire VAR40,
input wire VAR23,
output reg VAR63,
input wire VAR56,
output reg VAR... | bsd-3-clause |
AbhishekShah212/School_Projects | ELEN232/pset6/CLA_Adder.v | 1,624 | module MODULE1 (
input [3:0] VAR17,
input [3:0] VAR14,
input VAR1,
output [3:0] VAR11,
output VAR10
);
wire [2:0] VAR8;
wire [2:0] VAR3;
wire [3:0] VAR5;
assign VAR8[0] = VAR17[0] & (VAR14[0] ^ VAR1);
assign VAR3[0] = VAR17[0] ^ (VAR14[0] ^ VAR1);
assign VAR8[1] = VAR17[1] & VAR14[1] ^ VAR1;
assign VAR3[1] = VAR17[1] ^... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o.pp.symbol.v | 1,431 | module MODULE1 (
input VAR10 ,
input VAR3 ,
input VAR8 ,
input VAR4 ,
input VAR9 ,
output VAR2 ,
input VAR6 ,
input VAR7,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
cliffordwolf/yosys | techlibs/ice40/abc9_model.v | 3,612 | module \VAR11 (
output VAR14,
output VAR15,
input VAR5, VAR2,
input VAR4,
input VAR1, VAR9
);
parameter VAR10 = 0;
parameter VAR18 = 0;
wire VAR12 = VAR18 ? VAR4 : VAR9;
VAR16 VAR17 (
.VAR1(VAR5),
.VAR3(VAR2),
.VAR4(VAR4),
.VAR14(VAR14)
);
VAR13 #(
.VAR6(VAR10)
) VAR8 (
.VAR1(VAR1),
.VAR3(VAR5),
.VAR7(VAR2),
.VAR9(VAR1... | isc |
jotego/jt12 | hdl/jt12_pg_inc.v | 1,687 | module MODULE1 (
input [ 2:0] VAR1,
input [10:0] VAR4,
input signed [8:0] VAR5,
output reg [16:0] VAR2
);
reg [11:0] VAR3;
always @(*) begin
VAR3 = {VAR4,1'b0} + {{3{VAR5[8]}},VAR5};
case ( VAR1 )
3'd0: VAR2 = { 7'd0, VAR3[11:2] };
3'd1: VAR2 = { 6'd0, VAR3[11:1] };
3'd2: VAR2 = { 5'd0, VAR3[11:0] };
3'd3: VAR2 = { 4'd... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbn/sky130_fd_sc_ms__sdfbbn.pp.blackbox.v | 1,558 | module MODULE1 (
VAR6 ,
VAR11 ,
VAR3 ,
VAR2 ,
VAR10 ,
VAR5 ,
VAR8 ,
VAR12,
VAR4 ,
VAR9 ,
VAR7 ,
VAR1
);
output VAR6 ;
output VAR11 ;
input VAR3 ;
input VAR2 ;
input VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR12;
input VAR4 ;
input VAR9 ;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
sabertazimi/hust-lab | digitalLogic/design/clock_design/src/bcd_to_segment.v | 1,085 | module MODULE1
(
input [3:0] VAR1,
output reg [7:0] VAR2
);
always @(VAR1) begin
case (VAR1)
4'b0000: VAR2 <= 8'b11000000; 4'b0001: VAR2 <= 8'b11111001; 4'b0010: VAR2 <= 8'b10100100; 4'b0011: VAR2 <= 8'b10110000; 4'b0100: VAR2 <= 8'b10011001; 4'b0101: VAR2 <= 8'b10010010; 4'b0110: VAR2 <= 8'b10000010; 4'b0111: VAR2 <= ... | mit |
mammenx/pegasus | wxp/dgn/rtl/l2/mac/peg_l2_fcs_gen.v | 3,233 | module MODULE1 #(
parameter VAR6 = 8,
parameter VAR2 = 32'd0
)
(
input clk,
input VAR5,
input VAR10,
input VAR3,
input [VAR6-1:0] VAR7,
output [31:0] VAR8
);
reg [31:0] VAR9;
genvar VAR1;
always@(posedge clk, negedge VAR5)
begin
if(~VAR5)
begin
VAR9 <= VAR2;
end
else
begin
if(VAR10)
begin
VAR9 <= VAR2;
end
else if(VAR3... | gpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_dc2.v | 8,036 | module MODULE1 (
VAR23,
VAR16
);
parameter VAR8 = 16'h000C;
parameter VAR17 = 16'h001E;
parameter VAR19 = 16'h0400;
parameter VAR14 = 16'h0500;
parameter VAR5 = 16'h0088; parameter VAR4 = 16'h0019; parameter VAR3 = 16'h00C6;
parameter VAR1 = 16'h0019;
parameter VAR15 = 16'h0432;
parameter VAR11 = 16'h0011;
parameter VA... | mit |
alexforencich/verilog-ethernet | example/fb2CG/fpga_10g/rtl/fpga.v | 23,060 | module MODULE1 (
input wire VAR42,
output wire VAR261,
output wire VAR312,
output wire VAR267,
output wire [1:0] VAR194,
output wire [1:0] VAR280,
input wire [1:0] VAR163,
output wire VAR41,
output wire VAR209,
input wire VAR292,
input wire VAR109,
output wire VAR90,
output wire VAR72,
input wire VAR164,
input wire VAR... | mit |
kylemsguy/FPGA-Litecoin-Miner | experimental/DE2-115-SLOWSIXTEEN/ltcminer.v | 7,404 | module MODULE1 (VAR15); else
module MODULE1 (VAR15, VAR52);
parameter VAR67 = VAR67;
parameter VAR67 = 25;
parameter VAR3 = VAR3;
parameter VAR3 = 1;
function integer VAR11; input integer VAR54;
begin
VAR54 = VAR54-1;
for (VAR11=0; VAR54>0; VAR11=VAR11+1)
VAR54 = VAR54>>1;
end
endfunction
parameter VAR27 = VAR27; else
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtn/sky130_fd_sc_lp__sdfrtn.symbol.v | 1,508 | module MODULE1 (
input VAR7 ,
output VAR10 ,
input VAR6,
input VAR8 ,
input VAR9 ,
input VAR4
);
supply1 VAR5;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_regslice.v | 5,444 | module MODULE1
parameter VAR19 = 64,
parameter VAR14 = 64,
parameter VAR2 = 3 ,
parameter VAR9 = 2
)
(
input [VAR19-1:0 ] din ,
output [VAR19-1:0 ] dout ,
output [VAR19-1:0 ] VAR10 ,
input [VAR14-1:0] VAR8 ,
output [VAR14-1:0] VAR13 ,
output VAR15 ,
output reg VAR4,
output VAR11 ,
input clk ,
input reset
);
reg [VAR19-... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.pp.symbol.v | 1,230 | module MODULE1 (
input VAR2 ,
input VAR1 ,
output VAR4 ,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr.behavioral.v | 1,493 | module MODULE1 (
VAR8,
VAR1
);
output VAR8;
input VAR1;
supply1 VAR9 ;
supply0 VAR3 ;
supply1 VAR4;
supply1 VAR6 ;
supply0 VAR10 ;
wire VAR7;
buf VAR5 (VAR7, VAR1 );
buf VAR2 (VAR8 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn_1.v | 2,686 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR9 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR2 ,
VAR4,
VAR8 ,
VAR10
);
output VAR3 ;
output VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR11 ;
input VAR1 ;
input VAR2 ;
input VAR4;
input VAR8 ;
input VAR10 ;
VAR12 VAR5 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn_0.v | 2,150 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR4,
VAR6,
VAR3,
VAR9 ,
VAR5
);
output VAR7 ;
input VAR2 ;
input VAR4;
input VAR6;
input VAR3;
input VAR9 ;
input VAR5 ;
VAR8 VAR1 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7 ,
VAR2 ,
VAR4
);
output VAR7 ;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.functional.v | 1,664 | module MODULE1( VAR13, VAR17, VAR9, VAR1, VAR16, VAR11 );
input VAR1, VAR9, VAR13, VAR17, VAR11;
output VAR16;
wire VAR21;
not VAR20( VAR21, VAR9 );
wire VAR22;
not VAR14( VAR22, VAR13 );
wire VAR7;
and VAR10( VAR7, VAR21, VAR22 );
wire VAR6;
not VAR12( VAR6, VAR17 );
wire VAR2;
and VAR8( VAR2, VAR21, VAR6 );
wire VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a.behavioral.pp.v | 2,156 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR6 ,
VAR15 ,
VAR9 ,
VAR19,
VAR8,
VAR13 ,
VAR18
);
output VAR1 ;
input VAR10 ;
input VAR6 ;
input VAR15 ;
input VAR9 ;
input VAR19;
input VAR8;
input VAR13 ;
input VAR18 ;
wire VAR11 ;
wire VAR17 ;
wire VAR7 ;
wire VAR3;
or VAR2 (VAR11 , VAR6, VAR10 );
or VAR14 (VAR17 , VAR9, VAR15 );
a... | apache-2.0 |
vkchettimada/aayudha | mojo/src/serial_tx.v | 2,895 | module MODULE1 #(
parameter VAR18 = 50
)(
input clk,
input rst,
output VAR5,
input VAR11,
output VAR3,
input [7:0] VAR20,
input VAR15
);
parameter VAR10 = VAR16(VAR18);
localparam VAR13 = 2;
localparam VAR17 = 2'd0,
VAR27 = 2'd1,
VAR24 = 2'd2,
VAR22 = 2'd3;
reg [VAR10-1:0] VAR25, VAR8;
reg [2:0] VAR9, VAR1;
reg [7:0] V... | mit |
cr88192/bgbtech_bjx1core | smalltst/compdec/FbNtMod_0.v | 17,924 | module MODULE1(VAR84, reset, VAR57,
VAR14, VAR39, VAR40, VAR24, VAR97);
input VAR84;
input reset;
output[3:0] VAR57;
input[39:0] VAR14;
inout[31:0] VAR39;
input VAR40;
input VAR24;
output VAR97;
reg[7:0] VAR110[31:0];
reg VAR50; reg[31:0] VAR88; wire VAR19;
assign VAR97 = (VAR40 && VAR19) ? VAR50 : 1'VAR29;
assign VAR3... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/bsg_source_sync_channel_control_slave.v | 12,877 | module MODULE1 #( parameter VAR39(VAR13 )
, VAR29 = "VAR5")
( input VAR45
, input VAR43
, output reg VAR1
, output VAR48
, output [VAR13+1-1:0] VAR18
, input [VAR13+1-1:0] VAR40
, input VAR28
, output VAR23
, output VAR32
, output logic VAR12
, input VAR27 , output VAR31
, output VAR49
);
wire [4:0] VAR4;
wire VAR52;
w... | bsd-3-clause |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_int_mult64s.v | 5,288 | module MODULE1 (
enable,
VAR11,
VAR4,
VAR9,
VAR1);
parameter VAR2 = 64;
parameter VAR10 = 64;
localparam VAR6 = VAR2 < 64 ? VAR2 + 1 : VAR2;
localparam VAR12 = VAR10 < 64 ? VAR10 + 1 : VAR10;
input enable;
input VAR11;
input [VAR6 - 1 : 0] VAR4;
input [VAR12 - 1 : 0] VAR9;
output reg [63:0] VAR1;
reg [VAR6 - 1 : 0] VAR... | mit |
MarcoVogt/basil | firmware/modules/fast_spi_rx/fast_spi_rx.v | 1,704 | module MODULE1
parameter VAR6 = 16'h0000,
parameter VAR12 = 16'h0000,
parameter VAR7 = 16,
parameter VAR14 = 4'b0001
)(
input wire VAR27,
input wire [VAR7-1:0] VAR20,
inout wire [7:0] VAR5,
input wire VAR25,
input wire VAR3,
input wire VAR21,
input wire VAR1,
input wire VAR19,
input wire VAR4,
input wire VAR13,
output ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd/sky130_fd_sc_ms__tapvgnd.functional.v | 1,097 | module MODULE1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi.pp.blackbox.v | 1,405 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR2 ,
VAR5,
VAR9,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR5;
input VAR9;
input VAR8 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrbp/sky130_fd_sc_hs__dfrbp_1.v | 2,298 | module MODULE1 (
VAR5,
VAR7 ,
VAR3 ,
VAR2 ,
VAR8 ,
VAR9 ,
VAR6
);
input VAR5;
input VAR7 ;
input VAR3 ;
output VAR2 ;
output VAR8 ;
input VAR9 ;
input VAR6 ;
VAR4 VAR1 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR5,
VAR7 ,
VAR3 ,
VAR2 ,
VAR... | apache-2.0 |
azonenberg/antikernel-ipcores | graphics/display/SSD1306.v | 19,053 | module MODULE1 #(
parameter VAR14 = "VAR7" ) (
input wire clk, input wire[15:0] VAR2,
output reg VAR12 = 0, output reg VAR15 = 1, output reg VAR9 = 1,
output wire VAR8, output wire VAR4,
output reg VAR13 = 1,
output reg VAR11 = 0,
input wire VAR17, input wire VAR6, input wire VAR5,
output wire ready,
output reg VAR10 =... | bsd-3-clause |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/bd_0/ip/ip_4/synth/bd_c3fe_slot_0_b_0.v | 4,558 | module MODULE1 (
VAR68,
VAR57,
dout
);
input wire [0 : 0] VAR68;
input wire [0 : 0] VAR57;
output wire [1 : 0] dout;
VAR18 #(
.VAR54(1),
.VAR59(1),
.VAR36(1),
.VAR17(1),
.VAR10(1),
.VAR48(1),
.VAR39(1),
.VAR65(1),
.VAR41(1),
.VAR67(1),
.VAR31(1),
.VAR62(1),
.VAR23(1),
.VAR2(1),
.VAR14(1),
.VAR8(1),
.VAR33(1),
.VAR55(1)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi.behavioral.v | 1,572 | module MODULE1 (
VAR9 ,
VAR5,
VAR13,
VAR4,
VAR8,
VAR6
);
output VAR9 ;
input VAR5;
input VAR13;
input VAR4;
input VAR8;
input VAR6;
supply1 VAR11;
supply0 VAR15;
supply1 VAR14 ;
supply0 VAR7 ;
wire VAR2 ;
wire VAR12;
and VAR1 (VAR2 , VAR5, VAR13, VAR4, VAR8 );
nor VAR3 (VAR12, VAR6, VAR2 );
buf VAR10 (VAR9 , VAR12 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_1.v | 2,163 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3,
VAR7,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR2 ;
input VAR3;
input VAR7;
input VAR6 ;
input VAR8 ;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR3;
supply0 VAR7;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a_2.v | 2,348 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR6 ,
VAR4 ,
VAR10 ,
VAR7,
VAR1,
VAR9 ,
VAR11
);
output VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR4 ;
input VAR10 ;
input VAR7;
input VAR1;
input VAR9 ;
input VAR11 ;
VAR8 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VA... | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/usb_tx_data.v | 1,724 | module MODULE1
(input VAR5,
input [7:0] VAR25,
input VAR34,
output [7:0] VAR7,
output VAR8);
localparam VAR30 = 4'd0;
localparam VAR33 = 4'd1;
localparam VAR28 = 4'd2;
localparam VAR23 = 4'd3;
localparam VAR24 = 4'd4;
localparam VAR31 = 4'd5;
localparam VAR3=4, VAR27=5;
reg [VAR27+VAR3-1:0] VAR18;
wire [VAR3-1:0] state... | apache-2.0 |
CospanDesign/vivado-ip-cores | ip/axi_on_screen_display/console_osd.v | 16,230 | (VAR56 <= 2) ? 1 : \
(VAR56 <= 4) ? 2 : \
(VAR56 <= 8) ? 3 : \
(VAR56 <= 16) ? 4 : \
(VAR56 <= 32) ? 5 : \
(VAR56 <= 64) ? 6 : \
(VAR56 <= 128) ? 7 : \
(VAR56 <= 256) ? 8 : \
(VAR56 <= 512) ? 9 : \
(VAR56 <= 1024) ? 10: \
(VAR56 <= 2048) ? 11 : \
(VAR56 <= 4096) ? 12 : \
-1
module MODULE1 #(
parameter VAR6 = 12,
parame... | mit |
peteasa/oh | src/elink/hdl/etx_clocks.v | 8,409 | module MODULE1 (
VAR100, VAR50, VAR28, VAR18, VAR111, VAR87,
VAR51, VAR112, VAR35,
VAR126, VAR124, VAR120
);
parameter VAR73 = 100;
parameter VAR26 = 300;
parameter VAR8 = 600;
parameter VAR98 = 90; parameter VAR132 = VAR143;
parameter VAR86 = 4; else
parameter VAR86 = 8; VAR39
parameter VAR19 = 12; localparam real VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b.behavioral.pp.v | 2,015 | module MODULE1 (
VAR12 ,
VAR9 ,
VAR14 ,
VAR6 ,
VAR15,
VAR8,
VAR11 ,
VAR5
);
output VAR12 ;
input VAR9 ;
input VAR14 ;
input VAR6 ;
input VAR15;
input VAR8;
input VAR11 ;
input VAR5 ;
wire VAR7 ;
wire VAR13 ;
wire VAR10;
nor VAR2 (VAR7 , VAR9, VAR14 );
and VAR3 (VAR13 , VAR6, VAR7 );
VAR4 VAR1 (VAR10, VAR13, VAR15, VAR8... | apache-2.0 |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v | 1,158 | module MODULE1
VAR10 = 32,
VAR1 = 32,
VAR6 = 32,
VAR8 = 16, VAR9 = 32,
VAR2 = 8,
VAR7 = 1,
VAR3 = 8,
VAR5 = 1,
VAR4 = 1
) (
);
endmodule | mit |
Pylonight/MIPS-CPU | cpu/Control_Unit.v | 11,144 | module MODULE1(
output reg VAR5,
output reg VAR59,
output reg VAR57,
output reg VAR56,
output reg VAR31,
output reg VAR69,
output reg VAR6,
output reg [3 : 0] VAR13,
output reg [2 : 0] VAR21,
output reg [7 : 0] VAR10,
output reg VAR73,
output reg VAR70,
output reg [1 : 0] VAR17,
output reg VAR7,
output reg VAR66,
outpu... | gpl-2.0 |
kristianpaul/milkyminer | cores/fpgaminer/rtl/serial.v | 3,044 | module MODULE1(clk, VAR13, VAR1, VAR8);
input clk;
input VAR13;
wire VAR7;
wire [7:0] VAR11;
VAR15 VAR2(.clk(clk), .VAR13(VAR13), .VAR7(VAR7), .VAR11(VAR11));
output [255:0] VAR1;
output [255:0] VAR8;
reg [511:0] VAR19;
reg [511:0] VAR9;
reg [6:0] VAR17 = 7'b0000000;
assign VAR1 = VAR9[511:256];
assign VAR8 = VAR9[255:... | lgpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_lut_tc.v | 2,005 | module MODULE1( VAR1,VAR4,VAR2 );
input [5:0] VAR1 ;
input VAR4 ;
output [4:0] VAR2 ;
reg [4:0] VAR2 ;
wire [5:0] VAR3 = VAR1 + {VAR4,1'b0};
always @(VAR3) begin
case(VAR3)
'd18: VAR2 = 5'd1 ;
'd19: VAR2 = 5'd1 ;
'd20: VAR2 = 5'd1;
'd21: VAR2 = 5'd1;
'd22: VAR2 = 5'd1;
'd23: VAR2 = 5'd1;
'd24: VAR2 = 5'd1;
'd25: VAR2 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtn/sky130_fd_sc_ls__dfrtn.behavioral.pp.v | 2,391 | module MODULE1 (
VAR17 ,
VAR15 ,
VAR1 ,
VAR2,
VAR11 ,
VAR20 ,
VAR9 ,
VAR12
);
output VAR17 ;
input VAR15 ;
input VAR1 ;
input VAR2;
input VAR11 ;
input VAR20 ;
input VAR9 ;
input VAR12 ;
wire VAR23 ;
wire VAR10 ;
wire VAR6 ;
reg VAR13 ;
wire VAR4 ;
wire VAR16;
wire VAR21 ;
wire VAR5 ;
wire VAR3 ;
wire VAR7 ;
not VAR14 ... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v | 1,206 | module MODULE1 #(parameter VAR20(VAR8)
,parameter VAR20(VAR14)
,parameter VAR4=0
,parameter VAR6=VAR15(VAR14)
,parameter VAR5=0)
(
input VAR7
,input VAR9
,input VAR10
,input [VAR6-1:0] VAR1
,input [VAR17(VAR8, 1):0] VAR16
,input VAR11
,input [VAR6-1:0] VAR18
,output logic [VAR17(VAR8, 1):0] VAR22
);
wire VAR12 = VAR9;
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a.blackbox.v | 1,339 | module MODULE1 (
VAR7 ,
VAR3,
VAR8,
VAR1,
VAR2
);
output VAR7 ;
input VAR3;
input VAR8;
input VAR1;
input VAR2;
supply1 VAR6;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha_1.v | 2,184 | module MODULE1 (
VAR4,
VAR1 ,
VAR7 ,
VAR5 ,
VAR2,
VAR9,
VAR6 ,
VAR8
);
output VAR4;
output VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR2;
input VAR9;
input VAR6 ;
input VAR8 ;
VAR3 VAR10 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
... | apache-2.0 |
hightoon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/tx_trn_sm.v | 35,135 | module MODULE1(
input clk,
input VAR42,
input VAR87,
output VAR91,
input [63:0] VAR77,
output VAR51,
input VAR83,
input [63:0] VAR94,
output VAR29,
input VAR5,
input [63:0] VAR80,
input VAR18,
output VAR15,
output reg VAR19,
input [63:0] VAR35,
input VAR62,
output reg[11:0] VAR82, input [31:0] VAR7,
output reg [63:0] V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd.behavioral.pp.v | 1,200 | module MODULE1 (
VAR1,
VAR2,
VAR4 ,
VAR3
);
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
walkthetalk/fsref | ip/window_broadcaster/src/window_broadcaster.v | 3,085 | module MODULE1 #
(
parameter integer VAR54 = 12,
parameter integer VAR30 = 12,
parameter integer VAR36 = 32,
parameter integer VAR58 = 1
)
(
input wire [VAR30-1 : 0] VAR6,
input wire [VAR30-1 : 0] VAR16,
input wire [VAR54-1 : 0] VAR9,
input wire [VAR54-1 : 0] VAR32,
input wire [VAR36-1 : 0] VAR50,
output wire [VAR30-1 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3.functional.v | 1,759 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR5,
VAR7
);
output VAR9 ;
input VAR10 ;
input VAR5;
input VAR7;
wire VAR6 ;
wire VAR3;
not VAR2 (VAR6 , VAR10 );
VAR4 VAR8 (VAR3, VAR6, VAR5, VAR7);
buf VAR1 (VAR9 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b.functional.v | 1,409 | module MODULE1 (
VAR8 ,
VAR2,
VAR5 ,
VAR4
);
output VAR8 ;
input VAR2;
input VAR5 ;
input VAR4 ;
wire VAR9 ;
wire VAR7;
not VAR3 (VAR9 , VAR2 );
nand VAR1 (VAR7, VAR5, VAR9, VAR4 );
buf VAR6 (VAR8 , VAR7 );
endmodule | apache-2.0 |
MeshSr/onetswitch20 | ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/udp/op_lut_regs.v | 11,040 | module MODULE1
parameter VAR65 = 4,
parameter VAR13 = 2
)
(
input VAR33,
input VAR69,
input VAR71,
input [VAR6-1:0] VAR85,
input [VAR36-1:0] VAR39,
input [VAR13-1:0] VAR3,
output reg VAR68,
output reg VAR72,
output reg VAR20,
output reg [VAR6-1:0] VAR48,
output reg [VAR36-1:0] VAR22,
output reg [VAR13-1:0] VAR74,
outpu... | lgpl-2.1 |
rurume/openrisc_vision_hardware | ISE/or1200_spram_64x14.v | 10,655 | module MODULE1(
VAR53, VAR54, VAR1,
clk, rst, VAR4, VAR2, VAR28, addr, VAR16, VAR52
);
parameter VAR32 = 6;
parameter VAR14 = 14;
input VAR53;
input [VAR6 - 1:0] VAR1;
output VAR54;
input clk; input rst; input VAR4; input VAR2; input VAR28; input [VAR32-1:0] addr; input [VAR14-1:0] VAR16; output [VAR14-1:0] VAR52;
wire... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah.behavioral.v | 1,744 | module MODULE1 (
VAR16,
VAR12 ,
VAR2 ,
VAR7 ,
VAR15
);
output VAR16;
output VAR12 ;
input VAR2 ;
input VAR7 ;
input VAR15 ;
supply1 VAR19;
supply0 VAR20;
supply1 VAR14 ;
supply0 VAR6 ;
wire VAR11;
wire VAR17 ;
wire VAR4 ;
wire VAR13 ;
wire VAR21;
xor VAR1 (VAR11, VAR2, VAR7, VAR15 );
buf VAR5 (VAR12 , VAR11 );
and VAR3... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_vuadcol_dp.v | 6,581 | module MODULE1
(
VAR17,
VAR19, VAR16, VAR25, VAR15, VAR4
) ;
input [103:0] VAR19; input [103:0] VAR4;
input [3:0] VAR16; input [3:0] VAR25; input VAR15;
output [25:0] VAR17;
wire [25:0] VAR29;
wire [25:0] VAR14;
wire [25:0] VAR10;
wire [25:0] VAR27;
wire [25:0] VAR28;
wire [25:0] VAR2;
wire [25:0] VAR7;
wire [25:0] VAR... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/ModulosBasicos/PruebasFPGA/divisorprueba/conmutacion.v | 1,067 | module MODULE1
(
input [3:0] VAR1,
input [3:0] VAR2,
input [3:0] VAR5,
input VAR11,
input VAR4,
input VAR3,
input VAR10,
output reg [1:0] VAR8,
output reg [3:0] VAR6
);
reg VAR7;
reg [1:0] VAR9;
begin
begin
begin
end
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
begin | gpl-3.0 |
GLADICOS/UART | rtl/uart_rx.v | 3,543 | module MODULE1#(
parameter integer VAR17 = 12
)
(
input VAR13,
input VAR15,
input VAR7,
input [11:0] VAR9,
output reg [7:0] VAR6,
output reg VAR18,
output VAR16
);
localparam [3:0] VAR11 = 4'b0000,
VAR10 = 4'b0001,
VAR3 = 4'b0010,
VAR14 = 4'b0100,
VAR8 = 4'b1000;
reg [3:0] VAR2;
reg [3:0] VAR12;
reg [VAR17-1:0] VAR5;
r... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_mux_4to2/sky130_fd_sc_ms__udp_mux_4to2.symbol.v | 1,327 | module MODULE1 (
input VAR4,
input VAR5,
input VAR2,
input VAR6,
output VAR7 ,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b.functional.v | 1,356 | module MODULE1 (
VAR4 ,
VAR8,
VAR1
);
output VAR4 ;
input VAR8;
input VAR1 ;
wire VAR3 ;
wire VAR6;
not VAR2 (VAR3 , VAR1 );
or VAR5 (VAR6, VAR3, VAR8 );
buf VAR7 (VAR4 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.blackbox.v | 1,441 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR3 ,
VAR6 ,
VAR4,
VAR1 ,
VAR2
);
output VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR6 ;
input VAR4;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.pp.blackbox.v | 1,263 | module MODULE1 (
VAR1,
VAR2,
VAR4 ,
VAR3
);
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/Arty/fpga/rtl/debounce_switch.v | 2,576 | module MODULE1 #(
parameter VAR4=1, parameter VAR2=3, parameter VAR5=125000 )(
input wire clk,
input wire rst,
input wire [VAR4-1:0] in,
output wire [VAR4-1:0] out
);
reg [23:0] VAR1 = 24'd0;
reg [VAR2-1:0] VAR6[VAR4-1:0];
reg [VAR4-1:0] state;
assign out = state;
integer VAR3;
always @(posedge clk or posedge rst) begi... | mit |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkTop_HW_Side.v | 11,128 | module MODULE1(VAR72,
VAR102);
input VAR72;
input VAR102;
reg VAR96;
wire VAR79, VAR20;
reg [11 : 0] VAR106;
wire [11 : 0] VAR104;
wire VAR90;
wire [352 : 0] VAR50;
wire [255 : 0] VAR38;
wire VAR9,
VAR81,
VAR74,
VAR59;
wire [352 : 0] VAR5;
wire [255 : 0] VAR17;
wire [63 : 0] VAR95,
VAR105;
wire [7 : 0] VAR43,
VAR18,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a.blackbox.v | 1,373 | module MODULE1 (
VAR3 ,
VAR6,
VAR5,
VAR4,
VAR9,
VAR2
);
output VAR3 ;
input VAR6;
input VAR5;
input VAR4;
input VAR9;
input VAR2;
supply1 VAR10;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21o/sky130_fd_sc_hs__a21o.functional.v | 1,913 | module MODULE1 (
VAR10,
VAR6,
VAR11 ,
VAR12 ,
VAR8 ,
VAR3
);
input VAR10;
input VAR6;
output VAR11 ;
input VAR12 ;
input VAR8 ;
input VAR3 ;
wire VAR2 ;
wire VAR14 ;
wire VAR4;
and VAR7 (VAR2 , VAR12, VAR8 );
or VAR9 (VAR14 , VAR2, VAR3 );
VAR13 VAR5 (VAR4, VAR14, VAR10, VAR6);
buf VAR1 (VAR11 , VAR4 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_ecl_eccctl.v | 10,186 | module MODULE1 (
VAR67, VAR55, VAR101,
VAR93, VAR25, VAR52,
VAR94, VAR81, VAR35,
VAR37, VAR5, VAR34,
VAR53, VAR71, VAR105,
VAR36, VAR64, VAR77,
clk, VAR29, VAR65, VAR99, VAR43,
VAR31, VAR90, VAR79, VAR4,
VAR16, VAR73,
VAR62, VAR104, VAR17, VAR27,
VAR24, VAR7, VAR96, VAR72,
VAR30, VAR50, VAR63,
VAR66, VAR38, VAR33,
VAR8... | gpl-2.0 |
thinkoco/de1_soc_opencl | de10_nano_sharedonly_hdmi/ip/i2c/I2C_WRITE_WDATA.v | 2,365 | module MODULE1 (
input VAR13 ,
input VAR4,
input VAR7,
input [15:0] VAR12,
input [7:0] VAR10,
input VAR14,
output reg VAR15,
output reg VAR6,
output reg VAR2,
output reg [7:0] VAR8 ,
output reg [7:0] VAR11,
output reg [7:0] VAR3,
output reg VAR9,
input [7:0] VAR5 );
reg [8:0]VAR16 ;
reg [7:0]VAR1 ;
always @( negedge VA... | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_sb.v | 6,640 | module MODULE1(
clk, rst,
VAR24, VAR36, VAR19, VAR29, VAR25, VAR7, VAR20,
VAR11, VAR33, VAR31,
VAR28, VAR15, VAR12, VAR27, VAR38, VAR40, VAR16,
VAR37, VAR2, VAR1
);
parameter VAR17 = VAR18;
parameter VAR10 = VAR18;
input clk; input rst;
input [VAR17-1:0] VAR24; input [VAR10-1:0] VAR36; input VAR19; input VAR29; input V... | gpl-2.0 |
Xilinx/PYNQ | boards/ip/color_swap_1.1/color_swap.v | 1,426 | module MODULE1(
VAR10,
VAR6,
VAR5,
VAR2,
VAR1,
VAR8,
VAR3,
VAR4
);
parameter VAR7 = "VAR12";
parameter VAR13 = "VAR9";
input VAR10;
output VAR6;
input VAR3;
output VAR4;
input [23:0]VAR5;
output [23:0]VAR2;
input VAR1;
output VAR8;
wire [23:0]VAR11;
assign VAR6 = VAR10;
assign VAR4 = VAR3;
assign VAR8 = VAR1;
if (VAR7 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufinv/sky130_fd_sc_hd__bufinv.symbol.v | 1,272 | module MODULE1 (
input VAR1,
output VAR2
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222o/sky130_fd_sc_ms__a222o.pp.symbol.v | 1,419 | module MODULE1 (
input VAR10 ,
input VAR7 ,
input VAR5 ,
input VAR11 ,
input VAR3 ,
input VAR9 ,
output VAR6 ,
input VAR2 ,
input VAR4,
input VAR1,
input VAR8
);
endmodule | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/picosoc_wrappers/picosoc_wrap.v | 1,405 | module MODULE1 (
input clk,
output VAR21,
input VAR8,
input [15:0] VAR3,
output [15:0] VAR2
);
wire VAR16;
VAR13 VAR18 (.VAR24(clk), .VAR7(VAR16));
reg [5:0] VAR5 = 0;
wire VAR22 = &VAR5;
always @(posedge VAR16) begin
VAR5 <= VAR5 + !VAR22;
end
wire VAR19;
reg VAR23;
wire [3:0] VAR15;
wire [31:0] VAR20;
wire [31:0] VAR... | isc |
sabertazimi/hust-lab | architecture/design/fpga/src/led_unit.v | 1,985 | module MODULE1
(
input VAR3,
input [(VAR4-1):0] VAR7,
output reg [7:0] VAR6,
output reg [7:0] VAR1
);
reg [2:0] VAR5; wire [(VAR4*2)-1:0] VAR2; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isobufsrc/sky130_fd_sc_lp__isobufsrc.functional.pp.v | 2,044 | module MODULE1 (
VAR13 ,
VAR14,
VAR9 ,
VAR4 ,
VAR2 ,
VAR6 ,
VAR15
);
output VAR13 ;
input VAR14;
input VAR9 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR15 ;
wire VAR5 ;
wire VAR12 ;
wire VAR10;
not VAR7 (VAR5 , VAR14 );
and VAR3 (VAR12 , VAR5, VAR9 );
VAR8 VAR11 (VAR10, VAR12, VAR4, VAR2, VAR14);
buf VAR1 (VAR13 ... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/alt_mem_ddrx_ecc_encoder.v | 10,443 | module MODULE1 #
( parameter
VAR25 = 40,
VAR28 = 8,
VAR11 = 0,
VAR12 = 7,
VAR10 = 7,
VAR31 = 1
)
(
VAR15,
VAR17,
VAR14,
VAR22,
VAR26,
VAR4,
VAR20,
VAR21,
VAR9
);
localparam VAR24 = (VAR25 > 8) ? (VAR25 - VAR28) : (VAR25);
input VAR15;
input VAR17;
input [VAR12 - 1 : 0] VAR14;
input [VAR10 - 1 : 0] VAR22;
input [VAR31 -... | lgpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/primitives.v | 7,338 | module MODULE5(VAR15,VAR13,VAR20,out);
parameter VAR1=8'b00000000;
input VAR20,VAR13,VAR15;
output reg out;
integer VAR10;
wire [2:0] VAR18;
VAR4 VAR2(VAR20 , VAR18[0]);
VAR4 VAR8(VAR13 , VAR18[1]);
VAR4 VAR11(VAR15 , VAR18[2]);
always@(VAR18[0], VAR18[1], VAR18[2])
begin
VAR10 = {VAR18[2], VAR18[1], VAR18[0]};
out = V... | mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_register_slice_v2_1/353278bf/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v | 18,630 | module MODULE1 #
(
parameter VAR55 = "VAR126",
parameter VAR86 = 0,
parameter integer VAR90 = 4,
parameter integer VAR12 = 32,
parameter integer VAR137 = 32,
parameter integer VAR36 = 0,
parameter integer VAR58 = 1,
parameter integer VAR143 = 1,
parameter integer VAR149 = 1,
parameter integer VAR68 = 1,
parameter integ... | mit |
peteasa/parallella-fpga | AdaptevaLib/ip_repo/axi_traffic_controller_1.0/hdl/axi_traffic_controller_v1_0_M_AXI.v | 49,083 | module MODULE1 #
(
parameter VAR51 = "VAR16",
parameter VAR28 = "VAR13",
parameter VAR61 = "VAR7",
parameter VAR65 = "VAR3",
parameter VAR42 = 32'hAA000000,
parameter VAR26 = 32'h40000000,
parameter integer VAR62 = 32,
parameter integer VAR41 = 32,
parameter integer VAR46 = 4
)
(
input wire VAR29,
output reg VAR74,
out... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi.functional.pp.v | 1,971 | module MODULE1 (
VAR10,
VAR1,
VAR12 ,
VAR15 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR7
);
input VAR10;
input VAR1;
output VAR12 ;
input VAR15 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR7 ;
wire VAR4 VAR3 ;
wire VAR8 ;
wire VAR11;
and VAR13 (VAR3 , VAR15, VAR5, VAR2, VAR4 );
nor VAR16 (VAR8 , VAR7, VAR3 );
VAR14 VAR9 (VAR11, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4.blackbox.v | 1,339 | module MODULE1 (
VAR2 ,
VAR7,
VAR8,
VAR10,
VAR5,
VAR4,
VAR3
);
output VAR2 ;
input VAR7;
input VAR8;
input VAR10;
input VAR5;
input VAR4;
input VAR3;
supply1 VAR6;
supply0 VAR11;
supply1 VAR9 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb.pp.blackbox.v | 1,263 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR1,
VAR4,
VAR5 ,
VAR6
);
output VAR3 ;
output VAR2 ;
input VAR1;
input VAR4;
input VAR5 ;
input VAR6 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/ddr1_top.v | 16,045 | module MODULE1 (
VAR29,
VAR121,
VAR104,
VAR108,
VAR46,
VAR79,
VAR71,
VAR56,
VAR16,
VAR60,
VAR37,
VAR97,
VAR52,
VAR14,
VAR39,
VAR32,
VAR77,
VAR119,
VAR67,
VAR1,
VAR102,
VAR66,
VAR47,
VAR100,
VAR4,
VAR112,
VAR103,
VAR18,
VAR10,
VAR33,
VAR9,
VAR55,
VAR83,
VAR78,
VAR23,
VAR12,
VAR6,
VAR88,
VAR107,
VAR13,
VAR96,
VAR57,
VAR8... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4.pp.blackbox.v | 1,347 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR9 ,
VAR2,
VAR7,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR9 ;
input VAR2;
input VAR7;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_registers.v | 19,073 | module MODULE1
parameter VAR19 = 0 ,
parameter VAR47 = 0 ,
parameter VAR123 = 32,
parameter VAR158 = 1 ,
parameter VAR21 = 32,
parameter VAR80 = 1 ,
parameter VAR26 = 1 ,
parameter VAR84 = 0 ,
parameter VAR3 = 0 , parameter VAR153 = 0 , parameter VAR122 = 0 ,
parameter VAR112 = 0 ,
parameter VAR57 = 0 ,
parameter VAR10... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_p_src_cols_V_2_loc_channel.v | 3,043 | module MODULE2 (
clk,
VAR12,
VAR1,
VAR4,
VAR20);
parameter VAR9 = 32'd12;
parameter VAR6 = 32'd2;
parameter VAR10 = 32'd3;
input clk;
input [VAR9-1:0] VAR12;
input VAR1;
input [VAR6-1:0] VAR4;
output [VAR9-1:0] VAR20;
reg[VAR9-1:0] VAR3 [0:VAR10-1];
integer VAR5;
always @ (posedge clk)
begin
if (VAR1)
begin
for (VAR5=0... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/sync_pulse_synchronizer.v | 2,153 | module MODULE1 (
VAR9, VAR13,
VAR7, VAR6, VAR19, VAR12, VAR1
);
output VAR9;
output VAR13;
input VAR7;
input VAR6;
input VAR19;
input VAR12;
input VAR1;
wire VAR17;
wire VAR10;
wire VAR11;
VAR3 VAR15 (
.VAR2 (VAR17),
.VAR13 (VAR10),
.VAR4 (VAR6),
.VAR16 (VAR7),
.VAR1 (VAR1),
.VAR18 (VAR12)
);
VAR8 VAR14 (
.VAR13 (VAR11... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_buf_pdl_odd.v | 5,156 | module MODULE1(
VAR15, VAR30,
VAR10, VAR14,
VAR27, VAR28,
VAR7, VAR22,
VAR24, VAR11,
VAR6, VAR29,
VAR25, VAR17,
VAR8,
VAR4, VAR9,
VAR19, VAR3,
VAR21, VAR13,
VAR16, VAR5,
VAR1, VAR2,
VAR23, VAR12,
VAR26, VAR18,
VAR20
);
output VAR15 ;
output VAR30 ;
output VAR10 ;
output VAR14 ;
output VAR27 ;
output VAR28 ;
output VAR7... | gpl-2.0 |
crespum/N64-controller-FPGA | n64_readcmd.v | 1,966 | module MODULE1(input wire VAR30,
inout VAR14,
output wire [31:0] VAR20,
output wire VAR16);
wire VAR29; wire VAR18;
wire VAR3;
wire VAR10;
VAR22 #(
.VAR1(6'VAR8 101001),
.VAR11(1'VAR8 1)
) VAR17 (
.VAR21(VAR14),
.VAR13(VAR18),
.VAR9(VAR3),
.VAR4(VAR10)
);
wire VAR31;
VAR23 #(.VAR19(4))
VAR28 (
.VAR15(VAR30),
.VAR12(VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o_1.v | 2,448 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR11 ,
VAR8 ,
VAR7 ,
VAR4 ,
VAR1,
VAR3,
VAR10 ,
VAR9
);
output VAR2 ;
input VAR5 ;
input VAR11 ;
input VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR3;
input VAR10 ;
input VAR9 ;
VAR12 VAR6 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VA... | apache-2.0 |
aj-michael/Digital-Systems | hw2problem3/hw2problem3.v | 1,051 | module MODULE1(VAR4, VAR1, VAR3, VAR5, VAR6);
input VAR4, VAR3, VAR5;
output reg VAR1;
output reg [1:0] VAR6;
reg [1:0] VAR2;
parameter VAR8 = 2'b00, VAR7 = 2'b01, VAR9 = 2'b10, VAR10 = 2'b11;
always @ (VAR6)
if (VAR6 == VAR9) VAR1 <= 1;
else VAR1 <= 1;
always @ (posedge VAR5 or negedge VAR3)
if (VAR3 == 0) VAR6 <= VAR... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/fpu/hardlogic/ode.v | 2,853 | module MODULE1(VAR52,
reset,
select,
VAR13,
VAR54,
VAR22,
VAR43,
VAR45,
VAR21
);
input VAR52;
input reset;
input select;
input [VAR11-1:0] VAR13;
input [VAR11-1:0] VAR54;
input [VAR11-1:0] VAR22;
input [VAR11-1:0] VAR43;
output [VAR11-1:0] VAR45;
output [VAR11-1:0] VAR21;
output [7:0] VAR9;
wire [VAR11-1:0] VAR39;
wire... | mit |
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