repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
asicguy/gplgpu | hdl/crt_sp/dc_adout.v | 6,290 | module MODULE1
(
input VAR27,
input VAR16,
input VAR4,
input VAR5,
input VAR13,
input VAR12,
input [9:0] VAR20,
input [9:0] VAR18,
input [10:0] VAR33,
input [10:0] VAR19,
input [1:0] VAR26,
input [127:0] VAR31,
input [7:0] VAR15,
input VAR9,
output reg [23:0] VAR8,
output VAR25
);
reg [3:0] counter; reg [3:0] VAR30, VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp.pp.symbol.v | 1,413 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR2 ,
input VAR6 ,
input VAR7 ,
input VAR3 ,
input VAR8,
input VAR1,
input VAR9
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3b/sky130_fd_sc_ls__or3b_1.v | 2,209 | module MODULE2 (
VAR9 ,
VAR10 ,
VAR5 ,
VAR8 ,
VAR2,
VAR6,
VAR1 ,
VAR4
);
output VAR9 ;
input VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR2;
input VAR6;
input VAR1 ;
input VAR4 ;
VAR3 VAR7 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
YurongYou/MIPS_CPU | decoder.v | 12,084 | module MODULE1 (
input rst,
input[VAR29-1:0] VAR1,
output reg VAR30,
output reg VAR50,
output reg VAR23,
output reg VAR41,
output reg[VAR46-1:0] VAR45,
output reg[VAR15-1:0] VAR33,
output reg VAR18,
output reg VAR6,
output reg VAR16,
output reg VAR35,
output reg VAR54
);
wire[VAR19] VAR11;
wire[VAR51] VAR25;
assign VAR... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi.functional.pp.v | 2,267 | module MODULE1 (
VAR2 ,
VAR14,
VAR7,
VAR10 ,
VAR19 ,
VAR3,
VAR15,
VAR4 ,
VAR11
);
output VAR2 ;
input VAR14;
input VAR7;
input VAR10 ;
input VAR19 ;
input VAR3;
input VAR15;
input VAR4 ;
input VAR11 ;
wire VAR6 ;
wire VAR12 ;
wire VAR16 ;
wire VAR13;
and VAR18 (VAR6 , VAR10, VAR19 );
nor VAR9 (VAR12 , VAR14, VAR7 );
no... | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/Interleaver.v | 1,289 | module MODULE1(
input clk,
input VAR6,
input VAR5,
input VAR3,
output reg VAR7 = 1'b1
output reg VAR7 = 1'b0
);
reg VAR1 = 1'b0, VAR4 = 1'b0;
reg VAR8 = 1'b0, VAR2 = 1'b0;
always @(posedge clk) begin
VAR1 <= VAR4;
VAR4 <= VAR5;
VAR8 <= VAR3;
VAR2 <= VAR8;
if (VAR6 && VAR2) VAR7 <= (VAR1) ? ~VAR7 : 1'b1;
end
else if (VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl.functional.pp.v | 1,992 | module MODULE1 (
VAR5 ,
VAR11 ,
VAR9 ,
VAR8 ,
VAR3,
VAR13 ,
VAR2
);
output VAR5 ;
input VAR11 ;
input VAR9 ;
input VAR8 ;
input VAR3;
input VAR13 ;
input VAR2 ;
wire VAR12;
wire VAR1 ;
VAR7 VAR4 (VAR12, VAR11, VAR9, VAR8 );
buf VAR6 (VAR1 , VAR12 );
VAR7 VAR10 (VAR5 , VAR1, VAR3, VAR8);
endmodule | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_stratix/src/lpm_ff_v1.v | 3,918 | module MODULE1 (
VAR10,
VAR4,
VAR15);
input VAR10;
input [63:0] VAR4;
output [63:0] VAR15;
wire [63:0] VAR17;
wire [63:0] VAR15 = VAR17[63:0];
VAR1 VAR16 (
.VAR10 (VAR10),
.VAR4 (VAR4),
.VAR15 (VAR17)
,
.VAR9 (),
.VAR5 (),
.VAR8 (),
.enable (),
.VAR6 (),
.VAR13 (),
.VAR3 ()
);
VAR16.VAR14 = "VAR12",
VAR16.VAR11 = "VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtn/sky130_fd_sc_lp__dfrtn.pp.symbol.v | 1,436 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR8,
input VAR4 ,
input VAR6 ,
input VAR3 ,
input VAR7 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b.behavioral.v | 1,460 | module MODULE1 (
VAR10 ,
VAR8,
VAR6
);
output VAR10 ;
input VAR8;
input VAR6 ;
supply1 VAR12;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR11 ;
wire VAR5 ;
wire VAR1;
not VAR2 (VAR5 , VAR6 );
or VAR9 (VAR1, VAR5, VAR8 );
buf VAR3 (VAR10 , VAR1 );
endmodule | apache-2.0 |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/sdram_control/command.v | 16,652 | module MODULE1(
VAR42,
VAR28,
VAR31,
VAR61,
VAR40,
VAR50,
VAR5,
VAR33,
VAR9,
VAR34,
VAR37,
VAR55,
VAR58,
VAR26,
VAR38,
VAR46,
VAR13,
VAR7,
VAR22,
VAR49,
VAR54,
VAR18,
VAR6
);
input VAR42; input VAR28; input [VAR4-1:0] VAR31; input VAR61; input VAR40; input VAR50; input VAR5; input VAR33; input VAR9; input VAR34; input ... | gpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_jtag_uart_0.v | 16,748 | module MODULE1 (
clk,
VAR13,
VAR48,
VAR35,
VAR12,
VAR37,
VAR9
)
;
output VAR35;
output [ 7: 0] VAR12;
output VAR37;
output [ 5: 0] VAR9;
input clk;
input [ 7: 0] VAR13;
input VAR48;
wire VAR35;
wire [ 7: 0] VAR12;
wire VAR37;
wire [ 5: 0] VAR9;
always @(posedge clk)
begin
if (VAR48)
("%VAR30", VAR13);
end
assign VAR9 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp_4.v | 2,024 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR3,
VAR6,
VAR1 ,
VAR2
);
output VAR8 ;
input VAR5 ;
input VAR3;
input VAR6;
input VAR1 ;
input VAR2 ;
VAR4 VAR7 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR8,
VAR5
);
output VAR8;
input VAR5;
supply1 VAR3;
supply0 VAR6;... | apache-2.0 |
julioamerico/prj_crc_ip | src/SoC/component/work/crc_ahb_ip_MSS/crc_ahb_ip_MSS.v | 18,976 | module MODULE1(
VAR303,
VAR198,
VAR289,
VAR272,
VAR189,
VAR205,
VAR20,
VAR88,
VAR40,
VAR111,
VAR101,
VAR283,
VAR58,
VAR63
);
input [31:0] VAR303;
input VAR198;
input VAR289;
input VAR272;
input VAR189;
output VAR205;
output VAR20;
output [19:0] VAR88;
output VAR40;
output [1:0] VAR111;
output [1:0] VAR101;
output [31:0... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w.v | 1,850 | module MODULE1 #(parameter VAR2(VAR6)
,parameter VAR2(VAR17)
, parameter VAR5=0
, parameter VAR11=VAR10(VAR17)
, parameter VAR15=0
)
(input VAR13
, input VAR18
, input VAR12
, input [VAR11-1:0] VAR7
, input [VAR1(VAR6, 1):0] VAR3
, input VAR16
, input [VAR11-1:0] VAR9
, output logic [VAR1(VAR6, 1):0] VAR4
);
VAR8
,.VAR... | bsd-3-clause |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/acl_ic_to_avm.v | 2,685 | module MODULE1 #(
parameter integer VAR19 = 256,
parameter integer VAR21 = 6,
parameter integer VAR14 = 32,
parameter integer VAR27 = VAR19 / 8,
parameter integer VAR7 = 1
)
(
output logic VAR22,
output logic VAR29,
output logic VAR12,
output logic [VAR19-1:0] VAR30,
output logic [VAR21-1:0] VAR17,
output logic [VAR14-... | mit |
HeTpro/Verilog | S3/Contador0-9.v | 1,115 | module MODULE1(VAR11, VAR18, VAR5, VAR1);
input VAR11;
output reg VAR18=0;
output VAR5=1;
output reg [6:0] VAR1=0;
reg [24:0] VAR2 = 0;
reg [3:0] VAR7=0;
parameter [6:0] VAR3 = 7'b0000001;
parameter [6:0] VAR17 = 7'b0000001;
parameter [6:0] VAR9 = 7'b0000001;
parameter [6:0] VAR6 = 7'b0000001;
parameter [6:0] VAR16 = 7... | unlicense |
camsoupa/cc3000 | cc3000fpga/hdl/rgb_led.v | 3,681 | module MODULE1
(
VAR6,
VAR3,
VAR9,
VAR20,
VAR25,
VAR1,
VAR26,
VAR10, VAR8, VAR12
);
input VAR6, VAR3, VAR9, VAR20;
input [7:0] VAR25;
input [31:0] VAR1;
output reg [31:0] VAR26;
output reg VAR10, VAR8, VAR12;
reg [31:0] VAR15;
reg [31:0] VAR2;
reg [31:0] VAR14;
reg [7:0] VAR11;
reg [31:0] VAR19;
reg [31:0] VAR23;
reg [... | mit |
MeshSr/onetswitch30 | ons30-app21-ref_switch/vivado/onets_7030_4x_ref_switch/ip/ref_switch_core/src/core/unused_reg.v | 1,133 | module MODULE1
parameter VAR3 = 5
)
(
input VAR1,
output VAR7,
input VAR10,
input [VAR3 - 1:0] VAR9,
output [VAR8 - 1:0] VAR6,
input [VAR8 - 1:0] VAR5,
input clk,
input reset
);
reg VAR2;
assign VAR6 = 'VAR11 VAR4;
assign VAR7 = VAR1 && !VAR2;
always @(posedge clk)
begin
VAR2 <= VAR1;
end
endmodule | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4bb/sky130_fd_sc_hs__nand4bb.blackbox.v | 1,300 | module MODULE1 (
VAR3 ,
VAR4,
VAR6,
VAR7 ,
VAR2
);
output VAR3 ;
input VAR4;
input VAR6;
input VAR7 ;
input VAR2 ;
supply1 VAR1;
supply0 VAR5;
endmodule | apache-2.0 |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter_008.v | 6,161 | module MODULE1 #(
parameter VAR23 = 18,
parameter VAR5 = 0,
parameter VAR25 = 18,
parameter VAR21 = 0,
parameter VAR14 = 0,
parameter VAR1 = 0,
parameter VAR19 = 1,
parameter VAR6 = 1,
parameter VAR10 = 0,
parameter VAR17 = 18,
parameter VAR24 = 0,
parameter VAR22 = 1,
parameter VAR18 = 0,
parameter VAR4 = 1,
parameter... | gpl-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_Pixel_Buffer.v | 8,827 | module MODULE1 (
clk,
reset,
address,
VAR18,
read,
write,
VAR16,
VAR5,
VAR10,
VAR19,
VAR3,
VAR13,
VAR24,
VAR8,
VAR15,
VAR1,
VAR25,
VAR4,
VAR26,
VAR11,
VAR22,
VAR21,
VAR14,
VAR7
);
input clk;
input reset;
input [18: 0] address;
input [ 3: 0] VAR18;
input read;
input write;
input [31: 0] VAR16;
inout [31: 0] VAR5; inout ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/verilog/convolve_kernel_fbkb.v | 1,946 | module MODULE1
VAR6 = 7,
VAR2 = 9,
VAR1 = 32,
VAR12 = 32,
VAR21 = 32
)(
input wire clk,
input wire reset,
input wire VAR4,
input wire [VAR1-1:0] VAR24,
input wire [VAR12-1:0] VAR26,
output wire [VAR21-1:0] dout
);
wire VAR3;
wire VAR8;
wire VAR20;
wire [31:0] VAR15;
wire VAR19;
wire [31:0] VAR22;
wire VAR16;
wire [31:0... | mit |
kactus2/ipxactexamplelib | tut.fi/peripheral.logic/wb_external_mem/1.0/wb_memory.v | 6,535 | module MODULE1 #(
parameter VAR3 = 16, parameter VAR21 = 32, parameter VAR8 = 128, parameter VAR13 = 'h0F00, parameter VAR15 = 'hDEADF00D ) (
input [VAR3-1:0] VAR10, input VAR20, input [VAR21-1:0] VAR2, input VAR19, input VAR11, output reg VAR14, output reg [VAR21-1:0] VAR24, output reg VAR16,
input VAR7, input VAR22,
... | mit |
hhuang25/uwaterloo_ece224 | Lab1/pio_dutycycle.v | 2,120 | module MODULE1 (
address,
VAR1,
clk,
VAR8,
VAR9,
VAR2,
VAR4,
VAR5
)
;
output [ 3: 0] VAR4;
output [ 3: 0] VAR5;
input [ 1: 0] address;
input VAR1;
input clk;
input VAR8;
input VAR9;
input [ 3: 0] VAR2;
wire VAR6;
reg [ 3: 0] VAR7;
wire [ 3: 0] VAR4;
wire [ 3: 0] VAR3;
wire [ 3: 0] VAR5;
assign VAR6 = 1;
assign VAR3 = {... | mit |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/example_design/rtl/example_top.v | 32,267 | module MODULE1 #
(
parameter VAR57 = 32'h00000000,
parameter VAR221 = 32'h00ffffff,
parameter VAR211 = 32'hff000000,
parameter VAR50 = 0,
parameter VAR215 = 8'h11,
parameter VAR194 = 3'b000,
parameter VAR133 = 0,
parameter VAR216 = 0,
parameter VAR232 = 1,
parameter VAR112 = 1,
parameter VAR54 = 1,
parameter VAR72 = 8,... | mit |
finnball/igloo | projects/mandlebrot/hdl/mandlebrot_factory.v | 3,153 | module MODULE1(
input clk,
input [VAR9 - 1 : 0]VAR20,
output [VAR17 - 1 : 0] VAR26
);
parameter VAR17 = 8;
parameter VAR9 = 9;
parameter VAR13 = 2 * VAR17 + 7;
localparam VAR12 = 5;
reg VAR10 = 0;
reg [VAR17 - 1 : 0] VAR14[VAR13 - 1 : 0];
reg [VAR9 - 1 : 0] VAR7 = 0;
reg [VAR9 - 1 : 0] VAR25[VAR13 - 1 : 0];
wire VAR3;
... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_controller/axi_mc_controller.v | 22,111 | module MODULE1
(
input VAR140, input VAR175,
output VAR57,
output VAR229,
output VAR27,
output VAR45,
output VAR195,
output VAR177,
output VAR205,
output [3:0] VAR222,
input VAR88,
input VAR210,
input VAR110,
input VAR30,
input [31:0] VAR137,
input [31:0] VAR219,
input [31:0] VAR19,
input [31:0] VAR143,
input [31:0] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbp/sky130_fd_sc_ls__dlrbp_1.v | 2,474 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR11,
VAR9 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR8 ,
VAR7
);
output VAR3 ;
output VAR2 ;
input VAR11;
input VAR9 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR7 ;
VAR4 VAR6 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR8(VAR8)... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_video_itu_656_decoder.v | 9,353 | module MODULE1 (
clk,
reset,
VAR12,
ready,
VAR5,
VAR2,
VAR6,
valid
);
input clk;
input reset;
input [ 7: 0] VAR12;
input ready;
output [15: 0] VAR5;
output VAR2;
output VAR6;
output valid;
wire VAR14;
wire VAR19;
wire VAR23;
wire [ 7: 0] VAR11;
reg [ 7: 0] VAR9;
reg [ 7: 0] VAR20 [ 5: 1];
reg VAR29;
reg [ 6: 1] VAR24;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi_4.v | 2,361 | module MODULE2 (
VAR11 ,
VAR10 ,
VAR6 ,
VAR8 ,
VAR1 ,
VAR2,
VAR4,
VAR5 ,
VAR3
);
output VAR11 ;
input VAR10 ;
input VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR2;
input VAR4;
input VAR5 ;
input VAR3 ;
VAR7 VAR9 (
.VAR11(VAR11),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi.pp.symbol.v | 1,402 | module MODULE1 (
input VAR6 ,
input VAR5 ,
input VAR4,
output VAR3 ,
input VAR2 ,
input VAR1,
input VAR7,
input VAR8
);
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_MATLAB_Function.v | 1,169 | module MODULE1
(
VAR1,
VAR2
);
input [35:0] VAR1; output [17:0] VAR2;
assign VAR2 = VAR1[17:0];
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcon/sky130_fd_sc_hd__fahcon_1.v | 2,412 | module MODULE2 (
VAR2,
VAR6 ,
VAR9 ,
VAR3 ,
VAR10 ,
VAR8 ,
VAR4 ,
VAR7 ,
VAR11
);
output VAR2;
output VAR6 ;
input VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR4 ;
input VAR7 ;
input VAR11 ;
VAR1 VAR5 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_adder.v | 4,349 | module MODULE1 (
VAR21,
VAR5,
VAR12,
VAR4,
VAR8,
VAR16,
VAR2
);
input VAR21; input VAR5; input [VAR17] VAR12; input [VAR17] VAR4;
output [VAR17] VAR8; wire [VAR17] VAR8;
output VAR16; wire VAR16;
output VAR2; reg VAR2;
wire VAR6; wire VAR11; wire VAR10;
VAR14 VAR3 (
.VAR7 (VAR12),
.VAR20 (VAR4),
.VAR15 (VAR21),
.VAR9 (... | lgpl-3.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_iodelay16.v | 1,848 | module MODULE1 #(
parameter VAR2 = 30
) (
input [15:0] VAR22,
output [15:0] VAR1,
input [15:0] VAR14,
output [15:0] VAR21,
input [15:0] VAR10,
output [15:0] VAR11,
input VAR7,
input VAR17,
input VAR15,
input VAR23,
input VAR13,
input VAR4,
input VAR20
);
genvar VAR3;
generate
for(VAR3=0;VAR3<16;VAR3=VAR3+1)
VAR18 #(
.V... | lgpl-3.0 |
tmatsuya/milkymist-ml401 | cores/minimac/rtl/minimac_asfifo.v | 4,288 | module MODULE1
VAR18 = 4,
VAR14 = (1 << VAR18))
(output wire [VAR25-1:0] VAR27,
output reg VAR1,
input wire VAR8,
input wire VAR19,
input wire [VAR25-1:0] VAR4,
output reg VAR17,
input wire VAR21,
input wire VAR16,
input wire VAR11);
reg [VAR25-1:0] VAR9 [VAR14-1:0];
wire [VAR18-1:0] VAR30, VAR24;
wire VAR15;
wire VAR7... | lgpl-3.0 |
m-labs/milkymist | cores/tmu2/rtl/tmu2_alpha.v | 2,986 | module MODULE1 #(
parameter VAR16 = 26
) (
input VAR43,
input VAR11,
output VAR20,
input [5:0] VAR31,
input VAR28,
input VAR45,
output VAR15,
input [15:0] VAR35,
input [VAR16-1-1:0] VAR12,
input [15:0] VAR1,
output VAR42,
input VAR6,
output reg [VAR16-1-1:0] VAR36,
output [15:0] VAR21
);
wire en;
reg VAR27;
reg VAR13;
... | lgpl-3.0 |
ptracton/pmodacl2 | rtl/fpga.v | 4,988 | module MODULE1 (
VAR13, VAR14, VAR5,
VAR20, VAR17, VAR12, VAR10, VAR4
) ;
input wire VAR20;
input wire VAR17;
output wire VAR13;
output wire VAR14;
output wire VAR5;
input wire VAR12;
input wire VAR10;
input wire VAR4;
wire VAR18; wire VAR11; wire clk; wire VAR25; wire VAR8; wire [7:0] VAR21; wire VAR1; wire rst; wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1.blackbox.v | 1,323 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR6;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22oi/sky130_fd_sc_hdll__a22oi_2.v | 2,368 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR7,
VAR11,
VAR4 ,
VAR2
);
output VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR7;
input VAR11;
input VAR4 ;
input VAR2 ;
VAR10 VAR8 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR... | apache-2.0 |
JohnOrlando/gnuradio-bitshark | gr-sounder/src/fpga/lib/dac_interface.v | 1,737 | module MODULE1(VAR5,VAR12,VAR4,VAR15,VAR11,VAR13,VAR8,VAR3);
input VAR5;
input VAR12;
input VAR4;
input VAR15;
input [13:0] VAR11;
input [13:0] VAR13;
output [13:0] VAR8;
output VAR3;
wire VAR2;
reg VAR9;
reg [13:0] VAR8;
VAR10 VAR6(.VAR14(VAR12),.VAR7(VAR5),.VAR1(VAR2));
always @(posedge VAR2)
VAR9 <= VAR5;
always @(p... | gpl-3.0 |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/bench/verilog/DAC121S101.v | 3,762 | module MODULE1 (
VAR9,
din, VAR2, VAR3 );
output [11:0] VAR9;
input din; input VAR2; input VAR3;
reg VAR1;
always @ (negedge VAR2)
VAR1 <= VAR3;
wire VAR6 = ~VAR3 & VAR1;
reg [3:0] VAR5;
wire VAR7 = (VAR5==4'hf);
always @ (negedge VAR2)
if (VAR3) VAR5 <= 4'hf;
else if (VAR6) VAR5 <= 4'he;
else if (~VAR7) VAR5 <= VAR5-1... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4/sky130_fd_sc_hdll__and4.behavioral.pp.v | 1,855 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR12 ,
VAR1 ,
VAR14 ,
VAR6,
VAR7,
VAR11 ,
VAR5
);
output VAR4 ;
input VAR3 ;
input VAR12 ;
input VAR1 ;
input VAR14 ;
input VAR6;
input VAR7;
input VAR11 ;
input VAR5 ;
wire VAR8 ;
wire VAR2;
and VAR10 (VAR8 , VAR3, VAR12, VAR1, VAR14 );
VAR13 VAR15 (VAR2, VAR8, VAR6, VAR7);
buf VAR9 (VA... | apache-2.0 |
alexforencich/verilog-uart | example/VCU108/fpga/rtl/fpga_core.v | 3,480 | module MODULE1 (
input wire clk,
input wire rst,
input wire VAR22,
input wire VAR24,
input wire VAR27,
input wire VAR11,
input wire VAR5,
input wire [7:0] VAR16,
output wire [7:0] VAR20,
input wire VAR23,
output wire VAR2,
output wire VAR29,
input wire VAR26
);
reg [7:0] VAR13;
reg VAR14;
wire VAR31;
wire [7:0] VAR15;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1p/sky130_fd_sc_lp__iso1p.pp.symbol.v | 1,267 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR7,
input VAR2,
input VAR6 ,
input VAR4 ,
input VAR1
);
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_dpram_256x32.v | 6,489 | module MODULE1(
VAR26, VAR36, VAR15, VAR10, VAR34, VAR20,
VAR35, VAR2, VAR18, VAR32, VAR25, VAR8
);
parameter VAR19 = 8;
parameter VAR28 = 32;
input VAR26; input VAR36; input VAR15; input VAR10; input [VAR19-1:0] VAR34; output [VAR28-1:0] VAR20; input VAR35; input VAR2; input VAR18; input VAR32; input [VAR19-1:0] VAR25... | gpl-3.0 |
csturton/wirepatch | system/hardware/cores/dbg_if/dbg_wb.v | 33,670 | module MODULE1(
VAR48,
VAR106,
VAR4,
VAR89,
VAR17,
VAR73,
VAR37,
VAR15,
VAR62,
VAR76,
VAR77,
VAR45,
VAR128, VAR20, VAR42, VAR25, VAR68, VAR11,
VAR132, VAR39, VAR124, VAR52, VAR27, VAR56
);
input VAR48;
input VAR106;
output VAR4;
input VAR89;
input VAR17;
input VAR73;
input VAR37;
input VAR15;
output VAR62;
output VAR76... | mit |
scalable-networks/ext | uhd/fpga/usrp2/extramfifo/refill_randomizer.v | 2,021 | module MODULE1
(
input clk,
input rst,
input VAR8,
output VAR3
);
wire VAR4;
reg VAR7;
wire VAR1;
reg [6:0] VAR5;
reg [6:0] VAR2;
reg VAR6;
always @(posedge clk)
VAR7 <= VAR8;
assign VAR1 = VAR7 & ~VAR8;
always @(posedge clk)
if (rst)
VAR5 <= 7'b1;
else
if (VAR1)
VAR5 <= {VAR5[5:0],VAR4};
assign VAR4 = ^(VAR5 & 7'h41);... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp_4.v | 2,273 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR4 ,
VAR3,
VAR8 ,
VAR9 ,
VAR5 ,
VAR1
);
output VAR6 ;
input VAR10 ;
input VAR4 ;
input VAR3;
input VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR1 ;
VAR7 VAR2 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODU... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_01/011J1G2/hdl/j1soc.v | 3,153 | module MODULE1#(
parameter VAR32 = "../VAR35/VAR13/VAR34.VAR18" )
(VAR25, VAR10,
VAR17, VAR31,VAR21,VAR14,VAR12,VAR1);
input VAR17, VAR31;
output VAR25;
output VAR10;
output VAR21;
output VAR14;
output VAR12;
input VAR1;
wire VAR23; wire VAR20; wire [15:0] VAR24; reg [15:0] VAR27; wire [15:0] VAR9;
reg [1:5]VAR29;
wire... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/addr.v | 26,442 | module MODULE1(
clk,
rst,
enable,
VAR6,
counter,
VAR38,
VAR37 ,
VAR101 ,
VAR50 ,
VAR7 ,
VAR123 ,
VAR62 ,
VAR3 ,
VAR53 ,
VAR81 ,
VAR11 ,
VAR105,
VAR128,
VAR17,
VAR108,
VAR60,
VAR68,
VAR75,
VAR31,
VAR125,
VAR28,
VAR95,
VAR119,
VAR110,
VAR2,
VAR25,
VAR10,
VAR49,
VAR83,
VAR94,
VAR27,
VAR100,
VAR71,
VAR47 ,
VAR106 ,
VAR42 ,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxtp/sky130_fd_sc_lp__dfxtp.pp.blackbox.v | 1,279 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR1 ,
VAR3,
VAR6,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR3;
input VAR6;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_078.v | 1,521 | module MODULE1 (
VAR14,
VAR6
);
input [31:0] VAR14;
output [31:0]
VAR6;
wire [31:0]
VAR9,
VAR10,
VAR3,
VAR12,
VAR8,
VAR2,
VAR7,
VAR4,
VAR11;
assign VAR9 = VAR14;
assign VAR2 = VAR9 << 4;
assign VAR12 = VAR3 << 2;
assign VAR8 = VAR9 + VAR12;
assign VAR7 = VAR8 + VAR2;
assign VAR3 = VAR10 - VAR9;
assign VAR10 = VAR9 << 9... | mit |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_uart/qmfir_240MHz/ISE_project/iReg.v | 11,333 | module MODULE1
(
VAR29, VAR33, VAR4, VAR2, VAR32, VAR21,
clk, VAR3, VAR5, VAR27, VAR34, VAR23, VAR15
);
parameter VAR13 = 15;
parameter VAR1 = 8'h60;
input clk; input VAR3; input [15:0] VAR5;
input [13:0] VAR27;
input VAR34;
input VAR23;
input VAR15;
output [15:0] VAR29;
output [15:0] VAR33;
output [15:0] VAR4;
output ... | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_avalon_bridge/verilog/avalon_to_wb_bridge.v | 2,994 | module MODULE1 #(
parameter VAR20 = 32, parameter VAR6 = 32 )(
input clk,
input rst,
input [VAR6-1:0] VAR17,
input [VAR20/8-1:0] VAR19,
input VAR3,
output [VAR20-1:0] VAR11,
input [7:0] VAR12,
input VAR10,
input [VAR20-1:0] VAR7,
output VAR18,
output VAR15,
output [VAR6-1:0] VAR14,
output [VAR20-1:0] VAR25,
output [VAR... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/common/rtl/bw_clk_cl_ctu_jbus.v | 2,735 | module MODULE1(
VAR2, VAR13, VAR4, VAR9,
VAR10, VAR11, VAR5, VAR6, VAR7, VAR14, VAR1, VAR8
);
input VAR8; input VAR1; input VAR14; input VAR7; input VAR6; input VAR5; input VAR11; input VAR10;
output VAR9; output VAR4; output VAR13; output VAR2; VAR12 VAR3 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR13(VAR13),
.VAR2 (VAR2),
.VAR7(... | gpl-2.0 |
kkiningh/cs231n-project | src/rtl/MultiplyAccumulateCell.v | 1,397 | module MODULE1 #(
parameter VAR13 = 8,
parameter VAR4 = 8,
parameter VAR1 = 16
) (
input VAR11,
input reset,
input [VAR13-1:0] VAR3,
input [VAR1-1:0] VAR5,
input VAR8,
output [VAR13-1:0] VAR9,
output [VAR1-1:0] VAR2,
input [VAR4-1:0] VAR7,
input VAR10
);
reg [VAR13-1:0] VAR12;
reg [VAR4-1:0] VAR6;
reg [VAR1-1:0] VAR14;... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/saed_90/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v | 2,808 | if (VAR24 == VAR19 && VAR42 == VAR7) \
begin: VAR16 \
VAR20 VAR38 \
(.VAR10 (VAR48) \
,.VAR46 (~VAR43) \
,.VAR2 (1'b0) \
,.VAR3 (~VAR33) \
,.VAR31 (VAR30) \
,.VAR29 (VAR41) \
,.VAR17 (VAR28) \
,.VAR13 (VAR36) \
); \
end
module MODULE1 #(parameter VAR40(VAR42)
, parameter VAR40(VAR24)
, parameter VAR21=VAR8(VAR24)
, par... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2a/sky130_fd_sc_ls__o2bb2a.pp.blackbox.v | 1,400 | module MODULE1 (
VAR3 ,
VAR8,
VAR7,
VAR1 ,
VAR9 ,
VAR6,
VAR5,
VAR4 ,
VAR2
);
output VAR3 ;
input VAR8;
input VAR7;
input VAR1 ;
input VAR9 ;
input VAR6;
input VAR5;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_nh_lcd/rtl/nh_lcd.v | 4,975 | module MODULE1 #(
parameter VAR11 = 12
)(
input rst,
input clk,
output [31:0] VAR6,
input VAR21,
input VAR41,
input VAR38,
input VAR14,
input VAR33,
input VAR16,
input VAR36,
input [7:0] VAR46,
output [7:0] VAR51,
output VAR4,
input VAR12,
input VAR43,
input VAR35,
input [31:0] VAR45,
output [1:0] VAR2,
input [1:0] VAR... | mit |
takeshineshiro/fpga_linear_128 | mult30_9.v | 4,723 | module MODULE1 (
VAR16,
VAR4,
VAR9,
VAR17);
input VAR16;
input [29:0] VAR4;
input [8:0] VAR9;
output [38:0] VAR17;
wire [38:0] VAR1;
wire [38:0] VAR17 = VAR1[38:0];
VAR8 VAR11 (
.VAR4 (VAR4),
.VAR9 (VAR9),
.VAR16 (VAR16),
.VAR17 (VAR1),
.VAR13 (1'b0),
.VAR10 (1'b1),
.sum (1'b0));
VAR11.VAR19 = "VAR5=5",
VAR11.VAR2 = 1... | mit |
DougFirErickson/parallella-hw | fpga/old/hdl/elink-gold/axi_slave.v | 12,945 | module MODULE1 (
VAR77, VAR30, VAR43, VAR46, VAR52, VAR65, VAR16, VAR15,
VAR19, VAR60, VAR2, VAR21, VAR74, VAR31,
VAR78, VAR13, VAR54,
VAR27, VAR72, VAR62,
VAR44, VAR9,
VAR17, VAR7, reset, VAR6, VAR50, VAR76, VAR23, VAR5, VAR59,
VAR71, VAR55, VAR32, VAR45, VAR61, VAR33, VAR8, VAR57, VAR20,
VAR58, VAR37, VAR10, VAR68, V... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/sctag_scbuf_rptr0.v | 7,720 | module MODULE1 (
VAR9, VAR22,
VAR1, VAR42,
VAR19, VAR20,
VAR34, VAR46,
VAR25, VAR16,
VAR4, VAR41,
VAR15, VAR44,
VAR27, VAR35,
VAR31, VAR10,
VAR2, VAR32,
VAR50, VAR18,
VAR29, VAR24,
VAR12,
VAR48, VAR43,
VAR21, VAR40,
VAR5, VAR3,
VAR6, VAR30,
VAR45, VAR8,
VAR49, VAR37,
VAR47, VAR11,
VAR7, VAR36,
VAR39, VAR33,
VAR38, VAR1... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/CS_bak/synthesis/submodules/altera_up_video_scaler_shrink.v | 7,628 | module MODULE1 (
clk,
reset,
VAR13,
VAR6,
VAR10,
VAR21,
VAR16,
VAR23,
VAR27,
VAR15,
VAR24,
VAR4
);
parameter VAR22 = 15; parameter VAR7 = 9; parameter VAR26 = 9;
parameter VAR9 = 640;
parameter VAR1 = 4'b0101;
parameter VAR25 = 4'b0000;
input clk;
input reset;
input [VAR22: 0] VAR13;
input VAR6;
input VAR10;
input VAR2... | mit |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_ob_audio.v | 6,858 | module MODULE1 (
VAR12,
VAR1
);
parameter VAR3 = 9'h01A;
parameter VAR4 = 9'h01A;
parameter VAR9 = 9'h07B;
parameter VAR7 = 9'h07B;
parameter VAR11 = 9'h0F8;
parameter VAR6 = 9'h006;
parameter VAR13 = 9'h000;
parameter VAR2 = 9'h001;
parameter VAR5 = 9'h002;
parameter VAR10 = 9'h001;
input [ 5: 0] VAR12;
output [26: 0]... | mit |
DreamSourceLab/DSLogic-hdl | src/uart/baud_gen.v | 1,851 | module MODULE1
(
VAR2, reset,
VAR4, VAR1, VAR3
);
input VAR2; input reset; output VAR4; input [11:0] VAR1; input [15:0] VAR3;
reg VAR4;
reg [15:0] counter;
always @ (posedge VAR2 or posedge reset)
begin
if (reset)
counter <= 16'b0;
end
else if (counter >= VAR3)
counter <= counter - VAR3;
else
counter <= counter + VAR1;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai.functional.pp.v | 2,174 | module MODULE1 (
VAR17 ,
VAR2 ,
VAR4 ,
VAR9,
VAR8,
VAR11,
VAR6 ,
VAR15
);
output VAR17 ;
input VAR2 ;
input VAR4 ;
input VAR9;
input VAR8;
input VAR11;
input VAR6 ;
input VAR15 ;
wire VAR10 ;
wire VAR3 ;
wire VAR12 ;
wire VAR18;
not VAR1 (VAR10 , VAR9 );
or VAR7 (VAR3 , VAR4, VAR2 );
nand VAR5 (VAR12 , VAR10, VAR3 );
V... | apache-2.0 |
ILoveSpeccy/Aeon-Lite | cores/radio-86rk/src/radio86rk.v | 6,695 | module MODULE1(
input VAR93,
inout [15:0] VAR141, output [17:0] VAR41, output VAR84, output VAR45, output VAR136, output VAR31, output VAR19,
output VAR43,
output VAR123,
output VAR131,
output VAR102,
output [3:0] VAR86,
output [3:0] VAR35,
output [3:0] VAR30,
input VAR60,
input VAR145,
input VAR44, output VAR137, outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2b/sky130_fd_sc_lp__and2b_lp.v | 2,144 | module MODULE2 (
VAR9 ,
VAR7 ,
VAR4 ,
VAR3,
VAR6,
VAR1 ,
VAR2
);
output VAR9 ;
input VAR7 ;
input VAR4 ;
input VAR3;
input VAR6;
input VAR1 ;
input VAR2 ;
VAR8 VAR5 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR9 ,
VAR7,
VAR4
);
output VAR9 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4/sky130_fd_sc_hd__nor4_1.v | 2,275 | module MODULE2 (
VAR4 ,
VAR10 ,
VAR11 ,
VAR2 ,
VAR9 ,
VAR3,
VAR1,
VAR5 ,
VAR8
);
output VAR4 ;
input VAR10 ;
input VAR11 ;
input VAR2 ;
input VAR9 ;
input VAR3;
input VAR1;
input VAR5 ;
input VAR8 ;
VAR7 VAR6 (
.VAR4(VAR4),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.... | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_jesd_align.v | 3,712 | module MODULE1 (
VAR2,
VAR7,
VAR6,
VAR5,
VAR8);
input VAR2;
input [ 3:0] VAR7;
input [31:0] VAR6;
output VAR5;
output [31:0] VAR8;
reg [31:0] VAR4 = 'd0;
reg [ 3:0] VAR3 = 'd0;
reg VAR5 = 'd0;
reg VAR1 = 'd0;
reg [31:0] VAR8 = 'd0;
always @(posedge VAR2) begin
VAR4 <= VAR6;
VAR1 <= VAR7;
if (VAR7 != 4'h0) begin
VAR3 <=... | lgpl-3.0 |
omicronns/studies-sys-rek | lab2/counter/src/counter.v | 1,066 | module MODULE1 #(
parameter VAR5 = 0,
parameter VAR2 = 0
)(
input clk,
input VAR3,
input VAR1,
output [VAR5 - 1:0] out
);
reg[VAR5 - 1:0] VAR4 = 0;
always@(posedge clk)
begin
if(VAR1)
VAR4[VAR5 - 1:0] <= 0;
end
else
begin
if(VAR3)
VAR4 <= (VAR4 + 1) % VAR2;
end
else
VAR4 <= VAR4;
end
end
assign out = VAR4;
endmodule | mit |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/soc_system_master_secure_p2b_adapter.v | 1,339 | module MODULE1 (
input clk,
input VAR1,
output reg VAR12,
input VAR11,
input [ 7: 0] VAR3,
input VAR6,
input VAR2,
input VAR7,
output reg VAR10,
output reg [ 7: 0] VAR5,
output reg VAR9,
output reg VAR8,
output reg [ 7: 0] VAR13
);
reg VAR4 = 0;
always @* begin
VAR12 = VAR7;
VAR10 = VAR11;
VAR5 = VAR3;
VAR9 = VAR6;
VAR... | mit |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/FPU_Interface_and_NaN/NaN_mod_64.v | 1,642 | module MODULE1
(
input wire [1:0] VAR4,
input wire [63:0] VAR2,
input wire [63:0] VAR1,
output reg VAR3
);
always @*
begin
case(VAR4)
2'b00:
begin
if((VAR2 == 64'h7ff0000000000000) && (VAR1 == 64'h7ff0000000000000))
VAR3 = 1'b1;
end
else if((VAR2 == 64'hfff0000000000000) && (VAR1 == 64'hfff0000000000000))
VAR3 = 1'b1;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill_diode/sky130_fd_sc_hs__fill_diode.behavioral.pp.v | 1,178 | module MODULE1 (
VAR2,
VAR4,
VAR3 ,
VAR1
);
input VAR2;
input VAR4;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp.pp.blackbox.v | 1,465 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR9 ,
VAR4 ,
VAR2 ,
VAR10,
VAR5 ,
VAR3 ,
VAR1 ,
VAR8
);
output VAR7 ;
output VAR6 ;
input VAR9 ;
input VAR4 ;
input VAR2 ;
input VAR10;
input VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR8 ;
endmodule | apache-2.0 |
cynngah/virtualsynthesizer | ram30x4.v | 7,042 | module MODULE1 (
address,
VAR12,
VAR4,
VAR2,
VAR10);
input [4:0] address;
input VAR12;
input [3:0] VAR4;
input VAR2;
output [3:0] VAR10;
tri1 VAR12;
wire [3:0] VAR51;
wire [3:0] VAR10 = VAR51[3:0];
VAR33 VAR28 (
.VAR6 (address),
.VAR20 (VAR12),
.VAR23 (VAR4),
.VAR26 (VAR2),
.VAR35 (VAR51),
.VAR54 (1'b0),
.VAR37 (1'b0),... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvn/sky130_fd_sc_ls__einvn.blackbox.v | 1,280 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR7
);
output VAR1 ;
input VAR6 ;
input VAR7;
supply1 VAR2;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4SharedKES_v1_0_0/8069a058/src/d_KES_top.v | 38,577 | module MODULE1
(
input wire VAR66,
input wire VAR106,
input wire VAR104,
input wire [3:0] VAR80,
input wire VAR94,
input wire VAR148,
input wire VAR12,
input wire VAR55,
input wire VAR33,
output reg VAR92,
output wire VAR168,
output wire VAR145,
output reg [3:0] VAR26,
output reg VAR36,
output reg VAR28,
output reg [VA... | gpl-3.0 |
sh-chris110/chris | FPGA/chris.convolution.ok/Qsys/soc_design/synthesis/submodules/soc_design_mm_interconnect_0_avalon_st_adapter.v | 6,164 | module MODULE1 #(
parameter VAR25 = 18,
parameter VAR20 = 0,
parameter VAR9 = 18,
parameter VAR14 = 0,
parameter VAR5 = 0,
parameter VAR17 = 0,
parameter VAR6 = 1,
parameter VAR13 = 1,
parameter VAR23 = 0,
parameter VAR18 = 18,
parameter VAR21 = 0,
parameter VAR1 = 1,
parameter VAR22 = 0,
parameter VAR19 = 1,
parameter... | gpl-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_frame_join.v | 11,255 | module MODULE1 #
(
parameter VAR50 = 4,
parameter VAR13 = 8,
parameter VAR5 = 1,
parameter VAR30 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR50*VAR13-1:0] VAR52,
input wire [VAR50-1:0] VAR23,
output wire [VAR50-1:0] VAR26,
input wire [VAR50-1:0] VAR48,
input wire [VAR50-1:0] VAR3,
output wire [VAR13-1:0] VA... | mit |
nishtahir/arty-blaze | src/bd/system/ip/system_microblaze_0_axi_intc_0/system_microblaze_0_axi_intc_0_stub.v | 2,521 | module MODULE1(VAR12, VAR22, VAR21,
VAR9, VAR14, VAR23, VAR19, VAR15, VAR7,
VAR2, VAR5, VAR10, VAR8, VAR18, VAR17,
VAR6, VAR16, VAR24, VAR11, VAR20, VAR4, VAR13, irq,
VAR3, VAR1)
;
input VAR12;
input VAR22;
input [8:0]VAR21;
input VAR9;
output VAR14;
input [31:0]VAR23;
input [3:0]VAR19;
input VAR15;
output VAR7;
output... | apache-2.0 |
tdene/synth_opt_adders | src/pptrees/mappings/asap7sc7p5t_28_R.v | 4,458 | module MODULE21
(
VAR18, VAR25
);
output VAR18;
input VAR25;
VAR13 MODULE21(.VAR18(VAR18), .VAR25(VAR25));
endmodule
module MODULE20
(
VAR18, VAR25
);
output VAR18;
input VAR25;
VAR20 MODULE20(.VAR33(VAR18), .VAR25(VAR25));
endmodule
module MODULE15
(
VAR18, VAR25, VAR7
);
output VAR18;
input VAR25, VAR7;
VAR10 MODULE1... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_hls_macc_0_0/synth/zybo_zynq_design_hls_macc_0_0.v | 10,152 | module MODULE1 (
VAR6,
VAR20,
VAR19,
VAR17,
VAR18,
VAR5,
VAR23,
VAR15,
VAR4,
VAR9,
VAR1,
VAR10,
VAR21,
VAR22,
VAR8,
VAR7,
VAR3,
VAR2,
VAR16,
interrupt
);
input wire [5 : 0] VAR6;
input wire VAR20;
output wire VAR19;
input wire [31 : 0] VAR17;
input wire [3 : 0] VAR18;
input wire VAR5;
output wire VAR23;
output wire [1 ... | mit |
nikhilghanathe/HLS-for-EMTF | verilog/sp_find_segment_stn1.v | 1,037 | module MODULE1 (
VAR8,
VAR2,
VAR6,
VAR3,
VAR4,
VAR7,
VAR1,
VAR5
);
input [11:0] VAR8;
input [6:0] VAR2;
input [6:0] VAR6;
input [3:0] VAR3;
output [11:0] VAR4;
output [3:0] VAR7;
output [6:0] VAR1;
output [6:0] VAR5;
assign VAR4 = VAR8;
assign VAR7 = VAR3;
assign VAR1 = VAR2;
assign VAR5 = VAR6;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_gt_common.v | 9,872 | module MODULE1 (
VAR89,
VAR168,
VAR88,
VAR94,
VAR137,
VAR192,
VAR76,
VAR31,
VAR55,
VAR28,
VAR38,
VAR169);
parameter integer VAR122 = 0;
parameter integer VAR179 = 1;
parameter integer VAR165 = 2;
parameter [26:0] VAR59 = 27'h06801C1;
parameter integer VAR56 = 1'b1;
parameter [ 9:0] VAR65 = 10'b0000110000;
input VAR89;
... | lgpl-3.0 |
alexforencich/xfcp | lib/eth/example/HXT100G/fpga/rtl/eth_gth_phy_quad.v | 17,237 | module MODULE1 (
input wire VAR144,
input wire VAR45,
input wire VAR75,
input wire VAR214,
output wire VAR268,
input wire VAR151,
output wire VAR17,
input wire VAR55,
input wire VAR137,
output wire VAR263,
output wire VAR165,
input wire VAR226,
input wire VAR63,
output wire VAR122,
output wire VAR21,
input wire VAR110,... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cpu/apu/apu_noise.v | 5,851 | module MODULE1
(
input wire VAR25, input wire VAR27, input wire VAR19, input wire VAR24, input wire VAR13, input wire VAR5, input wire [1:0] VAR8, input wire [7:0] din, input wire VAR42, output wire [3:0] VAR15, output wire VAR31 );
wire VAR2;
wire VAR29;
wire [3:0] VAR12;
VAR1 VAR41(
.VAR25(VAR25),
.VAR27(VAR27),
.VAR... | mit |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_decay.v | 2,060 | module MODULE1 #(
parameter VAR12 = 26
) (
input VAR1,
input VAR23,
output VAR22,
input [5:0] VAR6,
input VAR8,
input [15:0] VAR26,
input VAR7,
output VAR20,
input [15:0] VAR24,
input [VAR12-1-1:0] VAR4,
output VAR14,
input VAR2,
output [15:0] VAR13,
output reg [VAR12-1-1:0] VAR5
);
wire en;
reg VAR19;
reg VAR3;
always... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o_4.v | 2,448 | module MODULE2 (
VAR11 ,
VAR6 ,
VAR10 ,
VAR7 ,
VAR8 ,
VAR2 ,
VAR4,
VAR3,
VAR1 ,
VAR9
);
output VAR11 ;
input VAR6 ;
input VAR10 ;
input VAR7 ;
input VAR8 ;
input VAR2 ;
input VAR4;
input VAR3;
input VAR1 ;
input VAR9 ;
VAR5 VAR12 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a.behavioral.v | 1,607 | module MODULE1 (
VAR15 ,
VAR8,
VAR1,
VAR9,
VAR5
);
output VAR15 ;
input VAR8;
input VAR1;
input VAR9;
input VAR5;
supply1 VAR6;
supply0 VAR12;
supply1 VAR7 ;
supply0 VAR2 ;
wire VAR14 ;
wire VAR3 ;
wire VAR10;
or VAR4 (VAR14 , VAR1, VAR8 );
or VAR13 (VAR3 , VAR5, VAR9 );
and VAR11 (VAR10, VAR14, VAR3);
buf VAR16 (VAR15... | apache-2.0 |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/mkDM_GPR_Tap.v | 7,754 | module MODULE1(VAR1,
VAR59,
VAR51,
VAR54,
VAR55,
VAR20,
VAR13,
VAR4,
VAR53,
VAR2,
VAR33,
VAR17,
VAR31,
VAR65,
VAR71,
VAR42,
VAR68);
input VAR1;
input VAR59;
input VAR51;
output [69 : 0] VAR54;
output VAR55;
input [64 : 0] VAR20;
input VAR13;
output VAR4;
input [69 : 0] VAR53;
input VAR2;
output VAR33;
input VAR17;
outp... | apache-2.0 |
orbancedric/DeepGate | src/core/weight_RAM.v | 3,693 | module MODULE1 #(
parameter VAR21 = 4,
parameter VAR19 = VAR21,
parameter VAR11 = 1,
parameter VAR7 = 3,
parameter VAR20 = VAR12(VAR22(VAR18(VAR21*VAR7)/8))
)(
input VAR8,
input VAR14,
input VAR15,
input [7:0] VAR2,
output reg VAR10 = 1'b1,
output reg [VAR21*VAR7 - 1'b1:0] VAR6 = 0
);
localparam VAR17 = VAR19/VAR11;
lo... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4bb/sky130_fd_sc_hd__nand4bb_2.v | 2,334 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR3,
VAR7,
VAR8 ,
VAR11
);
output VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR3;
input VAR7;
input VAR8 ;
input VAR11 ;
VAR10 VAR5 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR11... | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0_stub.v | 4,374 | module MODULE1(VAR46, VAR19, VAR10, VAR25,
VAR38, VAR37, VAR36, VAR42, VAR1, VAR29, VAR43, VAR58, VAR50,
VAR39, VAR60, VAR20, VAR23, VAR41, VAR18, VAR30, VAR4,
VAR17, VAR55, VAR12, VAR15, VAR34, VAR35, VAR9,
VAR47, VAR28, VAR61, VAR27, VAR11, VAR16,
VAR44, VAR52, VAR3, VAR7, VAR51, VAR26, VAR33,
VAR53, VAR54, VAR32, VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o.functional.v | 1,588 | module MODULE1 (
VAR1 ,
VAR5,
VAR6,
VAR9,
VAR8,
VAR12
);
output VAR1 ;
input VAR5;
input VAR6;
input VAR9;
input VAR8;
input VAR12;
wire VAR11 ;
wire VAR7 ;
wire VAR4;
and VAR13 (VAR11 , VAR9, VAR5, VAR6 );
and VAR10 (VAR7 , VAR8, VAR12 );
or VAR2 (VAR4, VAR7, VAR11);
buf VAR3 (VAR1 , VAR4 );
endmodule | apache-2.0 |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_de0_nano_adc_0.v | 5,886 | module MODULE1 (
VAR1,
reset,
read,
write,
VAR4,
VAR19,
address,
VAR17,
VAR3,
VAR7,
VAR11,
VAR12
);
parameter VAR5 = 8'd16;
parameter VAR16 = 4'd4;
input VAR1, reset, read, write;
input [31:0] VAR19;
input [2:0] address;
output reg [31:0] VAR4;
output reg VAR17;
input VAR12;
output VAR3, VAR7, VAR11;
reg VAR13;
reg [11... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi_1.v | 2,350 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR1 ,
VAR5 ,
VAR6 ,
VAR11,
VAR10,
VAR4 ,
VAR7
);
output VAR2 ;
input VAR8 ;
input VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR11;
input VAR10;
input VAR4 ;
input VAR7 ;
VAR9 VAR3 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb.blackbox.v | 1,330 | module MODULE1 (
VAR2 ,
VAR7,
VAR5,
VAR1 ,
VAR4
);
output VAR2 ;
input VAR7;
input VAR5;
input VAR1 ;
input VAR4 ;
supply1 VAR9;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
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