repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_004bits.v | 1,917 | module MODULE2 (
clk,
VAR8, VAR3, VAR25, VAR29, VAR34, VAR14, VAR27, VAR6,
sum,
);
input clk;
input [VAR30+0-1:0] VAR8, VAR3, VAR25, VAR29, VAR34, VAR14, VAR27, VAR6;
output [VAR30 :0] sum;
reg [VAR30 :0] sum;
wire [VAR30+3-1:0] VAR15;
wire [VAR30+2-1:0] VAR21, VAR9;
wire [VAR30+1-1:0] VAR5, VAR31, VAR19, VAR24;
reg [V... | mit |
adamgreig/bladeRF | hdl/fpga/ip/opencores/i2c/bench/verilog/wb_master_model.v | 5,566 | module MODULE1(clk, rst, VAR7, din, dout, VAR6, VAR5, VAR3, sel, ack, VAR1, VAR8);
parameter VAR2 = 32;
parameter VAR9 = 32;
input clk, rst;
output [VAR9 -1:0] VAR7;
input [VAR2 -1:0] din;
output [VAR2 -1:0] dout;
output VAR6, VAR5;
output VAR3;
output [VAR2/8 -1:0] sel;
input ack, VAR1, VAR8;
reg [VAR9 -1:0] VAR7;
reg... | gpl-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/iobs_flow.v | 3,081 | module MODULE1 (
VAR17,
VAR20,
VAR27,
VAR2,
VAR24,
VAR16,
VAR8
);
input VAR17;
input VAR20;
input [1:0] VAR27;
input [1:0] VAR2;
output [1:0] VAR24;
output [1:0] VAR16;
inout [1:0] VAR8;
reg [1:0] VAR16 = 2'b11;
reg VAR12 = 0;
wire VAR6;
wire [1:0] VAR5;
assign VAR24 = VAR10;
assign VAR6 = VAR12 | VAR2;
always @(posedg... | lgpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_p_dst_rows_V_channel.v | 3,019 | module MODULE1 (
clk,
VAR16,
VAR11,
VAR5,
VAR9);
parameter VAR4 = 32'd12;
parameter VAR21 = 32'd2;
parameter VAR10 = 32'd3;
input clk;
input [VAR4-1:0] VAR16;
input VAR11;
input [VAR21-1:0] VAR5;
output [VAR4-1:0] VAR9;
reg[VAR4-1:0] VAR27 [0:VAR10-1];
integer VAR3;
always @ (posedge clk)
begin
if (VAR11)
begin
for (VA... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_qspi_media_2.v | 15,080 | module MODULE1(
input VAR70,
input reset,
output VAR10,
input VAR111,
output VAR115,
output VAR20,
input VAR53,
output VAR113,
output VAR64,
input VAR160,
output VAR50,
output VAR138,
input VAR16,
output VAR38,
output VAR126,
output VAR99,
input [11:0] VAR8,
input VAR83,
input VAR141,
input [7:0] VAR58,
input [7:0] VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a.functional.v | 2,063 | module MODULE1 (
VAR5,
VAR15,
VAR16 ,
VAR9,
VAR17,
VAR4 ,
VAR10
);
input VAR5;
input VAR15;
output VAR16 ;
input VAR9;
input VAR17;
input VAR4 ;
input VAR10 ;
wire VAR10 VAR13 ;
wire VAR10 VAR14 ;
wire VAR6 ;
wire VAR3;
nand VAR11 (VAR13 , VAR17, VAR9 );
or VAR12 (VAR14 , VAR10, VAR4 );
and VAR8 (VAR6 , VAR13, VAR14 );... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_fft_v1_00_a/hdl/verilog/axi_fft.v | 9,091 | module MODULE1 (
VAR41,
VAR46,
VAR13,
VAR94,
VAR78,
VAR95,
VAR115,
VAR25,
VAR4,
VAR107,
VAR89,
VAR73,
VAR99,
VAR37,
VAR70,
VAR22,
VAR48,
VAR75,
VAR51,
VAR119,
VAR61,
VAR65,
VAR50,
VAR98,
VAR113,
VAR57,
VAR35,
VAR15,
VAR88,
VAR8,
VAR21,
VAR91);
parameter VAR55 = 0;
parameter VAR103 = 0;
parameter VAR74 = 0;
parameter VA... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/ks116.v | 10,408 | module MODULE1(VAR2, VAR5, VAR12);
input wire [115:0] VAR2;
input wire [115:0] VAR5;
output wire [230:0] VAR12;
wire [114:0] VAR7;
wire [114:0] VAR11;
wire [114:0] VAR1;
wire [57:0] VAR8;
wire [57:0] VAR6;
VAR10 VAR3(VAR2[57:0], VAR5[57:0], VAR11);
VAR10 VAR9(VAR2[115:58], VAR5[115:58], VAR7);
assign VAR8[57:0] = VAR2[... | gpl-3.0 |
velizarefremov/Rijndael | shiftRows.v | 1,949 | module MODULE1(
output [127:0] VAR1, input [127:0] VAR3, input VAR2 );
assign VAR1[127:120] = VAR3[127:120];
assign VAR1[95:88] = VAR3[95:88];
assign VAR1[63:56] = VAR3[63:56];
assign VAR1[31:24] = VAR3[31:24];
assign VAR1[119:112] = (VAR2)?(VAR3[23:16]):(VAR3[87:80]);
assign VAR1[87:80] = (VAR2)?(VAR3[119:112]):(VAR3[... | gpl-2.0 |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/imports/verilog/AXI_SP32B1024.v | 3,658 | module MODULE1(
input VAR5,
input VAR11,
input VAR6,
output VAR1,
input [32-1:0] VAR8,
input [3-1:0] VAR16,
input VAR24,
output VAR25,
input [32-1:0] VAR30,
input [4-1:0] VAR29,
output VAR7,
input VAR18,
input VAR20,
output VAR17,
input [32-1:0] VAR2,
input [3-1:0] VAR13,
output VAR22,
input VAR15,
output [32-1:0] VAR1... | mit |
alexforencich/xfcp | lib/eth/rtl/lfsr.v | 16,134 | module MODULE1 #
(
parameter VAR14 = 31,
parameter VAR10 = 31'h10000001,
parameter VAR3 = "VAR18",
parameter VAR8 = 0,
parameter VAR17 = 0,
parameter VAR20 = 8,
parameter VAR5 = "VAR21"
)
(
input wire [VAR20-1:0] VAR7,
input wire [VAR14-1:0] VAR1,
output wire [VAR20-1:0] VAR12,
output wire [VAR14-1:0] VAR22
);
reg [VAR... | mit |
LSaldyt/qnp | output/vs/var13_multi.v | 1,141 | module MODULE1 (VAR18, VAR3, VAR7, VAR11, VAR9, VAR19, VAR6, VAR16, VAR4, VAR13, VAR2, VAR1, VAR8, valid);
input VAR18, VAR3, VAR7, VAR11, VAR9, VAR19, VAR6, VAR16, VAR4, VAR13, VAR2, VAR1, VAR8;
output valid;
wire [7:0] VAR14 = 8'd121;
wire [7:0] VAR12 = 8'd60;
wire [7:0] VAR10 = 8'd60;
wire [7:0] VAR17 =
VAR18 * 8'd4... | mit |
olajep/oh | src/adi/hdl/library/xilinx/common/ad_serdes_clk.v | 4,858 | module MODULE1 #(
parameter VAR27 = 0,
parameter VAR4 = 1,
parameter VAR17 = 1,
parameter VAR43 = 8,
parameter VAR15 = 1,
parameter VAR30 = 1.667,
parameter VAR5 = 6,
parameter VAR20 = 12.000,
parameter VAR49 = 2.000,
parameter VAR9 = 6) (
input rst,
input VAR12,
input VAR10,
output clk,
output VAR13,
output VAR21,
out... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41a/sky130_fd_sc_ls__o41a.symbol.v | 1,366 | module MODULE1 (
input VAR6,
input VAR9,
input VAR1,
input VAR2,
input VAR3,
output VAR5
);
supply1 VAR10;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_nsr_pp_pg_n.blackbox.v | 1,636 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR1 ,
VAR4 ,
VAR3 ,
VAR7,
VAR8 ,
VAR6
);
output VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR3 ;
input VAR7;
input VAR8 ;
input VAR6 ;
endmodule | apache-2.0 |
silverneko/dsdl | lab2/Countdowner.v | 1,522 | module MODULE1(VAR3, VAR5, VAR4, VAR1);
input VAR3;
input [31:0] VAR5;
input [2:0] VAR4;
output [31:0] VAR1;
reg [31:0] counter;
reg [1:0] state;
reg [31:0] VAR2;
assign VAR1 = VAR2; | mit |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipitc131_common_to_binary.v | 1,178 | module MODULE1(
VAR9,
VAR10
);
parameter VAR6 = 3;
parameter VAR5 = 2;
input [VAR6-1:0] VAR9;
output [VAR5-1:0] VAR10;
generate
genvar VAR3, VAR7;
wire [(VAR6*VAR5)-1:0] VAR4;
wire [(VAR6*VAR5)-1:0] VAR2;
for(VAR7=0; VAR7<VAR6; VAR7=VAR7+1) begin : VAR8
assign VAR4[(VAR7*VAR5)+(VAR5-1):(VAR7*VAR5)] = (VAR9[VAR7]) ? VAR... | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_drp.v | 38,970 | module MODULE1 #
(
parameter VAR96 = "VAR125", parameter VAR37 = "3.0", parameter VAR18 = "VAR204", parameter VAR136 = "VAR32", parameter VAR126 = "VAR104", parameter VAR56 = "VAR204", parameter VAR33 = "VAR104", parameter VAR26 = 0, parameter VAR46 = 0, parameter VAR186 = 2'd1, parameter VAR105 = 5'd21
)
(
input VAR49... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/src_axi_stream.v | 4,049 | module MODULE1 #(
parameter VAR39 = 3,
parameter VAR5 = 64,
parameter VAR3 = 24,
parameter VAR27 = 4)(
input VAR31,
input VAR33,
input enable,
output VAR40,
input [VAR39-1:0] VAR19,
output [VAR39-1:0] VAR47,
input VAR1,
output VAR26,
input VAR49,
output [VAR39+3-1:0] VAR45,
output VAR30,
input VAR18,
output [VAR27-1:0]... | mit |
Vadman97/ImageAES | vga/decrypter.v | 2,886 | module MODULE1(
input clk,
input reset,
input [7:0] VAR17,
input VAR15,
input [63:0] VAR4,
output reg [14:0] VAR6,
output reg [7:0] VAR18,
output reg [14:0] VAR14,
output reg VAR11
);
wire [63:0] VAR22;
wire [63:0] VAR13;
wire VAR19;
reg VAR16, ack;
VAR3 VAR2 (
.VAR22(VAR22),
.VAR21(VAR4),
.VAR13(VAR13),
.VAR11(VAR19),... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2.behavioral.v | 8,879 | module MODULE1( VAR45, VAR51, VAR50, VAR26, VAR18 );
input VAR45, VAR51, VAR26, VAR50;
output VAR18;
reg VAR34;
VAR37 VAR35(.VAR45(VAR45),.VAR51(VAR51),.VAR50(VAR50),.VAR26(VAR26),.VAR18(VAR18),.VAR34(VAR34));
VAR37 VAR42(.VAR45(VAR45),.VAR51(VAR51),.VAR50(VAR50),.VAR26(VAR26),.VAR18(VAR18),.VAR34(VAR34));
not VAR46(VA... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/SINGLE/FSM_Add_Subtract_syn.v | 5,547 | module MODULE1 ( clk, rst, VAR29, VAR151, VAR21,
VAR121, VAR27, VAR105, VAR85, VAR64,
VAR115, VAR113, VAR70, VAR124, VAR83, VAR103,
VAR90, VAR22, VAR95, VAR79, VAR147, VAR107,
VAR88, VAR120, VAR73, ready );
output [1:0] VAR147;
input clk, rst, VAR29, VAR151, VAR21, VAR121,
VAR27, VAR105;
output VAR85, VAR64, VAR115, VA... | gpl-3.0 |
bluespec/Flute | builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkBoot_ROM.v | 57,603 | module MODULE1(VAR153,
VAR84,
VAR130,
VAR35,
VAR134,
VAR32,
VAR178,
VAR146,
VAR135,
VAR167,
VAR168,
VAR102,
VAR162,
VAR100,
VAR79,
VAR150,
VAR61,
VAR110,
VAR60,
VAR74,
VAR174,
VAR53,
VAR93,
VAR142,
VAR43,
VAR40,
VAR9,
VAR85,
VAR132,
VAR149,
VAR90,
VAR19,
VAR143,
VAR154,
VAR96,
VAR59,
VAR105,
VAR108,
VAR103,
VAR175,
VAR... | apache-2.0 |
mshaklunov/mips_onemore | rtl/mips_instr_decoder.v | 32,722 | module MODULE1 #(parameter VAR127=32'h80000000)
(
input VAR58,
output VAR59,
output VAR148,
output VAR82,
output VAR132,
input[5:0] VAR62,
input[4:0] VAR137,
input[4:0] VAR141,
input[4:0] VAR6,
input[4:0] VAR74,
input[5:0] VAR118,
input VAR37,
input[31:0] VAR65,
input[31:0] VAR77,
input[63:0] VAR99,
input[31:0] VAR19,
... | mit |
TAUTIC/VGA_Controller | VGA_Memory_Controller.v | 2,915 | module MODULE1
(
VAR9, VAR6, VAR1, VAR12, VAR4, VAR10, VAR8
);
input wire VAR9;
input wire [0:9] VAR6;
output reg [0:3] VAR1;
output reg [0:3] VAR12;
output reg [0:3] VAR4;
output reg [0:0] VAR10;
output reg [0:0] VAR8;
reg [0:10] VAR3;
reg [0:9] VAR2;
reg [0:0] VAR7;
reg [0:0] VAR5;
reg [0:0] VAR11;
reg [0:9] VAR13;
b... | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_spigpioport_1.v | 4,352 | module MODULE1(
input VAR15,
input reset,
input VAR20,
output VAR37,
input VAR6,
input VAR3,
output VAR53,
input VAR29,
input VAR35,
output VAR45,
input VAR8,
input VAR9,
output VAR51,
input VAR54,
input VAR28,
input VAR10,
input VAR23,
output VAR7,
output VAR1,
output VAR16,
output VAR25,
output VAR40,
input VAR22,
ou... | apache-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/inband_lib/rx_buffer_inband.v | 5,391 | module MODULE1
( input VAR21,
input VAR32,
input reset, input VAR30, output [15:0] VAR36,
input VAR41,
output wire VAR40,
output reg VAR55,
input wire [3:0] VAR58,
input wire [15:0] VAR70,
input wire [15:0] VAR24,
input wire [15:0] VAR15,
input wire [15:0] VAR12,
input wire [15:0] VAR20,
input wire [15:0] VAR73,
input ... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/rx_engine_ultrascale.v | 10,604 | module MODULE1
( input VAR43,
input VAR10, input VAR50, output VAR22,
output VAR60,
input VAR41,
input VAR55,
input [VAR38-1:0] VAR56,
input [(VAR38/32)-1:0] VAR69,
input [VAR18-1:0] VAR39,
output VAR65,
input VAR29,
input VAR72,
input [VAR38-1:0] VAR49,
input [(VAR38/32)-1:0] VAR26,
input [VAR35-1:0] VAR15,
output VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf_12.v | 1,999 | module MODULE2 (
VAR8 ,
VAR6 ,
VAR7,
VAR2,
VAR1 ,
VAR5
);
output VAR8 ;
input VAR6 ;
input VAR7;
input VAR2;
input VAR1 ;
input VAR5 ;
VAR4 VAR3 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR8,
VAR6
);
output VAR8;
input VAR6;
supply1 VAR7;
supply0 VAR2;... | apache-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/new/AXI_BRAM.v | 5,229 | module MODULE1(
input VAR15, input VAR5,
input VAR59,
output VAR44,
input [32-1:0] VAR47,
input [3-1:0] VAR25,
input VAR51,
output VAR49,
input [32-1:0] VAR7,
input [4-1:0] VAR2,
output reg VAR12,
input VAR36,
input VAR41,
output VAR37,
input [32-1:0] VAR34,
input [3-1:0] VAR16,
output reg VAR58,
input VAR20,
output re... | mit |
jhennessy/parallella-hw-old | boards/archive/gen1.1/fpga/hdl/axi_master_wr.v | 13,262 | module MODULE1 (
VAR10, VAR16, VAR67, VAR62, VAR11, VAR30, VAR38, VAR54,
VAR73, VAR84, VAR51, VAR40, VAR14, VAR13, VAR79,
VAR85,
VAR8, VAR87, reset, VAR21, VAR42, VAR59, VAR83, VAR28,
VAR7, VAR33, VAR70,
VAR12, VAR4, VAR75,
VAR24
);
parameter VAR9 = 6; parameter VAR35 = 32; parameter VAR44 = 64; parameter VAR63 = VAR35... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/rep_jbi_sc2_2.v | 2,844 | module MODULE1(
VAR8, VAR14, VAR4,
VAR12, VAR16,
VAR1, VAR3,
VAR5, VAR11,
VAR17, VAR18, VAR2, VAR9,
VAR13, VAR10, VAR15,
VAR7, VAR6
);
output [31:0] VAR8;
output [31:0] VAR14;
output [6:0] VAR4;
output VAR12;
output VAR16;
output VAR1;
output VAR3;
output VAR5;
output VAR11;
input [31:0] VAR17;
input [31:0] VAR18;
inpu... | gpl-2.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/vga_controller.v | 2,489 | module MODULE1(
input wire clk, input wire [9:0] VAR11,
input wire [8:0] VAR40,
input wire [32:0] VAR26,
output wire [2:0] VAR13, output wire [2:0] VAR15, output wire [1:0] VAR32, output wire VAR24, output wire VAR27 );
wire [9:0] hc; wire [9:0] VAR33; wire [9:0] VAR19; wire [8:0] VAR5; wire [7:0] VAR2, VAR9; wire [4:0... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.behavioral.pp.v | 5,425 | module MODULE1( VAR5, VAR8, VAR2, VAR10, VAR12, VAR6, VAR1, VAR4, VAR7 );
input VAR12, VAR6, VAR1, VAR2, VAR8, VAR5;
inout VAR4, VAR7;
output VAR10;
VAR9 VAR3(.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),.VAR10(VAR10),.VAR12(VAR12),.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4),.VAR7(VAR7));
VAR9 VAR11(.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),... | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/prcfg/bist/prcfg_adc.v | 5,227 | module MODULE1 (
clk,
VAR25,
VAR12,
VAR1,
VAR6,
VAR23,
VAR19,
VAR28,
VAR2
);
localparam VAR16 = 8'hA1;
parameter VAR24 = 0;
input clk;
input [31:0] VAR25;
output [31:0] VAR12;
input VAR1;
input VAR6;
input [15:0] VAR23;
output VAR19;
output VAR28;
output [15:0] VAR2;
reg VAR19;
reg VAR28;
reg [15:0] VAR2;
reg [31:0] VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2.symbol.v | 1,423 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR7
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
tta/gnuradio-tta | gr-radar-mono/src/fpga/lib/radar.v | 3,494 | module MODULE1(VAR47,VAR4,VAR32,VAR36,
VAR28,VAR17,VAR23,VAR38,
VAR50,VAR22,
VAR7,VAR19,VAR46,VAR40);
input VAR47; input [6:0] VAR4; input [31:0] VAR32; input VAR36;
output VAR28; output VAR17; output [13:0] VAR23; output [13:0] VAR38; output VAR40;
input [15:0] VAR50; input [15:0] VAR22; output VAR7; output [15:0] VAR... | gpl-3.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/code/Dynamic_Controller.v | 10,130 | module MODULE1( VAR78,VAR1,VAR23,VAR106,VAR84,
VAR43,VAR116,VAR111,VAR108,VAR24,VAR17,VAR10,VAR27,VAR118,VAR65,VAR59,
VAR107,VAR87,VAR105,VAR47,VAR112,VAR13,VAR54,VAR15,VAR72);
input VAR78;
input VAR1;
input VAR23;
input VAR106;
input VAR84;
input VAR43;
input [127:0] VAR116;
input VAR111;
input VAR108;
input [255:0] V... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v | 5,302 | module MODULE1(
din,
VAR73,
VAR36,
rst,
VAR65,
VAR58,
dout,
VAR24,
VAR70,
VAR71,
VAR94);
input [18 : 0] din;
input VAR73;
input VAR36;
input rst;
input VAR65;
input VAR58;
output [18 : 0] dout;
output VAR24;
output VAR70;
output [4 : 0] VAR71;
output [4 : 0] VAR94;
VAR35 #(
.VAR79(0),
.VAR104(0),
.VAR34(5),
.VAR40("VAR... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_axi_lite_module.v | 8,988 | module MODULE1
(
VAR48,
VAR17,
VAR64,
VAR36,
VAR3,
VAR32,
VAR22,
VAR40,
VAR10,
VAR49,
VAR37,
VAR13,
VAR23,
VAR33,
VAR60,
VAR53,
VAR26,
VAR56,
VAR4,
VAR54,
VAR28,
VAR42,
VAR39,
VAR50,
VAR46
);
input VAR48;
input VAR17; input [31:0] VAR64; input VAR36; input [31:0] VAR3; input [3:0] VAR32; input VAR22; input VAR40; input... | gpl-3.0 |
drichmond/riffa | fpga/xilinx/vc707/VC707_Gen2x8If128/hdl/VC707_Gen2x8If128.v | 20,945 | module MODULE1
parameter VAR45 = 8,
parameter VAR123 = 128,
parameter VAR86 = 256,
parameter VAR93 = 6
)
(output [(VAR45 - 1) : 0] VAR33,
output [(VAR45 - 1) : 0] VAR124,
input [(VAR45 - 1) : 0] VAR110,
input [(VAR45 - 1) : 0] VAR100,
output [3:0] VAR126,
input VAR175,
input VAR57,
input VAR71
);
wire VAR32;
wire VAR18... | bsd-3-clause |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/bank_cntrl.v | 25,514 | module MODULE1 #
(
parameter VAR118 = 100,
parameter VAR136 = "1T",
parameter VAR33 = 3,
parameter VAR58 = 2,
parameter VAR1 = "8",
parameter VAR135 = 12,
parameter VAR85 = 5,
parameter VAR42 = 8,
parameter VAR140 = "VAR129",
parameter VAR20 = "VAR18",
parameter VAR44 = 4,
parameter VAR100 = 4,
parameter VAR137 = 2,
pa... | mit |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_charSent.v | 2,207 | module MODULE1 (
address,
VAR9,
clk,
VAR6,
VAR4,
VAR8,
VAR5,
VAR3
)
;
output VAR5;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR6;
input VAR4;
input [ 31: 0] VAR8;
wire VAR2;
reg VAR1;
wire VAR5;
wire VAR7;
wire [ 31: 0] VAR3;
assign VAR2 = 1;
assign VAR7 = {1 {(address == 0)}} & VAR1;
a... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | wwp/prog_counter2.v | 1,429 | module MODULE1 (VAR1,rst,clk);
output [0:31] VAR1;
input clk;
input rst;
reg [0:31] VAR1; reg [0:31] VAR2;
always @(posedge clk)
begin
if(rst)
begin
VAR1<=32'd0;
VAR2<=32'd0;
end
else
begin
VAR2<=VAR2+32'd4;
VAR1<=VAR2>>2;
end
end
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.functional.v | 1,360 | module MODULE1( VAR15, VAR6, VAR10, VAR7 );
input VAR10, VAR15, VAR7;
output VAR6;
wire VAR9;
not VAR3( VAR9, VAR10 );
wire VAR2;
not VAR13( VAR2, VAR7 );
wire VAR5;
and VAR4( VAR5, VAR9, VAR2 );
wire VAR8;
not VAR14( VAR8, VAR15 );
wire VAR1;
and VAR12( VAR1, VAR8, VAR2 );
or VAR11( VAR6, VAR5, VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/diode/sky130_fd_sc_lp__diode.symbol.v | 1,245 | module MODULE1 (
input VAR5
);
supply1 VAR4;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_switches.v | 1,911 | module MODULE1 (
address,
clk,
VAR5,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR5;
input VAR3;
wire VAR6;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR4;
reg [ 31: 0] VAR1;
assign VAR6 = 1;
assign VAR4 = {8 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR3)
begin
if (VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb.pp.blackbox.v | 1,351 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR6 ,
VAR4 ,
VAR5 ,
VAR1,
VAR3,
VAR8 ,
VAR9
);
output VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR1;
input VAR3;
input VAR8 ;
input VAR9 ;
endmodule | apache-2.0 |
asciilifeform/Stierlitz | ml501/stierlitz.v | 8,786 | module MODULE1
(clk,
reset,
enable,
VAR33,
VAR20,
VAR6,
VAR30,
VAR27,
VAR4,
VAR9,
VAR7,
VAR23,
VAR36,
VAR21,
VAR19
);
localparam [1:0]
VAR22 = 2'b00,
VAR17 = 2'b01,
VAR13 = 2'b10,
VAR34 = 2'b11;
localparam [2:0]
VAR28 = 0,
VAR25 = 1,
VAR18 = 2,
VAR14 = 3,
VAR35 = 4,
VAR5 = 5,
VAR32 = 6,
VAR24 = 7;
input wire clk;
input... | gpl-3.0 |
cathalmccabe/PYNQ | boards/ip/io_switch_1.1/hdl/io_switch_v1_1.v | 5,829 | module MODULE1 #
(
parameter VAR43=4, parameter VAR57 = 28,
parameter VAR28 = 6,
parameter VAR35 = 8,
parameter VAR72 = 2,
parameter integer VAR6 = 32,
parameter integer VAR83 = 6
)
(
input [VAR57-1:0] VAR99,
output [VAR57-1:0] VAR26,
output [VAR57-1:0] VAR79,
output [VAR57-1:0] VAR93,
input [VAR57-1:0] VAR39,
input [V... | bsd-3-clause |
spike556/HuffmanCode | rtl model/sortnet/BitonicSortX8.v | 2,066 | module MODULE1 # (
parameter VAR23 = 18,
parameter VAR16 = 8
)(
input [VAR23-1:0] VAR25,
input [VAR23-1:0] VAR7,
input [VAR23-1:0] VAR36,
input [VAR23-1:0] VAR21,
input [VAR23-1:0] VAR4,
input [VAR23-1:0] VAR14,
input [VAR23-1:0] VAR11,
input [VAR23-1:0] VAR2,
output wire [VAR23-1:0] VAR12,
output wire [VAR23-1:0] VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3.blackbox.v | 1,296 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR2;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
sirchuckalot/zet-ng | rtl/zet_wb_master.v | 5,742 | module MODULE1 (
input clk,
input rst,
input [19:0] VAR19,
output reg [15:0] VAR32,
input VAR13,
input VAR28,
output reg VAR22,
input [19:0] VAR1,
output reg [15:0] VAR21,
input [15:0] VAR26,
input VAR27,
input VAR29,
input VAR15,
output reg VAR10,
input VAR16,
input [15:0] VAR18,
output reg [15:0] VAR3,
output reg [19... | gpl-3.0 |
ptracton/wb_soc_template | rtl/LM32/rtl/jtag_tap_spartan6.v | 1,957 | module MODULE1(
output VAR1,
output VAR8,
input VAR5,
output VAR20,
output VAR10,
output reset
);
wire VAR4;
wire VAR19;
wire sel;
assign VAR20 = VAR4 & sel;
assign VAR10 = VAR19 & sel;
VAR11 #(
.VAR2(1)
) VAR3 (
.VAR21(),
.VAR16(VAR1),
.VAR9(reset),
.VAR6(),
.VAR7(sel),
.VAR14(VAR4),
.VAR17(),
.VAR15(VAR8),
.VAR18(),
... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_piso_1.v | 24,171 | module MODULE1(
clk ,
VAR5 ,
VAR65 ,
VAR30 ,
VAR28 ,
VAR57 ,
VAR66 ,
VAR4 ,
VAR60 ,
VAR14 ,
VAR39 ,
VAR19 ,
VAR48 ,
VAR46 ,
VAR53 ,
VAR17 ,
VAR41 ,
VAR59 ,
VAR29 ,
VAR56 ,
VAR23 ,
VAR12 ,
VAR47 ,
VAR54 ,
VAR38
);
input clk ; input VAR5 ; input [3:0] VAR65 ; input [10:0] VAR30 ; input [10:0] VAR28 ; input [10:0] VAR57 ;... | gpl-3.0 |
sam-falvo/remex | example/rtl/alu.v | 2,559 | module MODULE1(
input [63:0] VAR12,
input [63:0] VAR3,
input VAR5,
input VAR24,
input VAR23,
input VAR26,
input VAR37,
input VAR38,
input VAR21,
input VAR7, input VAR43, output [63:0] VAR8,
output VAR31,
output VAR33,
output VAR42
);
wire [63:0] VAR20 = VAR3 ^ ({64{VAR37}});
wire [63:0] VAR11 = VAR12[62:0] + VAR20[62:0... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2.behavioral.pp.v | 1,827 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR12 ,
VAR2,
VAR4,
VAR13 ,
VAR10
);
output VAR3 ;
input VAR8 ;
input VAR12 ;
input VAR2;
input VAR4;
input VAR13 ;
input VAR10 ;
wire VAR5 ;
wire VAR9;
xnor VAR11 (VAR5 , VAR8, VAR12 );
VAR7 VAR6 (VAR9, VAR5, VAR2, VAR4);
buf VAR1 (VAR3 , VAR9 );
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/DEBUG_VERILOG/write_axi.v | 1,722 | module MODULE1(
input VAR3,
input VAR2,
input VAR4,
input [13:0] VAR1,
output reg [13:0] VAR5
);
always@(posedge VAR2 or negedge VAR4 )
begin
if(!VAR4)
begin
VAR5 <= 14'd0;
end
else
begin
if(VAR3)
VAR5 <= VAR1;
end
else
VAR5 <= VAR5;
end
end
endmodule | gpl-3.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_rst_ps7_0_49M_0/gcd_zynq_snick_rst_ps7_0_49M_0_stub.v | 1,923 | module MODULE1(VAR2, VAR9, VAR7,
VAR3, VAR6, VAR10, VAR1, VAR4,
VAR5, VAR8)
;
input VAR2;
input VAR9;
input VAR7;
input VAR3;
input VAR6;
output VAR10;
output [0:0]VAR1;
output [0:0]VAR4;
output [0:0]VAR5;
output [0:0]VAR8;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2.pp.symbol.v | 1,322 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR3 ,
input VAR6,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3b/sky130_fd_sc_ms__or3b_2.v | 2,209 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR4 ,
VAR10 ,
VAR2,
VAR9,
VAR1 ,
VAR8
);
output VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR10 ;
input VAR2;
input VAR9;
input VAR1 ;
input VAR8 ;
VAR7 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/amber25/a25_coprocessor.v | 8,844 | module MODULE1
(
input VAR25,
input VAR1, input [2:0] VAR12,
input [2:0] VAR5,
input [3:0] VAR15, input [3:0] VAR10,
input [3:0] VAR26,
input [1:0] VAR14,
input [31:0] VAR23,
input VAR18, input [7:0] VAR6,
input [31:0] VAR19,
output reg [31:0] VAR27,
output VAR17,
output VAR2,
output [31:0] VAR24
);
reg [2:0] VAR21 = 3... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp.pp.symbol.v | 1,386 | module MODULE1 (
input VAR8 ,
output VAR5 ,
input VAR6,
input VAR3 ,
input VAR4 ,
input VAR7 ,
input VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
jayant-sharma/uart | hdl/fsm_ADC.v | 2,152 | module MODULE1
(
input clk,
input rst,
input rd,
input wr,
input [6:0] addr,
input [15:0] VAR7,
output reg [15:0] VAR2,
output reg valid,
input VAR13,
input VAR10,
input VAR6,
input VAR12,
input VAR4,
input [4:0] VAR3,
input [15:0] dout,
output reg VAR9,
output reg VAR5,
output reg [6:0] VAR1,
output reg [15:0] din
);
... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcin/sky130_fd_sc_hs__fahcin.symbol.v | 1,294 | module MODULE1 (
input VAR5 ,
input VAR7 ,
input VAR4 ,
output VAR6,
output VAR3
);
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/Bluetooth/UART_tx.v | 2,551 | module MODULE1(clk,VAR2,VAR3,VAR8,VAR11,VAR14,VAR10);
input clk;
input VAR2;
input VAR8; input [7:0] VAR14; input VAR10; output VAR11; output VAR3;
reg VAR16,VAR6,VAR12; wire VAR5;
always @(posedge clk or negedge VAR2) begin
if(!VAR2) begin
VAR16 <= 1'b0;
VAR6 <= 1'b0;
VAR12 <= 1'b0;
end
else begin
VAR16 <= VAR10;
VAR6... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3_1.v | 2,174 | module MODULE2 (
VAR8 ,
VAR2 ,
VAR6 ,
VAR1 ,
VAR3,
VAR5,
VAR7 ,
VAR10
);
output VAR8 ;
input VAR2 ;
input VAR6 ;
input VAR1 ;
input VAR3;
input VAR5;
input VAR7 ;
input VAR10 ;
VAR9 VAR4 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf_1.v | 1,993 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR8,
VAR4,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR6 ;
input VAR8;
input VAR4;
input VAR2 ;
input VAR7 ;
VAR5 VAR1 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR6
);
output VAR3;
input VAR6;
supply1 VAR8;
supply0 VAR4;... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/small_hb_int.v | 2,977 | module MODULE1
(input clk,
input rst,
input VAR19,
input VAR8,
input [VAR2-1:0] VAR17,
input [7:0] VAR13,
input VAR21,
output reg [VAR2-1:0] VAR28);
reg VAR34;
reg [VAR2-1:0] VAR39, VAR45, VAR47, VAR36, VAR20, VAR46;
localparam VAR29 = 36;
wire [VAR29-1:0] VAR26;
reg [6:0] VAR40;
always @(posedge clk)
VAR40 <= {VAR40[5... | gpl-2.0 |
Valakor/EE201-Text-Editor | hvsync_generator.v | 1,719 | module MODULE1(clk, reset,VAR4, VAR6, VAR7, VAR1, VAR5);
input clk;
input reset;
output VAR4, VAR6;
output VAR7;
output [9:0] VAR1;
output [9:0] VAR5;
reg [9:0] VAR1;
reg [9:0] VAR5;
reg VAR3, VAR2;
reg VAR7;
always @(posedge clk)
begin
if(reset)
VAR1 <= 0;
end
else if(VAR1==10'h320) VAR1 <= 0;
else
VAR1 <= VAR1 + 1'b1... | mit |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/PackAdder.v | 1,590 | module MODULE1(
input VAR5,
input [31:0] VAR4,
input [27:0] VAR6,
input VAR3,
output reg [31:0] VAR2
);
parameter VAR1 = 1'b0,
VAR9 = 1'b1;
wire VAR7;
wire [7:0] VAR8;
assign VAR7 = VAR4[31];
assign VAR8 = VAR4[30:23];
always @ (posedge VAR3)
begin
if (VAR5 != VAR9) begin
VAR2[22:0] <= VAR6[25:3];
VAR2[30:23] <= VAR8 +... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/timer/timer.v | 1,297 | module MODULE1 #
(
parameter VAR13 = 64,
parameter VAR8 = 0,
parameter VAR10 = 2
)
(
input clk,
input VAR6,
input VAR5,
input [VAR10-1:0] VAR14, input [VAR13-1:0] VAR3,
input VAR1,
input VAR2,
input [VAR13/8-1:0] VAR15,
output VAR4,
output [VAR13-1:0] VAR9,
output VAR11
);
reg [VAR13-1:0] counter;
reg [VAR13-1:0] VAR7;... | mit |
jairov4/accel-oil | solution_spartan3/syn/verilog/nfa_accept_samples_generic_hw_add_6ns_6ns_6_2.v | 3,958 | module MODULE2(clk, reset, VAR16, VAR13, VAR10, VAR15);
input clk;
input reset;
input VAR16;
input [6 - 1 : 0] VAR13;
input [6 - 1 : 0] VAR10;
output [6 - 1 : 0] VAR15;
wire [6 - 1 : 0] VAR34;
wire [6 - 1 : 0] VAR18;
wire [3 - 1 : 0] VAR21;
wire [3 - 1 : 0] VAR29;
wire [6 - 1 : 3] VAR26;
wire [6 - 1 : 3] VAR31;
reg [3 ... | lgpl-3.0 |
praveendath92/securePUF | source/puf_files/PDL_PUF.v | 1,625 | module MODULE1(VAR16, VAR12, VAR7, reset, VAR13);
parameter VAR4 = 63;
input [VAR4:0] VAR16, VAR12;
input VAR7, reset;
output VAR13;
wire [VAR4:0] VAR5,VAR21;
wire VAR9, VAR3;
VAR24 #(
.VAR20(2'b10) ) VAR19 (
.VAR23(VAR9), .VAR10(VAR7) );
VAR15 VAR17 [VAR4:0] (.VAR5({VAR9,VAR5[VAR4:1]}),.VAR21({VAR9,VAR21[VAR4:1]}), .V... | gpl-2.0 |
agnicol88/Gaussian_Num_Gen | Vivado/gng/gng.srcs/sources_1/new/mask_to_zero.v | 2,106 | module MODULE1(
input clk,
input [14:0] VAR3,
input [5:0] VAR1,
output [14:0] VAR2
);
wire [14:0] VAR5;
reg [14:0] VAR4 = 15'd0;
reg [14:0] VAR6 = 15'd0;
assign VAR5 = {VAR3[0], VAR3[1], VAR3[2], VAR3[3], VAR3[4],
VAR3[5], VAR3[6], VAR3[7], VAR3[8], VAR3[9],
VAR3[10], VAR3[11], VAR3[12], VAR3[13], VAR3[14]};
always @ (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxbp/sky130_fd_sc_hs__sdfxbp.pp.symbol.v | 1,401 | module MODULE1 (
input VAR2 ,
output VAR8 ,
output VAR3 ,
input VAR5 ,
input VAR7 ,
input VAR6 ,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | deco_hold_registros.v | 10,198 | module MODULE1(
input VAR12,
input [7:0] VAR7,
input [1:0] VAR5,
output reg VAR13,
output reg VAR3,
output reg VAR6,
output reg VAR1,
output reg VAR11,
output reg VAR8,
output reg VAR9,
output reg VAR4,
output reg VAR2,
output reg VAR10
);
always@*
begin
case(VAR5)
2'b00: if (VAR12) begin
case(VAR7)
8'h03: begin
VAR13 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fah/sky130_fd_sc_hd__fah.blackbox.v | 1,297 | module MODULE1 (
VAR9,
VAR6 ,
VAR5 ,
VAR2 ,
VAR1
);
output VAR9;
output VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
supply1 VAR3;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/vga/vcrt.v | 15,605 | module MODULE1
(
input VAR58,
input VAR83,
input VAR9,
input VAR57, input VAR33, input VAR50, input [15:0] VAR38, input [5:0] VAR18, input [7:0] VAR11, input VAR71, input VAR3, input VAR7, input VAR91, input VAR80, input VAR61, input VAR1, input VAR64, input VAR62,
input VAR37,
input [15:8] VAR53, input VAR28,
output r... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/bram_patch/BRAM2_cur.v | 3,809 | module MODULE1(VAR16,
VAR3,
VAR12,
VAR17,
VAR13,
VAR19,
VAR10,
VAR1,
VAR20,
VAR11,
VAR4,
VAR18
);
parameter VAR14 = 0;
parameter VAR8 = 1;
parameter VAR21 = 1;
parameter VAR9 = 1;
input VAR16;
input VAR3;
input VAR12;
input [VAR8-1:0] VAR17;
input [VAR21-1:0] VAR13;
output [VAR21-1:0] VAR19;
input VAR10;
input VAR1;
in... | lgpl-3.0 |
ankitshah009/Double_base_Number_system_parallel_adder | DBNS_Project_files_ISE/case.v | 39,552 | module MODULE1(
VAR4,
VAR2,
VAR6,
VAR1,
VAR3,
out
);
input wire VAR2;
input wire [1:0] VAR4;
output wire [1:0] VAR6;
input wire [3:0] VAR1;
input wire [3:0] VAR3;
output reg [3:0] out;
reg [1:0] VAR5;
assign VAR6 = VAR5;
always@(posedge VAR2)
begin
if(VAR4 == 2'b00)
begin
if(VAR1 == 4'b0000)
begin
case (VAR3)
4'b0000 :... | apache-2.0 |
himingway/PIC16C5x | src/PIC16C55.v | 4,306 | module MODULE1 (
input clk , input VAR38, inout [VAR40 - 1:0] VAR72,
inout [VAR7 - 1:0] VAR19,
inout [VAR22 - 1:0] VAR20
);
wire [VAR59-1:0] VAR8;
wire [VAR43-1:0] VAR3;
wire [VAR77-1:0] VAR75;
wire [VAR88-1:0] VAR60;
wire [VAR84-1:0] VAR57;
wire [VAR88-1:0] VAR37;
wire [VAR88-1:0] VAR1;
wire [VAR66-1:0] VAR46;
wire [2... | mit |
kielfriedt/ece472 | lab4/reg32.v | 1,080 | module MODULE1 (clk, reset, din, dout);
input clk, reset;
input [31:0] din;
output [31:0] dout;
reg [31:0] dout;
always @(posedge clk)
begin
if (reset) dout <= 0;
end
else dout <= din;
end
endmodule | gpl-3.0 |
Canaan-Creative/MM | verilog/superkdf9/components/uart_core/modem.v | 5,274 | module MODULE1 #(parameter VAR13 = 8)
(
input reset,
input clk,
output [VAR13-1:0] VAR14, input [1:0] VAR1,
input VAR2,
input VAR4, input VAR8, input VAR5, input VAR10, output VAR11, output VAR15 );
reg [VAR13-1:0] VAR7;
reg VAR9;
reg VAR3;
reg VAR12;
reg VAR6;
assign VAR11 = ~VAR1[0];
assign VAR15 = ~VAR1[1];
assign V... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2/sky130_fd_sc_hs__or2.pp.blackbox.v | 1,201 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR3,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR3;
input VAR5;
endmodule | apache-2.0 |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_xbar_0/synth/week1_xbar_0.v | 19,676 | module MODULE1 (
VAR77,
VAR122,
VAR53,
VAR19,
VAR81,
VAR125,
VAR80,
VAR110,
VAR3,
VAR32,
VAR54,
VAR113,
VAR29,
VAR111,
VAR84,
VAR45,
VAR92,
VAR88,
VAR87,
VAR104,
VAR86,
VAR26,
VAR35,
VAR70,
VAR97,
VAR8,
VAR11,
VAR21,
VAR115,
VAR114,
VAR17,
VAR83,
VAR100,
VAR106,
VAR74,
VAR128,
VAR47,
VAR127,
VAR56,
VAR108
);
input wire... | lgpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fme/fme_ip_quarter_ver.v | 62,903 | module MODULE1 (
clk ,
VAR355 ,
VAR52 ,
VAR10 ,
VAR373 ,
VAR61 ,
VAR431 ,
VAR60 ,
VAR403 ,
VAR104 ,
VAR187 ,
VAR227 ,
VAR313 ,
VAR108 ,
VAR374 ,
VAR332 ,
VAR73 ,
VAR413 ,
VAR111 ,
VAR35 ,
VAR456 ,
VAR113 ,
VAR202 ,
VAR138 ,
VAR354 ,
VAR194 ,
VAR324 ,
VAR160 ,
VAR81 ,
VAR390 ,
VAR442 ,
VAR210 ,
VAR279 ,
VAR471 ,
VAR233 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2_lp.v | 2,125 | module MODULE2 (
VAR6 ,
VAR5 ,
VAR8 ,
VAR9,
VAR3,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR9;
input VAR3;
input VAR1 ;
input VAR2 ;
VAR4 VAR7 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6,
VAR5,
VAR8
);
output VAR6;
... | apache-2.0 |
FuzzyLogic/Trivium | hdl/src/trivium_top.v | 6,465 | module MODULE1(
input wire VAR18,
input wire VAR12,
input wire [31:0] VAR3,
input wire [31:0] VAR4,
input wire [2:0] VAR15,
input wire [2:0] VAR13,
input wire VAR16,
input wire VAR21,
output reg [31:0] VAR20,
output wire VAR7
);
reg [2:0] VAR5;
reg [2:0] VAR8;
reg [10:0] VAR19;
reg VAR2;
reg [31:0] VAR23;
wire VAR10;
i... | lgpl-3.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_led_pio.v | 2,257 | module MODULE1 (
address,
VAR7,
clk,
VAR3,
VAR9,
VAR6,
VAR8,
VAR4
)
;
output [ 3: 0] VAR8;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR7;
input clk;
input VAR3;
input VAR9;
input [ 31: 0] VAR6;
wire VAR5;
reg [ 3: 0] VAR2;
wire [ 3: 0] VAR8;
wire [ 3: 0] VAR1;
wire [ 31: 0] VAR4;
assign VAR5 = 1;
assign VAR1 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/conb/sky130_fd_sc_hd__conb.pp.symbol.v | 1,268 | module MODULE1 (
output VAR1 ,
output VAR4 ,
input VAR2 ,
input VAR5,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
lsnow/mips32 | div.v | 2,135 | module MODULE1(
VAR15, VAR3, VAR9,
clk, VAR7, VAR2, VAR6, VAR4
);
input clk, VAR7;
input [31:0] VAR2, VAR6;
input VAR4;
output [31:0] VAR15, VAR3;
output VAR9;
reg VAR9;
wire [32:0] VAR10;
wire [31:0] VAR11;
reg [31:0] VAR13;
reg [31:0] VAR14;
reg [31:0] VAR12;
reg [5:0] VAR8;
reg VAR1;
reg VAR5;
always @(posedge clk) ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_2.functional.pp.v | 2,125 | module MODULE1( VAR15, VAR5, VAR14, VAR13, VAR1, VAR4, VAR24, VAR25 );
input VAR1, VAR4, VAR13, VAR5, VAR14;
inout VAR24, VAR25;
output VAR15;
wire VAR10;
not VAR16( VAR10, VAR1 );
wire VAR3;
not VAR20( VAR3, VAR13 );
wire VAR8;
not VAR7( VAR8, VAR14 );
wire VAR19;
and VAR6( VAR19, VAR10, VAR3, VAR8 );
wire VAR21;
not ... | apache-2.0 |
YosysHQ/yosys | techlibs/machxo2/cells_map.v | 1,369 | module MODULE6 (VAR32, VAR35);
parameter VAR21 = 0;
parameter VAR4 = 0;
input [VAR21-1:0] VAR32;
output VAR35;
localparam VAR13 = 1<<(4-VAR21);
wire [3:0] VAR30;
generate
if(VAR21 == 1) begin
assign VAR30 = {1'b0, 1'b0, 1'b0, VAR32[0]};
end else if(VAR21 == 2) begin
assign VAR30 = {1'b0, 1'b0, VAR32[1], VAR32[0]};
end ... | isc |
FrankMuenzner/proxmark3 | fpga/fpga.v | 8,024 | module MODULE1(
VAR44, VAR72, VAR6, VAR129,
VAR95, VAR113, VAR15,
VAR116, VAR73, VAR9, VAR48, VAR98, VAR108,
VAR137, VAR41, VAR70,
VAR53, VAR107, VAR55, VAR20,
VAR64, VAR94,
VAR2
);
input VAR44, VAR6, VAR129;
output VAR72;
input VAR95, VAR113, VAR15;
output VAR116, VAR73, VAR9, VAR48, VAR98, VAR108;
input [7:0] VAR137;... | gpl-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/board/mem_splitter/acl_iface_address_to_bankaddress.v | 2,012 | module MODULE1 #(
parameter integer VAR7 = 32, parameter integer VAR6 = 2, parameter integer VAR5 = VAR7-VAR3(VAR6)
)
(
input logic [VAR7-1:0] address,
output logic [VAR6-1:0] VAR2, output logic [VAR3(VAR6)-1:0] VAR1, output logic [VAR7-VAR3(VAR6)-1:0] VAR8
);
integer VAR9;
logic [VAR7:0] VAR4;
assign VAR4 = {1'b0,addr... | mit |
ncos/Xilinx-Verilog | SINGEN/src/sandbox.v | 2,126 | module MODULE1
(
input wire VAR8,
output wire [7:0] VAR43,
input wire [7:0] VAR28,
output wire [7:0] VAR30,
input wire [7:0] VAR29,
input wire VAR37,
input wire VAR24,
input wire VAR2,
input wire VAR3,
input wire VAR21
);
wire VAR39;
wire VAR25;
reg VAR15 = 1'b0;
reg VAR23 = 1'b0;
reg VAR1 = 1'b1;
reg VAR10 = 1'b0;
reg... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms1/ac701/system_top.v | 9,679 | module MODULE1 (
VAR22,
VAR44,
VAR62,
VAR15,
VAR108,
VAR26,
VAR74,
VAR94,
VAR43,
VAR118,
VAR18,
VAR61,
VAR80,
VAR17,
VAR115,
VAR41,
VAR28,
VAR91,
VAR57,
VAR11,
VAR55,
VAR23,
VAR123,
VAR109,
VAR107,
VAR8,
VAR125,
VAR5,
VAR31,
VAR122,
VAR124,
VAR116,
VAR95,
VAR72,
VAR27,
VAR114,
VAR16,
VAR71,
VAR106,
VAR126,
VAR36,
VAR86... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/timing/time_sender.v | 3,581 | module MODULE1
(input clk, input rst,
input [63:0] VAR18,
input VAR17,
output reg VAR22);
reg [7:0] VAR12;
reg VAR1;
wire [9:0] VAR7;
reg [9:0] VAR26;
reg VAR24;
wire VAR20, VAR6;
reg [4:0] state;
reg [3:0] VAR28;
VAR19 VAR19
(.VAR12({VAR1,VAR12}),.VAR3(VAR24),
.VAR7(VAR7),.VAR29(VAR20));
always @(posedge clk)
if(rst)
... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_fft_v1_00_a/hdl/verilog/axi_fft_win.v | 10,144 | module MODULE1 (
clk,
VAR77,
VAR70,
VAR48,
VAR16,
VAR1,
VAR9,
VAR78,
VAR17,
VAR41,
VAR59);
input clk;
input VAR77;
input [15:0] VAR70;
input VAR48;
output VAR16;
output VAR1;
output [15:0] VAR9;
output VAR78;
input VAR17;
input [15:0] VAR41;
input VAR59;
reg [15:0] VAR62 = 'd0;
reg VAR47 = 'd0;
reg VAR44 = 'd0;
reg VAR... | mit |
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