repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb.behavioral.v | 1,287 | module MODULE1 (
VAR6,
VAR8
);
output VAR6;
output VAR8;
supply1 VAR3;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR7 ;
pullup VAR4 (VAR6 );
pulldown VAR1 (VAR8 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_2.behavioral.v | 1,317 | module MODULE1( VAR2, VAR4, VAR5, VAR3, VAR7 );
input VAR2, VAR4, VAR5, VAR3;
output VAR7;
VAR1 VAR6(.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7));
VAR1 VAR8(.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
queq/just-stuff | pov/TopMobile/LEDS/select_efect.v | 1,764 | module MODULE1(
input [6:0]VAR4,
output reg VAR5,
output reg VAR7,
output reg VAR1,
output reg VAR2,
output reg VAR6,
output reg VAR3
);
always @(VAR4) begin
case(VAR4)
7'd48: begin
VAR5 =1'b1;
VAR7 =1'b0;
VAR1 =1'b0;
VAR2 =1'b0;
VAR6 =1'b0;
VAR3 =1'b0;
end
7'd49: begin
VAR5 =1'b0;
VAR7 =1'b1;
VAR1 =1'b0;
VAR2 =1'b0;
V... | mit |
miguelgarcia/sase2017-hls-video | hdmi_in/repo/sase/hdl/verilog/my_video_filter_mul_16ns_32ns_48_3.v | 1,429 | module MODULE2(clk, VAR14, VAR7, VAR10, VAR15);
input clk;
input VAR14;
input[16 - 1 : 0] VAR7; input[32 - 1 : 0] VAR10; output[48 - 1 : 0] VAR15;
reg [16 - 1 : 0] VAR2;
reg [32 - 1 : 0] VAR3;
wire [48 - 1 : 0] VAR6;
reg [48 - 1 : 0] VAR8;
assign VAR15 = VAR8;
assign VAR6 = VAR2 * VAR3;
always @ (posedge clk) begin
if ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor3/sky130_fd_sc_hvl__nor3.functional.v | 1,313 | module MODULE1 (
VAR7,
VAR4,
VAR2,
VAR3
);
output VAR7;
input VAR4;
input VAR2;
input VAR3;
wire VAR6;
nor VAR5 (VAR6, VAR3, VAR4, VAR2 );
buf VAR1 (VAR7 , VAR6 );
endmodule | apache-2.0 |
theapi/nand2tetris_fpga | hack/rtl/verilog/memory.v | 2,899 | module MODULE1 (
input clk,
input [15:0] in,
input [14:0] address,
input [12:0] VAR2,
input VAR12,
input [7:0] VAR6,
output [15:0] out,
output [15:0] VAR13,
output ready
);
reg [31:0] VAR15 = 32'b0;
reg VAR7 = 1'b0;
assign ready = VAR7;
reg VAR21;
wire VAR18;
reg [12:0] VAR19 = 13'b0;
wire [12:0] VAR23;
assign VAR23 = ... | mit |
SeanZarzycki/openSPARC-FPU | project/src/fpu_out.v | 6,783 | module MODULE1 (
VAR24,
VAR45,
VAR21,
VAR14,
VAR31,
VAR26,
VAR10,
VAR13,
VAR8,
VAR9,
VAR17,
VAR30,
VAR5,
VAR4,
VAR44,
VAR35,
VAR23,
VAR43,
VAR33,
VAR29,
VAR20,
VAR42,
VAR22,
VAR6,
VAR15,
VAR2,
VAR25,
VAR16,
VAR41,
VAR38,
VAR40,
VAR1,
VAR18,
VAR19,
VAR37,
VAR34,
VAR36,
VAR32,
VAR39,
VAR28
);
input VAR24; input VAR45; in... | gpl-3.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,758 | module MODULE1
parameter VAR35 = 8,
VAR38 = 8,
VAR25 = 0,
VAR9 = 0,
VAR12 = 1,
VAR20 = 0,
VAR26 = 1,
VAR21 = 2,
VAR31 = 2,
VAR33 = 1,
VAR30 = VAR35 / VAR38,
VAR15 = VAR8(VAR30)
)
(
input VAR4,
input VAR10,
input VAR41,
input VAR5,
output VAR36,
input VAR32,
input [VAR35 - 1 : 0] VAR18,
input [VAR12 - 1 : 0] VAR27,
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi_2.v | 2,350 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR2 ,
VAR6 ,
VAR11 ,
VAR10,
VAR7,
VAR5 ,
VAR8
);
output VAR9 ;
input VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR11 ;
input VAR10;
input VAR7;
input VAR5 ;
input VAR8 ;
VAR1 VAR4 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR5(VAR5),
.... | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_arb_mux_64_4.v | 5,813 | module MODULE1 #
(
parameter VAR6 = 64,
parameter VAR20 = (VAR6/8),
parameter VAR26 = "VAR38",
parameter VAR28 = "VAR12"
)
(
input wire clk,
input wire rst,
input wire [VAR6-1:0] VAR17,
input wire [VAR20-1:0] VAR36,
input wire VAR19,
output wire VAR1,
input wire VAR41,
input wire VAR35,
input wire [VAR6-1:0] VAR37,
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.symbol.v | 1,252 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a_2.v | 2,322 | module MODULE2 (
VAR3 ,
VAR9 ,
VAR2 ,
VAR1 ,
VAR5 ,
VAR4,
VAR8,
VAR11 ,
VAR6
);
output VAR3 ;
input VAR9 ;
input VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR4;
input VAR8;
input VAR11 ;
input VAR6 ;
VAR10 VAR7 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_4.v | 2,218 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR7,
VAR5
);
input VAR2 ;
input VAR9 ;
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR7;
input VAR5;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR2,
VAR9 ,
VAR4 ,
VAR1,
VAR3
)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a.pp.symbol.v | 1,372 | module MODULE1 (
input VAR5 ,
input VAR2 ,
input VAR7 ,
input VAR4 ,
output VAR9 ,
input VAR1 ,
input VAR6,
input VAR3,
input VAR8
);
endmodule | apache-2.0 |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/ipshared/xilinx.com/axi_crossbar_v2_1/da4c95fc/hdl/verilog/axi_crossbar_v2_1_addr_decoder.v | 11,495 | module MODULE1 #
(
parameter VAR33 = "none",
parameter integer VAR27 = 2, parameter integer VAR40 = 1, parameter integer VAR38 = 1, parameter integer VAR18 = 32, parameter integer VAR16 = 0, parameter integer VAR31 = 1, parameter integer VAR4 = 0, parameter [VAR27*VAR38*64-1:0] VAR35 = {VAR27*VAR38*64{1'b1}},
parameter... | gpl-3.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/ultrasonicReceiver.v | 8,953 | module MODULE1 # (
parameter VAR4 = 8,
parameter VAR3 = 12'h7FF,
parameter VAR88 = 3'b000)(
input VAR66,
input VAR101, VAR79,
input VAR86,
output VAR80,
output VAR67,
output VAR78,
input VAR58,
input VAR64,
input VAR46,
input VAR106,
input VAR9,
input VAR23,
input VAR12,
input [15:0] VAR6,
input [23:0] VAR68,
input VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxbp/sky130_fd_sc_hd__sedfxbp.pp.blackbox.v | 1,455 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR2 ,
VAR3 ,
VAR7 ,
VAR9 ,
VAR5 ,
VAR4,
VAR8,
VAR10 ,
VAR6
);
output VAR1 ;
output VAR11 ;
input VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR5 ;
input VAR4;
input VAR8;
input VAR10 ;
input VAR6 ;
endmodule | apache-2.0 |
dawsonjon/fpu | adder/file_reader_b.v | 7,932 | module MODULE1(VAR30,clk,rst,VAR15,VAR38);
integer VAR8;
integer VAR17;
input VAR30;
input clk;
input rst;
output [31:0] VAR15;
output VAR38;
reg [31:0] VAR26;
reg VAR22;
reg VAR35;
reg VAR12;
reg VAR28;
reg [3:0] VAR33;
reg [3:0] VAR32;
reg [39:0] VAR3;
reg [3:0] VAR31;
reg [1:0] VAR6;
reg [1:0] VAR10;
reg [1:0] VAR13... | mit |
danshanley/FPU | fpu.v | 12,602 | module MODULE1(clk, VAR1, VAR30, VAR24, VAR26);
input clk;
input [31:0] VAR1, VAR30;
input [1:0] VAR24;
output [31:0] VAR26;
wire [31:0] VAR26;
wire [7:0] VAR61;
wire [23:0] VAR58;
wire [7:0] VAR38;
wire [23:0] VAR27;
reg VAR46;
reg [7:0] VAR49;
reg [24:0] VAR31;
reg [31:0] VAR22;
reg [31:0] VAR29;
wire [31:0] VAR18;
r... | gpl-3.0 |
revaldinho/opc | copro/src/Tube/tube.v | 14,740 | module MODULE1 (
input [2:0] VAR22,
input VAR11,
input [7:0] VAR58,
output [7:0] VAR8,
inout [7:0] VAR69,
input VAR35,
input VAR49,
input VAR21,
output VAR13,
output VAR28,
input VAR39,
input [2:0] VAR7,
input VAR66,
input [7:0] VAR31,
output [7:0] VAR29,
inout [7:0] VAR34,
input VAR63,
input VAR41,
output VAR6,
output... | gpl-3.0 |
maltanar/fpga-tidbits | src/main/scala/fpgatidbits/platform-wrapper/convey/cae_pers.v | 4,072 | module MODULE1 #(
parameter VAR40 = 1,
parameter VAR27 = 32
) (
input clk, input VAR21, input VAR13, input VAR23,
input VAR6,
input [4:0] VAR1,
input [17:0] VAR18,
input VAR44,
input VAR42,
input [63:0] VAR41,
output [17:0] VAR5,
output [15:0] VAR49,
output VAR3,
output VAR33,
output [63:0] VAR37,
output VAR2,
output [... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfstp/sky130_fd_sc_ms__sdfstp.pp.blackbox.v | 1,434 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR4 ,
VAR9 ,
VAR10 ,
VAR8,
VAR6 ,
VAR3 ,
VAR7 ,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR10 ;
input VAR8;
input VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_4.behavioral.pp.v | 1,167 | module MODULE1( VAR4, VAR7, VAR5, VAR6 );
input VAR4;
inout VAR5, VAR6;
output VAR7;
VAR2 VAR3(.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6));
VAR2 VAR1(.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31a/sky130_fd_sc_ls__o31a.symbol.v | 1,346 | module MODULE1 (
input VAR8,
input VAR5,
input VAR7,
input VAR9,
output VAR4
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2i/sky130_fd_sc_hd__mux2i.pp.blackbox.v | 1,317 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR1 ,
VAR7 ,
VAR5,
VAR6,
VAR3 ,
VAR8
);
output VAR2 ;
input VAR4 ;
input VAR1 ;
input VAR7 ;
input VAR5;
input VAR6;
input VAR3 ;
input VAR8 ;
endmodule | apache-2.0 |
mlarouche/sd2snes | verilog/sd2sneslite/mcu_cmd.v | 3,974 | module MODULE1(
input clk,
input VAR7,
input VAR10,
input [7:0] VAR3,
input [7:0] VAR19,
output VAR12,
output VAR20,
input VAR13,
output [7:0] VAR15,
input [7:0] VAR21,
output [7:0] VAR16,
input [31:0] VAR17,
input [2:0] VAR18,
output [23:0] VAR11,
output [23:0] VAR1,
output [23:0] VAR6
);
reg [7:0] VAR2;
reg [7:0] VAR... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_bae_stage3.v | 10,802 | module MODULE1(
VAR20 ,
VAR2 ,
VAR14 ,
VAR11 ,
VAR21 ,
VAR7 ,
VAR4 ,
VAR6 ,
VAR13 ,
VAR17 ,
VAR15
);
input [ 9:0] VAR20 ;
input [ 3:0] VAR2 ; input [ 8:0] VAR14 ; input VAR11 ; input VAR21 ; input [ 8:0] VAR7 ;
input [ 9:0] VAR4 ;
output [ 9:0] VAR6 ;
output [ 2:0] VAR13 ;
output [ 5:0] VAR17 ;
output VAR15 ;
reg [ 9:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxbp/sky130_fd_sc_ls__sdfxbp.functional.v | 1,869 | module MODULE1 (
VAR15 ,
VAR1,
VAR3,
VAR13 ,
VAR10,
VAR2
);
output VAR15 ;
output VAR1;
input VAR3;
input VAR13 ;
input VAR10;
input VAR2;
wire VAR12 ;
wire VAR5;
VAR8 VAR14 (VAR5, VAR13, VAR10, VAR2 );
VAR7 VAR6 VAR11 (VAR12 , VAR5, VAR3 );
buf VAR9 (VAR15 , VAR12 );
not VAR4 (VAR1 , VAR12 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/common/rtl/iobdg_1r1w_rf32.v | 8,798 | module MODULE1 (
dout,
VAR22, VAR74, VAR33, VAR70, din, VAR16
);
parameter VAR62 = 64;
input VAR22;
input VAR74;
input [4:0] VAR33;
input [4:0] VAR70;
input [VAR62-1:0] din;
input VAR16;
output [VAR62-1:0] dout;
wire [4:0] VAR27;
wire [VAR62-1:0] VAR35;
wire VAR12;
wire [31:0] VAR68;
wire [31:0] VAR80;
wire [VAR62-1:0]... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai_2.v | 2,457 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR12 ,
VAR2 ,
VAR4 ,
VAR5 ,
VAR1,
VAR6,
VAR10 ,
VAR11
);
output VAR7 ;
input VAR8 ;
input VAR12 ;
input VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR1;
input VAR6;
input VAR10 ;
input VAR11 ;
VAR9 VAR3 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221a/sky130_fd_sc_hdll__o221a.pp.symbol.v | 1,409 | module MODULE1 (
input VAR10 ,
input VAR4 ,
input VAR5 ,
input VAR7 ,
input VAR2 ,
output VAR9 ,
input VAR3 ,
input VAR8,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/scripts/user_logic.v | 5,073 | module MODULE1(
input VAR18, input VAR65, input VAR37, input VAR5,
input [31:0] VAR25,
input [19:0] VAR9,
input VAR49,
output reg [31:0] VAR54,
output reg VAR40,
input VAR52,
output [255:0] VAR35,
output [31:0] VAR24,
output VAR17,
output [26:0] VAR20,
output VAR19,
input [255:0] VAR36,
input VAR1,
input VAR68,
input V... | mit |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_receivecontrol.v | 14,431 | module MODULE1 (VAR37, VAR35, VAR23, VAR1, VAR36, VAR11, VAR12,
VAR54, VAR14, VAR24, VAR55, VAR33, VAR49,
VAR15, VAR17, VAR59, VAR50,
VAR13, VAR56, VAR60, VAR19,
VAR27, VAR2, VAR34
);
parameter VAR18 = 1;
input VAR37;
input VAR35;
input VAR23;
input VAR1;
input [7:0] VAR36;
input VAR11;
input VAR12;
input VAR54;
input ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp.behavioral.pp.v | 2,938 | module MODULE1 (
VAR13 ,
VAR5 ,
VAR18 ,
VAR11 ,
VAR3 ,
VAR6,
VAR2 ,
VAR26 ,
VAR14 ,
VAR15 ,
VAR21
);
output VAR13 ;
input VAR5 ;
input VAR18 ;
input VAR11 ;
input VAR3 ;
input VAR6;
input VAR2 ;
input VAR26 ;
input VAR14 ;
input VAR15 ;
input VAR21 ;
wire VAR24 ;
wire VAR1 ;
reg VAR16 ;
wire VAR9 ;
wire VAR10 ;
wire VA... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_altdqdqs.v | 5,763 | module MODULE1 (
VAR76,
VAR49,
VAR12,
VAR40,
VAR32,
VAR74,
VAR46,
VAR69,
VAR25,
VAR36,
VAR71,
VAR1,
VAR21,
VAR55,
VAR5,
VAR4,
VAR19,
VAR24,
VAR73,
VAR18,
VAR22,
VAR38,
VAR66,
VAR58,
VAR37,
VAR27,
VAR60,
VAR2,
VAR59
);
input [6-1:0] VAR59;
input VAR76;
input VAR49;
input VAR12;
input VAR40;
input VAR32;
input VAR74;
inp... | lgpl-3.0 |
nyaxt/dmix | ddr3_fb.v | 4,964 | module MODULE1(
input wire clk, input wire rst,
input wire VAR40,
output wire VAR19,
output wire VAR16,
output wire [2:0] VAR35,
output wire [5:0] VAR26,
output wire [29:0] VAR12,
input wire VAR20,
input wire VAR13,
output wire VAR5,
output wire VAR24,
output wire [3:0] VAR54,
output wire [31:0] VAR39,
input wire VAR32... | mit |
ShirmanXia/EE469SPRING16 | lab4/db/ip/nios_system/submodules/nios_system_nios2_qsys_0_jtag_debug_slave_tck.v | 8,428 | module MODULE1 (
VAR7,
VAR30,
VAR29,
VAR13,
VAR1,
VAR28,
VAR16,
VAR21,
VAR39,
VAR25,
VAR19,
VAR14,
VAR40,
VAR9,
VAR37,
VAR32,
VAR34,
VAR20,
VAR11,
VAR10,
VAR24,
VAR35,
VAR27,
VAR38,
VAR4,
VAR23,
VAR22,
VAR26,
VAR12,
VAR33,
VAR3
)
;
output [ 1: 0] VAR22;
output VAR26;
output [ 37: 0] VAR12;
output VAR33;
output VAR3;
in... | gpl-3.0 |
hydai/Verilog-Practice | HardwareLab/Lab7/LCD_display.v | 2,646 | module MODULE1(VAR10, VAR8, VAR1, VAR12, VAR3, VAR9, VAR4, VAR11, VAR14, clk);
input clk;
input VAR14;
input [0:255] VAR11;
output VAR10;
output VAR8;
output VAR1;
output VAR12;
output VAR3;
output VAR9;
output [7:0] VAR4;
reg [7:0] VAR4;
reg [1:0] VAR16;
reg [2:0] VAR6;
reg [2:0] VAR5;
reg [1:0] VAR15;
reg [7:0] VAR7;... | mit |
Jawanga/ece385final | usb_system/synthesis/submodules/usb_system_mm_interconnect_1.v | 16,686 | module MODULE1 (
input wire VAR60, input wire VAR3, input wire [21:0] VAR95, output wire VAR69, input wire [0:0] VAR79, input wire [3:0] VAR75, input wire VAR56, output wire [31:0] VAR1, output wire VAR36, input wire VAR11, input wire [31:0] VAR16, input wire VAR93, output wire [1:0] VAR23, output wire VAR96, output wi... | apache-2.0 |
alexforencich/verilog-ethernet | example/DE5-Net/fpga/cores/phy_reconfig.v | 9,359 | module MODULE1 (
output wire VAR3, input wire VAR2, input wire VAR33, input wire [6:0] VAR30, input wire VAR18, output wire [31:0] VAR11, output wire VAR20, input wire VAR31, input wire [31:0] VAR26, output wire [559:0] VAR35, input wire [367:0] VAR4 );
VAR17 #(
.VAR25 ("VAR14 VAR23"),
.VAR7 (8),
.VAR29 (1),
.VAR28 (1)... | mit |
ptracton/vscale_soc | rtl/uart16550-1.5.4/rtl/verilog/uart_sync_flops.v | 5,591 | module MODULE1
(
VAR2,
VAR8,
VAR3,
VAR6,
VAR1,
VAR5
);
parameter VAR9 = 1;
parameter VAR4 = 1'b0;
input VAR2; input VAR8; input VAR3; input VAR6; input [VAR9-1:0] VAR1; output [VAR9-1:0] VAR5;
reg [VAR9-1:0] VAR5;
reg [VAR9-1:0] VAR7;
always @ (posedge VAR8 or posedge VAR2)
begin
if (VAR2)
VAR7 <= {VAR9{VAR4}};
end
els... | mit |
jakubfi/mera400f | src/sevenseg.v | 3,282 | module MODULE4(
input clk,
input [6:0] VAR6 [7:0],
input [7:0] VAR7,
output reg [7:0] VAR13,
output reg [7:0] VAR9
);
reg [0:18] counter;
always @ (posedge clk) begin
counter <= counter + 1'b1;
end
wire [2:0] addr = counter[0:2]; always @ (addr, VAR7, VAR6) begin
VAR13 <= ~(1'b1 << addr);
VAR9 <= ~{VAR7[addr], VAR6[add... | gpl-2.0 |
pwwu/FPGA | VGAbased/final/vga_font_gen.v | 1,675 | module MODULE1
(
input wire clk,
input wire VAR6,
input wire [9:0] VAR11, VAR4,
output reg [2:0] VAR10
);
wire [10:0] VAR3;
wire [6:0] VAR13;
wire [3:0] VAR8;
wire [2:0] VAR7;
wire [7:0] VAR12;
wire VAR5, VAR1;
VAR14 VAR9
(.clk(clk), .addr(VAR3), .VAR2(VAR12));
assign VAR13 = {VAR4[5:4], VAR11[7:3]};
assign VAR8 = VAR4... | mit |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/radio_controller_v1_22_a/hdl/verilog/user_logic.v | 35,856 | module MODULE1
(
VAR128,
VAR157,
VAR57,
VAR122,
VAR39,
VAR144,
VAR85,
VAR213,
VAR200,
VAR7,
VAR9,
VAR201,
VAR107,
VAR141,
VAR219,
VAR98,
VAR102,
VAR173,
VAR44,
VAR26,
VAR42,
VAR38,
VAR217,
VAR175,
VAR46,
VAR95,
VAR75,
VAR28,
VAR58,
VAR22,
VAR205,
VAR192,
VAR72,
VAR154,
VAR109,
VAR174,
VAR216,
VAR222,
VAR177,
VAR112,
VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o.symbol.v | 1,371 | module MODULE1 (
input VAR2,
input VAR7,
input VAR1,
input VAR6,
output VAR8
);
supply1 VAR4;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
ryos36/polyphony-tutorial | OpenSuCo2017/VivadoHLS/fib.v | 4,349 | module MODULE1 (
VAR5,
VAR26,
VAR3,
VAR8,
VAR6,
VAR27,
VAR18,
VAR11
);
parameter VAR24 = 2'b1;
parameter VAR2 = 2'b10;
parameter VAR9 = 32'b00000000000000000000000000000000;
parameter VAR4 = 32'b1;
parameter VAR10 = 64'b1;
parameter VAR12 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter... | mit |
efabless/openlane | designs/spm/src/spm.v | 2,781 | module MODULE3(clk, rst, VAR10, VAR16, VAR2);
parameter VAR3 = 32;
input clk, rst;
input VAR16;
input[VAR3-1:0] VAR10;
output VAR2;
wire[VAR3-1:1] VAR18;
wire[VAR3-1:0] VAR11;
genvar VAR17;
MODULE2 MODULE1 (.clk(clk), .rst(rst), .VAR10(VAR10[0]&VAR16), .VAR16(VAR18[1]), .sum(VAR2));
generate for(VAR17=1; VAR17<VAR3-1; ... | apache-2.0 |
benreynwar/fpga-sdrlib | verilog/uhd/bits.v | 1,902 | module MODULE1
parameter VAR5 = 32
)
(
input wire clk,
input wire reset,
input wire [VAR5-1:0] VAR10,
input wire VAR11,
output reg [VAR5-1:0] VAR2,
output reg VAR6,
output reg VAR9
);
reg ready;
reg [VAR8-1:0] VAR7;
reg VAR3;
reg [VAR5-1:0] VAR1;
always @ (posedge clk)
if (reset)
begin
ready <= 1'b1;
VAR9 <= 1'b0;
VAR6... | mit |
hoglet67/AtomBusMon | src/MultiBootLoader.v | 9,488 | module MODULE1
(
input VAR26,
input VAR59,
input [3:0] VAR20,
output VAR51, output VAR18, output VAR10, output VAR3,
output VAR15,
output VAR37,
output VAR9,
output VAR33,
output VAR40,
output VAR42,
output VAR5
);
reg [1:0] clk;
reg [15:0] VAR7;
reg VAR31;
reg VAR52;
reg [15:0] VAR21;
reg VAR11;
reg VAR17;
reg [15:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21o/sky130_fd_sc_hd__a21o.functional.pp.v | 1,994 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR2 ,
VAR16 ,
VAR1,
VAR14,
VAR4 ,
VAR5
);
output VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR16 ;
input VAR1;
input VAR14;
input VAR4 ;
input VAR5 ;
wire VAR12 ;
wire VAR3 ;
wire VAR15;
and VAR11 (VAR12 , VAR7, VAR2 );
or VAR10 (VAR3 , VAR12, VAR16 );
VAR13 VAR8 (VAR15, VAR3, VAR1, VAR14);... | apache-2.0 |
bgamari/timetag-fpga | register.v | 1,443 | module MODULE1(
VAR9, VAR3, VAR4, VAR6,
clk, VAR11
);
parameter VAR1 = 1;
input VAR9;
input [15:0] VAR3;
inout [31:0] VAR4;
input VAR6;
input clk;
output [31:0] VAR11;
reg [31:0] VAR11;
VAR5 VAR11 = 32'h0;
always @(posedge VAR9)
if (VAR3 == VAR1 && VAR6)
VAR11 <= VAR4;
assign VAR4 = (VAR3 == VAR1 && !VAR6) ? VAR11 : 32... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_16.v | 2,264 | module MODULE2 (
VAR1 ,
VAR3,
VAR8 ,
VAR5 ,
VAR2 ,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR3;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR4 ;
VAR9 VAR7 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR1 ,
VAR3,
VAR8
);
output VAR... | apache-2.0 |
SymbiFlow/yosys | techlibs/anlogic/cells_map.v | 3,928 | module \VAR3 (input VAR2, VAR10, VAR43, VAR51, output VAR32); VAR48 #(.VAR6("VAR4"), .VAR37("VAR30"), .VAR45("VAR7"), .VAR18("VAR38")) VAR34 (.VAR55(VAR2), .VAR22(VAR32), .clk(VAR10) ,.VAR41(VAR51), .VAR39(VAR43)); wire VAR24 = 1'b1; endmodule
module \VAR13 (input VAR2, VAR10, VAR43, VAR51, output VAR32); VAR48 #(.VAR6... | isc |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,553 | module MODULE1
parameter VAR45 = 8,
VAR12 = 8,
VAR29 = 0,
VAR42 = 0,
VAR32 = 1,
VAR44 = 0,
VAR20 = 1,
VAR26 = 2,
VAR1 = 2,
VAR11 = 1,
VAR34 = VAR45 / VAR12,
VAR35 = VAR36(VAR34)
)
(
input VAR7,
input VAR33,
input VAR10,
input VAR39,
output VAR22,
input VAR5,
input [VAR45 - 1 : 0] VAR30,
input [VAR32 - 1 : 0] VAR9,
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2.functional.pp.v | 1,814 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR7 ,
VAR10,
VAR12,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR10;
input VAR12;
input VAR6 ;
input VAR2 ;
wire VAR13 ;
wire VAR11;
xor VAR4 (VAR13 , VAR7, VAR5 );
VAR8 VAR3 (VAR11, VAR13, VAR10, VAR12);
buf VAR9 (VAR1 , VAR11 );
endmodule | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/rtl/dram.v | 11,213 | module MODULE1(input wire VAR71,
input wire VAR10,
output wire VAR75,
output wire VAR31,
input wire [VAR12-1:0] VAR59,
input wire [VAR69-1:0] VAR21,
input wire VAR45,
input wire VAR39,
output reg [VAR69-1:0] VAR4,
output reg VAR16,
output wire VAR19,
inout wire [VAR55] VAR53,
inout wire [1:0] VAR6,
inout wire [1:0] VAR... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o31ai/sky130_fd_sc_hdll__o31ai.functional.pp.v | 2,047 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR3 ,
VAR16 ,
VAR8 ,
VAR4,
VAR11,
VAR1 ,
VAR17
);
output VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR16 ;
input VAR8 ;
input VAR4;
input VAR11;
input VAR1 ;
input VAR17 ;
wire VAR15 ;
wire VAR9 ;
wire VAR10;
or VAR5 (VAR15 , VAR3, VAR7, VAR16 );
nand VAR14 (VAR9 , VAR8, VAR15 );
VAR2 VAR13... | apache-2.0 |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_wrapper.v | 9,436 | module MODULE1 (
VAR39,
VAR31,
clk,
VAR25,
VAR27,
VAR46,
VAR54,
VAR44,
VAR6,
VAR1,
VAR16,
VAR43,
VAR50,
VAR8,
VAR17,
VAR13,
VAR10,
VAR52,
VAR49,
VAR2,
VAR37,
VAR53,
VAR30,
VAR19,
VAR28,
VAR22,
VAR57,
VAR55,
VAR41,
VAR5,
VAR35,
VAR4,
VAR32
)
;
output [ 37: 0] VAR37;
output VAR53;
output VAR30;
output VAR19;
output VAR28... | gpl-2.0 |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_clamp.v | 3,449 | module MODULE1
(
input VAR6, input VAR8,
input VAR2,
input [10:0] VAR7,
input [10:0] VAR18,
input [10:0] VAR3,
input [10:0] VAR4,
input [8:0] VAR16,
input [8:0] VAR9,
output reg VAR13,
output reg [8:0] VAR11,
output reg [8:0] VAR10,
output reg [8:0] VAR1,
output reg [8:0] VAR15
);
reg VAR12;
wire VAR14,
VAR17;
assign V... | gpl-3.0 |
esonghori/TinyGarbled | circuit_synthesis/syn_lib/ADD.v | 1,224 | module MODULE1 #(parameter VAR14 = 8, VAR7 = VAR14)( input [VAR14-1:0] VAR18,
input [VAR7-1:0] VAR8,
input VAR17,
output VAR4,
output [VAR14-1:0] VAR20
);
wire [VAR14-1:0] VAR19;
generate
if (VAR14 > VAR7) begin: VAR10
assign VAR19 = {{(VAR14-VAR7){1'b0}}, VAR8};
end else begin: VAR2
assign VAR19 = VAR8;
end
endgenerat... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai.symbol.v | 1,313 | module MODULE1 (
input VAR3,
input VAR2,
input VAR4,
output VAR5
);
supply1 VAR6;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.behavioral.v | 1,903 | module MODULE1 (
VAR16,
VAR2,
VAR8
);
output VAR16;
input VAR2;
input VAR8 ;
supply1 VAR12;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR10 ;
wire VAR15 ;
wire VAR13 ;
wire VAR17 ;
wire VAR5;
reg VAR3 ;
wire VAR11 ;
not VAR6 (VAR13 , VAR17 );
VAR14 VAR4 (VAR15 , VAR5, VAR13, VAR3, VAR12, VAR9);
and VAR1 (VAR16 , VAR15, VAR1... | apache-2.0 |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/mm.v | 2,121 | module MODULE1(addr, VAR2, VAR1);
input [31:0] addr;
output [7:0] VAR2;
output [31:0] VAR1;
assign VAR2 = (addr[31:20] == 12'h000) ? 0 :
(addr[31:24] == 8'h10) ? 1 :
(addr[31:20] == 12'hf00) ? 2 :
(addr[31:20] == 12'hf01) ? 3 :
(addr[31:20] == 12'hf02) ? 4 :
(addr[31:20] == 12'hf03) ? 5 :
(addr[31:20] == 12'hf04) ? 6 :... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b.symbol.v | 1,285 | module MODULE1 (
input VAR2 ,
input VAR4,
output VAR5
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi.blackbox.v | 1,342 | module MODULE1 (
VAR2 ,
VAR3,
VAR7,
VAR4
);
output VAR2 ;
input VAR3;
input VAR7;
input VAR4;
supply1 VAR5;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/pcie_egress.v | 7,702 | module MODULE1 (
input clk,
input rst,
input VAR27,
output reg VAR28,
input [7:0] VAR6,
input [13:0] VAR12,
input [31:0] VAR36,
input [15:0] VAR37,
input [7:0] VAR7,
input [9:0] VAR35,
input VAR20,
output [31:0] VAR40,
output [3:0] VAR2,
output reg VAR26,
output reg VAR16,
input VAR8,
output reg VAR25,
input [23:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221a/sky130_fd_sc_ms__o221a.pp.symbol.v | 1,401 | module MODULE1 (
input VAR5 ,
input VAR1 ,
input VAR2 ,
input VAR8 ,
input VAR9 ,
output VAR7 ,
input VAR6 ,
input VAR3,
input VAR4,
input VAR10
);
endmodule | apache-2.0 |
ZiCog/xoro | rtl/gpio.v | 1,279 | module MODULE1 (
input wire clk,
input wire VAR3,
input wire enable,
input wire VAR8,
output wire VAR1,
input wire VAR4,
input wire [3:0] VAR9,
input wire [31:0] VAR6,
input wire [31:0] VAR5,
output wire [31:0] VAR7,
output reg [31:0] MODULE1
);
reg [7:0] VAR2;
reg VAR10;
always @(posedge clk) begin
if (!VAR3) begin
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbn/sky130_fd_sc_lp__dlxbn.functional.v | 1,817 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR2 ,
VAR9
);
output VAR4 ;
output VAR5 ;
input VAR2 ;
input VAR9;
wire VAR8 ;
wire VAR11 ;
wire VAR12;
wire VAR1 ;
VAR13 VAR3 VAR6 (VAR11 , VAR2, VAR8 );
not VAR7 (VAR8 , VAR9 );
buf VAR14 (VAR4 , VAR11 );
not VAR10 (VAR5 , VAR11 );
endmodule | apache-2.0 |
jmahler/EECE344-Digital_System_Design | lab03/CPLD/mem_ctl.v | 1,516 | module MODULE1(
input VAR10,
VAR11,
VAR4,
input [6:0] VAR2,
inout [7:0] VAR3,
inout [7:0] VAR7,
output [16:0] VAR8,
output wire VAR6,
VAR5,
VAR12,
VAR9);
assign VAR8[16:7] = 0;
assign VAR8[6:0] = VAR2;
assign VAR3 = (~(VAR4 | VAR10 | ~VAR11)) ? VAR7 : 8'VAR1;
assign VAR7 = (~(VAR4 | VAR11 | ~VAR10)) ? VAR3 : 8'VAR1;
as... | gpl-3.0 |
jotego/jt51 | syn/xilinx/contra_snd/hdl/uart_transceiver.v | 5,377 | module MODULE1(
input VAR2,
input VAR17,
input VAR10,
output reg VAR14,
input [4:0] VAR18,
input [4:0] VAR29,
output reg [7:0] VAR30,
output reg VAR9,
output reg VAR27,
output reg [7:0] VAR3,
input [7:0] VAR1,
input VAR26,
output reg VAR22
);
reg [4:0] VAR28;
wire VAR4;
assign VAR4 = !VAR28;
always @(posedge VAR17 or p... | gpl-3.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/usb_system_cpu_jtag_debug_module_sysclk.v | 7,058 | module MODULE1 (
clk,
VAR18,
VAR9,
VAR23,
VAR30,
VAR14,
VAR27,
VAR12,
VAR4,
VAR29,
VAR22,
VAR5,
VAR28,
VAR20,
VAR32,
VAR11,
VAR8,
VAR10,
VAR25
)
;
output [ 37: 0] VAR14;
output VAR27;
output VAR12;
output VAR4;
output VAR29;
output VAR22;
output VAR5;
output VAR28;
output VAR20;
output VAR32;
output VAR11;
output VAR8;... | apache-2.0 |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/new/CORDIC_Arch3.v | 20,433 | module MODULE1 #(parameter VAR3 = 32, parameter VAR33 = 8, parameter VAR126 = 23, parameter VAR10=26, parameter VAR43 = 5)/*#(parameter VAR3 = 64, parameter VAR33 = 11, parameter VAR126 = 52, parameter VAR10 = 55, parameter VAR43 = 6) (
input wire clk, input wire rst, input wire VAR49, input wire VAR141, input wire VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlxtp/sky130_fd_sc_hvl__dlxtp.functional.pp.v | 1,937 | module MODULE1 (
VAR4 ,
VAR14 ,
VAR6,
VAR12,
VAR13,
VAR7 ,
VAR5
);
output VAR4 ;
input VAR14 ;
input VAR6;
input VAR12;
input VAR13;
input VAR7 ;
input VAR5 ;
wire VAR2 ;
wire VAR3;
VAR11 VAR10 VAR1 (VAR2 , VAR14, VAR6, , VAR12, VAR13 );
buf VAR15 (VAR3, VAR2 );
VAR9 VAR8 (VAR4 , VAR3, VAR12, VAR13);
endmodule | apache-2.0 |
Tsung-Wei/OpenTimer | benchmark/s344/s344.v | 13,069 | module MODULE1 (
VAR112,
VAR288,
VAR128,
VAR205,
VAR45,
VAR201,
VAR211,
VAR268,
VAR222,
VAR404,
VAR91,
VAR378,
VAR38,
VAR398,
VAR397,
VAR389,
VAR363,
VAR129,
VAR372,
VAR120,
VAR216,
VAR387);
input VAR112;
input VAR288;
input VAR128;
input VAR205;
input VAR45;
input VAR201;
input VAR211;
input VAR268;
input VAR222;
inpu... | gpl-3.0 |
niketancm/tsea26 | lab2-3/rtl/agu_rf.v | 1,237 | module MODULE1
parameter VAR9 = 2,
parameter VAR5 = 0)
(
input wire VAR6,
input wire [VAR9-1:0] VAR3,
input wire [VAR9-1:0] VAR13,
output reg [VAR11-1:0] VAR17,
output reg [VAR11-1:0] VAR2,
input wire VAR1,
input wire VAR7,
input wire [VAR9-1:0] VAR12,
input wire [VAR11-1:0] VAR19);
reg [VAR11-1:0] VAR18 [1:0];
wire [V... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/yacc/decoder.v | 33,218 | module MODULE1(VAR56,VAR169,VAR128,VAR119,VAR80,VAR84,
VAR5,VAR198,VAR30,VAR149,VAR48,
VAR28,VAR109,VAR96,VAR1,VAR186,
VAR155,VAR74,VAR219,VAR133,VAR29,VAR179,VAR200,VAR210,VAR231,VAR112,VAR86,VAR176,
VAR4,VAR208,VAR150,VAR87,VAR214,VAR234,VAR95,VAR14,VAR177,VAR42,
VAR66,VAR102,VAR98,VAR232,VAR17,VAR167,
VAR207,VAR142,... | mit |
freecores/tiny_tate_bilinear_pairing | group_size_is_911_bits/rtl/cubic.v | 62,682 | module MODULE1(VAR1, VAR2);
input [1185:0] VAR1;
output [1185:0] VAR2;
assign VAR2[1:0] = VAR1[1:0];
assign VAR2[3:2] = VAR1[1113:1112];
assign VAR2[5:4] = VAR1[793:792];
assign VAR2[7:6] = VAR1[3:2];
assign VAR2[9:8] = VAR1[1115:1114];
assign VAR2[11:10] = VAR1[1041:1040];
assign VAR2[13:12] = {VAR1[720], VAR1[721]};
... | apache-2.0 |
alexforencich/verilog-axis | rtl/axis_broadcast.v | 7,416 | module MODULE1 #
(
parameter VAR33 = 4,
parameter VAR36 = 8,
parameter VAR31 = (VAR36>8),
parameter VAR26 = ((VAR36+7)/8),
parameter VAR48 = 1,
parameter VAR29 = 0,
parameter VAR51 = 8,
parameter VAR42 = 0,
parameter VAR37 = 8,
parameter VAR50 = 1,
parameter VAR11 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR... | mit |
asicguy/gplgpu | hdl/de_temp/dex_sm.v | 27,883 | module MODULE1
(
input VAR227, input VAR229, input VAR104, input VAR191, input VAR245, input VAR16, input VAR206, input VAR225, input VAR87, input [1:0] VAR130, input [1:0] VAR140, input VAR93, input VAR27, input VAR254, input VAR94, input VAR232, input VAR1, input VAR153, input VAR125, input VAR50, input VAR180, input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux4/sky130_fd_sc_ls__mux4.behavioral.pp.v | 1,983 | module MODULE1 (
VAR2 ,
VAR15 ,
VAR7 ,
VAR11 ,
VAR6 ,
VAR14 ,
VAR10 ,
VAR12,
VAR13,
VAR18 ,
VAR17
);
output VAR2 ;
input VAR15 ;
input VAR7 ;
input VAR11 ;
input VAR6 ;
input VAR14 ;
input VAR10 ;
input VAR12;
input VAR13;
input VAR18 ;
input VAR17 ;
wire VAR1 ;
wire VAR3;
VAR16 VAR9 (VAR1 , VAR15, VAR7, VAR11, VAR6, V... | apache-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkTLB.v | 35,027 | module MODULE1(VAR68,
VAR117,
VAR108,
VAR15,
VAR48,
VAR65,
VAR74,
VAR98,
VAR125,
VAR170,
VAR126,
VAR43,
VAR212,
VAR67,
VAR85,
VAR146,
VAR120,
VAR174,
VAR154);
parameter [0 : 0] VAR213 = 1'b0;
parameter [2 : 0] VAR59 = 3'b0;
input VAR68;
input VAR117;
input [63 : 0] VAR108;
input [63 : 0] VAR15;
input VAR48;
input [1 : ... | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/udp_inbound_chain_writer.v | 8,394 | module MODULE1
(input VAR46,
input [7:0] VAR75,
input VAR57,
input VAR95, input VAR18,
input [7:0] VAR26,
input VAR6,
input VAR97,
input VAR79,
input [7:0] VAR87,
input VAR4,
output VAR9,
output [1:0] VAR84);
wire [4:0] VAR16;
wire VAR67;
VAR35 VAR59
(.VAR80(VAR46), .rst(~VAR57 & ~VAR95 & VAR16 < 5'h2),
.en(VAR95 & VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3b/sky130_fd_sc_lp__and3b_1.v | 2,218 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR4,
VAR10,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR4;
input VAR10;
input VAR3 ;
input VAR1 ;
VAR7 VAR9 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi_0.v | 2,350 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR6 ,
VAR8 ,
VAR2 ,
VAR3,
VAR5,
VAR1 ,
VAR9
);
output VAR10 ;
input VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR3;
input VAR5;
input VAR1 ;
input VAR9 ;
VAR7 VAR11 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.blackbox.v | 1,445 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR1 ,
VAR6 ,
VAR7,
VAR4 ,
VAR3
);
output VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR6 ;
input VAR7;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b.functional.v | 1,402 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR8 ,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR4;
wire VAR5 ;
wire VAR3;
not VAR7 (VAR5 , VAR4 );
or VAR10 (VAR3, VAR5, VAR2, VAR8, VAR6);
buf VAR9 (VAR1 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbp/sky130_fd_sc_hd__sdfbbp.blackbox.v | 1,532 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR6 ,
VAR1 ,
VAR7 ,
VAR10 ,
VAR12 ,
VAR5
);
output VAR2 ;
output VAR4 ;
input VAR6 ;
input VAR1 ;
input VAR7 ;
input VAR10 ;
input VAR12 ;
input VAR5;
supply1 VAR9;
supply0 VAR3;
supply1 VAR11 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
alanachtenberg/CSCE-350 | Project 2/Control.v | 3,010 | module MODULE1(VAR7, VAR13, VAR8, VAR12, VAR15, VAR1, VAR11, VAR5, VAR9, VAR10, VAR3);
input [5:0] VAR3;
output VAR7;
output VAR13;
output VAR8;
output VAR12;
output VAR15;
output VAR1;
output VAR11;
output VAR5;
output VAR9;
output [3:0] VAR10;
reg VAR7, VAR13, VAR8, VAR12, VAR15, VAR1, VAR11, VAR5, VAR9;
reg [3:0] VA... | gpl-2.0 |
defano/digital-design | seven-segment-counter/rtl/displaydriver.v | 2,379 | module MODULE1 (
clk,
reset,
VAR2,
VAR3,
VAR5,
VAR7,
VAR6,
VAR8
);
input clk;
input reset;
input [6:0] VAR2;
input [6:0] VAR3;
input [6:0] VAR5;
input [6:0] VAR7;
output [6:0] VAR6;
output [3:0] VAR8;
reg [7:0] VAR4;
reg [1:0] VAR1;
assign VAR6 =
(VAR1 == 2'd0) ? ~VAR7 :
(VAR1 == 2'd1) ? ~VAR5 :
(VAR1 == 2'd2) ? ~VAR3 ... | mit |
keith-epidev/VHDL-lib | top/stereo_radio/ip/multi_fft/multi_fft_stub.v | 1,206 | module MODULE1(VAR1, VAR4, VAR2, VAR3)
;
input VAR1;
input [28:0]VAR4;
input [28:0]VAR2;
output [57:0]VAR3;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf.behavioral.v | 1,319 | module MODULE1 (
VAR4,
VAR7
);
output VAR4;
input VAR7;
supply1 VAR1;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR8 ;
wire VAR9;
buf VAR2 (VAR9, VAR7 );
buf VAR3 (VAR4 , VAR9 );
endmodule | apache-2.0 |
kDaniu/miaow | src/verilog/rtl/issue/finished_wf.v | 4,034 | module MODULE1
(
VAR34, VAR5,
VAR52,
clk, rst, VAR29, VAR39,
VAR22, VAR17, VAR8, VAR11,
VAR37, VAR26, VAR51, VAR49,
VAR33, VAR13
);
input clk,rst;
input [VAR53-1:0] VAR29, VAR39,
VAR22, VAR17,
VAR8;
input VAR11, VAR37, VAR26,
VAR51, VAR49, VAR33;
input [VAR44-1:0] VAR13;
output VAR34;
output [VAR53-1:0] VAR5;
output [V... | bsd-3-clause |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/ram_harv_cache.v | 3,133 | module MODULE1
(input VAR50, input VAR26,
input [VAR45-1:0] VAR40,
input [31:0] VAR7,
input VAR54,
input [3:0] VAR23,
input VAR30,
output VAR58,
input VAR24,
input [VAR45-1:0] VAR5,
input VAR1,
output [31:0] VAR21,
output VAR35,
input [VAR45-1:0] VAR61,
input [31:0] VAR2,
output [31:0] VAR28,
input VAR18,
output VAR3,
... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat1_4.v | 1,064 | module MODULE1(
VAR4,
VAR1,
VAR3,
VAR2,
o0,
o1,
o2,
o3
);
input signed [18:0] VAR4;
input signed [18:0] VAR1;
input signed [18:0] VAR3;
input signed [18:0] VAR2;
output signed [18:0] o0;
output signed [18:0] o1;
output signed [18:0] o2;
output signed [18:0] o3;
assign o0=VAR4;
assign o1=VAR3;
assign o2=VAR1;
assign o3=... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1.pp.symbol.v | 1,322 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR5 ,
input VAR6,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3.behavioral.pp.v | 1,768 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR2,
VAR10
);
output VAR9 ;
input VAR1 ;
input VAR2;
input VAR10;
wire VAR3 ;
wire VAR4;
not VAR5 (VAR3 , VAR1 );
VAR8 VAR6 (VAR4, VAR3, VAR2, VAR10);
buf VAR7 (VAR9 , VAR4 );
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/16-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_pipe_rate.v | 46,133 | module MODULE1 #
(
parameter VAR19 = "VAR77", parameter VAR16 = "VAR49", parameter VAR35 = "3.0", parameter VAR83 = "VAR47", parameter VAR18 = "VAR135", parameter VAR43 = "VAR77", parameter VAR40 = "VAR77", parameter VAR97 = "VAR135", parameter VAR48 = 4'd15
)
(
input VAR90,
input VAR21,
input VAR108,
input VAR30,
inpu... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/altpllpll_bb.v | 11,855 | module MODULE1 (
VAR3,
VAR2,
VAR1);
input VAR3;
output VAR2;
output VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1.functional.pp.v | 1,768 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR4,
VAR3
);
output VAR10 ;
input VAR5 ;
input VAR4;
input VAR3;
wire VAR7 ;
wire VAR8;
not VAR1 (VAR7 , VAR5 );
VAR6 VAR2 (VAR8, VAR7, VAR4, VAR3);
buf VAR9 (VAR10 , VAR8 );
endmodule | apache-2.0 |
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