repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM | ii2dcam.v | 6,305 | module MODULE1
reg VAR13 ;
reg [VAR18(VAR3)+9:0] VAR17;
reg [VAR26*9-1:0] VAR4;
reg [VAR26*9-1:0] VAR38;
wire VAR24 ;
wire [VAR18(VAR3)+9:0] VAR10;
wire [VAR26*9-1:0] VAR7;
wire [VAR26*9-1:0] VAR31;
always @(posedge clk, posedge rst)
if (rst) {VAR13,VAR17,VAR4,VAR38} <= {(VAR18(VAR3)+18*VAR26+11){1'b0}};
else {VAR13,VA... | bsd-3-clause |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/rgb2hue.v | 12,236 | module MODULE1(
input VAR47,
input VAR27,
input VAR63,
input [7:0] VAR29,
input [7:0] VAR69,
input [7:0] VAR62,
input VAR54,
input VAR10,
output VAR59,
output [7:0] VAR26,
output [7:0] VAR13,
output [7:0] VAR3,
output [7:0] VAR32,
output VAR45,
output VAR38
);
reg VAR24;
reg [7:0] VAR4;
reg [7:0] VAR17;
reg [7:0] VAR56... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_hamgenerator.v | 3,143 | module MODULE1
(
input wire clk, input wire VAR24, input wire [ 9-1:1] VAR13, input wire [ 12-1:0] VAR7, input wire [ 8-1:0] select, input wire [ 8-1:0] VAR6, input wire [ 3-1:0] VAR18, input wire VAR16, input wire VAR10, output reg [ 24-1:0] VAR27 );
parameter VAR9 = 9'h180;
wire [ 8-1:0] VAR11 = select ^ VAR6;
wire [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3b/sky130_fd_sc_hs__nor3b_4.v | 2,127 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR7,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR7;
input VAR1;
VAR3 VAR8 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR4
);
output VAR5 ;
input VAR6 ;
input VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlclkp/sky130_fd_sc_hs__dlclkp_2.v | 2,027 | module MODULE1 (
VAR6,
VAR3,
VAR4 ,
VAR7,
VAR5
);
output VAR6;
input VAR3;
input VAR4 ;
input VAR7;
input VAR5;
VAR1 VAR2 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR6,
VAR3,
VAR4
);
output VAR6;
input VAR3;
input VAR4 ;
supply1 VAR7;
supply0 VAR5;
VAR1 VAR2 (
.VAR... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/acl_address_to_bankaddress.v | 1,822 | module MODULE1 #(
parameter integer VAR7 = 32, parameter integer VAR4 = 2, parameter integer VAR6 = VAR7-VAR8(VAR4)
)
(
input logic [VAR7-1:0] address,
output logic [VAR4-1:0] VAR1, output logic [VAR7-VAR8(VAR4)-1:0] VAR2
);
integer VAR3;
logic [VAR7:0] VAR5;
assign VAR5 = {1'b0,address};
always@*
begin
for (VAR3=0; VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4b/sky130_fd_sc_hs__or4b_4.v | 2,164 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR7 ,
VAR6 ,
VAR2 ,
VAR5,
VAR1
);
output VAR3 ;
input VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR5;
input VAR1;
VAR4 VAR9 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3 ,
VAR8 ,
VAR7 ,
VAR6 ,
VAR2... | apache-2.0 |
azonenberg/antikernel-ipcores | device_abstraction/ShiftRegisterMacro.v | 6,408 | module MODULE1 #(
parameter VAR3 = 16,
parameter VAR2 = 32,
parameter VAR4 = 5
) (
input wire clk,
input wire[VAR4-1 : 0] addr,
input wire[VAR3-1 : 0] din,
input wire VAR5,
output wire[VAR3-1 : 0] dout
, output reg[VAR3*VAR2 - 1 : 0] VAR1
);
generate | bsd-3-clause |
lvd2/ngs | fpga/obsolete/fpgaF_dma2/sound/sound_main2.v | 9,378 | module MODULE1(
VAR17,
VAR33, VAR24, VAR34,
VAR7, VAR14, VAR13, VAR6,
VAR30, VAR15, VAR36 );
input VAR17;
input VAR33;
input VAR24;
input VAR34;
input VAR7;
input VAR14;
input [2:0] VAR13;
input [7:0] VAR6;
output VAR30;
output VAR15;
output VAR36;
reg VAR10;
reg VAR4;
reg [5:0] VAR23;
reg VAR29;
reg VAR20, VAR39, VAR1... | gpl-3.0 |
gyurco/ZX_Spectrum-128K_MIST | gs.v | 7,637 | module MODULE1
(
input VAR22,
input VAR39,
input VAR54,
input VAR32,
input VAR68,
input [7:0] VAR10,
output [7:0] VAR33,
input VAR20,
input VAR49,
input VAR1,
output [20:0] VAR58,
output [7:0] VAR45,
input [7:0] VAR47,
output VAR56,
output VAR11,
input VAR16,
output [14:0] VAR3,
output [14:0] VAR23
);
parameter VAR13 =... | gpl-2.0 |
toyoshim/tvcl | SerialReceiver.v | 3,463 | module MODULE1(
VAR10,
VAR13,
VAR15,
VAR21,
VAR8,
VAR20);
input VAR10;
input VAR13;
input VAR15;
output [7:0] VAR21;
output VAR8;
output VAR20;
reg [1:0] VAR17;
reg [3:0] VAR9;
reg [7:0] VAR14;
wire VAR25;
wire VAR18;
wire VAR19;
wire VAR5;
wire VAR23;
localparam VAR3 = 4'b0000;
localparam VAR2 = 4'b0001;
localparam VA... | bsd-3-clause |
unihd-cag/openhmc | rtl/building_blocks/fifos/sync/xilinx/openhmc_srl_fifo_16.v | 4,583 | module MODULE1 #(
parameter VAR13 = 0,
parameter VAR10 = 0,
parameter VAR34 = 8
) (
input wire clk,
input wire VAR21,
input wire [VAR34-1:0] din,
input wire VAR26,
input wire VAR16,
output wire [VAR34-1:0]dout,
output reg VAR33,
output reg VAR23,
output reg VAR7,
output reg VAR4
);
reg [3:0] VAR25;
wire VAR27;
wire VAR... | lgpl-3.0 |
asicguy/gplgpu | hdl/ramdac_sp/ram_dp_8x512.v | 2,693 | module MODULE1
(
VAR6,
VAR1,
VAR7,
VAR2,
VAR5,
VAR9,
VAR3,
VAR10,
VAR11,
VAR8
);
input VAR6;
input VAR1;
input [8:0] VAR7;
input [7:0] VAR2;
input VAR5;
input VAR9;
input [8:0] VAR3;
input [7:0] VAR10;
output [7:0] VAR11,
VAR8;
reg [7:0] VAR11,
VAR8;
reg [7:0] VAR4 [0:511];
always @(posedge VAR6) if(VAR1) VAR4[VAR7] <=... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2.functional.v | 1,305 | module MODULE1 (
VAR6,
VAR2,
VAR1
);
output VAR6;
input VAR2;
input VAR1;
wire VAR3;
xnor VAR4 (VAR3, VAR2, VAR1 );
buf VAR5 (VAR6 , VAR3 );
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/nios_design_nios2_gen2_0_cpu_mult_cell.v | 8,084 | module MODULE1 (
VAR41,
VAR20,
VAR9,
clk,
VAR5,
VAR36,
VAR7,
VAR39
)
;
output [ 31: 0] VAR36;
output [ 31: 0] VAR7;
output [ 31: 0] VAR39;
input [ 31: 0] VAR41;
input [ 31: 0] VAR20;
input VAR9;
input clk;
input VAR5;
wire [ 31: 0] VAR36;
wire [ 31: 0] VAR7;
wire [ 31: 0] VAR39;
wire VAR1;
wire [ 31: 0] VAR50;
wire [ 3... | gpl-2.0 |
egyp7/mor1kx | rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v | 14,496 | module MODULE1
(
VAR39, VAR61, VAR64, VAR23, VAR24,
VAR36, VAR15, VAR11, VAR59,
VAR29, VAR56,
clk, rst, VAR34, VAR55, VAR58, VAR12,
VAR45, VAR47, VAR16, VAR44,
VAR19, VAR32, VAR28,
VAR20, VAR21, VAR42, VAR9
);
parameter VAR33 = 32;
parameter VAR18 = 5;
parameter VAR22 = {{(VAR33-13){1'b0}},
input clk, rst;
output [VAR3... | mpl-2.0 |
chriz2600/DreamcastHDMI | Core/source/pll_hdmi/pll_hdmi_reconf.v | 73,311 | module MODULE1
(
VAR116,
VAR178,
VAR185,
VAR218,
VAR104,
VAR70,
VAR56,
VAR94,
VAR142,
VAR88,
VAR153,
VAR92,
VAR35,
VAR14,
VAR54,
VAR219,
reset,
VAR168,
VAR207,
VAR18,
VAR103,
VAR68,
VAR206) ;
output VAR116;
input VAR178;
input [2:0] VAR185;
input [3:0] VAR218;
input [8:0] VAR104;
output [8:0] VAR70;
output VAR56;
input... | mit |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/clk_gen_top/clk_div_module.v | 5,571 | module MODULE1(
VAR5 , VAR6 , VAR4 , VAR3 );
input VAR5 ; input VAR6 ; output VAR4 ; output VAR3 ;
reg [01:00] VAR2 ;
always @(posedge VAR5 or negedge VAR6) begin : VAR1
if(!VAR6)
begin
VAR2 <= 'd0;
end
else
begin
VAR2 <= VAR2 + 1'b1;
end
end
assign VAR4 = VAR2[0];
assign VAR3 = VAR2[1];
endmodule | apache-2.0 |
joseluisquiroga/bj-actor-model | hlang/hgen_net/vlg_fnd/hprb_source.v | 2,028 | module MODULE1
VAR28=0,
VAR16=0,
VAR20=VAR11,
VAR6=VAR3,
VAR12=VAR13
)(
);
parameter VAR25 = VAR24;
reg [0:0] VAR8 = VAR26;
reg [VAR6-1:0] VAR9 = 0;
reg [0:0] VAR2 = VAR26;
reg [0:0] VAR32 = VAR26;
reg [0:0] VAR19 = VAR26;
reg [0:0] VAR21 = VAR26;
reg [VAR20-1:0] VAR15 = VAR28;
reg [VAR6-1:0] VAR30 = 0;
reg [VAR20-1:0]... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_v1_00_a/hdl/verilog/user_logic.v | 7,547 | module MODULE1 (
VAR18,
VAR36,
VAR26,
VAR5,
VAR34,
VAR24,
VAR16,
VAR35,
VAR40,
VAR17,
VAR11,
VAR28,
VAR9,
VAR31,
VAR7,
VAR29,
VAR13,
VAR6,
VAR44,
VAR4,
VAR25,
VAR42,
VAR3,
VAR14,
VAR23,
VAR33,
VAR15,
VAR39,
VAR2);
parameter VAR41 = 32;
parameter VAR10 = 32;
input VAR18;
input VAR36;
output VAR26;
output VAR5;
output [1... | mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_2_stub.v | 1,409 | module MODULE1(clk, rst, din, VAR1, VAR2, dout, VAR3, VAR4)
;
input clk;
input rst;
input [88:0]din;
input VAR1;
input VAR2;
output [88:0]dout;
output VAR3;
output VAR4;
endmodule | mit |
sabertazimi/hust-lab | architecture/design/fpga/src/instruction_typer.v | 3,049 | module MODULE1
(
input [5:0] VAR58,
input [5:0] VAR15,
output VAR41,
output VAR32,
output VAR34,
output VAR24,
output VAR51,
output VAR3,
output VAR10,
output VAR8,
output VAR39,
output VAR52,
output VAR20,
output VAR38,
output VAR35,
output VAR18,
output VAR26,
output VAR5,
output VAR47,
output VAR54,
output VAR55,
ou... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch3/FORMATTER.v | 2,329 | module MODULE1
(
input wire [VAR1-1:0] VAR7, output wire VAR4, output wire VAR10
);
wire [VAR1-1:0] VAR6; wire [VAR1-1:0] VAR3;
VAR13 #(.VAR14(VAR1)) VAR12 (
.VAR15(VAR7),
.VAR8(VAR6),
.VAR5(VAR4)
);
VAR9 #(.VAR14(VAR1)) VAR2 (
.VAR15(VAR7),
.VAR8(VAR3),
.VAR11(VAR10)
);
generate
if(VAR1 == 9) begin
assign VAR6 = 9'hfe... | gpl-3.0 |
mbus/mbus | m3_mbus_releases/r04p2g/source/lname_mbus_isolation.v | 3,314 | module MODULE1(
input VAR31,
input [VAR21-1:0] VAR24,
input [VAR30-1:0] VAR7,
input VAR12,
input VAR5,
input VAR13,
input VAR19,
input VAR29,
output reg [VAR21-1:0] VAR22,
output reg [VAR30-1:0] VAR4,
output reg VAR6,
output reg VAR2,
output reg VAR28,
output reg VAR18,
output reg VAR1,
input [VAR25-1:0] VAR8,
output r... | apache-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/ddr2/alt_ddrx_bypass.v | 45,264 | module MODULE1 #
( parameter
VAR116 = 2,
VAR140 = 4,
VAR35 = 16, VAR40 = 3,
VAR184 = 1,
VAR41 = 4,
VAR52 = 8
)
(
VAR58,
VAR33,
VAR27,
VAR101,
VAR77,
VAR18,
VAR161,
VAR114,
VAR14,
VAR55,
VAR142,
VAR128,
VAR118,
VAR84,
VAR48,
VAR170,
VAR130,
VAR137,
VAR6,
VAR190,
VAR104,
VAR87,
VAR91,
VAR121,
VAR60,
VAR7,
VAR120,
VAR150,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2oi/sky130_fd_sc_hd__a2bb2oi.symbol.v | 1,460 | module MODULE1 (
input VAR2,
input VAR5,
input VAR8 ,
input VAR4 ,
output VAR1
);
supply1 VAR7;
supply0 VAR9;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
q3k/q3kmips | rtl/verilog/qm_decode.v | 3,045 | module MODULE1(
input wire [31:0] VAR4,
input wire [4:0] VAR22,
input wire VAR12,
input wire [31:0] VAR34,
output wire [31:0] VAR26,
output wire [31:0] VAR24,
output wire [31:0] VAR29,
output wire [4:0] VAR25,
output wire [4:0] VAR31,
output wire [5:0] VAR10,
output wire [5:0] VAR8,
input wire VAR20,
input wire VAR35,
... | bsd-2-clause |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_clock_pair_generator.v | 4,067 | module MODULE1
(
VAR16,
VAR13,
VAR25) ;
input [0:0] VAR16;
output [0:0] VAR13;
output [0:0] VAR25;
wire [0:0] VAR1;
wire [0:0] VAR32;
wire [0:0] VAR10;
wire [0:0] VAR23;
wire [0:0] VAR6;
wire [0:0] VAR24;
wire [0:0] VAR9;
wire [0:0] VAR20;
wire [0:0] VAR35;
wire [0:0] VAR3;
VAR22 VAR18
(
.VAR5(VAR24),
.VAR7(VAR1[0:0]),... | gpl-3.0 |
kyzhai/NUNY | src/hardware/life_new_bb.v | 5,006 | module MODULE1 (
address,
VAR1,
VAR2);
input [9:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvp/sky130_fd_sc_hdll__einvp.blackbox.v | 1,276 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR5
);
output VAR6 ;
input VAR3 ;
input VAR5;
supply1 VAR7;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bushold0/sky130_fd_sc_lp__bushold0.symbol.v | 1,410 | module MODULE1 (
inout VAR4 ,
input VAR2
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbp/sky130_fd_sc_ls__sdfbbp.pp.symbol.v | 1,579 | module MODULE1 (
input VAR5 ,
output VAR2 ,
output VAR8 ,
input VAR10,
input VAR7 ,
input VAR6 ,
input VAR4 ,
input VAR1 ,
input VAR11 ,
input VAR3 ,
input VAR9 ,
input VAR12
);
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/ram_2port.v | 1,549 | module MODULE1
parameter VAR6=9)
(input VAR4,
input VAR1,
input VAR2,
input [VAR6-1:0] VAR12,
input [VAR14-1:0] VAR9,
output reg [VAR14-1:0] VAR13,
input VAR3,
input VAR7,
input VAR5,
input [VAR6-1:0] VAR16,
input [VAR14-1:0] VAR15,
output reg [VAR14-1:0] VAR8);
reg [VAR14-1:0] VAR10 [(1<<VAR6)-1:0];
integer VAR11;
beg... | gpl-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T06-multiples-prescalers/mpres.v | 1,933 | module MODULE1(input VAR5, output VAR3, output VAR17, output VAR10, output VAR11);
wire VAR5;
wire VAR3;
wire VAR17;
wire VAR10;
wire VAR11;
parameter VAR6 = 21; parameter VAR13 = 1;
parameter VAR18 = 2;
parameter VAR16 = 1;
parameter VAR1 = 2;
wire VAR4;
VAR15 #(.VAR19(VAR6))
VAR14(
.VAR5(VAR5),
.VAR9(VAR4)
);
VAR15 #... | gpl-2.0 |
hhuang25/uwaterloo_ece224 | Lab1Good/pio_pulse.v | 3,255 | module MODULE1 (
address,
VAR3,
clk,
VAR12,
VAR6,
VAR8,
VAR15,
irq,
VAR2
)
;
output irq;
output VAR2;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR12;
input VAR6;
input VAR8;
input VAR15;
wire VAR11;
reg VAR7;
reg VAR10;
wire VAR9;
reg VAR14;
wire VAR4;
wire VAR13;
wire irq;
reg VAR1;
wire VAR5;
reg VAR2;
ass... | mit |
fpgasystems/Centaur | rtl/mem/quick_fifo.v | 5,989 | module MODULE1 #(
parameter VAR9 = 32,
parameter VAR5 = 8,
parameter VAR27 = 2**VAR5 - 4
) (
input wire clk,
input wire VAR7,
input wire VAR21, input wire [VAR9 - 1:0] din,
input wire VAR23, output reg valid, output reg [VAR9 - 1:0] dout,
output reg [VAR5 - 1:0] VAR17, output reg VAR22, output reg VAR15, output reg VAR... | apache-2.0 |
BoolLi/Pollard-s-p-1-algorithm | BinaryExponentiation.v | 1,908 | module MODULE1( input clk, input [8:0] VAR4, input [7:0] VAR7, input reset,
output reg [99:0] VAR8, output reg VAR1
);
reg [99:0] VAR5;
reg VAR2;
reg [3:0] VAR6;
reg [3:0] VAR9;
reg VAR3;
reg VAR10; | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/med_hb_int.v | 3,424 | module MODULE1
(input clk,
input rst,
input VAR32,
input VAR40,
input [VAR18-1:0] VAR22,
input [7:0] VAR1,
input VAR41,
output reg [VAR18-1:0] VAR51);
localparam VAR16 = -597;
localparam VAR57 = 4283;
localparam VAR27 = -17516;
localparam VAR42 = 79365;
reg VAR19;
reg [VAR18-1:0] VAR34, VAR35, VAR39, VAR15, VAR17, VAR6... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_36b_v1_00_a/hdl/verilog/cf_hdmi_tx_36b.v | 12,230 | module MODULE1 (
VAR5,
VAR26,
VAR39,
VAR25,
VAR74,
VAR3,
VAR69,
VAR58,
VAR35,
VAR79,
VAR21,
VAR68,
VAR54,
VAR36,
VAR88,
VAR81,
VAR2,
VAR51,
VAR28,
VAR78,
VAR37,
VAR41,
VAR70,
VAR1);
input VAR5;
output VAR26;
output VAR39;
output VAR25;
output [35:0] VAR74;
input VAR3;
output VAR69;
input VAR58;
input VAR35;
input [ 7:0... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v | 55,990 | module MODULE1
VAR187 = 2,
VAR62 = 2, VAR16 = 16, VAR161 = 16, VAR108 = 12, VAR127 = 3, VAR122 = 1,
VAR36 = 3,
VAR124 = 2,
VAR19 = 2,
VAR209 = 8,
VAR7 = 4,
VAR2 = 4,
VAR206 = 1,
VAR90 = 2,
VAR8 = 5,
VAR144 = 5,
VAR190 = 5,
VAR80 = 4,
VAR58 = 4,
VAR150 = 2
)
(
VAR65,
VAR38,
VAR102,
VAR149,
VAR162,
VAR202,
VAR97,
VAR20,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a.functional.pp.v | 2,036 | module MODULE1 (
VAR11 ,
VAR8 ,
VAR12 ,
VAR14 ,
VAR2 ,
VAR15,
VAR4,
VAR5 ,
VAR6
);
output VAR11 ;
input VAR8 ;
input VAR12 ;
input VAR14 ;
input VAR2 ;
input VAR15;
input VAR4;
input VAR5 ;
input VAR6 ;
wire VAR13 ;
wire VAR1 ;
wire VAR3;
or VAR17 (VAR13 , VAR12, VAR8 );
and VAR7 (VAR1 , VAR13, VAR14, VAR2 );
VAR9 VAR1... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/RCA_N20_syn.v | 8,538 | module MODULE1 ( VAR70, VAR269, VAR165 );
input [19:0] VAR70;
input [19:0] VAR269;
output [20:0] VAR165;
wire VAR123, VAR270, VAR296, VAR247, VAR299, VAR8, VAR186, VAR278, VAR95, VAR212, VAR122, VAR128, VAR30, VAR6, VAR126,
VAR11, VAR233, VAR29, VAR158, VAR205, VAR239, VAR245, VAR257, VAR58, VAR19, VAR118, VAR83, VAR86... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb_4.v | 2,334 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR6 ,
VAR8 ,
VAR11 ,
VAR5,
VAR9,
VAR3 ,
VAR1
);
output VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR8 ;
input VAR11 ;
input VAR5;
input VAR9;
input VAR3 ;
input VAR1 ;
VAR4 VAR10 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1.behavioral.pp.v | 1,867 | module MODULE1 (
VAR10 ,
VAR12 ,
VAR1,
VAR9,
VAR11 ,
VAR8
);
output VAR10 ;
input VAR12 ;
input VAR1;
input VAR9;
input VAR11 ;
input VAR8 ;
wire VAR5 ;
wire VAR3;
not VAR6 (VAR5 , VAR12 );
VAR7 VAR4 (VAR3, VAR5, VAR1, VAR9);
buf VAR2 (VAR10 , VAR3 );
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/ICAP_config.v | 2,540 | module MODULE1
(
input VAR1,
input [3:0] VAR15,
output [3:0] VAR4,
input [2:0] VAR8,
input VAR21,
inout [7:0] VAR7,
input VAR14,
input VAR3,
input VAR16
);
reg VAR19 = 1'b0;
reg VAR6 = 1'b0;
reg VAR12 = 1'b0;
reg [4:0] VAR5;
wire [3:0] VAR2;
wire VAR13;
reg VAR17 = 1'b1;
reg VAR11;
reg [2:0] VAR10;
reg VAR18;
VAR9 VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.v | 2,345 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR9 ,
VAR10 ,
VAR8 ,
VAR11,
VAR4,
VAR1 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR9 ;
input VAR10 ;
input VAR8 ;
input VAR11;
input VAR4;
input VAR1 ;
input VAR3 ;
VAR5 VAR2 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR1(VAR1),
.... | apache-2.0 |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/RegFile_1port.v | 3,072 | module MODULE1(VAR2, VAR5,
VAR4, VAR9, VAR7,
VAR3, VAR11
);
parameter VAR6 = 1;
parameter VAR8 = 1;
parameter VAR10 = 1<<VAR8;
input VAR2;
input VAR5;
input [VAR8 - 1 : 0] VAR4;
input [VAR6 - 1 : 0] VAR9;
input VAR7;
input [VAR8 - 1 : 0] VAR3;
output [VAR6 - 1 : 0] VAR11;
reg [VAR6 - 1 : 0] VAR12[0 : VAR10-1];
always@(... | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/axis_xgmii_rx_32.v | 11,277 | module MODULE1 #
(
parameter VAR9 = 32,
parameter VAR15 = (VAR9/8),
parameter VAR7 = (VAR9/8),
parameter VAR5 = 0,
parameter VAR17 = 96,
parameter VAR13 = (VAR5 ? VAR17 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR9-1:0] VAR1,
input wire [VAR7-1:0] VAR3,
output wire [VAR9-1:0] VAR14,
output wire [VAR15-1... | mit |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/usb_system_keycode.v | 2,256 | module MODULE1 (
address,
VAR5,
clk,
VAR3,
VAR2,
VAR7,
VAR4,
VAR9
)
;
output [ 7: 0] VAR4;
output [ 31: 0] VAR9;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR3;
input VAR2;
input [ 31: 0] VAR7;
wire VAR1;
reg [ 7: 0] VAR8;
wire [ 7: 0] VAR4;
wire [ 7: 0] VAR6;
wire [ 31: 0] VAR9;
assign VAR1 = 1;
assign VAR6 ... | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_lvds_clk.v | 3,291 | module MODULE1 (
VAR13,
VAR3,
clk);
parameter VAR10 = 0;
localparam VAR2 = 0;
localparam VAR8 = 1;
input VAR13;
input VAR3;
output clk;
wire VAR18;
VAR1 VAR12 (
.VAR11 (VAR13),
.VAR17 (VAR3),
.VAR9 (VAR18));
generate
if (VAR10 == VAR8) begin
VAR16 #(.VAR4("VAR15")) VAR5 (
.VAR19 (1'b0),
.VAR14 (1'b1),
.VAR11 (VAR18),
.... | lgpl-3.0 |
toomij/DE2Labs | Lab2/lab2_part4.v | 3,065 | module MODULE7 (VAR29, VAR26, VAR21, VAR24, VAR2);
input [17:0] VAR29;
output [8:0] VAR21, VAR26;
output [0:6] VAR24, VAR2;
assign VAR21[8:0] = VAR29[8:0];
wire VAR35, VAR23;
MODULE5 VAR15 (VAR29[3:0], VAR35);
MODULE5 VAR20 (VAR29[7:4], VAR23);
assign VAR26[8] = VAR35 | VAR23;
wire MODULE11, MODULE4, VAR7;
wire [4:0] V... | gpl-2.0 |
dawsonjon/fpu | double_multiplier/double_multiplier.v | 6,518 | module MODULE1(
VAR11,
VAR20,
VAR15,
VAR27,
VAR28,
clk,
rst,
VAR5,
VAR14,
VAR6,
VAR30);
input clk;
input rst;
input [63:0] VAR11;
input VAR15;
output VAR6;
input [63:0] VAR20;
input VAR27;
output VAR30;
output [63:0] VAR5;
output VAR14;
input VAR28;
reg VAR32;
reg [63:0] VAR3;
reg VAR17;
reg VAR37;
reg [3:0] state;
par... | mit |
mballance/oc_wb_ip | rtl/wb_dma/rtl/verilog/wb_dma_wb_mast.v | 6,474 | module MODULE1(clk, rst,
VAR10, VAR13, VAR15, VAR16, VAR2, VAR1,
VAR6, VAR3, VAR8, VAR22,
VAR27, VAR11, VAR9, VAR21, VAR14, VAR5, VAR17,
VAR24, VAR4,
VAR25, VAR23, VAR7
);
input clk, rst;
input [31:0] VAR10;
output [31:0] VAR13;
output [31:0] VAR15;
output [3:0] VAR16;
output VAR2;
output VAR1;
output VAR6;
input VAR3;... | apache-2.0 |
Digilent/vivado-library | ip/Pmods/PmodMTDS_v1_0/src/PmodMTDS.v | 19,960 | module MODULE1
(VAR236,
VAR115,
VAR168,
VAR110,
VAR132,
VAR162,
VAR160,
VAR268,
VAR77,
VAR101,
VAR37,
VAR71,
VAR62,
VAR126,
VAR220,
VAR45,
VAR164,
VAR131,
VAR151,
VAR203,
VAR70,
VAR267,
VAR250,
VAR146,
VAR231,
VAR9,
VAR181,
VAR24,
VAR109,
VAR193,
VAR32,
VAR241,
VAR36,
VAR273,
VAR63,
VAR144,
VAR212,
VAR72,
VAR26,
VAR177... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fah/sky130_fd_sc_hs__fah.behavioral.v | 2,485 | module MODULE1 (
VAR22,
VAR18 ,
VAR11 ,
VAR7 ,
VAR24 ,
VAR12,
VAR16
);
output VAR22;
output VAR18 ;
input VAR11 ;
input VAR7 ;
input VAR24 ;
input VAR12;
input VAR16;
wire VAR23 ;
wire VAR2 ;
wire VAR21 ;
wire VAR15 ;
wire VAR13 ;
wire VAR14 ;
wire VAR10;
xor VAR1 (VAR23 , VAR11, VAR7, VAR24 );
VAR5 VAR3 (VAR2 , VAR23,... | apache-2.0 |
karshan/fpga-rgbmatrix | src/rgbmatrix.v | 3,318 | module MODULE1 (
input clk,
input rst,
output reg VAR13,
output reg VAR1,
output reg VAR8,
output reg VAR6,
output reg VAR18,
output reg VAR22,
output reg VAR4,
output reg VAR15,
output reg VAR7,
output reg VAR5,
output reg VAR23,
output reg VAR21,
output reg VAR3
);
localparam VAR14 = 0,
VAR19 = 1,
VAR16 = 2,
VAR9 = 3... | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/sram_init.v | 4,206 | module MODULE1;
reg [7:0] VAR5 [135005:0];
reg [31:0] VAR3;
task VAR4;
integer VAR10;
begin
for (VAR10=0; VAR10 < 135000; VAR10=VAR10+4) begin
VAR9.VAR1.VAR7[VAR10/4] = VAR5[VAR10];
VAR9.VAR8.VAR7[VAR10/4] = VAR5[VAR10+1];
VAR9.VAR11.VAR7[VAR10/4] = VAR5[VAR10+2];
VAR9.VAR6.VAR7[VAR10/4] = VAR5[VAR10+3];
end
for (VAR10... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv.behavioral.v | 1,326 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR8 ;
supply0 VAR5 ;
supply1 VAR4;
supply1 VAR7 ;
supply0 VAR2 ;
buf VAR6 (VAR1 , VAR3 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck.v | 9,515 | module MODULE1 (
VAR32,
VAR11,
VAR25,
VAR30,
VAR6,
VAR17,
VAR27,
VAR2,
VAR21,
VAR24,
VAR13,
VAR12,
VAR29,
VAR7,
VAR31,
VAR38,
VAR23,
VAR9,
VAR1,
VAR18,
VAR8,
VAR22,
VAR34,
VAR40,
VAR15,
VAR39,
VAR3,
VAR16,
VAR5,
VAR26,
VAR36
)
;
output [ 1: 0] VAR3;
output VAR16;
output [ 37: 0] VAR5;
output VAR26;
output VAR36;
input ... | lgpl-3.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/fpuuart/Mux_8x1.v | 1,173 | module MODULE1
(
input wire [2:0] select,
input wire [7:0] VAR8,
input wire [7:0] VAR6,
input wire [7:0] VAR7,
input wire [7:0] VAR2,
input wire [7:0] VAR5,
input wire [7:0] VAR4,
input wire [7:0] VAR9,
input wire [7:0] VAR3,
output reg [7:0] VAR1
);
always @*
begin
case(select)
3'b111: VAR1 = VAR8;
3'b110: VAR1 = VAR6... | gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/LX150_makomk_dualcore/hdl/golden_nonce_fifo.v | 13,376 | module MODULE1(
VAR362,
VAR265,
din,
VAR213,
VAR287,
dout,
VAR329,
VAR280
);
input VAR362;
input VAR265;
input [31 : 0] din;
input VAR213;
input VAR287;
output [31 : 0] dout;
output VAR329;
output VAR280;
VAR47 #(
.VAR413(0),
.VAR328(0),
.VAR199(0),
.VAR50(0),
.VAR371(0),
.VAR249(0),
.VAR7(0),
.VAR349(32),
.VAR254(1),
... | gpl-3.0 |
google/yaricv32 | regs.v | 1,531 | module MODULE1(
input rst,
input clk,
input VAR4,
input [VAR1-1 : 0] VAR7,
input [VAR1-1 : 0] VAR12,
input [VAR1-1 : 0] VAR6,
input [VAR8-1 : 0] VAR14,
output [VAR8-1 : 0] VAR3,
output [VAR8-1 : 0] VAR5);
parameter VAR1 = 5;
parameter VAR8 = 32;
parameter VAR2 = 2;
parameter VAR13 = 1024; localparam VAR11 = 1 << VAR1;
... | apache-2.0 |
svofski/mahponk | src/scores2.v | 7,722 | module MODULE4(clk, VAR54, VAR43, VAR62, VAR12, VAR5, VAR25, VAR4, VAR27, VAR29);
input clk;
input VAR54;
input [9:0] VAR43, VAR62;
input VAR12, VAR5, VAR25;
output [7:0]VAR4, VAR27;
output VAR29;
wire VAR76, VAR11, VAR48, VAR18;
wire [3:0] VAR42;
wire [3:0] VAR53;
wire [3:0] VAR59;
wire [3:0] VAR17;
MODULE6 MODULE3(VA... | bsd-2-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.v | 7,883 | module MODULE1 (
input VAR50,
input VAR28,
input VAR110,
input [31:0] VAR68,
output VAR46,
input [2:0] VAR82,
input VAR21,
input [31:0] VAR59,
input [ 3:0] VAR88,
output VAR3,
output VAR29,
output [ 1:0] VAR22,
input VAR67,
input VAR62,
input [31:0] VAR129,
output VAR17,
input [2:0] VAR66,
output VAR37,
input VAR119,
o... | gpl-3.0 |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_master_slave_fast.v | 2,154 | module MODULE1
(
input rst,
input clk,
input [68:0] VAR1,
output [68:0] VAR20,
input VAR8,
input [1:0] VAR24,
output VAR30,
input wr,
input [3:0] VAR22,
input [23:0] addr,
input [31:0] VAR13,
output VAR23,
output VAR18,
output [1:0] VAR3,
output [3:0] VAR7,
output [23:0] VAR31,
output [31:0] VAR4,
output VAR27,
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor2/sky130_fd_sc_ls__xnor2.pp.blackbox.v | 1,301 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2 ,
VAR7,
VAR5,
VAR3 ,
VAR6
);
output VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR7;
input VAR5;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/Pmods/PmodGYRO_v1_0/src/PmodGYRO.v | 13,590 | module MODULE1
(VAR47,
VAR101,
VAR214,
VAR132,
VAR11,
VAR96,
VAR168,
VAR21,
VAR76,
VAR189,
VAR194,
VAR9,
VAR112,
VAR51,
VAR57,
VAR46,
VAR23,
VAR142,
VAR78,
VAR68,
VAR97,
VAR130,
VAR13,
VAR94,
VAR199,
VAR62,
VAR88,
VAR77,
VAR44,
VAR137,
VAR109,
VAR49,
VAR181,
VAR191,
VAR141,
VAR175,
VAR40,
VAR85,
VAR92,
VAR54,
VAR198,
V... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/01BLUETOOTH/Version_02/02 verilog/periferico_BT/peripheral_bt.v | 1,967 | module MODULE1(clk , rst , din , VAR10 , addr , rd , wr, dout, VAR14, VAR7 );
input clk;
input rst;
input [15:0]din;
input VAR10;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
output VAR7;
output VAR14;
reg [5:0] VAR8;
reg VAR16;
reg [7:0] VAR6; wire VAR13;
wire VAR3; wire VAR4;
wire VAR9;
VAR12 VAR19(.VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv_8.v | 2,003 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR5,
VAR1,
VAR3 ,
VAR6
);
output VAR2 ;
input VAR7 ;
input VAR5;
input VAR1;
input VAR3 ;
input VAR6 ;
VAR4 VAR8 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR2,
VAR7
);
output VAR2;
input VAR7;
supply1 VAR5;
supply0 VAR1;... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/26bit/BinaryKOA/ks16.v | 1,893 | module MODULE1(VAR5, VAR4, VAR11);
input wire [15:0] VAR5;
input wire [15:0] VAR4;
output wire [30:0] VAR11;
wire [14:0] VAR12;
wire [14:0] VAR9;
wire [14:0] VAR7;
wire [7:0] VAR2;
wire [7:0] VAR10;
VAR1 VAR6(VAR5[7:0], VAR4[7:0], VAR9);
VAR1 VAR8(VAR5[15:8], VAR4[15:8], VAR12);
assign VAR2[7:0] = VAR5[15:8] ^ VAR5[7:0... | gpl-3.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/mpx/mpx_regfile_xil.v | 5,791 | module MODULE1
(
VAR39,
VAR14,
VAR16,
VAR26,
VAR22,
VAR24,
VAR4,
VAR23,
VAR30,
VAR38
);
input VAR39 ;
input VAR14 ;
input VAR16 ;
input VAR26 ;
input [4:0] VAR22 ;
input [4:0] VAR24 ;
input [4:0] VAR4 ;
output [31:0] VAR23 ;
output [31:0] VAR30 ;
input [31:0] VAR38 ;
reg [4:0] VAR37;
wire [31:0] VAR31;
wire [31:0] VAR3... | mit |
peteasa/parallella-fpga | ohLocal/common/dv/dv_ctrl_local.v | 2,459 | module MODULE1(
VAR12, VAR15, VAR10, VAR13,
VAR14, VAR16, VAR7
);
parameter VAR3 = 10;
parameter VAR5 = VAR3/2;
parameter VAR9 = 100;
parameter VAR8 = VAR9/2;
parameter VAR6 = 50000;
parameter VAR4 = 10000;
output VAR12; output VAR15; output VAR10; output VAR13;
input VAR14; input VAR16; input VAR7;
reg VAR12;
reg VAR1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2.pp.symbol.v | 1,330 | module MODULE1 (
input VAR4 ,
output VAR1 ,
input VAR6 ,
input VAR2,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_idelay32.v | 9,689 | module MODULE1(
input [31:0] VAR8,
output [31:0] VAR36,
input VAR35,
input VAR26,
input VAR20,
input VAR29,
input VAR19,
input VAR47,
input VAR30
);
VAR9 #(
.VAR44("VAR8"),
.VAR38("VAR13"),
.VAR27("VAR22")
) VAR37 (
.VAR8(VAR8[0]),
.VAR36(VAR36[0]),
.VAR35(VAR35),
.VAR26(VAR26),
.VAR20(VAR20),
.VAR19(VAR19),
.VAR47(VAR... | lgpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ui_rd_data.v | 19,405 | module MODULE1 #
(
parameter VAR7 = 100,
parameter VAR52 = 256,
parameter VAR27 = 5,
parameter VAR14 = "VAR88",
parameter VAR18 = 2 ,
parameter VAR2 = "VAR9"
)
(
VAR65, VAR47, VAR8, VAR13,
VAR59, VAR23, VAR60, VAR58,
rst, clk, VAR68, VAR72, VAR79, VAR89,
VAR87, VAR1, VAR50
);
input rst;
input clk;
output wire VAR65;
ou... | mit |
c4puter/bridge-hdl | modules/drac_wb_adapter/drac_wb_adapter.v | 4,386 | module MODULE1 (
output VAR14,
output VAR2,
output [33:5] VAR21,
output [255:0] VAR19,
output [31:0] VAR22,
input [255:0] VAR6,
input VAR15,
input VAR3,
input [35:0] VAR8,
input VAR17,
input [3:0] VAR12,
input VAR18,
input VAR13,
input [31:0] VAR7,
output [31:0] VAR9,
output VAR1,
input VAR10,
input reset
);
reg [31:0]... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_mm_interconnect_0_avalon_st_adapter.v | 6,158 | module MODULE1 #(
parameter VAR18 = 34,
parameter VAR8 = 0,
parameter VAR23 = 34,
parameter VAR12 = 0,
parameter VAR16 = 0,
parameter VAR5 = 0,
parameter VAR22 = 1,
parameter VAR1 = 1,
parameter VAR7 = 0,
parameter VAR21 = 34,
parameter VAR6 = 0,
parameter VAR17 = 1,
parameter VAR10 = 0,
parameter VAR13 = 1,
parameter ... | gpl-3.0 |
tdaede/daala_zynq | daala_4x4_transpose_1.0/hdl/daala_4x4_transpose_v1_0_S00_AXIS.v | 4,931 | module MODULE1 #
(
parameter integer VAR17 = 32
)
(
input wire VAR21,
input wire VAR18,
output wire VAR6,
input wire [VAR17-1 : 0] VAR2,
input wire [(VAR17/8)-1 : 0] VAR15,
input wire VAR7,
input wire VAR4
);
function integer VAR13 (input integer VAR23);
begin
for(VAR13=0; VAR23>0; VAR13=VAR13+1)
VAR23 = VAR23 >> 1;
en... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtp/sky130_fd_sc_ms__dlxtp.symbol.v | 1,339 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR3
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_auto_pc_3/synth/OpenSSD2_auto_pc_3.v | 15,727 | module MODULE1 (
VAR94,
VAR73,
VAR52,
VAR64,
VAR68,
VAR107,
VAR33,
VAR26,
VAR51,
VAR109,
VAR17,
VAR96,
VAR90,
VAR57,
VAR82,
VAR9,
VAR4,
VAR105,
VAR23,
VAR48,
VAR37,
VAR75,
VAR38,
VAR110,
VAR89,
VAR22,
VAR18,
VAR31,
VAR2,
VAR45,
VAR53,
VAR60,
VAR16,
VAR30,
VAR36,
VAR47,
VAR102,
VAR66,
VAR76,
VAR98,
VAR91,
VAR69,
VAR95,
... | gpl-3.0 |
eda-globetrotter/PicenoDecoders | extra_credit/spare/build1/ee577bHw2q1a.v | 9,012 | module MODULE1(VAR12,VAR21,VAR15,VAR17,VAR9,
VAR14,VAR2,VAR8,clk,reset);
output reg VAR12,VAR21,VAR15,VAR17,VAR9;
input [6:0] VAR14,VAR2;
input VAR8,clk,reset;
reg [3:0] state, VAR10;
reg [6:0] VAR7;
reg VAR20;
parameter VAR11 = 4'b0000;
parameter VAR13 = 4'b0001;
parameter VAR1 = 4'b0010;
parameter VAR6 = 4'b0011;
par... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3/sky130_fd_sc_hs__nand3_2.v | 2,048 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR8 ,
VAR2 ,
VAR7,
VAR5
);
output VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR7;
input VAR5;
VAR1 VAR3 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR4,
VAR6,
VAR8,
VAR2
);
output VAR4;
input VAR6;
input VAR8;
in... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkmux2/sky130_fd_sc_hdll__clkmux2.blackbox.v | 1,282 | module MODULE1 (
VAR8 ,
VAR7,
VAR1,
VAR3
);
output VAR8 ;
input VAR7;
input VAR1;
input VAR3 ;
supply1 VAR4;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/packet_memory_block.v | 4,531 | module MODULE1(
clk,
VAR7,
addr,
VAR11,
VAR20
);
input clk;
input [3:0] VAR7;
input [5:0] addr;
input [31:0] VAR11;
output [31:0] VAR20;
genvar VAR16;
generate
for(VAR16 = 0; VAR16 < 4; VAR16 = VAR16 + 1) begin:VAR5
VAR15 #(.VAR17(64'h0000000000000000))
VAR24(
.VAR8(VAR20[VAR16*8]), .VAR23(addr[0]), .VAR25(addr[1]), .V... | mit |
silverfoxy/MIPS-Verilog | Pipeline/reg_bank.v | 1,089 | module MODULE1(clk, VAR2, VAR1, VAR6, VAR9, wr, VAR5, din, VAR8, VAR4, VAR3);
input clk;
input wr;
input [4:0] VAR2, VAR6, VAR5;
input [31:0] din;
output reg[31:0] VAR1, VAR9;
output wire[31:0] VAR8;
output wire[31:0] VAR4;
output wire[31:0] VAR3;
reg [31:0] VAR7 [0:31];
assign VAR8 = VAR7[5'b00001];
assign VAR4 = VAR7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2_4.v | 2,203 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR1 ,
VAR5 ,
VAR7,
VAR3,
VAR6 ,
VAR2
);
output VAR10 ;
input VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR7;
input VAR3;
input VAR6 ;
input VAR2 ;
VAR8 VAR9 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
545/Atari7800 | new_atari/project_1/project_1.srcs/sources_1/imports/Atari7800/riot/riot.v | 5,238 | module MODULE1(VAR20, VAR13, VAR17, VAR14, VAR28, VAR1, VAR7, VAR11, VAR10, VAR19, VAR30, VAR2, VAR29, VAR33); input [6:0] VAR20;
input [7:0] VAR13;
output [7:0] VAR17;
input VAR14, VAR28, VAR1, VAR7, VAR11, VAR19;
output VAR10;
input [7:0] VAR30, VAR29;
output [7:0] VAR2, VAR33; reg [7:0] VAR17; reg [7:0] VAR22[127:0]... | gpl-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_nh_lcd/rtl/nh_lcd_data_writer.v | 6,064 | module MODULE1#(
parameter VAR19 = 12
)(
input rst,
input clk,
output [31:0] VAR52,
input VAR33,
input [31:0] VAR35,
input VAR49,
output [1:0] VAR14,
input [1:0] VAR17,
input VAR4,
output [23:0] VAR13,
input [31:0] VAR23,
output VAR50,
output [7:0] VAR36,
input [7:0] VAR30,
output VAR6,
output VAR26,
output VAR27,
inpu... | mit |
zKarp/Karpentium-Processor | src/verilog/controller.v | 4,034 | module MODULE1(clk,VAR17,VAR18,VAR2,VAR20,VAR10,VAR5,VAR9,VAR1,VAR14,VAR19,VAR15,VAR3,VAR4,VAR11,VAR6,VAR13,VAR7);
input clk,VAR17;
input [3:0]VAR18;
output reg VAR20,VAR10,VAR5;
output reg [1:0] VAR2,VAR9;
output VAR1,VAR14,VAR19,VAR15,VAR3,VAR4,VAR11,VAR6;
reg VAR1,VAR14,VAR19,VAR15,VAR3,VAR4,VAR11,VAR6;
output reg V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.symbol.v | 1,486 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR2 ,
input VAR7 ,
input VAR3,
input VAR1 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22o/sky130_fd_sc_ls__a22o.functional.v | 1,511 | module MODULE1 (
VAR11 ,
VAR1,
VAR7,
VAR12,
VAR10
);
output VAR11 ;
input VAR1;
input VAR7;
input VAR12;
input VAR10;
wire VAR3 ;
wire VAR6 ;
wire VAR2;
and VAR9 (VAR3 , VAR12, VAR10 );
and VAR4 (VAR6 , VAR1, VAR7 );
or VAR8 (VAR2, VAR6, VAR3);
buf VAR5 (VAR11 , VAR2 );
endmodule | apache-2.0 |
walkthetalk/fsref | ip/axis_reshaper/src/axis_reshaper.v | 5,135 | module MODULE1 #
(
parameter integer VAR22 = 8,
parameter integer VAR10 = 2,
parameter integer VAR33 = 12,
parameter integer VAR1 = 12
) (
input wire clk,
input wire VAR14,
input wire VAR2,
input wire [VAR22-1:0] VAR9,
input wire VAR18,
input wire VAR13,
output reg VAR12,
output wire VAR17,
output wire [VAR22-1:0] VAR7... | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | contador_AD_SS_2dig.v | 4,764 | module MODULE1
(
input wire clk,
input wire reset,
input wire [3:0] VAR1,
input wire VAR7,
input wire VAR8,
output wire [7:0] VAR3);
localparam VAR2 = 6; reg [VAR2-1:0] VAR9, VAR4;
wire [VAR2-1:0] VAR5;
reg [3:0] VAR10, VAR6;
always@(posedge clk, posedge reset)
begin
if(reset)
begin
VAR9 <= 6'b0;
end
else
begin
VAR9 <=... | mit |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkNear_Mem_IO_AXI4.v | 97,898 | module MODULE1(VAR170,
VAR2,
VAR201,
VAR165,
VAR48,
VAR338,
VAR320,
VAR258,
VAR3,
VAR47,
VAR251,
VAR292,
VAR168,
VAR91,
VAR200,
VAR310,
VAR127,
VAR196,
VAR259,
VAR75,
VAR245,
VAR26,
VAR138,
VAR134,
VAR341,
VAR122,
VAR132,
VAR265,
VAR162,
VAR29,
VAR250,
VAR303,
VAR183,
VAR92,
VAR98,
VAR112,
VAR95,
VAR81,
VAR205,
VAR246,... | apache-2.0 |
ShepardSiegel/ocpi | coregen/temac_v6/example_design/v6_emac_v1_3_block.v | 14,569 | module MODULE1
(
VAR64,
VAR77,
VAR65,
VAR5,
VAR69,
VAR21,
VAR18,
VAR8,
VAR11,
VAR53,
VAR75,
VAR80,
VAR55,
VAR60,
VAR30,
VAR84,
VAR68,
VAR87,
VAR2,
VAR14,
VAR36,
VAR81,
VAR71,
VAR6,
VAR29,
VAR62,
VAR41,
VAR58,
VAR13,
VAR12,
VAR15,
VAR9,
VAR22,
VAR7,
VAR3,
VAR50,
VAR52,
VAR72,
VAR28,
VAR56,
VAR82,
VAR74,
VAR61,
VAR32,
VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o_1.v | 2,426 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR12 ,
VAR8 ,
VAR10 ,
VAR1 ,
VAR3,
VAR4,
VAR5 ,
VAR9
);
output VAR7 ;
input VAR2 ;
input VAR12 ;
input VAR8 ;
input VAR10 ;
input VAR1 ;
input VAR3;
input VAR4;
input VAR5 ;
input VAR9 ;
VAR6 VAR11 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311ai/sky130_fd_sc_ms__o311ai.functional.v | 1,481 | module MODULE1 (
VAR11 ,
VAR7,
VAR8,
VAR5,
VAR9,
VAR4
);
output VAR11 ;
input VAR7;
input VAR8;
input VAR5;
input VAR9;
input VAR4;
wire VAR3 ;
wire VAR2;
or VAR10 (VAR3 , VAR8, VAR7, VAR5 );
nand VAR6 (VAR2, VAR4, VAR3, VAR9);
buf VAR1 (VAR11 , VAR2 );
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | final/src/tosynth Folder/alu.v | 176,760 | module MODULE1 (VAR21,VAR12,VAR2,VAR11,VAR27);
output [0:127] VAR27;
input [0:127] VAR21;
input [0:127] VAR12;
input [0:1] VAR2;
input [0:4] VAR11;
parameter VAR10 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR27;
reg [0:127] VAR37;
reg [0:15] VAR6;
reg [0:15] VAR7;
reg [0:15] VAR13;
reg [0:15] VAR24;
reg [0:... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/cordic.v | 4,281 | module MODULE1(VAR54, reset, enable, VAR40, VAR9, VAR19, VAR6, VAR66, VAR49 );
parameter VAR41 = 16;
parameter VAR77 = 16;
input VAR54;
input reset;
input enable;
input [VAR41-1:0] VAR40, VAR9;
output [VAR41-1:0] VAR6, VAR66;
input [VAR77-1:0] VAR19;
output [VAR77-1:0] VAR49;
reg [VAR41+1:0] VAR39,VAR43;
reg [VAR77-2:0... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.behavioral.pp.v | 1,686 | module MODULE1( VAR8, VAR4, VAR5, VAR9, VAR2, VAR6 );
input VAR9, VAR4, VAR5;
inout VAR2, VAR6;
output VAR8;
VAR3 VAR1(.VAR8(VAR8),.VAR4(VAR4),.VAR5(VAR5),.VAR9(VAR9),.VAR2(VAR2),.VAR6(VAR6));
VAR3 VAR7(.VAR8(VAR8),.VAR4(VAR4),.VAR5(VAR5),.VAR9(VAR9),.VAR2(VAR2),.VAR6(VAR6)); | apache-2.0 |
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