repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4/sky130_fd_sc_hd__nor4.functional.v | 1,329 | module MODULE1 (
VAR1,
VAR8,
VAR6,
VAR4,
VAR7
);
output VAR1;
input VAR8;
input VAR6;
input VAR4;
input VAR7;
wire VAR2;
nor VAR5 (VAR2, VAR8, VAR6, VAR4, VAR7 );
buf VAR3 (VAR1 , VAR2 );
endmodule | apache-2.0 |
alankarkotwal/lca-processor | processor/lca_processor.v | 9,402 | module MODULE1(clk,reset);
input clk,reset;
wire [15:0] VAR26, VAR244 ,VAR214 ,VAR95, VAR42, VAR170, VAR86, VAR167,
VAR110, VAR24, VAR245, VAR121, VAR251, VAR37, VAR193,
VAR130, VAR32, VAR16, VAR208, VAR224, VAR141, VAR234, VAR118,
VAR157, VAR104, VAR200, VAR34, VAR100, VAR165, VAR242, VAR258,
VAR135, VAR153, VAR106, V... | gpl-2.0 |
danidim13/labo-digitales | Experimento4/Module_ROM.v | 1,894 | module MODULE1
(
input wire[15:0] VAR12,
output reg [27:0] VAR11
);
always @ ( VAR12 )
begin
case (VAR12)
0: VAR11 = { VAR14 ,24'd4000 };
1: VAR11 = { VAR16 ,VAR1, 16'h0002};
2: VAR11 = { VAR16 ,VAR13, 16'h0005};
3: VAR11 = { VAR16 ,VAR10, 16'h0008};
4: VAR11 = { VAR9, 8'd14, 16'd0};
5: VAR11 = { VAR16 ,VAR8, 16'h0000}... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/CLS_Fadeout_Timer.v | 1,854 | module MODULE1
parameter VAR4 = 50000000, parameter VAR2 = 1000 )
(
output reg VAR3,
input VAR1
);
begin
begin
begin
end
begin | mit |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/acquire/raw_acquire.v | 5,259 | module MODULE1
parameter VAR19 = 0,
parameter VAR43 = 3)
(
input VAR23, input VAR37,
input VAR29, input VAR5,
input VAR35,
input VAR33, input VAR13, input [VAR26:0] VAR3,
output VAR15,
output VAR45,
input VAR39,
output [VAR22:0] VAR31,
output [31:0] VAR21,
output VAR4, output [2:0] VAR42 );
wire [VAR26:0] VAR24;
wire [... | lgpl-3.0 |
cpulabs/mist1032isa | src/core/dispatch/dispatch_general_register.v | 5,371 | module MODULE1(
input wire VAR22,
input wire VAR26,
input wire VAR9,
input wire VAR31,
input wire [4:0] VAR5,
input wire [31:0] VAR15,
input wire [4:0] VAR32,
output wire [31:0] VAR11,
input wire [4:0] VAR17,
output wire [31:0] VAR44,
output wire [31:0] VAR27,
output wire [31:0] VAR19,
output wire [31:0] VAR25,
output ... | bsd-2-clause |
rohit21122012/CPU | MU/Register.v | 1,762 | module MODULE1(
input VAR2,clk,reset,VAR3,VAR7;
output VAR6;
wire VAR5,VAR1,VAR11;
VAR4 VAR9(VAR5,VAR2,VAR3,VAR1);
VAR8 VAR12(VAR5, VAR11, clk,reset, VAR1);
VAR10 VAR13(VAR6, VAR5, VAR7);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2b/sky130_fd_sc_ms__nor2b.blackbox.v | 1,307 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR4;
supply1 VAR6;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/Write_Master/ST_to_MM_Adapter.v | 5,311 | module MODULE1 (
clk,
reset,
enable,
address,
VAR14,
VAR20,
VAR7,
VAR21,
VAR11,
VAR18,
VAR16
);
parameter VAR2 = 32;
parameter VAR19 = 2;
parameter VAR17 = 32;
parameter VAR15 = 0; localparam VAR6 = VAR19 + 1;
input clk;
input reset;
input enable; input [VAR17-1:0] address;
input VAR14; input VAR20;
input VAR7;
output ... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_reset_controller.v | 3,490 | module MODULE1
parameter VAR17 = 6,
parameter VAR4 = "VAR21",
parameter VAR25 = 2
)
(
input VAR18,
input VAR20,
input VAR14,
input VAR6,
input VAR22,
input VAR23,
input VAR1,
input VAR5,
input VAR24,
input VAR8,
input VAR13,
input VAR9,
input VAR11,
input VAR27,
input VAR16,
input VAR10,
input clk,
output VAR3
);
local... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_strong_filter.v | 17,069 | module MODULE1(
VAR55,
VAR48 , VAR189 , VAR73 , VAR177,
VAR181 , VAR50 , VAR227 , VAR206,
VAR93 , VAR106 , VAR30 , VAR49,
VAR220 , VAR135 , VAR235 , VAR14,
VAR67 , VAR153 , VAR88 , VAR159,
VAR134 , VAR223 , VAR216 , VAR68,
VAR201 , VAR89 , VAR202 , VAR81,
VAR118 , VAR236 , VAR105 , VAR164,
VAR84 , VAR42 , VAR109,
VAR22... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai.behavioral.pp.v | 2,174 | module MODULE1 (
VAR12 ,
VAR9 ,
VAR13 ,
VAR7,
VAR17,
VAR14,
VAR4 ,
VAR16
);
output VAR12 ;
input VAR9 ;
input VAR13 ;
input VAR7;
input VAR17;
input VAR14;
input VAR4 ;
input VAR16 ;
wire VAR8 ;
wire VAR2 ;
wire VAR10 ;
wire VAR5;
not VAR18 (VAR8 , VAR7 );
or VAR15 (VAR2 , VAR13, VAR9 );
nand VAR3 (VAR10 , VAR8, VAR2 )... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_mm_interconnect_0.v | 15,823 | module MODULE1 (
input wire VAR1, input wire VAR55, input wire VAR63, input wire [31:0] VAR94, output wire VAR5, input wire [3:0] VAR54, input wire VAR80, output wire [31:0] VAR68, output wire VAR74, input wire VAR78, input wire [31:0] VAR61, output wire [31:0] VAR72, output wire VAR86, output wire VAR59, input wire [3... | gpl-3.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/Block_Mat_exit570_pr.v | 10,921 | module MODULE1 (
VAR43,
VAR38,
VAR36,
VAR2,
VAR7,
VAR33,
VAR39,
VAR26,
VAR34,
VAR14,
VAR37,
VAR12,
VAR4,
VAR9,
VAR22,
VAR8,
VAR10,
VAR6,
VAR23,
VAR1,
VAR32,
VAR25,
VAR3,
VAR28,
VAR41,
VAR31,
VAR27,
VAR46,
VAR18,
VAR42
);
parameter VAR5 = 1'd1;
input VAR43;
input VAR38;
input VAR36;
input VAR2;
output VAR7;
input VAR33;... | mit |
jairov4/accel-oil | solution_spartan3/impl/verilog/nfa_accept_samples_generic_hw_add_6ns_6ns_6_2.v | 3,958 | module MODULE3(clk, reset, VAR8, VAR7, VAR10, VAR24);
input clk;
input reset;
input VAR8;
input [6 - 1 : 0] VAR7;
input [6 - 1 : 0] VAR10;
output [6 - 1 : 0] VAR24;
wire [6 - 1 : 0] VAR12;
wire [6 - 1 : 0] VAR16;
wire [3 - 1 : 0] VAR5;
wire [3 - 1 : 0] VAR33;
wire [6 - 1 : 3] VAR6;
wire [6 - 1 : 3] VAR18;
reg [3 - 1 : ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3/sky130_fd_sc_hdll__and3.behavioral.pp.v | 1,828 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR9 ,
VAR1 ,
VAR11,
VAR3,
VAR5 ,
VAR14
);
output VAR8 ;
input VAR6 ;
input VAR9 ;
input VAR1 ;
input VAR11;
input VAR3;
input VAR5 ;
input VAR14 ;
wire VAR4 ;
wire VAR10;
and VAR13 (VAR4 , VAR1, VAR6, VAR9 );
VAR12 VAR7 (VAR10, VAR4, VAR11, VAR3);
buf VAR2 (VAR8 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o_1.v | 2,248 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR3 ,
VAR4 ,
VAR1,
VAR6,
VAR9 ,
VAR8
);
output VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR1;
input VAR6;
input VAR9 ;
input VAR8 ;
VAR5 VAR10 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE2 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor3/sky130_fd_sc_hd__xnor3_1.v | 2,184 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR5 ,
VAR8 ,
VAR2,
VAR9,
VAR1 ,
VAR10
);
output VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR8 ;
input VAR2;
input VAR9;
input VAR1 ;
input VAR10 ;
VAR4 VAR7 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.symbol.v | 1,505 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR7 ,
input VAR3 ,
input VAR5,
input VAR4 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv.pp.blackbox.v | 1,267 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR1,
VAR2,
VAR4 ,
VAR3
);
output VAR5 ;
input VAR6 ;
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.v | 2,461 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR12 ,
VAR8 ,
VAR6 ,
VAR10,
VAR5,
VAR7 ,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR12 ;
input VAR8 ;
input VAR6 ;
input VAR10;
input VAR5;
input VAR7 ;
input VAR2 ;
VAR9 VAR11 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi.behavioral.pp.v | 2,207 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR8 ,
VAR3 ,
VAR20 ,
VAR6 ,
VAR7,
VAR18,
VAR2 ,
VAR15
);
output VAR9 ;
input VAR10 ;
input VAR8 ;
input VAR3 ;
input VAR20 ;
input VAR6 ;
input VAR7;
input VAR18;
input VAR2 ;
input VAR15 ;
wire VAR16 ;
wire VAR19 ;
wire VAR1 ;
wire VAR5;
and VAR12 (VAR16 , VAR3, VAR20 );
and VAR14 (VAR... | apache-2.0 |
travisg/cpu | rtl/lib/uart.v | 3,024 | module MODULE1(
input clk,
input rst,
input VAR6,
output VAR3,
input addr, input VAR4,
input VAR5,
input [31:0] VAR7,
output reg [31:0] VAR2,
output reg [7:0] VAR1,
output reg VAR8
);
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.v | 2,026 | module MODULE2 (
VAR6,
VAR7 ,
VAR2 ,
VAR4 ,
VAR1
);
input VAR6;
input VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR1 ;
VAR5 VAR3 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 ();
supply1 VAR6;
supply1 VAR7 ;
supply0 VAR2 ;
supply1 VAR4 ;
supply0 VAR1 ;
VAR5 VAR3 ();
endmodul... | apache-2.0 |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/data_controller.v | 2,515 | module MODULE1(
clk,
VAR1,
rst,
VAR4,
sel,
VAR9,
VAR13,
VAR10,
VAR19,
VAR7,
VAR2
);
input clk;
input VAR1;
input rst;
input VAR4;
input [1:0] sel;
input [15:0] VAR9;
output [3:0] VAR13;
output [3:0] VAR10;
output [3:0] VAR19;
output [3:0] VAR7;
output [15:0] VAR2;
wire [15:0] VAR18;
wire [19:0] VAR15;
wire [15:0] VAR14... | mit |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/coregen/rom_8x2k_hi.v | 3,950 | module MODULE1(
addr,
clk,
din,
dout,
en,
VAR28);
input [10 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input VAR28;
VAR26 #(
.VAR2(11),
.VAR1("0"),
.VAR38(2048),
.VAR32(0),
.VAR4(1),
.VAR46(1),
.VAR44(1),
.VAR29(0),
.VAR43(0),
.VAR40(0),
.VAR15(0),
.VAR31(0),
.VAR16(1),
.VAR37(18),
.VAR11("... | bsd-3-clause |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Position/bit_ctrl.v | 11,958 | module MODULE1(
input clk,
input VAR20,
input rst,
input en,
input VAR7,
input VAR33,
input VAR21,
input VAR1,
output reg VAR15,
output reg VAR34,
output reg VAR14,
input VAR13,
output reg VAR36,
output reg VAR10
);
reg VAR22,VAR5; reg VAR39,VAR25; reg[4:0] state; reg[2:0] VAR18; reg VAR24; reg VAR35,VAR9,VAR26;
localp... | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_spram_128x32.v | 7,625 | module MODULE1(
VAR26, VAR5, VAR21,
clk, rst, VAR11, VAR28, VAR24, addr, VAR19, VAR8
);
parameter VAR2 = 7;
parameter VAR3 = 32;
input VAR26;
input [VAR25 - 1:0] VAR21;
output VAR5;
input clk; input rst; input VAR11; input VAR28; input VAR24; input [VAR2-1:0] addr; input [VAR3-1:0] VAR19; output [VAR3-1:0] VAR8;
VAR23 ... | apache-2.0 |
takeshineshiro/fpga_linear_128 | DynamicFocus.v | 6,544 | module MODULE1 (
address,
VAR3,
VAR8);
input [14:0] address;
input VAR3;
output [7:0] VAR8;
wire [7:0] VAR6;
wire [7:0] VAR8 = VAR6[7:0];
VAR14 VAR16 (
.VAR22 (VAR3),
.VAR44 (address),
.VAR13 (VAR6),
.VAR41 (1'b0),
.VAR21 (1'b0),
.VAR26 (1'b1),
.VAR46 (1'b0),
.VAR9 (1'b0),
.VAR48 (1'b1),
.VAR40 (1'b1),
.VAR19 (1'b1),
.... | mit |
bigeagle/riffa | fpga/riffa_hdl/txc_engine_classic.v | 16,045 | parameter VAR111 = 128,
parameter VAR24 = 1,
parameter VAR52 = 0,
parameter VAR22 = 64,
parameter VAR61 = 10,
parameter VAR132 = "VAR6"
)
(
input VAR108,
input VAR124,
input [VAR65-1:0] VAR45,
input VAR21,
output [VAR111-1:0] VAR54,
output VAR131,
output VAR107,
output [VAR62(VAR111/32)-1:0] VAR130,
output VAR98,
outpu... | bsd-3-clause |
rkrajnc/minimig-mist | rtl/minimig/debug.v | 3,264 | module MODULE1 (
input wire clk,
input wire VAR26,
input wire [ 9-1:1] VAR33,
input wire [ 16-1:0] VAR13
);
wire [236-1:0] VAR29;
VAR32 VAR32 (
.VAR33 (VAR33),
.VAR29 (VAR29)
);
reg VAR24 ;
reg [ 4-1:0] VAR20 ;
reg VAR8 ;
reg VAR1 ;
reg VAR30 ;
reg VAR10 ;
reg VAR21 ;
reg VAR7 ;
always @ (posedge clk) begin
if (VAR26) ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2_1.v | 2,086 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR7 ,
VAR2,
VAR3,
VAR6 ,
VAR8
);
output VAR5 ;
input VAR1 ;
input VAR7 ;
input VAR2;
input VAR3;
input VAR6 ;
input VAR8 ;
VAR4 VAR9 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR5,
VAR1,
VAR7
);
output VAR5;
... | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/PC-104_Interface/NPSAT1_ARM_CFTP_Interface.v | 6,844 | module MODULE1(
inout wire [15:0] VAR40,
input wire [10:0] VAR19,
input wire VAR12, input wire VAR27, input wire VAR46, input wire VAR32, output wire VAR24, output wire VAR2,
input wire VAR17,
input wire [31:0] VAR45,
output wire [31:0] VAR23,
input wire VAR43, input wire VAR49, output wire VAR53, input wire VAR50, inp... | lgpl-3.0 |
scarlso/LED_controller | Design01.cydsn/Design01.cydsn/codegentemp/Design01.v | 6,380 | module MODULE1 ;
wire [7:0] VAR9;
wire VAR14;
wire VAR45;
wire VAR28;
wire VAR37;
wire VAR48;
wire VAR61;
wire VAR17;
wire VAR25;
wire VAR63;
wire VAR44;
wire VAR39;
wire VAR54;
wire VAR7;
wire VAR66;
wire VAR62;
VAR55 VAR51 (
.VAR40(VAR62),
.VAR38(1'b0),
.VAR19(VAR7),
.VAR20(VAR54),
.VAR41(VAR39));
VAR60
.VAR5... | apache-2.0 |
hanw/sonic-lite | hw/verilog/port/async_fifo.v | 1,824 | module MODULE1(
VAR10,
VAR1,
VAR12,
VAR2,
VAR13,
VAR4,
VAR7,
VAR11,
VAR9
);
parameter VAR3 = 4;
parameter VAR14 = 1 << VAR3;
parameter VAR17 = 32;
input VAR12;
input VAR13;
input VAR2;
input VAR10;
input VAR1;
input [65:0] VAR4;
output reg [65:0] VAR7;
output reg VAR9;
output reg VAR11;
reg [VAR3-1:0] VAR5;
reg [VAR3-1... | mit |
CospanDesign/vivado-ip-cores | ip/axi_on_screen_display/axi_on_screen_display.v | 18,993 | module MODULE1 #(
parameter VAR54 = 12,
parameter VAR103 = 7,
parameter VAR17 = 32,
parameter VAR132 = (VAR17 / 8),
parameter VAR145 = 24,
parameter VAR89 = 1,
parameter VAR57 = 1,
parameter VAR128 = 480,
parameter VAR169 = 272,
parameter VAR13 = 9,
parameter VAR163 = 24,
parameter VAR77 = 24'hFFFFFF,
parameter VAR81 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31o/sky130_fd_sc_ls__a31o.blackbox.v | 1,354 | module MODULE1 (
VAR5 ,
VAR6,
VAR7,
VAR9,
VAR8
);
output VAR5 ;
input VAR6;
input VAR7;
input VAR9;
input VAR8;
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
MeshSr/onetswitch20 | ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/ip/rxfifo_2kx36_to_72.v | 13,770 | module MODULE1(
rst,
VAR274,
VAR83,
din,
VAR213,
VAR24,
dout,
VAR149,
VAR336,
VAR5
);
input rst;
input VAR274;
input VAR83;
input [35 : 0] din;
input VAR213;
input VAR24;
output [71 : 0] dout;
output VAR149;
output VAR336;
output VAR5;
VAR220 #(
.VAR375(0),
.VAR369(0),
.VAR389(0),
.VAR1(0),
.VAR111(0),
.VAR108(0),
.VAR... | lgpl-2.1 |
bbrown1867/ObjectTracking | hw/common/fixed_point/qmult.v | 2,359 | module MODULE1 #(
parameter VAR4 = 15,
parameter VAR7 = 32
)
(
input [VAR7-1:0] VAR2,
input [VAR7-1:0] VAR5,
output [VAR7-1:0] VAR8,
output reg VAR1
);
reg [2*VAR7-1:0] VAR6; reg [VAR7-1:0] VAR3;
assign VAR8 = VAR3;
always @(VAR2, VAR5) begin VAR6 <= VAR2[VAR7-2:0] * VAR5[VAR7-2:0]; end
always @(VAR6) begin VAR3[VAR7-1... | mit |
ptracton/wb_soc_template | rtl/ZIP/rtl/pipemem.v | 7,007 | module MODULE1(VAR31, VAR27, VAR38, VAR11,
VAR10, VAR23, VAR4, VAR12,
VAR42, VAR44, VAR8, VAR35, VAR26, VAR1,
VAR40, VAR14,
VAR33, VAR2,
VAR20, VAR19, VAR15, VAR39,
VAR16, VAR9, VAR32, VAR28);
parameter VAR21=30;
parameter [0:0] VAR24=1'b0,
VAR5=1'b1;
localparam VAR6=VAR21;
input wire VAR31, VAR27;
input wire VAR38, VA... | mit |
liuyenting/CA-Project | src/MEMWB_Reg.v | 1,166 | module MODULE1 (
input clk,
input rst,
input VAR18,
input VAR19,
input [2-1:0] VAR6,
output [2-1:0] VAR11,
input [32-1:0] VAR12,
output [32-1:0] VAR17,
input [32-1:0] VAR4,
output [32-1:0] VAR13,
input [5-1:0] VAR8,
output [5-1:0] VAR10
);
VAR15 #(.VAR5(2)) VAR2 (
.clk (clk),
.rst (~VAR18),
.VAR7 (~VAR19),
.VAR14 (VAR6... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/edistrib/hdl/edistrib.v | 5,848 | module MODULE1 (
VAR41, VAR39, VAR29, VAR8,
VAR1, VAR9, VAR32, VAR2,
VAR17, VAR34, VAR36, VAR42,
VAR22, VAR35, VAR21, VAR6,
VAR37, VAR11, VAR40, VAR3,
VAR28, VAR25, VAR18, VAR16,
VAR30, VAR43, VAR5, VAR31,
VAR15, VAR38, VAR10
);
parameter [11:0] VAR20 = 12'h810;
parameter VAR33 = 7;
parameter [31:0] VAR4 = 32'h3E000000... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b.behavioral.v | 1,513 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR8 ,
VAR7
);
output VAR11 ;
input VAR3 ;
input VAR8 ;
input VAR7;
supply1 VAR10;
supply0 VAR13;
supply1 VAR2 ;
supply0 VAR1 ;
wire VAR6 ;
wire VAR12;
nor VAR9 (VAR6 , VAR3, VAR8 );
and VAR4 (VAR12, VAR7, VAR6 );
buf VAR5 (VAR11 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311ai/sky130_fd_sc_hs__o311ai.behavioral.pp.v | 1,966 | module MODULE1 (
VAR7,
VAR16,
VAR9 ,
VAR11 ,
VAR1 ,
VAR10 ,
VAR14 ,
VAR15
);
input VAR7;
input VAR16;
output VAR9 ;
input VAR11 ;
input VAR1 ;
input VAR10 ;
input VAR14 ;
input VAR15 ;
wire VAR14 VAR6 ;
wire VAR8 ;
wire VAR13;
or VAR12 (VAR6 , VAR1, VAR11, VAR10 );
nand VAR3 (VAR8 , VAR15, VAR6, VAR14 );
VAR4 VAR5 (VAR... | apache-2.0 |
jairov4/accel-oil | solution_spartan3/syn/verilog/nfa_accept_samples_generic_hw_add_17ns_17s_17_4.v | 5,917 | module MODULE3(clk, reset, VAR21, VAR18, VAR11, VAR27);
input clk;
input reset;
input VAR21;
input [17 - 1 : 0] VAR18;
input [17 - 1 : 0] VAR11;
output [17 - 1 : 0] VAR27;
wire [17 - 1 : 0] VAR15;
wire [17 - 1 : 0] VAR40;
wire [5 - 1 : 0] VAR23;
wire [5 - 1 : 0] VAR28;
wire [10 - 1 : 5] VAR46;
wire [10 - 1 : 5] VAR30;
... | lgpl-3.0 |
fzyz999/5-stage-MIPS | mips.v | 5,758 | module MODULE1(clk, rst, VAR50, VAR70, VAR66, VAR10, VAR6);
input clk ;
input rst ;
output [31:0] VAR10;
output [31:2] VAR50;
output [3:0] VAR70;
input [31:0] VAR66;
input [7:2] VAR6;
wire VAR87,VAR67;
wire VAR23;
wire VAR48,VAR98;
wire VAR65,VAR80;
wire VAR59,VAR22,VAR82,VAR12;
wire VAR57,VAR54,VAR83;
wire VAR35,VAR92... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/syn/v/bsg_mem_1rw_sync.v | 1,993 | if (VAR15 == VAR24 && VAR1 == VAR2) \
begin: VAR14 \
VAR17 \
VAR19 \
(.VAR18 (VAR18) \
,.VAR5(VAR5) \
,.VAR10 (VAR10) \
,.VAR12 (VAR12) \
,.VAR22 (VAR22) \
,.VAR8 (VAR8) \
,.VAR9 (VAR9) \
); \
end: VAR14
module MODULE1 #( parameter VAR27(VAR1 )
, parameter VAR27(VAR15 )
, parameter VAR4 = VAR26(VAR15)
, parameter VAR16... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a_4.v | 2,339 | module MODULE2 (
VAR3 ,
VAR2 ,
VAR8 ,
VAR1 ,
VAR4 ,
VAR7,
VAR10,
VAR6 ,
VAR11
);
output VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR1 ;
input VAR4 ;
input VAR7;
input VAR10;
input VAR6 ;
input VAR11 ;
VAR5 VAR9 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR6(VAR6),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ba/sky130_fd_sc_lp__o21ba_0.v | 2,316 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR10 ,
VAR2,
VAR3,
VAR6,
VAR9 ,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR10 ;
input VAR2;
input VAR3;
input VAR6;
input VAR9 ;
input VAR4 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE1 ... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_decoder_64_syn.v | 58,573 | module MODULE2
(
VAR235,
VAR252) ;
input [6:0] VAR235;
output [127:0] VAR252;
tri0 [6:0] VAR235;
wire [5:0] VAR41;
wire VAR166;
wire VAR253;
wire [127:0] VAR73;
wire [63:0] VAR145;
wire [63:0] VAR193;
wire [3:0] VAR127;
wire [3:0] VAR45;
wire [3:0] VAR125;
wire [3:0] VAR120;
wire [3:0] VAR182;
wire [3:0] VAR74;
wire [3... | gpl-2.0 |
ptracton/pmodacl2 | soc/xilinx/LUT6.v | 4,056 | module MODULE1 (VAR3, VAR24, VAR1, VAR5, VAR19, VAR7, VAR17);
parameter VAR20 = 64'h0000000000000000;
parameter VAR8 = "VAR15";
output VAR3;
input VAR24, VAR1, VAR5, VAR19, VAR7, VAR17;
wire VAR16, VAR25, VAR4, VAR14, VAR21, VAR6;
wire VAR2;
buf b0 (VAR16, VAR24);
buf b1 (VAR25, VAR1);
buf VAR9 (VAR4, VAR5);
buf VAR23 ... | mit |
Masahiro000Shimasaki/NeuralNetwork | Hardware/Perceptron_xor/fp_add_sub.v | 140,017 | module MODULE1
(
VAR14,
VAR13,
VAR12,
VAR7,
VAR9,
VAR5) ;
input VAR14;
input VAR13;
input VAR12;
input [25:0] VAR7;
input [4:0] VAR9;
output [25:0] VAR5;
tri0 VAR14;
tri1 VAR13;
tri0 VAR12;
reg [0:0] VAR11;
reg [25:0] VAR8;
wire [5:0] VAR1;
wire VAR4;
wire [15:0] VAR2;
wire [155:0] VAR3;
wire [4:0] VAR6;
wire [129:0] V... | mit |
LoniasGR/Just_NTUA_ECE_Stuff | MicroSys/Assignment_2/Exercise_7/exercise_6_36_withGates.v | 1,151 | module MODULE2 (output VAR14, input VAR1, VAR10);
reg VAR14;
VAR13 VAR14 = 1'b0;
always @ (posedge VAR10) VAR14 <= VAR1;
endmodule
module MODULE1 (output VAR14, input VAR17, VAR10);
wire VAR6;
assign VAR6 = VAR14 ^ VAR17;
MODULE2 VAR8 (VAR14, VAR6, VAR10);
endmodule
module 1bitupdowncounter (output VAR18, input VAR19, ... | mit |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/controller_command_fifo.v | 13,456 | module MODULE1(
clk,
rst,
din,
VAR231,
VAR216,
dout,
VAR315,
VAR190,
VAR77
);
input clk;
input rst;
input [127 : 0] din;
input VAR231;
input VAR216;
output [127 : 0] dout;
output VAR315;
output VAR190;
output [4 : 0] VAR77;
VAR64 #(
.VAR185(0),
.VAR321(0),
.VAR103(0),
.VAR61(0),
.VAR262(0),
.VAR253(0),
.VAR6(0),
.VAR12... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_dir_in.v | 2,757 | module MODULE1(
VAR20, VAR11, VAR9,
VAR18, VAR7, VAR8, VAR14,
VAR27, VAR3, VAR6, VAR16
);
output [32:0] VAR20; output [31:0] VAR11;
output VAR9;
input [32:0] VAR18;
input [31:0] VAR7; input [31:0] VAR8; input VAR14; input VAR27;
input VAR3, VAR6;
input VAR16;
wire [31:0] VAR4;
wire VAR26;
VAR19 VAR5 (.clk(VAR26), .VAR2... | gpl-2.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_pm.v | 2,888 | module MODULE1(
input [6:0] VAR15,
input [5:0] VAR12,
input [8:0] VAR1,
input VAR3,
output reg [12:0] VAR4
);
reg [9:0] VAR7;
reg [13:0] VAR6, VAR8;
reg [1:0] VAR16;
reg [6:0] VAR14;
reg VAR2;
always @ begin : VAR9
VAR7 = { 1'd0, VAR1 } + { 4'd0, VAR12 };
case( VAR14[3:0] )
default:
if( VAR7>=10'd448 ) VAR16 = 2'd2;
en... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/crc16.v | 2,508 | module MODULE1(
input [7:0] VAR1,
input VAR2,
output [15:0] VAR4,
input rst,
input clk);
reg [15:0] VAR3,VAR5;
assign VAR4 = VAR3;
always @(*) begin
VAR5[0] = VAR3[8] ^ VAR3[9] ^ VAR3[10] ^ VAR3[11] ^ VAR3[12] ^ VAR3[13] ^ VAR3[14] ^ VAR3[15] ^ VAR1[0] ^ VAR1[1] ^ VAR1[2] ^ VAR1[3] ^ VAR1[4] ^ VAR1[5] ^ VAR1[6] ^ VAR1[... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/niosII_system/synthesis/submodules/niosII_system_jtag_uart_0.v | 23,624 | module MODULE1 (
clk,
VAR34,
VAR32,
valid
)
;
input clk;
input [ 7: 0] VAR34;
input VAR32;
input valid;
reg [31:0] VAR49; VAR67 VAR49 =
always @(posedge clk) begin
if (valid && VAR32) begin
VAR82 (VAR49);
end
end
endmodule
module MODULE7 (
clk,
VAR11,
VAR64,
VAR84,
VAR33,
VAR6,
VAR10
)
;
output VAR84;
output [ 7: 0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4_lp2.v | 2,269 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR5 ,
VAR11 ,
VAR2 ,
VAR3,
VAR6,
VAR4 ,
VAR10
);
output VAR1 ;
input VAR9 ;
input VAR5 ;
input VAR11 ;
input VAR2 ;
input VAR3;
input VAR6;
input VAR4 ;
input VAR10 ;
VAR7 VAR8 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VA... | apache-2.0 |
jotego/jt51 | hdl/jt51_phrom.v | 3,321 | module MODULE1
(
input [4:0] addr,
input clk,
input VAR1,
output reg [45:0] VAR3
);
reg [45:0] VAR2[31:0];
begin | gpl-3.0 |
AbhishekShah212/School_Projects | ELEN232/pset3/Problem2.v | 1,430 | module MODULE1(
input VAR1,
input VAR3,
input VAR4,
input VAR5,
output reg VAR2
);
always @ (VAR1 or VAR3 or VAR4 or VAR5)
begin
if ((~VAR1 & VAR3 & ~VAR4 & ~VAR5) == 1)
VAR2 = 1;
end
else if ((~VAR1 & ~VAR3 & VAR4 & VAR5) == 1)
VAR2 = 1;
else if ((VAR1 & VAR5 & ~VAR3 & ~VAR4) == 1)
VAR2 = 1;
else if ((VAR1 & VAR3 & VA... | mit |
rkrajnc/minimig-mist | rtl/minimig/agnus_blitter_minterm.v | 1,498 | module MODULE1
(
input [7:0] VAR1, input [15:0] VAR5, input [15:0] VAR6, input [15:0] VAR13, output [15:0] out );
reg [15:0] VAR8; reg [15:0] VAR3; reg [15:0] VAR9; reg [15:0] VAR4; reg [15:0] VAR7; reg [15:0] VAR2; reg [15:0] VAR11; reg [15:0] VAR12;
integer VAR10;
always @(VAR5 or VAR6 or VAR13 or VAR1)
for (VAR10=15... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp.pp.blackbox.v | 1,311 | module MODULE1 (
VAR2,
VAR6 ,
VAR8,
VAR5 ,
VAR3,
VAR4,
VAR1 ,
VAR7
);
output VAR2;
input VAR6 ;
input VAR8;
input VAR5 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR7 ;
endmodule | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/ip/Audio_DAC_FIFO/hdl/AUDIO_DAC_FIFO.v | 3,386 | module MODULE1 ( VAR26,VAR31,VAR9,
VAR8,
VAR21,
VAR19,
VAR24,
VAR32,
VAR4,
VAR18 );
parameter VAR12 = 18432000; parameter VAR2 = 48000; parameter VAR16 = 16; parameter VAR34 = 2;
input [VAR16-1:0] VAR26;
input VAR31;
input VAR9;
output [VAR16-1:0] VAR8;
wire [VAR16-1:0] VAR11;
reg VAR1;
output VAR19;
output VAR24;
outp... | gpl-3.0 |
martinmiranda14/Digitales | Lab5/ALU_and_display.v | 1,360 | module MODULE1(
input VAR14,
input reset,
input [15:0] VAR4,
input [15:0] VAR17,
input [2:0] VAR13,
output [7:0] VAR19,
output [7:0] VAR22 ,
output [15:0] VAR12
);
wire VAR7;
wire [31:0] VAR15;
VAR6 VAR11(
.clk(VAR14),
.rst (reset),
.VAR18 (VAR7)
);
VAR8 alu(
.VAR3({VAR4}),
.VAR9({VAR17}),
.VAR13 (VAR13),
.VAR12 (VAR12... | apache-2.0 |
efabless/openlane | designs/151/src/no_cache_mem.v | 1,904 | module MODULE1 #(
parameter VAR8 = VAR6,
parameter VAR11 = VAR10-VAR20(VAR6/8)
) (
input clk,
input reset,
input VAR9,
output VAR16,
input [VAR11-1:0] VAR17,
input [VAR8-1:0] VAR21,
input [3:0] VAR2,
output reg VAR15,
output reg [VAR8-1:0] VAR14
);
localparam VAR4 = 2*512*512;
localparam VAR19 = VAR1/VAR8;
reg [VAR1-1:... | apache-2.0 |
mathiashelsen/WolfCoreOne | logic/quartus_prj/DE0_NANO_SOC_Default.v | 5,052 | module MODULE1(
output VAR32,
output VAR83,
output VAR8,
input VAR73,
input VAR60,
input VAR23,
input VAR63,
inout VAR69,
output [14:0] VAR75,
output [2:0] VAR104,
output VAR16,
output VAR103,
output VAR98,
output VAR45,
output VAR110,
output [3:0] VAR90,
inout [31:0] VAR43,
inout [3:0] VAR87,
inout [3:0] VAR59,
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3.behavioral.v | 1,581 | module MODULE1 (
VAR6,
VAR4,
VAR15,
VAR10
);
output VAR6;
input VAR4;
input VAR15;
input VAR10;
supply1 VAR11;
supply0 VAR17;
supply1 VAR8 ;
supply0 VAR14 ;
wire VAR5 ;
wire VAR9 ;
wire VAR12 ;
wire VAR3;
or VAR7 (VAR5 , VAR15, VAR4 );
and VAR2 (VAR9 , VAR5, VAR10 );
and VAR1 (VAR12 , VAR4, VAR15 );
or VAR13 (VAR3, VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf.behavioral.v | 1,319 | module MODULE1 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR5;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR9 ;
wire VAR8;
buf VAR7 (VAR8, VAR6 );
buf VAR4 (VAR2 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_hl_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.symbol.v | 1,578 | module MODULE1 (
input VAR4,
output VAR3
);
wire VAR2;
supply1 VAR5 ;
supply0 VAR1 ;
supply1 VAR6 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/ninja3.v | 6,363 | module MODULE1 (
address,
VAR51,
VAR20);
input [11:0] address;
input VAR51;
output [11:0] VAR20;
tri1 VAR51;
wire [11:0] VAR8;
wire [11:0] VAR20 = VAR8[11:0];
VAR24 VAR14 (
.VAR31 (address),
.VAR22 (VAR51),
.VAR13 (VAR8),
.VAR21 (1'b0),
.VAR12 (1'b0),
.VAR3 (1'b1),
.VAR37 (1'b0),
.VAR26 (1'b0),
.VAR19 (1'b1),
.VAR47 (1... | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_src0_rows_V.v | 2,983 | module MODULE1 (
clk,
VAR22,
VAR2,
VAR6,
VAR17);
parameter VAR27 = 32'd12;
parameter VAR8 = 32'd2;
parameter VAR10 = 32'd3;
input clk;
input [VAR27-1:0] VAR22;
input VAR2;
input [VAR8-1:0] VAR6;
output [VAR27-1:0] VAR17;
reg[VAR27-1:0] VAR13 [0:VAR10-1];
integer VAR7;
always @ (posedge clk)
begin
if (VAR2)
begin
for (V... | gpl-3.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/vcr_vc_alloc_sep_if.v | 19,277 | module MODULE1
(clk, reset, VAR34, VAR27, VAR17, VAR82,
VAR97, VAR47, VAR31, VAR79, VAR15,
VAR49, VAR77);
parameter VAR6 = 2;
parameter VAR52 = 2;
localparam VAR40 = VAR6 * VAR52;
parameter VAR9 = 1;
localparam VAR56 = VAR40 * VAR9;
parameter VAR29 = 5;
parameter VAR58 = VAR94;
parameter VAR24 = VAR45;
input clk;
input... | gpl-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/acl_kernel_finish_detector.v | 5,511 | module MODULE1 #(
parameter integer VAR4 = 1, parameter integer VAR11 = 1, parameter integer VAR2 = 32 )
(
input logic VAR10,
input logic VAR24,
input logic VAR9,
input logic [VAR11-1:0] VAR22,
input logic [VAR4-1:0] VAR6,
input logic [VAR4-1:0] VAR13,
input logic VAR8,
input logic [VAR4-1:0] VAR3,
input logic [VAR4-1:... | mit |
kwantam/multiexp-a5gx | verilog/mac_element.v | 5,140 | module MODULE1 #( parameter VAR47 = 27
, parameter VAR56 = 27
, parameter VAR74 = 64
)( input [VAR47-1:0] VAR40
, input [VAR56-1:0] VAR11
, output [VAR74-1:0] VAR89
, input clk
, input VAR41
, input VAR19
, input VAR31
, input VAR32
, input VAR25
);
VAR30 #( .VAR66 (VAR56)
, .VAR53 (VAR47)
, .VAR12 (0)
, .VAR75 (0)
, .... | gpl-3.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/soc/uart.v | 9,156 | module MODULE1
(
VAR16,
VAR3,
VAR11,
VAR12,
VAR15,
VAR21,
VAR7,
VAR8,
VAR10,
VAR4
);
parameter [31:0] VAR9 = 278;
input VAR16 ;
input VAR3 ;
input [7:0] VAR15 ;
output [7:0] VAR7 ;
input VAR21 ;
input VAR8 ;
output VAR11 ;
output VAR12 ;
input VAR10 ;
output VAR4 ;
parameter VAR20 = VAR9;
parameter VAR19 = (VAR20 / 2);... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4_4.v | 2,231 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR10 ,
VAR2 ,
VAR3 ,
VAR11,
VAR7,
VAR8 ,
VAR6
);
output VAR1 ;
input VAR9 ;
input VAR10 ;
input VAR2 ;
input VAR3 ;
input VAR11;
input VAR7;
input VAR8 ;
input VAR6 ;
VAR4 VAR5 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VAR8),
.... | apache-2.0 |
cpulabs/gci-std-display | rtl/display_controller/gci_std_display_top.v | 8,281 | module MODULE1 #(
parameter VAR134 = 307200,
parameter VAR89 = 0,
parameter VAR20 = 640,
parameter VAR88 = 480,
parameter VAR24 = 19,
parameter VAR97 = 23
)(
input wire VAR180,
input wire VAR160,
input wire VAR52,
input wire VAR153,
input wire VAR14,
output wire VAR122,
input wire VAR51,
input wire [31:0] VAR156,
input... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3b/sky130_fd_sc_hd__nor3b.behavioral.pp.v | 1,995 | module MODULE1 (
VAR11 ,
VAR9 ,
VAR12 ,
VAR5 ,
VAR6,
VAR3,
VAR15 ,
VAR14
);
output VAR11 ;
input VAR9 ;
input VAR12 ;
input VAR5 ;
input VAR6;
input VAR3;
input VAR15 ;
input VAR14 ;
wire VAR16 ;
wire VAR4 ;
wire VAR13;
nor VAR2 (VAR16 , VAR9, VAR12 );
and VAR10 (VAR4 , VAR5, VAR16 );
VAR7 VAR1 (VAR13, VAR4, VAR6, VAR3... | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/ip/fifo_bt_txd/fifo_bt_txd_stub.v | 1,436 | module MODULE1(rst, VAR4, VAR3, din, VAR2, VAR1, dout, VAR5,
VAR6)
;
input rst;
input VAR4;
input VAR3;
input [7:0]din;
input VAR2;
input VAR1;
output [7:0]dout;
output VAR5;
output VAR6;
endmodule | gpl-3.0 |
d16-processor/d16 | verilog/src/sdram_controller3.v | 11,196 | module MODULE1
(
input VAR44,
input VAR50,
input VAR42,
input rst,
input [23:0] address,
input VAR33,
input VAR25,
input [31:0] VAR81,
output reg [31:0] VAR85,
output reg VAR58= 0,
output reg VAR71= 0,
output reg [12:0] VAR12,
output reg [1:0] VAR76,
output reg VAR78,
output VAR37,
output VAR43,
output reg VAR101,
inou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41a/sky130_fd_sc_ls__o41a.behavioral.v | 1,549 | module MODULE1 (
VAR3 ,
VAR1,
VAR10,
VAR8,
VAR12,
VAR14
);
output VAR3 ;
input VAR1;
input VAR10;
input VAR8;
input VAR12;
input VAR14;
supply1 VAR4;
supply0 VAR15;
supply1 VAR7 ;
supply0 VAR9 ;
wire VAR5 ;
wire VAR6;
or VAR13 (VAR5 , VAR12, VAR8, VAR10, VAR1 );
and VAR2 (VAR6, VAR5, VAR14 );
buf VAR11 (VAR3 , VAR6 );
... | apache-2.0 |
chebykinn/university | circuitry/lab4/src/hdl/if_stage.v | 2,026 | module MODULE1( input clk, rst,
input VAR9,
input VAR6,
input [1:0] VAR18,
input VAR4,
output VAR12,
output [31:0] VAR13,
input [31:0] VAR10,
input [31:0] VAR15, VAR14, VAR1,
output reg [31:0] VAR2,
output reg [31:0] VAR5 );
reg [31:0] VAR7, VAR3; wire [31:0] VAR8;
localparam VAR16 = 6'b100011,
VAR17 = 6'b101011;
wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0p/sky130_fd_sc_lp__inputiso0p.behavioral.v | 1,453 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR3;
supply1 VAR7;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR8 ;
wire VAR6;
not VAR10 (VAR6, VAR3 );
and VAR2 (VAR1 , VAR5, VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3b/sky130_fd_sc_ls__or3b.functional.pp.v | 1,951 | module MODULE1 (
VAR6 ,
VAR16 ,
VAR7 ,
VAR4 ,
VAR2,
VAR14,
VAR15 ,
VAR9
);
output VAR6 ;
input VAR16 ;
input VAR7 ;
input VAR4 ;
input VAR2;
input VAR14;
input VAR15 ;
input VAR9 ;
wire VAR11 ;
wire VAR8 ;
wire VAR13;
not VAR12 (VAR11 , VAR4 );
or VAR5 (VAR8 , VAR7, VAR16, VAR11 );
VAR1 VAR3 (VAR13, VAR8, VAR2, VAR14);... | apache-2.0 |
CospanDesign/vivado-ip-cores | ip/axi_on_screen_display/adapter_ppfifo_2_axi_stream.v | 4,627 | module MODULE1 #(
parameter VAR15 = 32,
parameter VAR4 = VAR15 / 8,
parameter VAR14 = 0
)(
input rst,
input VAR12,
output reg VAR5,
input [23:0] VAR17,
input [(VAR15 + 1) - 1:0] VAR1,
output VAR19,
input VAR9,
output [3:0] VAR16,
input VAR13,
output [VAR15 - 1:0] VAR6,
output VAR8,
output reg VAR11,
output [31:0] VAR18... | mit |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/clock_1.v | 28,024 | module MODULE7 (
clk,
VAR28,
VAR34,
VAR68
)
;
output VAR68;
input clk;
input VAR28;
input VAR34;
reg VAR66 ;
reg VAR68 ;
always @(posedge clk or negedge VAR34)
begin
if (VAR34 == 0)
VAR66 <= 0;
end
else if (1)
VAR66 <= VAR28;
end
always @(posedge clk or negedge VAR34)
begin
if (VAR34 == 0)
VAR68 <= 0;
end
else if (1)
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2.functional.pp.v | 1,237 | module MODULE1 (
VAR2,
VAR4,
VAR1 ,
VAR3
);
input VAR2;
input VAR4;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
alexforencich/verilog-axis | rtl/axis_pipeline_fifo.v | 10,243 | module MODULE1 #
(
parameter VAR42 = 8,
parameter VAR20 = (VAR42>8),
parameter VAR24 = ((VAR42+7)/8),
parameter VAR23 = 1,
parameter VAR40 = 0,
parameter VAR9 = 8,
parameter VAR45 = 0,
parameter VAR39 = 8,
parameter VAR12 = 1,
parameter VAR32 = 1,
parameter VAR22 = 2
)
(
input wire clk,
input wire rst,
input wire [VAR4... | mit |
vipinkmenon/scas | hw/fpga/source/memory_if/v7_ddr.v | 24,915 | module MODULE1 #
(
parameter VAR54 = 3,
parameter VAR153 = 1,
parameter VAR59 = 10,
parameter VAR86 = 1,
parameter VAR144 = 1,
parameter VAR108 = 1,
parameter VAR90 = 4,
parameter VAR15 = 6,
parameter VAR163 = 8,
parameter VAR130 = 8,
parameter VAR92 = 64,
parameter VAR141 = 8,
parameter VAR84 = 3,
parameter VAR73 = 8,... | mit |
teknohog/Xilinx-Serial-Miner | sources/hdl/raw7seg.v | 1,670 | module MODULE1(clk, VAR13, VAR5, word);
parameter VAR6 = 4;
parameter VAR8 = 1;
parameter VAR14 = 1;
input clk;
output [(VAR6 - 1):0] VAR5;
output [7:0] VAR13;
input [(VAR6 * 8 - 1):0] word;
reg [15:0] VAR4;
always @(posedge clk) VAR4<=VAR4+16'h1;
wire VAR9 = &VAR4;
reg [3:0] VAR1;
reg [7:0] VAR12;
reg [(VAR6 * 8 - 1):... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/bw_clk_cl_dram_ddr.v | 2,767 | module MODULE1 (
VAR11, VAR8, VAR2, VAR4,
VAR10, VAR7, VAR1, VAR5, VAR12, VAR13, VAR6,
VAR3
);
output VAR4; output VAR2; output VAR8; output VAR11;
input VAR3; input VAR6; input VAR13; input VAR12; input VAR5; input VAR1; input VAR7; input VAR10;
VAR9 VAR9
(
.VAR2 (VAR2),
.VAR4 (VAR4),
.VAR8 (VAR8),
.VAR11 (VAR11),
.VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha_0.v | 2,184 | module MODULE1 (
VAR6,
VAR1 ,
VAR5 ,
VAR2 ,
VAR7,
VAR3,
VAR10 ,
VAR4
);
output VAR6;
output VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR7;
input VAR3;
input VAR10 ;
input VAR4 ;
VAR9 VAR8 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODULE1... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_gtx_cpllpd_ovrd.v | 4,125 | module MODULE1 (
input VAR1,
output VAR4,
output VAR5
);
reg [95:0] VAR3 = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
reg [127:0] VAR2 = 128'h000000000000000000000000000000FF;
always @(posedge VAR1)
begin
VAR3 <= {VAR3[94:0], 1'b0};
VAR2 <= {VAR2[126:0], 1'b0};
end
assign VAR4 = VAR3[95];
assign VAR5 = VAR2[127];
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_altdqdqs.v | 5,751 | module MODULE1 (
VAR45,
VAR44,
VAR42,
VAR60,
VAR70,
VAR9,
VAR71,
VAR11,
VAR43,
VAR73,
VAR1,
VAR12,
VAR24,
VAR25,
VAR8,
VAR46,
VAR19,
VAR7,
VAR5,
VAR50,
VAR15,
VAR14,
VAR20,
VAR77,
VAR64,
VAR22,
VAR68,
VAR21,
VAR30
);
input [6-1:0] VAR30;
input VAR45;
input VAR44;
input VAR42;
input VAR60;
input VAR70;
input VAR9;
input... | lgpl-3.0 |
xuefei1/ElectronicEngineControl | niosII_system/synthesis/submodules/niosII_system_sysid_qsys_0.v | 1,415 | module MODULE1 (
address,
VAR2,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR2;
input VAR3;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1491173393 : 0;
endmodule | apache-2.0 |
hoangt/NOCulator | hring/hw/bless_age/priority_comp.v | 5,593 | module MODULE1(
input VAR23 VAR9,
input VAR23 VAR31,
input VAR23 VAR29,
input VAR23 VAR54,
output [1:0] VAR34,
output [1:0] VAR18,
output [1:0] VAR1,
output [1:0] VAR57);
wire VAR69 ha00, ha01, ha10, ha11, ha20;
wire VAR64 VAR52, VAR17, VAR15, VAR51, VAR43;
wire VAR69 VAR58, VAR50, VAR28, VAR44, VAR61;
wire VAR64 VAR32... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxtp/sky130_fd_sc_ls__sdfxtp.behavioral.v | 2,340 | module MODULE1 (
VAR17 ,
VAR13,
VAR16 ,
VAR1,
VAR21
);
output VAR17 ;
input VAR13;
input VAR16 ;
input VAR1;
input VAR21;
supply1 VAR10;
supply0 VAR24;
supply1 VAR12 ;
supply0 VAR2 ;
wire VAR6 ;
wire VAR25 ;
reg VAR9 ;
wire VAR14 ;
wire VAR22;
wire VAR5;
wire VAR18;
wire VAR15 ;
wire VAR23 ;
wire VAR11 ;
wire VAR19 ;
V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtn/sky130_fd_sc_hs__dfrtn.behavioral.pp.v | 2,332 | module MODULE1 (
VAR5 ,
VAR12 ,
VAR7 ,
VAR21 ,
VAR18 ,
VAR8
);
input VAR5 ;
input VAR12 ;
output VAR7 ;
input VAR21 ;
input VAR18 ;
input VAR8;
wire VAR14 ;
wire VAR11 ;
wire VAR3 ;
reg VAR6 ;
wire VAR15 ;
wire VAR13;
wire VAR1 ;
wire VAR19 ;
wire VAR4 ;
wire VAR17 ;
not VAR20 (VAR11 , VAR13 );
not VAR10 (VAR3, VAR1 );... | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/amer_put.v | 3,625 | module MODULE1(
VAR48,
VAR38,
VAR3,
VAR32,
VAR57,
VAR62,
VAR35,
VAR49,
VAR11,
VAR20,
VAR58
);
input VAR48;
input VAR38;
input VAR3;
input VAR32;
input VAR57;
input [63:0] VAR62;
input [63:0] VAR35;
input [63:0] VAR49;
input [63:0] VAR11;
input [63:0] VAR20;
output [63:0] VAR58;
wire [63:0] VAR8;
wire [63:0] VAR66;
wire... | apache-2.0 |
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