repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
q3k/q3kmips | rtl/verilog/qm_dcache.v | 9,242 | module MODULE1(
input wire reset,
input wire clk,
output reg VAR10,
input wire [31:0] address,
output reg [31:0] VAR29,
input wire [31:0] VAR21,
input wire VAR19,
input wire enable,
output wire VAR25, output reg VAR36,
output reg [2:0] VAR28,
output reg [5:0] VAR26,
output reg [29:0] VAR17,
input wire VAR11,
input wire... | bsd-2-clause |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/ModulosBasicos/PruebasFPGA/contadorprueba/contadorprueba.v | 1,621 | module MODULE1 (
input [7:0] VAR10,
input VAR29,
input VAR21,
input clk,
input reset,
output [3:0] VAR12,
output [6:0] VAR1,
output pulse
);
wire [7:0] VAR27;
wire [3:0] VAR7;
wire [3:0] VAR3;
wire [3:0] VAR24;
wire [1:0] VAR20;
wire [3:0] VAR9;
VAR8 VAR16 (
.VAR10 ( VAR10 ),
.VAR29 ( VAR29 ),
.VAR28 ( VAR28 ),
.reset ... | gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/amba_bfm/bfm_ahbl.v | 6,779 | module
MODULE1
(
VAR35
,
VAR46
,
VAR127
,
VAR26
,
VAR24
,
VAR32
,
VAR132
,
VAR122
,
VAR109
,
VAR20
,
VAR44
,
VAR16
,
VAR2
,
VAR137
,
VAR19
,
VAR99
,
VAR34
,
VAR28
,
VAR61
,
VAR104
,
VAR30
,
VAR144
,
VAR147
,
VAR65
,
VAR3
,
VAR48
)
;
parameter
VAR73
=
;
parameter
VAR70
=
16384
;
parameter
VAR117
=
1024
;
parameter
VAR9... | gpl-3.0 |
GREO/GNU-Radio | gr-radar-mono/src/fpga/lib/radar_rx.v | 2,909 | module MODULE1(VAR11,VAR19,VAR15,VAR6,VAR4,VAR16,
VAR8,VAR24,VAR23,VAR26);
input VAR11;
input VAR19;
input VAR15;
input VAR6;
input [15:0] VAR16;
input [15:0] VAR8;
input [15:0] VAR4;
output [15:0] VAR24;
output [15:0] VAR23;
output reg VAR26;
reg [15:0] VAR21;
always @(posedge VAR11)
if (VAR19 | ~VAR15)
VAR21 <= 16'b0... | gpl-3.0 |
jhennessy/parallella-hw-old | fpga/projects/vivado_parallella_7010_headless/parallella_7010_headless.srcs/sources_1/imports/parallella_7010_headless/system_stub.v | 21,013 | module MODULE1
(
VAR3,
VAR107,
VAR26,
VAR37,
VAR36,
VAR55,
VAR109,
VAR18,
VAR5,
VAR61,
VAR77,
VAR60,
VAR51,
VAR103,
VAR19,
VAR46,
VAR50,
VAR71,
VAR98,
VAR68,
VAR79,
VAR78,
VAR43,
VAR20,
VAR42,
VAR16,
VAR6,
VAR100,
VAR92,
VAR9,
VAR25,
VAR52,
VAR95,
VAR63,
VAR65,
VAR62,
VAR81,
VAR56,
VAR97,
VAR59,
VAR4,
VAR54,
VAR76,
VAR... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/nios_onchip_memory2_0.v | 4,448 | module MODULE1 (
address,
VAR36,
VAR29,
VAR1,
VAR48,
VAR57,
clk,
VAR39,
VAR13,
VAR51,
reset,
VAR47,
VAR40,
VAR44,
write,
VAR59,
VAR6,
VAR37,
VAR62,
VAR25
)
;
parameter VAR23 = "MODULE1.VAR46";
output [ 31: 0] VAR62;
output [ 31: 0] VAR25;
input [ 11: 0] address;
input [ 11: 0] VAR36;
input [ 3: 0] VAR29;
input [ 3: 0] ... | gpl-3.0 |
linuxbest/lzs | jhash/rtl/verilog/lookup3.v | 2,296 | module MODULE1(
VAR2, VAR12, VAR15,
VAR13, VAR9, VAR18, clk, VAR5
);
input [31:0] VAR13, VAR9, VAR18;
output [31:0] VAR2, VAR12, VAR15;
input clk;
input [4:0] VAR5;
assign VAR2 = (VAR13 - VAR18) ^ ( (VAR18 << VAR5) | (VAR18 >> (32 - VAR5)) );
assign VAR15 = VAR18 + VAR9;
assign VAR12 = VAR9;
endmodule
module MODULE2(
V... | gpl-2.0 |
huxiaolei/xapp1078_2014.4_zybo | design/work/project_2/project_2.srcs/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v | 13,138 | module MODULE1 (
VAR75,
VAR57,
VAR35,
VAR41,
VAR73,
VAR71,
VAR31,
VAR61,
VAR114,
VAR102,
VAR79,
VAR113,
VAR99,
VAR1,
VAR68,
VAR28,
VAR13,
VAR58,
VAR59,
VAR24,
VAR65,
VAR19,
VAR78,
VAR6,
VAR43,
VAR69,
VAR107,
VAR87,
VAR45,
VAR18,
VAR11,
VAR90,
VAR8,
VAR88,
VAR52,
VAR53,
VAR12,
VAR98,
VAR97,
VAR44,
VAR66,
VAR49,
VAR104,
... | gpl-2.0 |
davidkoltak/tawas-core | ip/tawas/rtl/tawas_fetch.v | 7,046 | module MODULE1
(
input clk,
input rst,
output VAR10,
output [23:0] VAR48,
input [31:0] VAR19,
output VAR44,
output [4:0] VAR54,
output [4:0] VAR70,
output [4:0] VAR47,
input [31:0] VAR29,
input [31:0] VAR82,
input VAR38,
input [7:0] VAR28,
input [23:0] VAR39,
output VAR63,
output [2:0] VAR66,
output [31:0] VAR72,
outpu... | mit |
trivoldus28/pulsarch-verilog | verif/env/cmp/ch_mem.v | 27,260 | module MODULE1 (
VAR2, VAR11, VAR5, VAR16,
VAR12, VAR9, VAR18, VAR8, VAR7, VAR14, VAR6, VAR4,
VAR10, VAR13, VAR3, VAR15, VAR17
);
input VAR12; input VAR9; input VAR18; input [3:0] VAR8; input VAR7; input [14:0] VAR14; input [2:0] VAR6; input [2:0] VAR4; input VAR10;
inout VAR2;
input VAR13;
input [3:0] VAR3;
input [3:0... | gpl-2.0 |
horia141/mv-parser | common/mux.v | 6,904 | module MODULE5(select,VAR3,VAR17,VAR21);
parameter VAR31 = 8;
input wire [('d1) - ('b1):0] select;
input wire [(VAR31) - ('b1):0] VAR3;
input wire [(VAR31) - ('b1):0] VAR17;
output reg [(VAR31) - ('b1):0] VAR21;
always @ (select or VAR3 or VAR17) begin
case (select)
'b0:VAR21 = VAR3;
'b1:VAR21 = VAR17;
endcase end
endm... | mit |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/Write_Master/write_burst_control.v | 12,701 | module MODULE1 (
clk,
reset,
VAR26,
VAR33,
VAR34,
VAR17,
VAR8,
ready,
valid,
VAR37,
VAR24,
VAR21,
VAR6,
VAR5,
VAR25,
VAR46,
VAR2,
VAR41,
VAR35,
VAR31,
VAR13,
VAR11,
VAR22,
VAR4
);
parameter VAR7 = 1; parameter VAR20 = 3;
parameter VAR10 = 4;
parameter VAR15 = 2;
parameter VAR9 = 32;
parameter VAR39 = 32;
parameter VAR1... | mit |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_qpll_wrapper.v | 29,089 | module MODULE1 #
(
parameter VAR67 = "VAR107", parameter VAR13 = "VAR85", parameter VAR38 = "3.0", parameter VAR24 = "VAR1", parameter VAR140 = 0
)
(
input VAR37,
input VAR9,
output VAR43,
output VAR42,
output VAR110,
input VAR35,
input VAR139,
input VAR64,
input [ 7:0] VAR141,
input VAR120,
input [15:0] VAR119,
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp.functional.pp.v | 2,330 | module MODULE1 (
VAR15 ,
VAR19 ,
VAR16 ,
VAR20 ,
VAR14 ,
VAR1 ,
VAR22,
VAR7 ,
VAR12 ,
VAR17 ,
VAR11
);
output VAR15 ;
output VAR19 ;
input VAR16 ;
input VAR20 ;
input VAR14 ;
input VAR1 ;
input VAR22;
input VAR7 ;
input VAR12 ;
input VAR17 ;
input VAR11 ;
wire VAR18 ;
wire VAR6 ;
wire VAR4;
not VAR10 (VAR6 , VAR22 );
V... | apache-2.0 |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v | 2,271 | module MODULE1(
VAR2,
VAR19,
VAR3,
VAR16,
req,
VAR18,
VAR4,
VAR10,
VAR17,
VAR9,
VAR21
);
input VAR2, VAR19;
output VAR3, VAR16;
input VAR21, VAR9;
input [VAR15-1:0] VAR17, VAR10;
input req, VAR18;
input [VAR1-1:0] VAR4;
reg [VAR14-1:0] VAR13 = 0, VAR8 = 0;
reg [VAR7-1:0] VAR11 [0:VAR20-1]; wire VAR3, VAR16;
assign VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv.pp.blackbox.v | 1,251 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR5,
VAR3,
VAR1 ,
VAR2
);
output VAR4 ;
input VAR6 ;
input VAR5;
input VAR3;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/hci/hci_back.v | 23,524 | module MODULE1
(
input wire clk, input wire rst, input wire VAR28, output wire VAR74,
input wire VAR14, output wire [15:0] VAR20, input wire [ 7:0] VAR83, output reg [ 7:0] VAR33, output reg VAR73,
output wire VAR51, output reg VAR11, output reg [ 3:0] VAR1, output reg [ 7:0] VAR37, input wire [ 7:0] VAR60,
output reg ... | mit |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/mkInputVCQueues.v | 20,029 | module MODULE1(VAR25,
VAR59,
VAR48,
VAR18,
VAR40,
VAR14,
VAR62,
VAR28,
VAR34,
VAR8);
input VAR25;
input VAR59;
input VAR48;
input [69 : 0] VAR18;
input VAR40;
input VAR14;
input VAR62;
output [69 : 0] VAR28;
output [1 : 0] VAR34;
output [1 : 0] VAR8;
wire [69 : 0] VAR28;
wire [1 : 0] VAR34, VAR8;
wire [2 : 0] VAR20,
VA... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_006bits.v | 1,917 | module MODULE2 (
clk,
VAR6, VAR9, VAR15, VAR8, VAR1, VAR2, VAR3, VAR29,
sum,
);
input clk;
input [VAR27+0-1:0] VAR6, VAR9, VAR15, VAR8, VAR1, VAR2, VAR3, VAR29;
output [VAR27 :0] sum;
reg [VAR27 :0] sum;
wire [VAR27+3-1:0] VAR23;
wire [VAR27+2-1:0] VAR34, VAR31;
wire [VAR27+1-1:0] VAR13, VAR17, VAR26, VAR16;
reg [VAR27... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator.v | 3,765 | module MODULE1
,parameter VAR1(VAR16)
,parameter VAR1(VAR25)
,parameter VAR1(VAR15)
,parameter VAR19 = 1
,parameter VAR24 = 0
,parameter VAR3 = VAR30(VAR26)
)
(input VAR20
,input VAR11
,input [VAR19-1:0][VAR3-1:0] VAR8
,output [VAR19-1:0][VAR3-1:0] VAR14
,input [VAR3-1:0] VAR10
,output [VAR3-1:0] VAR22
);
VAR32 [VAR19-... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlxtn/sky130_fd_sc_hdll__dlxtn.functional.pp.v | 1,795 | module MODULE1 (
VAR13 ,
VAR2 ,
VAR6,
VAR5 ,
VAR7 ,
VAR10 ,
VAR3
);
output VAR13 ;
input VAR2 ;
input VAR6;
input VAR5 ;
input VAR7 ;
input VAR10 ;
input VAR3 ;
wire VAR1 ;
wire VAR11;
not VAR12 (VAR1 , VAR6 );
VAR9 VAR4 (VAR11 , VAR2, VAR1, , VAR5, VAR7);
buf VAR8 (VAR13 , VAR11 );
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | matchfilter.v | 11,351 | module MODULE1 (
clk,
VAR6,
VAR10,
VAR9,
VAR11,
VAR3,
VAR1,
VAR4,
VAR2,
VAR8);
input clk;
input VAR6;
input [14:0] VAR10;
input VAR9;
input VAR11;
input [1:0] VAR3;
output [29:0] VAR1;
output VAR4;
output VAR2;
output [1:0] VAR8;
VAR5 VAR7(
.clk(clk),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR3(VAR3),... | mit |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/niosii/synthesis/submodules/niosii_onchip_memory2_0.v | 2,961 | module MODULE1 (
address,
VAR7,
VAR8,
clk,
VAR34,
reset,
VAR17,
write,
VAR18,
VAR20
)
;
parameter VAR4 = "MODULE1.VAR24";
output [ 31: 0] VAR20;
input [ 13: 0] address;
input [ 3: 0] VAR7;
input VAR8;
input clk;
input VAR34;
input reset;
input VAR17;
input write;
input [ 31: 0] VAR18;
wire VAR11;
wire [ 31: 0] VAR20;
w... | mit |
cpulabs/gci-std-display | rtl/display_controller/gci_std_display_command.v | 5,969 | module MODULE1 #(
parameter VAR51 = 640,
parameter VAR16 = 480,
parameter VAR66 = 19,
parameter VAR11 = 23
)(
input wire VAR40,
input wire VAR26,
input wire VAR32, input wire VAR24,
input wire VAR58,
output wire VAR55,
input wire VAR21,
input wire [VAR11-1:0] VAR36,
input wire [31:0] VAR46,
output wire VAR39,
input wir... | bsd-2-clause |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/altera_up_video_alpha_blender_normal.v | 9,997 | module MODULE1 (
VAR5,
VAR19,
VAR10,
VAR34,
VAR9
);
input [29: 0] VAR5;
input [39: 0] VAR19;
output [ 9: 0] VAR10;
output [ 9: 0] VAR34;
output [ 9: 0] VAR9;
wire [ 9: 0] VAR28;
wire [17: 0] VAR27;
wire [17: 0] VAR24;
wire [17: 0] VAR20;
wire [17: 0] VAR17;
wire [17: 0] VAR29;
wire [17: 0] VAR18;
assign VAR10 = {1'b0, ... | mit |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GDAN8M8P5_syn.v | 9,791 | module MODULE1 ( VAR248, VAR316, VAR159, VAR269 );
input [15:0] VAR316;
input [15:0] VAR159;
output [16:0] VAR269;
input VAR248;
wire VAR219, VAR174, VAR128, VAR268, VAR64, VAR141, VAR115, VAR346, VAR290, VAR104, VAR344, VAR256, VAR300, VAR119,
VAR283, VAR192, VAR195, VAR177, VAR305, VAR142, VAR317, VAR255, VAR231, VAR... | apache-2.0 |
asicguy/gplgpu | hdl/mc_graph/mc_vga.v | 8,074 | module MODULE1
(
input VAR58, input VAR6, input VAR39, input VAR43, input VAR21, input [17:0] VAR46, input VAR33, input [3:0] VAR12, input [31:0] VAR5, input VAR63, input VAR52, input VAR30, input [31:0] VAR14, input VAR29,
output reg VAR10, output reg [17:0] VAR62, output reg VAR59, output reg VAR40, output reg VAR38,... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/dest_axi_mm.v | 7,176 | module MODULE1 (
input VAR15,
input VAR80,
input VAR11,
output VAR26,
input [31:VAR65] VAR66,
input [3:0] VAR89,
input [2:0] VAR40,
input enable,
output VAR72,
input VAR52,
input VAR27,
output VAR43,
output VAR25,
input VAR42,
output [1:0] VAR74,
output VAR46,
input [VAR56-1:0] VAR16,
output [VAR56-1:0] VAR58,
output [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2b/sky130_fd_sc_hs__and2b_1.v | 2,009 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR7 ,
VAR6,
VAR3
);
output VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR6;
input VAR3;
VAR4 VAR1 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR2 ,
VAR5,
VAR7
);
output VAR2 ;
input VAR5;
input VAR7 ;
supply1 VAR6;
supply0 VAR3;
VAR4 VAR1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbp/sky130_fd_sc_ms__sdfbbp.behavioral.pp.v | 3,364 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR30 ,
VAR15 ,
VAR11 ,
VAR38 ,
VAR22 ,
VAR18,
VAR16 ,
VAR7 ,
VAR14 ,
VAR27
);
output VAR1 ;
output VAR9 ;
input VAR30 ;
input VAR15 ;
input VAR11 ;
input VAR38 ;
input VAR22 ;
input VAR18;
input VAR16 ;
input VAR7 ;
input VAR14 ;
input VAR27 ;
wire VAR35 ;
wire VAR31 ;
wire VAR21 ;
reg V... | apache-2.0 |
webmaster442/prog-elektonikak | Kodok/Verilog/10.v | 1,183 | module MODULE3(clk, VAR2)
input clk;
output VAR2;
wire [3:0] VAR2;
reg [2:0] VAR1;
always @(posedge clk)
begin
VAR1 <= VAR1 + 1;
if (VAR1 > 3'b100) VAR1 = 3'b000;
assign VAR2 =
(VAR1 == 3'b000) ? 4'b0001 :
(VAR1 == 3'b001) ? 4'b0010 :
(VAR1 == 3'b011) ? 4'b0100 :
(VAR1 == 3'b100) ? 4'b1000 : 4'b0000;
end
endmodule
modu... | bsd-2-clause |
lvd2/ngs | fpga/current/top.v | 15,387 | module MODULE1(
VAR137, VAR21,
VAR198, VAR112,
VAR86,
VAR93, VAR221,
VAR24, VAR212, VAR253, VAR171, VAR138, VAR148, VAR100, VAR58, VAR99, VAR282,
VAR228, VAR2, VAR227, VAR183, VAR1, VAR200, VAR73, VAR31, VAR216, VAR39, VAR106, VAR65, VAR210,
VAR15, VAR245, VAR25, VAR251, VAR169, VAR46, VAR128, VAR225, VAR104, VAR164, V... | gpl-3.0 |
P3Stor/P3Stor | pcie/app/REQ_QUEUE_WRAPPER.v | 6,567 | module MODULE1(
clk,
VAR39,
en,
VAR35,
VAR24,
VAR5,
VAR19,
VAR30,
VAR20,
VAR36,
VAR4,
VAR26,
VAR25,
VAR16,
VAR38
);
parameter VAR8 = 64;
parameter VAR44 = 64;
parameter VAR23 = 64;
parameter VAR37 = 8'h01;
parameter VAR7 = 8'h02;
parameter VAR15 = 2'b01;
parameter VAR17 = 2'b10;
input clk , VAR39;
input en;
input [127:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.v | 2,441 | module MODULE2 (
VAR11 ,
VAR6 ,
VAR5 ,
VAR3 ,
VAR4,
VAR2 ,
VAR10 ,
VAR9 ,
VAR7
);
output VAR11 ;
output VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR2 ;
input VAR10 ;
input VAR9 ;
input VAR7 ;
VAR8 VAR1 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9)... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/CRC16_D16.v | 3,487 | module MODULE1
(input [15:0] VAR3,
input [15:0] VAR5,
output [15:0] VAR4);
assign VAR4 = VAR1(VAR3,VAR5);
function [15:0] VAR1;
input [15:0] VAR3;
input [15:0] VAR5;
reg [15:0] VAR2;
reg [15:0] VAR6;
reg [15:0] VAR4;
begin
VAR2 = VAR3;
VAR6 = VAR5;
VAR4[0] = VAR2[12] ^ VAR2[11] ^ VAR2[8] ^ VAR2[4] ^ VAR2[0] ^ VAR6[0] ^... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b_4.v | 2,163 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR3 ,
VAR1,
VAR5,
VAR6 ,
VAR7
);
output VAR8 ;
input VAR9 ;
input VAR3 ;
input VAR1;
input VAR5;
input VAR6 ;
input VAR7 ;
VAR4 VAR2 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR8 ,
VAR9,
VAR3
);
output VAR8 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp.blackbox.v | 1,348 | module MODULE1 (
VAR8 ,
VAR1,
VAR2 ,
VAR7,
VAR4
);
output VAR8 ;
input VAR1;
input VAR2 ;
input VAR7;
input VAR4;
supply1 VAR9;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Prueba4.2/fifo.v | 3,735 | module MODULE1 # (parameter VAR16 = 400, VAR9 = 8)(
input reset, VAR13,
input rd, wr,
input [VAR9-1:0] din,
output [VAR9-1:0] dout,
output VAR7,
output VAR22,
output reg VAR3
);
wire VAR11;
wire VAR10;
reg VAR12, VAR25;
reg [VAR9-1:0] out;
VAR4 VAR3 = 0;
reg [1:0] VAR23;
reg [1:0] VAR5;
assign VAR11 = VAR12;
assign VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn_8.v | 2,166 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR7,
VAR1,
VAR6,
VAR3 ,
VAR4
);
output VAR8 ;
input VAR9 ;
input VAR7;
input VAR1;
input VAR6;
input VAR3 ;
input VAR4 ;
VAR2 VAR5 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR8 ,
VAR9 ,
VAR7
);
output VAR8 ;... | apache-2.0 |
ThotIP/async_fifo | src/vlog/async_bidir_ramif_fifo.v | 6,071 | module MODULE1
parameter VAR30 = 8,
parameter VAR8 = 4,
parameter VAR74 = "VAR21" ) (
input wire VAR63,
input wire VAR72,
input wire VAR34,
input wire [VAR30-1:0] VAR50,
input wire VAR7,
output wire [VAR30-1:0] VAR62,
output wire VAR59,
output wire VAR1,
output wire VAR28,
output wire VAR17,
input wire VAR67,
input wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4b/sky130_fd_sc_hd__and4b.blackbox.v | 1,320 | module MODULE1 (
VAR5 ,
VAR6,
VAR4 ,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR6;
input VAR4 ;
input VAR3 ;
input VAR2 ;
supply1 VAR1;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbn/sky130_fd_sc_hs__dlrbn.behavioral.v | 2,502 | module MODULE1 (
VAR8,
VAR13 ,
VAR16 ,
VAR4 ,
VAR14 ,
VAR19 ,
VAR12
);
input VAR8;
input VAR13 ;
input VAR16 ;
output VAR4 ;
output VAR14 ;
input VAR19 ;
input VAR12 ;
wire VAR3 ;
wire VAR20 ;
reg VAR1 ;
wire VAR5 ;
wire VAR23 ;
wire VAR21 ;
wire VAR24;
wire VAR15 ;
wire VAR11 ;
wire VAR6 ;
wire VAR7 ;
not VAR17 (VAR3 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a_2.v | 2,195 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR3 ,
VAR8 ,
VAR9 ,
VAR5,
VAR2
);
output VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR8 ;
input VAR9 ;
input VAR5;
input VAR2;
VAR7 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR4 ,
VAR6,
VAR3,
VAR8,
VAR9
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrbp/sky130_fd_sc_lp__dfrbp.behavioral.v | 2,313 | module MODULE1 (
VAR12 ,
VAR21 ,
VAR20 ,
VAR11 ,
VAR1
);
output VAR12 ;
output VAR21 ;
input VAR20 ;
input VAR11 ;
input VAR1;
supply1 VAR3;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR23 ;
wire VAR18 ;
wire VAR6 ;
reg VAR14 ;
wire VAR22 ;
wire VAR7;
wire VAR5 ;
wire VAR2 ;
wire VAR9 ;
wire VAR16 ;
not VAR4 (VAR6 , VAR7 )... | apache-2.0 |
frisnit/fpga-noise | verilog/clock_mgr.v | 2,749 | module MODULE1(VAR52,
VAR17,
VAR25,
VAR31);
input VAR52;
output VAR17;
output VAR25;
output VAR31;
wire VAR30;
wire VAR10;
wire VAR19;
wire VAR49;
wire VAR13;
assign VAR13 = 0;
assign VAR25 = VAR19;
assign VAR31 = VAR30;
VAR45 VAR27 (.VAR48(VAR10),
.VAR4(VAR17));
VAR14 VAR46 (.VAR48(VAR52),
.VAR4(VAR19));
VAR45 VAR16 (... | mit |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/mkRouterInputArbitersStatic.v | 11,654 | module MODULE1(VAR16,
VAR8,
VAR17,
VAR1,
VAR11,
VAR9,
VAR14,
VAR15,
VAR10,
VAR7,
VAR12,
VAR5,
VAR2,
VAR3,
VAR13,
VAR6,
VAR4);
input VAR16;
input VAR8;
input [4 : 0] VAR17;
output [4 : 0] VAR1;
input VAR11;
input [4 : 0] VAR9;
output [4 : 0] VAR14;
input VAR15;
input [4 : 0] VAR10;
output [4 : 0] VAR7;
input VAR12;
inpu... | gpl-2.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_auto_cc_0/synth/mig_wrap_auto_cc_0.v | 16,272 | module MODULE1 (
VAR54,
VAR68,
VAR108,
VAR96,
VAR51,
VAR20,
VAR69,
VAR22,
VAR25,
VAR26,
VAR82,
VAR72,
VAR87,
VAR92,
VAR34,
VAR36,
VAR103,
VAR53,
VAR112,
VAR104,
VAR18,
VAR35,
VAR107,
VAR37,
VAR61,
VAR88,
VAR97,
VAR89,
VAR110,
VAR115,
VAR7,
VAR45,
VAR113,
VAR38,
VAR85,
VAR71,
VAR78,
VAR98,
VAR47,
VAR15,
VAR64,
VAR29,
VA... | mit |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/apu/apu_length_counter.v | 4,125 | module MODULE1
(
input wire VAR8, input wire VAR3, input wire VAR5, input wire VAR2, input wire VAR9, input wire [4:0] VAR6, input wire VAR10, output wire VAR7 );
reg [7:0] VAR1, VAR4;
always @(posedge VAR8)
begin
if (VAR3)
begin
VAR1 <= 8'h00;
end
else
begin
VAR1 <= VAR4;
end
end
always @*
begin
VAR4 = VAR1;
if (!VAR5... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/example_design/pcie_app_v6.v | 11,726 | module MODULE1
(
input VAR76,
input VAR89,
input VAR5,
input [5:0] VAR4,
input VAR14,
input VAR54,
input VAR3,
output [63:0] VAR87,
output VAR93,
output VAR74,
output VAR64,
output VAR81,
output VAR33,
output VAR30,
output VAR24,
output VAR88,
input [63:0] VAR19,
input VAR49,
input VAR41,
input VAR58,
input VAR52,
inpu... | lgpl-3.0 |
gajjanag/6111_Project | assets/flash_IO/flash_int.v | 3,323 | module MODULE1(reset, VAR20, VAR5, address, VAR7, VAR16, VAR10, VAR19,
VAR17, VAR18, VAR11, VAR8,
VAR1, VAR4, VAR15);
parameter VAR6 = 5;
parameter VAR2 = 1000;
parameter VAR9 = 30;
input reset, VAR20; input [1:0] VAR5; input [22:0] address;
input [15:0] VAR7;
output [15:0] VAR16;
output VAR10;
inout [15:0] VAR19;
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221ai/sky130_fd_sc_hd__o221ai.behavioral.v | 1,688 | module MODULE1 (
VAR11 ,
VAR12,
VAR17,
VAR4,
VAR10,
VAR9
);
output VAR11 ;
input VAR12;
input VAR17;
input VAR4;
input VAR10;
input VAR9;
supply1 VAR6;
supply0 VAR2;
supply1 VAR14 ;
supply0 VAR16 ;
wire VAR7 ;
wire VAR5 ;
wire VAR15;
or VAR1 (VAR7 , VAR10, VAR4 );
or VAR3 (VAR5 , VAR17, VAR12 );
nand VAR13 (VAR15, VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o_2.v | 2,479 | module MODULE2 (
VAR4 ,
VAR10,
VAR1,
VAR9 ,
VAR6 ,
VAR2,
VAR11,
VAR8 ,
VAR5
);
output VAR4 ;
input VAR10;
input VAR1;
input VAR9 ;
input VAR6 ;
input VAR2;
input VAR11;
input VAR8 ;
input VAR5 ;
VAR3 VAR7 (
.VAR4(VAR4),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR5... | apache-2.0 |
jhennessy/parallella-hw-old | fpga/hdl/elink/ewrapper_link_top.v | 15,596 | module MODULE1 (
VAR1, VAR104, VAR106,
VAR87, VAR12, VAR131,
VAR132, VAR169, VAR56,
VAR138, VAR35, VAR65, VAR54,
VAR160, VAR122, VAR149, VAR59, VAR9,
VAR68, VAR123, VAR159, VAR119,
reset, VAR142, VAR27, VAR165, VAR37,
VAR74, VAR141, VAR114,
VAR140, VAR91, VAR143,
VAR23, VAR154, VAR145,
VAR57, VAR102, VAR136, VAR121, VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b.pp.blackbox.v | 1,322 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR8 ,
VAR6 ,
VAR1,
VAR3,
VAR2 ,
VAR4
);
output VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR6 ;
input VAR1;
input VAR3;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand2/sky130_fd_sc_hvl__nand2.behavioral.v | 1,370 | module MODULE1 (
VAR4,
VAR6,
VAR8
);
output VAR4;
input VAR6;
input VAR8;
supply1 VAR2;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR10 ;
wire VAR3;
nand VAR9 (VAR3, VAR8, VAR6 );
buf VAR1 (VAR4 , VAR3 );
endmodule | apache-2.0 |
olgirard/openmsp430 | core/synthesis/actel/src/omsp_frontend.v | 29,790 | module MODULE1 (
VAR119, VAR114, VAR103, VAR69, VAR5, VAR41, VAR25, VAR34, VAR136, VAR128, VAR122, VAR17, VAR8, VAR61, VAR12, VAR129, VAR36, VAR134, VAR57, VAR113, VAR107, VAR56,
VAR30, VAR124, VAR77, VAR73, VAR18, irq, VAR6, VAR35, VAR70, VAR99, VAR110, VAR80, VAR48 );
output VAR119; output VAR114; output [3:0] VAR103... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_4.behavioral.pp.v | 1,174 | module MODULE1( VAR2, VAR4, VAR6, VAR5 );
input VAR2;
inout VAR6, VAR5;
output VAR4;
VAR7 VAR1(.VAR2(VAR2),.VAR4(VAR4),.VAR6(VAR6),.VAR5(VAR5));
VAR7 VAR3(.VAR2(VAR2),.VAR4(VAR4),.VAR6(VAR6),.VAR5(VAR5)); | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/vdma_core.v | 8,409 | module MODULE1 (
VAR28,
VAR17,
VAR34,
VAR26,
VAR2,
VAR56,
VAR23,
VAR32,
VAR3,
VAR8,
VAR41,
VAR48,
VAR22,
VAR24);
parameter VAR4 = 64;
localparam VAR54 = VAR4 - 1;
localparam VAR37 = 6'd3;
localparam VAR36 = 6'd60;
localparam VAR45 = 6'd40;
localparam VAR9 = 6'd50;
input VAR28;
input VAR17;
output VAR34;
input VAR26;
in... | mit |
DProvinciani/Arquitectura_TPF | Codigo_fuente/6-pipe_registers/PC_counter.v | 1,484 | module MODULE1
parameter VAR13=32 )
(
input wire clk,
input wire reset,
input wire VAR14,
input wire VAR6,
input wire [VAR13-1:0] VAR4, input wire [VAR13-1:0] VAR8,
input wire VAR7, input wire VAR3,
output wire [VAR13-1:0] VAR11,
output wire [VAR13-1:0] VAR5
);
reg [VAR13-1:0] VAR15;
VAR10 VAR1 (
.VAR9(VAR15),
.VAR2(4)... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.functional.v | 1,040 | module MODULE1( VAR3, VAR7, VAR4 );
input VAR4, VAR7;
output VAR3;
wire VAR1;
not VAR5( VAR1, VAR4 );
wire VAR8;
not VAR6( VAR8, VAR7 );
and VAR2( VAR3, VAR1, VAR8 );
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_mul_double.v | 29,970 | module MODULE1
(
VAR47,
VAR3,
VAR50,
VAR57,
VAR64) ;
input VAR47;
input VAR3;
input [63:0] VAR50;
input [63:0] VAR57;
output [63:0] VAR64;
tri1 VAR47;
reg VAR59;
reg VAR55;
reg VAR60;
reg VAR51;
reg VAR61;
reg VAR14;
reg VAR12;
reg VAR23;
reg [12:0] VAR30;
reg [12:0] VAR34;
reg VAR6;
reg VAR37;
reg [11:0] VAR17;
reg [1... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_028bits.v | 1,917 | module MODULE2 (
clk,
VAR5, VAR31, VAR16, VAR4, VAR1, VAR21, VAR14, VAR7,
sum,
);
input clk;
input [VAR29+0-1:0] VAR5, VAR31, VAR16, VAR4, VAR1, VAR21, VAR14, VAR7;
output [VAR29 :0] sum;
reg [VAR29 :0] sum;
wire [VAR29+3-1:0] VAR28;
wire [VAR29+2-1:0] VAR6, VAR10;
wire [VAR29+1-1:0] VAR23, VAR8, VAR34, VAR25;
reg [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode.pp.blackbox.v | 1,204 | module MODULE1 (
VAR1,
VAR2,
VAR3 ,
VAR4
);
input VAR1;
input VAR2;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_fine_delay_tuner.v | 2,232 | module MODULE1
(input VAR34
, input VAR7
, input VAR20
, input [1:0] VAR15
, output VAR8
, output VAR42
);
wire [1:0] VAR38;
wire [1:0] VAR18;
wire [3:0] VAR19;
wire VAR44;
VAR3 VAR37 (.VAR40(VAR19[1]),.VAR29());
VAR3 VAR31 (.VAR40(VAR19[2]),.VAR29());
VAR26 VAR35 (.VAR40(VAR19[2]),.VAR29());
VAR3 VAR25 (.VAR40(VAR19[3... | bsd-3-clause |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_SYSTEM_HALT.v | 1,938 | module MODULE1 (
address,
clk,
VAR2,
VAR6,
VAR5
)
;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input clk;
input VAR2;
input VAR6;
wire VAR4;
wire VAR3;
wire VAR1;
reg [ 31: 0] VAR5;
assign VAR4 = 1;
assign VAR1 = {1 {(address == 0)}} & VAR3;
always @(posedge clk or negedge VAR6)
begin
if (VAR6 == 0)
VAR5 <= 0;
end
el... | gpl-2.0 |
CospanDesign/nysa-sata | rtl/command/sata_command_layer.v | 18,446 | module MODULE1 (
input rst, input VAR1,
input clk,
input VAR54,
input VAR111,
input VAR17,
input VAR26,
output VAR138,
output reg VAR109,
input VAR58,
input [15:0] VAR13,
output VAR104,
input VAR113,
input VAR44,
output reg VAR130,
input [7:0] VAR42,
input [15:0] VAR30,
input [47:0] VAR101,
input [31:0] VAR119,
input V... | mit |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_sysid_qsys.v | 1,419 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1490159079 : 2899645186;
endmodule | gpl-3.0 |
Marcoslz22/Tercer_Proyecto | control_digitos_2.v | 3,747 | module MODULE1
(
input [7:0] VAR2,
input [3:0]VAR17,
input [3:0]VAR8,
input [3:0]VAR3,
input VAR11,
input VAR9,
input wire clk,
input wire [3:0] VAR1,
input [3:0] VAR15,
output reg [3:0] VAR4, VAR10, VAR13, VAR14, VAR5, VAR7, VAR16, VAR12, VAR6
);
always @(posedge clk)
if (~VAR11)
if (VAR9)
case (VAR15)
4'b0000: VAR4<=... | mit |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RevertReg.v | 1,506 | module MODULE1(VAR4, VAR5, VAR6, VAR3);
parameter VAR2 = 1;
parameter VAR1 = { VAR2 {1'b0} } ;
input VAR4;
input VAR3;
input [VAR2 - 1 : 0] VAR6;
output [VAR2 - 1 : 0] VAR5;
assign VAR5 = VAR1;
endmodule | mit |
rurume/openrisc_vision_hardware | ISE/or1200_sys.v | 8,038 | module MODULE1(
input VAR53, input VAR99,
input [15:0] VAR194,
input VAR193,
output VAR157,
output [31:0] VAR154,
input VAR30,
output [31:0]VAR101,
input VAR37,
input [15:0] VAR60,
input [31:0] VAR140,
output [31:0] VAR97,
output [7:0] VAR14,
output VAR33,
output [7:0] VAR19,
input [1:0] VAR107
);
wire rst = ~VAR99;
wi... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_075.v | 1,549 | module MODULE2 (
VAR6,
VAR8
);
input [31:0] VAR6;
output [31:0]
VAR8;
wire [31:0]
VAR3,
VAR2,
VAR4,
VAR9,
VAR12,
VAR7,
VAR11,
VAR15,
VAR10,
VAR5;
assign VAR3 = VAR6;
assign VAR7 = VAR3 << 1;
assign VAR15 = VAR4 << 3;
assign VAR2 = VAR3 << 5;
assign VAR4 = VAR3 + VAR2;
assign VAR9 = VAR3 << 12;
assign VAR12 = VAR4 + VAR... | mit |
olajep/oh | src/emesh/hdl/emesh_wralign.v | 2,174 | module MODULE1 (
VAR2,
VAR1, VAR4
);
input [1:0] VAR1;
input [63:0] VAR4;
output [63:0] VAR2;
wire [3:0] VAR3;
assign VAR3[0]= (VAR1[1:0]==2'b00); assign VAR3[1]= (VAR1[1:0]==2'b01); assign VAR3[2]= (VAR1[1:0]==2'b10); assign VAR3[3]= (VAR1[1:0]==2'b11);
assign VAR2[7:0] = VAR4[7:0];
assign VAR2[15:8] = {(8){VAR3[0]}} ... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/nios_bb.v | 1,775 | module MODULE1 (
VAR6,
VAR32,
VAR7,
VAR22,
VAR9,
VAR38,
VAR26,
VAR13,
VAR5,
VAR25,
VAR4,
VAR30,
VAR11,
VAR23,
VAR16,
VAR31,
VAR18,
VAR41,
VAR24,
VAR39,
VAR10,
VAR27,
VAR29,
VAR12,
VAR34,
VAR33,
VAR3,
VAR35,
VAR28,
VAR19,
VAR1,
VAR2,
VAR15,
VAR20,
VAR14,
VAR21,
VAR37,
VAR17,
VAR8,
VAR40,
VAR36);
input VAR6;
input VAR32;... | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_sb_fifo.v | 5,310 | module MODULE1(
VAR7, VAR16, VAR4, VAR1, VAR2, VAR13, VAR17, VAR9
);
parameter VAR5 = 68;
parameter VAR11 = VAR15;
parameter VAR12 = VAR3;
input VAR7; input VAR16; input [VAR5-1:0] VAR4; input VAR1; input VAR2; output [VAR5-1:0] VAR13; output VAR17; output VAR9;
reg [VAR5-1:0] VAR10 [VAR12-1:0];
reg [VAR5-1:0] VAR13;
r... | gpl-3.0 |
Jawanga/ece385final | finalproject/synthesis/submodules/finalproject_mm_interconnect_1.v | 16,024 | module MODULE1 (
input wire VAR35, input wire VAR73, input wire [21:0] VAR91, output wire VAR84, input wire [0:0] VAR30, input wire [3:0] VAR62, input wire VAR19, output wire [31:0] VAR9, output wire VAR43, input wire VAR88, input wire [31:0] VAR87, input wire VAR42, output wire [1:0] VAR38, output wire VAR75, output w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s.behavioral.pp.v | 1,868 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR5,
VAR9,
VAR11 ,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR5;
input VAR9;
input VAR11 ;
input VAR2 ;
wire VAR3 ;
wire VAR8;
buf VAR12 (VAR3 , VAR1 );
VAR6 VAR7 (VAR8, VAR3, VAR5, VAR9);
buf VAR10 (VAR4 , VAR8 );
endmodule | apache-2.0 |
8l/kestrel | 2/nexys2/j1a/T_j1a.v | 20,104 | module MODULE1;
reg VAR2;
reg VAR1;
reg [15:0] VAR12;
reg VAR11;
reg [15:0] VAR10;
wire [13:1] VAR8;
wire VAR14;
wire VAR6;
wire [15:1] VAR13;
wire [15:0] VAR9;
wire VAR7;
wire VAR3;
VAR4 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR14(VAR14),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR13(VAR13),
.VAR9(VAR9),
... | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_arb_mux_4.v | 5,253 | module MODULE1 #
(
parameter VAR32 = 8,
parameter VAR34 = "VAR17",
parameter VAR18 = "VAR5"
)
(
input wire clk,
input wire rst,
input wire [VAR32-1:0] VAR24,
input wire VAR2,
output wire VAR8,
input wire VAR14,
input wire VAR33,
input wire [VAR32-1:0] VAR12,
input wire VAR31,
output wire VAR11,
input wire VAR35,
input ... | mit |
luebbers/reconos | support/pcores/plb_tft_cntlr_ref_v1_00_e/hdl/verilog/v_sync.v | 16,286 | module MODULE1(
clk, VAR11, rst, VAR6, VAR28, VAR9, VAR20);
input clk;
input VAR11;
input rst;
output VAR6;
output VAR28;
output VAR9;
output VAR20;
reg VAR28;
reg VAR6;
reg [0:1] VAR26; reg [0:4] VAR12; reg [0:8] VAR4; reg [0:3] VAR2; reg VAR18;
reg VAR19;
reg VAR5;
reg VAR21;
reg VAR27;
reg VAR25;
reg VAR17;
reg VAR2... | gpl-3.0 |
CospanDesign/vivado-ip-cores | ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl/nh_lcd_data_writer.v | 7,507 | module MODULE1#(
parameter VAR66 = 24,
parameter VAR64 = 12
)(
input rst,
input clk,
output [31:0] VAR18,
input VAR11,
input [31:0] VAR5,
input [31:0] VAR13,
input VAR43,
input VAR38,
input VAR62,
output [1:0] VAR8,
input [1:0] VAR19,
input VAR25,
output [23:0] VAR28,
input [VAR66:0] VAR55,
output VAR39,
output reg [7:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3.pp.symbol.v | 1,322 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR3 ,
input VAR2,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
unsignedzero/verilogLabs | labs/lab11/shift/shift_fifo.v | 1,358 | module MODULE1 (
VAR4, VAR2, VAR1, VAR5, clk, rst );
input VAR4, VAR2, clk, rst;
input VAR1;
output VAR5;
reg VAR5;
reg [7:0] VAR3; reg [2:0] VAR6;
always @(posedge clk or posedge rst)
if (rst) begin
VAR6 <= 3'h0;
VAR3 <= 8'h00;
end else begin
if (VAR4) begin
{VAR3, VAR5} <= {1'b0, VAR3}; VAR6 <= VAR6 - 1; end else if ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi.functional.v | 1,962 | module MODULE1 (
VAR6,
VAR12,
VAR2 ,
VAR8 ,
VAR5 ,
VAR11 ,
VAR13 ,
VAR15
);
input VAR6;
input VAR12;
output VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR11 ;
input VAR13 ;
input VAR15 ;
wire VAR13 VAR7 ;
wire VAR3 ;
wire VAR16;
and VAR14 (VAR7 , VAR8, VAR5, VAR11, VAR13 );
nor VAR1 (VAR3 , VAR15, VAR7 );
VAR4 VAR10 (VAR16... | apache-2.0 |
strigeus/fpganes | src/clk_wiz_v3_6.v | 6,891 | module MODULE1
( input VAR30,
output VAR77,
input VAR71,
output VAR73
);
VAR39 VAR8
(.VAR54 (VAR59),
.VAR15 (VAR30));
wire [15:0] VAR25;
wire VAR69;
wire VAR13;
wire VAR49;
wire VAR63;
wire VAR66;
wire VAR58;
wire VAR64;
wire VAR7;
wire VAR75;
wire VAR4;
wire VAR74;
wire VAR76;
wire VAR40;
wire VAR37;
wire VAR26;
wire ... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/NVMeHostController_v2_0_0/ba7abda2/src/pcie_tx.v | 7,060 | module MODULE1 # (
parameter VAR65 = 128,
parameter VAR60 = 36
)
(
input VAR30,
input VAR27,
input [15:0] VAR8,
output VAR50,
input VAR49,
input VAR33,
input VAR18,
input VAR14,
output [VAR65-1:0] VAR16,
output [(VAR65/8)-1:0] VAR43,
output [3:0] VAR31,
output VAR21,
output VAR67,
input VAR47,
input [7:0] VAR24,
input ... | gpl-3.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v | 9,229 | module MODULE1(
VAR82,
VAR15,
VAR41,
VAR107,
VAR79,
VAR3,
VAR11,
VAR85,
VAR22,
VAR44,
VAR14,
VAR114,
VAR27,
VAR90,
VAR103,
VAR40,
VAR26,
VAR31,
VAR10,
VAR77,
VAR64,
VAR19,
VAR108,
VAR32,
VAR38,
VAR59,
VAR48,
VAR45,
VAR101
);
parameter VAR81 = "";
parameter VAR97 = "";
parameter VAR9 = "";
parameter VAR36 = "";
paramete... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o.functional.pp.v | 2,064 | module MODULE1 (
VAR18 ,
VAR11 ,
VAR10 ,
VAR15 ,
VAR9 ,
VAR14 ,
VAR4,
VAR8,
VAR13 ,
VAR5
);
output VAR18 ;
input VAR11 ;
input VAR10 ;
input VAR15 ;
input VAR9 ;
input VAR14 ;
input VAR4;
input VAR8;
input VAR13 ;
input VAR5 ;
wire VAR17 ;
wire VAR6 ;
wire VAR1;
and VAR12 (VAR17 , VAR15, VAR11, VAR10 );
or VAR16 (VAR6 ... | apache-2.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CoreAPB3/4.0.100/rtl/vlog/core_obfuscated/coreapb3.v | 26,358 | module
MODULE1
(
parameter
[
5
:
0
]
VAR183
=
32
,
parameter
VAR28
=
0
,
parameter
[
0
:
0
]
VAR124
=
1
,
parameter
[
0
:
0
]
VAR111
=
1
,
parameter
[
0
:
0
]
VAR174
=
1
,
parameter
[
0
:
0
]
VAR88
=
1
,
parameter
[
0
:
0
]
VAR170
=
1
,
parameter
[
0
:
0
]
VAR148
=
1
,
parameter
[
0
:
0
]
VAR5
=
1
,
parameter
[
0
:
0
]... | mit |
PerezFederico/UART_Arquitectura | SeparadorNumeros.v | 4,941 | module MODULE1
(input [31:0] VAR11,
input VAR15,
input VAR8,
input clk,
output reg [7:0] VAR9 = 0,
output reg VAR13 = 0
);
reg [3:0] VAR21;
reg [3:0] VAR2;
reg [3:0] VAR17;
reg [3:0] VAR19;
reg [3:0] VAR14;
reg [3:0] VAR6;
reg [3:0] VAR10;
reg [3:0] VAR3;
reg [3:0] VAR7;
reg [3:0] VAR5;
reg VAR23 = 0;
reg VAR22 = 0;
re... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9643_v6_00_a/hdl/verilog/axi_ad9643.v | 14,532 | module MODULE1 (
VAR122,
VAR67,
VAR7,
VAR44,
VAR27,
VAR108,
VAR22,
VAR61,
VAR59,
VAR63,
VAR143,
VAR168,
VAR160,
VAR100,
VAR106,
VAR102,
VAR17,
VAR128,
VAR29,
VAR90,
VAR116,
VAR149,
VAR81,
VAR161,
VAR148,
VAR57,
VAR147,
VAR4,
VAR126,
VAR105,
VAR62,
VAR80,
VAR64,
VAR54,
VAR25,
VAR18);
parameter VAR8 = 0;
parameter VAR117... | mit |
richard42/CoCo3FPGA | uart_6551.v | 9,887 | module MODULE1(
VAR51,
VAR33,
VAR9,
VAR28,
VAR48,
VAR12,
VAR32,
VAR5,
VAR55,
VAR57,
VAR14,
VAR52,
VAR31,
VAR21,
VAR39,
VAR37,
VAR56,
VAR16
);
input VAR51;
output VAR33;
input VAR9;
input VAR28;
input VAR48;
input [7:0] VAR12;
output [7:0] VAR32;
output VAR5;
input [1:0] VAR55;
input [1:0] VAR14;
input VAR57;
output VAR... | bsd-3-clause |
svofski/mahponk | src/tehgame.v | 6,326 | module MODULE1(clk, VAR28, reset, VAR11, VAR34, VAR24, VAR10, VAR26, VAR22, VAR55, VAR39, VAR9, VAR38, VAR59);
parameter VAR21 = 10'd640;
parameter VAR65 = 10'd480;
parameter VAR5 = 10'd64;
parameter VAR37 = 8;
input clk, VAR28;
input reset;
input VAR11;
input VAR34;
input [9:0] VAR24;
input [9:0] VAR10;
input [9:0] VA... | bsd-2-clause |
alexforencich/xfcp | lib/eth/rtl/ssio_ddr_in.v | 4,137 | module MODULE1 #
(
parameter VAR31 = "VAR11",
parameter VAR17 = "VAR6",
parameter VAR14 = "VAR27",
parameter VAR13 = 1
)
(
input wire VAR22,
input wire [VAR13-1:0] VAR3,
output wire VAR36,
output wire [VAR13-1:0] VAR37,
output wire [VAR13-1:0] VAR26
);
wire VAR5;
wire VAR19;
generate
if (VAR31 == "VAR2") begin
if (VAR1... | mit |
manu3193/ControladorElevadorTDD | DecoBCDto7seg.v | 1,434 | module MODULE1(
VAR5, o1, o2, o3, o4, o5, o6, o7, VAR4, VAR3, VAR2, VAR1 );
input [2:0] VAR5;
output reg o1, o2, o3, o4, o5, o6, o7;
output VAR4, VAR3, VAR2, VAR1;
always @(o1, o2, o3, o4, o5, o6, o7,VAR5)
begin
o1 = !( (!VAR5[0]&!VAR5[2]) | VAR5[1] ); o2 = 1'b0; o3 = !( (!VAR5[1]) | VAR5[0] ); o4 = !( (!VAR5[2]&!VAR5[... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_rf.v | 57,726 | module MODULE1( clk, VAR8, rst,
VAR257, VAR75, VAR161, din, dout, VAR36, VAR158,
VAR224, VAR145,
VAR244,
VAR238, VAR100,
VAR103, VAR267, VAR118,
VAR35, VAR39,
VAR252, VAR48, VAR14,
VAR42, VAR82, VAR196,
VAR163,
VAR28, VAR151, VAR258,
VAR233,
VAR164, VAR203,
VAR266,
VAR141, VAR201, VAR256,
VAR47, VAR199, VAR260, VAR138,... | gpl-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_Char_Buffer_with_DMA.v | 13,450 | module MODULE1 (
clk,
reset,
VAR24,
VAR36,
VAR4,
VAR7,
VAR45,
VAR76,
VAR27,
VAR77,
VAR18,
VAR54,
VAR108,
VAR67,
VAR22,
VAR32,
VAR51,
VAR103,
VAR107,
VAR34,
VAR53,
VAR106,
VAR37
);
parameter VAR94 = 8;
parameter VAR21 = 0;
parameter VAR62 = 13;
parameter VAR26 = 8192;
parameter VAR8 = 640;
parameter VAR109 = 480;
input ... | mit |
d16-processor/d16 | verilog/src/ntsc_gen.v | 1,140 | module MODULE1(clk,VAR10,VAR5);
parameter VAR9 = 4;
input clk;
output reg [VAR9-1:0] VAR5;
output VAR10;
wire [VAR9-1:0] VAR1;
wire [VAR9-1:0] sync;
reg [9:0] VAR2 = 0;
reg [8:0] VAR4 = 0;
reg [3:0] counter = 0;
reg [7:0] VAR7 = 8'b01100100;
always @(posedge clk) begin
VAR7 <= {VAR7[5:0],VAR7[7:6]};
if(VAR2 == 903) beg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a.symbol.v | 1,310 | module MODULE1 (
input VAR1,
input VAR5,
input VAR6,
input VAR3,
output VAR4
);
supply1 VAR7;
supply0 VAR2;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_clk_cl_misc_jbus.v | 3,309 | module MODULE1 (
VAR10, VAR9, VAR4, VAR5,
VAR8, VAR6, VAR12, VAR3, VAR13, VAR1, VAR2,
VAR7
);
output VAR5; output VAR4; output VAR9; output VAR10;
input VAR7; input VAR2; input VAR1; input VAR13; input VAR3; input VAR12; input VAR6; input VAR8;
VAR11 VAR11
(
.VAR4 (VAR4),
.VAR5 (VAR5),
.VAR9 (VAR9),
.VAR10 (VAR10),
.VA... | gpl-2.0 |
finnball/igloo | projects/chip8/hdl/interpreter.v | 22,766 | module MODULE1(
input clk,
input [7 : 0] VAR52,
input VAR93,
output VAR136,
output VAR110,
output VAR90
);
localparam VAR118 = 0;
localparam VAR129 = 1;
localparam VAR99 = 2;
localparam VAR65 = 3;
localparam VAR11 = 4;
localparam VAR13 = 0;
localparam VAR83 = 1;
localparam VAR17 = 2;
localparam VAR77 = 3;
localparam VA... | gpl-3.0 |
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