repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
SiLab-Bonn/monopix_daq | firmware/src/pulse_gen640/pulse_gen640_core.v | 8,042 | module MODULE1
parameter VAR30 = 16,
parameter VAR26 = 4, parameter VAR35 =2
)
(
input wire VAR56,
input wire [VAR30-1:0] VAR19,
input wire [7:0] VAR70,
output reg [7:0] VAR57,
input wire VAR80,
input wire VAR45,
input wire VAR23,
input wire VAR58,
input wire VAR61,
input wire VAR10,
input wire VAR81,
output wire [VAR3... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_gt_common.v | 7,333 | module MODULE1 #(
parameter VAR7 = "VAR32", parameter VAR19 = "VAR14", parameter VAR38 = "2.1", parameter VAR31 = "VAR30", parameter VAR10 = 0 )
(
input VAR26,
input VAR20,
input VAR52,
input VAR18,
input VAR41,
input VAR46,
input VAR56,
input VAR11,
input VAR59,
output [5:0] VAR15,
output [8:0] VAR55,
output VAR44,
ou... | gpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_SRAM_TT_201020.v | 210,959 | module MODULE1 (VAR11, VAR1, VAR2, VAR5, VAR9);
output VAR11;
input VAR1, VAR2, VAR5, VAR9;
wire VAR10, VAR4, VAR8;
wire VAR7, VAR3, VAR6;
not (VAR7, VAR9);
not (VAR8, VAR5);
not (VAR4, VAR2);
and (VAR3, VAR4, VAR8);
not (VAR10, VAR1);
and (VAR6, VAR10, VAR8);
or (VAR11, VAR6, VAR3, VAR7); | bsd-3-clause |
vvk/sysrek | uart_echo/UART_memory.v | 3,562 | module MODULE1(
input VAR12,
output VAR25,
input VAR13,
output [7:0]VAR7,
output [7:0]VAR17,
output [7:0]VAR33,
output [7:0]VAR34,
output [7:0]VAR24,
output [7:0]VAR14,
output [7:0]VAR16,
output [7:0]VAR8,
output [7:0] VAR2
);
parameter VAR11 = 8;
reg [15:0]memory[VAR11-1:0];
VAR38 begin: VAR9
integer VAR1;
for (VAR1 =... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_22.v | 16,359 | module MODULE3 (
clk,
reset,
VAR77,
VAR43,
VAR34,
VAR119,
VAR112
);
parameter VAR56 = 18;
parameter VAR86 = 22;
parameter VAR48 = 11;
localparam VAR102 = 23;
input clk;
input reset;
input VAR77;
input VAR43;
input [VAR56-1:0] VAR34; output VAR119;
output [VAR56-1:0] VAR112;
localparam VAR59 = 18; localparam VAR115 = 36... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b.functional.v | 1,356 | module MODULE1 (
VAR7 ,
VAR2,
VAR3
);
output VAR7 ;
input VAR2;
input VAR3 ;
wire VAR1 ;
wire VAR5;
not VAR8 (VAR1 , VAR3 );
or VAR4 (VAR5, VAR1, VAR2 );
buf VAR6 (VAR7 , VAR5 );
endmodule | apache-2.0 |
skarpenko/ultiparc | rtl/src/interval_timer.v | 5,127 | module MODULE1(
clk,
VAR18,
VAR26,
VAR27,
VAR7,
VAR23,
VAR5,
VAR25,
VAR11,
VAR24
);
localparam [2:0] VAR17 = 3'b001;
localparam [2:0] VAR4 = 3'b010;
localparam [2:0] VAR14 = 3'b100;
localparam [VAR1-1:0] VAR2 = 32'h000;
localparam [VAR1-1:0] VAR19 = 32'h004;
localparam [VAR1-1:0] VAR9 = 32'h008;
input wire clk;
input w... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn_8.v | 2,164 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR2,
VAR7,
VAR5,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR4 ;
input VAR2;
input VAR7;
input VAR5;
input VAR3 ;
input VAR1 ;
VAR9 VAR8 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR6 ,
VAR4 ,
VAR2
);
output VAR6 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ebufn/sky130_fd_sc_ms__ebufn.pp.blackbox.v | 1,287 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR4,
VAR7,
VAR2,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR6 ;
input VAR4;
input VAR7;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
merckhung/zet | cores/zet/rtl/zet_fulladd16.v | 1,028 | module MODULE1 (
input [15:0] VAR5,
input [15:0] VAR6,
input VAR1,
output VAR4,
output [15:0] VAR3,
input VAR2
);
assign {VAR4,VAR3} = {1'b0, VAR5} + {VAR2, VAR6} + VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o.pp.symbol.v | 1,388 | module MODULE1 (
input VAR1 ,
input VAR5 ,
input VAR3 ,
input VAR4 ,
input VAR8 ,
output VAR10 ,
input VAR9 ,
input VAR7,
input VAR2,
input VAR6
);
endmodule | apache-2.0 |
Marcoslz22/Tercer_Proyecto | VGAInterface.v | 4,443 | module MODULE1(
input VAR20, output VAR1, input [7:0] VAR26, output reg [7:0] VAR27, output [9:0] VAR10, output [8:0] VAR36, output reg VAR5, output reg VAR22, input VAR3
);
wire [9:0] VAR37; wire [9:0] VAR21; wire VAR18;
VAR30 begin VAR5 = 0;
VAR22 = 0;
VAR27 = 8'b0;
end
parameter VAR23 = 10'd96;
parameter VAR17 = 10'... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b.behavioral.pp.v | 1,995 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR12 ,
VAR4 ,
VAR10,
VAR3,
VAR5 ,
VAR7
);
output VAR6 ;
input VAR1 ;
input VAR12 ;
input VAR4 ;
input VAR10;
input VAR3;
input VAR5 ;
input VAR7 ;
wire VAR9 ;
wire VAR13 ;
wire VAR8;
nor VAR16 (VAR9 , VAR1, VAR12 );
and VAR11 (VAR13 , VAR4, VAR9 );
VAR15 VAR14 (VAR8, VAR13, VAR10, VAR3);... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_016.v | 1,533 | module MODULE2 (
VAR4,
VAR2
);
input [31:0] VAR4;
output [31:0]
VAR2;
wire [31:0]
VAR7,
VAR3,
VAR12,
VAR8,
VAR13,
VAR1,
VAR11,
VAR10,
VAR14;
assign VAR7 = VAR4;
assign VAR10 = VAR11 << 2;
assign VAR3 = VAR7 << 8;
assign VAR12 = VAR7 + VAR3;
assign VAR11 = VAR1 - VAR12;
assign VAR1 = VAR7 << 12;
assign VAR14 = VAR10 - V... | mit |
rkrajnc/minimig-mist | rtl/or1200/or1200_pm.v | 6,711 | module MODULE1(
clk, rst, VAR11, VAR18, VAR23, VAR27, VAR8,
VAR15, VAR19, VAR28, VAR12, VAR2,
VAR10, VAR5, VAR13, VAR24, VAR26
);
input clk; input rst; input VAR11; input VAR18; input [31:0] VAR23; input [31:0] VAR27; output [31:0] VAR8;
input VAR19; output [3:0] VAR15; output VAR28; output VAR12; output VAR2; output V... | gpl-3.0 |
esonghori/TinyGarble | circuit_synthesis/lib/stdcells_S.v | 23,550 | module \not ;
endmodule
module MODULE45 ;
endmodule
module \VAR67 ;
endmodule
module MODULE23 (VAR77, VAR86);
parameter VAR30 = 0;
parameter VAR97 = 1;
parameter VAR1 = 1;
input [VAR97-1:0] VAR77;
output [VAR1-1:0] VAR86;
\VAR95 #(
.VAR30(VAR30),
.VAR36(VAR30),
.VAR97(1),
.VAR10(VAR97),
.VAR1(VAR1)
) VAR95 (
.VAR77(1'b... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/earb/hdl/earb.v | 4,459 | module MODULE1 (
VAR11, VAR17, VAR8, VAR2, VAR21,
VAR14, VAR7, VAR20, VAR22,
VAR6,
VAR24, reset, VAR10, VAR15, VAR4, VAR16,
VAR3, VAR18, VAR5, VAR19, VAR23
);
input VAR24;
input reset;
input [102:0] VAR10;
output VAR11;
input VAR15;
input [102:0] VAR4;
output VAR17;
input VAR16;
input [102:0] VAR3;
output VAR8;
input V... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_phy_write.v | 16,797 | module MODULE1 #
(
parameter VAR28 = 72,
parameter VAR53 = 1,
parameter VAR13 = 0,
parameter VAR50 = 5,
parameter VAR6 = 0,
parameter VAR51 = 1,
parameter VAR61 = 1,
parameter VAR31 = 1
)
(
input VAR18,
input VAR56,
input VAR9,
input [(2*VAR28)-1:0] VAR23,
input [(2*VAR28/8)-1:0] VAR41,
input VAR44,
input VAR58,
input ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_pwrgood_pp_g/sky130_fd_sc_ms__udp_pwrgood_pp_g.symbol.v | 1,285 | module MODULE1 (
input VAR1 ,
output VAR2,
input VAR3
);
endmodule | apache-2.0 |
PeterMagnusson/modexp | src/rtl/shr32.v | 2,264 | module MODULE1(
input wire [31 : 0] VAR3,
input wire VAR4,
output wire [31 : 0] VAR2,
output wire VAR1
);
assign VAR2 = {VAR4, VAR3[31 : 1]};
assign VAR1 = VAR3[0];
endmodule | bsd-2-clause |
zhangly/azpr_cpu | rtl/cpu/rtl/id_stage.v | 7,148 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR9] VAR49, input wire [VAR9] VAR8, output wire [VAR21] VAR36, output wire [VAR21] VAR29,
input wire VAR28, input wire [VAR9] VAR12, input wire [VAR21] VAR13, input wire VAR2, input wire [VAR9] VAR43,
input wire [VAR30] VAR48, input wire [VAR9] VAR11, outp... | mit |
ptracton/Picoblaze | PicoBlaze_GPIO_Example/PicoBlaze_GPIO_Example.srcs/sources_1/imports/PicoBlaze_GPIO_Example/gpio.v | 3,720 | module MODULE1 (
VAR1,
MODULE1,
clk, VAR8, VAR11
) ;
input clk;
input [7:0] VAR8;
output [7:0] VAR1; input [7:0] VAR11;
inout [7:0] MODULE1;
VAR12 VAR2(
.VAR1 (VAR1[0]),
.MODULE1 (MODULE1[0]),
.clk (clk),
.VAR8 (VAR8[0]),
.VAR11 (VAR11[0]));
VAR12 VAR6(
.VAR1 (VAR1[1]),
.MODULE1 (MODULE1[1]),
.clk (clk),
.VAR8 (VAR8[1]... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu7t5v0__latsnq_4.behavioral.v | 2,924 | module MODULE1( VAR26, VAR9, VAR23, VAR21 );
input VAR9, VAR26, VAR23;
output VAR21;
reg VAR22;
VAR7 VAR18(.VAR26(VAR26),.VAR9(VAR9),.VAR23(VAR23),.VAR21(VAR21),.VAR22(VAR22));
VAR7 VAR6(.VAR26(VAR26),.VAR9(VAR9),.VAR23(VAR23),.VAR21(VAR21),.VAR22(VAR22));
buf VAR10(VAR1,VAR23);
not VAR12(VAR15,VAR9);
and VAR5(VAR19,VA... | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_obc1/obc_lower.v | 7,045 | module MODULE1 (
address,
VAR2,
VAR15,
VAR27,
VAR24);
input [8:0] address;
input VAR2;
input [7:0] VAR15;
input VAR27;
output [7:0] VAR24;
tri1 VAR2;
wire [7:0] VAR20;
wire [7:0] VAR24 = VAR20[7:0];
VAR46 VAR18 (
.VAR44 (address),
.VAR13 (VAR2),
.VAR30 (VAR15),
.VAR7 (VAR27),
.VAR16 (VAR20),
.VAR37 (1'b0),
.VAR17 (1'b0... | gpl-2.0 |
natsutan/NPU | fpga_implement/npu8/npu8.ip_user_files/ip/mul8_16/mul8_16_stub.v | 1,252 | module MODULE1(VAR3, VAR1, VAR4, VAR2)
;
input VAR3;
input [7:0]VAR1;
input [15:0]VAR4;
output [15:0]VAR2;
endmodule | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_axi_basic_tx.v | 10,039 | module MODULE1 #(
parameter VAR34 = 128, parameter VAR22 = "VAR10", parameter VAR32 = "VAR2", parameter VAR20 = "VAR2", parameter VAR42 = 1,
parameter VAR26 = (VAR34 == 128) ? 2 : 1, parameter VAR8 = VAR34 / 8 ) (
input [VAR34-1:0] VAR41, input VAR15, output VAR29, input [VAR8-1:0] VAR17, input VAR6, input [3:0] VAR43,... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_nios2_gen2_0.v | 5,764 | module MODULE1 (
input wire clk, input wire VAR17, input wire VAR25, output wire [28:0] VAR13, output wire [3:0] VAR15, output wire VAR24, input wire [31:0] VAR22, input wire VAR5, output wire VAR16, output wire [31:0] VAR2, output wire VAR20, output wire [28:0] VAR8, output wire VAR19, input wire [31:0] VAR21, input w... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_2.behavioral.pp.v | 1,159 | module MODULE1( VAR4, VAR3, VAR7, VAR1 );
input VAR4;
inout VAR7, VAR1;
output VAR3;
VAR2 VAR5(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR1(VAR1));
VAR2 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3b/sky130_fd_sc_ms__nand3b.behavioral.v | 1,497 | module MODULE1 (
VAR2 ,
VAR9,
VAR3 ,
VAR10
);
output VAR2 ;
input VAR9;
input VAR3 ;
input VAR10 ;
supply1 VAR6;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR13 ;
wire VAR4 ;
wire VAR11;
not VAR1 (VAR4 , VAR9 );
nand VAR5 (VAR11, VAR3, VAR4, VAR10 );
buf VAR12 (VAR2 , VAR11 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp_dramgif.v | 8,240 | module MODULE1(
VAR37, VAR35, VAR49, VAR31,
VAR57, VAR14, VAR10,
VAR50, VAR22, VAR59,
VAR39, VAR27, VAR26, VAR63,
VAR33, VAR9, VAR54,
VAR6, VAR13, VAR30,
VAR25, VAR23,
VAR5, VAR61, VAR58,
VAR51, VAR4
);
input VAR39;
input VAR27;
input VAR26;
input VAR63;
input VAR33;
input [9:0] VAR9;
input VAR54;
input VAR6;
input VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai.behavioral.pp.v | 2,059 | module MODULE1 (
VAR5 ,
VAR11 ,
VAR16 ,
VAR4 ,
VAR7 ,
VAR1 ,
VAR6,
VAR9,
VAR14 ,
VAR15
);
output VAR5 ;
input VAR11 ;
input VAR16 ;
input VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR6;
input VAR9;
input VAR14 ;
input VAR15 ;
wire VAR3 ;
wire VAR12 ;
wire VAR10;
or VAR17 (VAR3 , VAR7, VAR4, VAR16, VAR11 );
nand VAR2 (VAR1... | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v | 3,933 | module MODULE1 #
(
parameter integer VAR18 = 4,
parameter integer VAR6 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR18-1:0] VAR20 ,
input wire [VAR6-1:0] VAR7 ,
input wire [7:0] VAR10 ,
input wire [2:0] VAR25 ,
input wire [1:0] VAR12 ,
input wire VAR27 ,
output wire VAR4 ,
output wire VAR8 ,
output wire ... | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_AsyncResetRegVec.v | 1,798 | module MODULE1(
input VAR3,
input reset,
input VAR2,
output VAR5,
input VAR4
);
wire VAR12;
wire VAR10;
wire VAR11;
wire VAR6;
wire VAR7;
VAR1 VAR13 (
.rst(VAR12),
.clk(VAR10),
.en(VAR11),
.VAR9(VAR6),
.VAR8(VAR7)
);
assign VAR5 = VAR6;
assign VAR12 = reset;
assign VAR10 = VAR3;
assign VAR11 = VAR4;
assign VAR7 = VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb_lp.v | 2,322 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR11 ,
VAR7 ,
VAR9 ,
VAR3,
VAR5,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR6 ;
input VAR11 ;
input VAR7 ;
input VAR9 ;
input VAR3;
input VAR5;
input VAR2 ;
input VAR1 ;
VAR8 VAR10 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi.pp.symbol.v | 1,380 | module MODULE1 (
input VAR1 ,
input VAR7 ,
input VAR9 ,
input VAR4 ,
output VAR8 ,
input VAR2 ,
input VAR6,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/cache/CacheBlockRAM_bb.v | 8,598 | module MODULE1 (
VAR5,
VAR8,
VAR6,
VAR9,
VAR3,
VAR1,
VAR7,
VAR4,
VAR2);
input [8:0] VAR5;
input [8:0] VAR8;
input VAR6;
input [17:0] VAR9;
input [17:0] VAR3;
input VAR1;
input VAR7;
output [17:0] VAR4;
output [17:0] VAR2;
tri1 VAR6;
tri0 VAR1;
tri0 VAR7;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn_8.v | 2,150 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR8,
VAR6,
VAR7,
VAR1 ,
VAR9
);
output VAR3 ;
input VAR5 ;
input VAR8;
input VAR6;
input VAR7;
input VAR1 ;
input VAR9 ;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR3 ,
VAR5 ,
VAR8
);
output VAR3 ;... | apache-2.0 |
nyaxt/dmix | mpemu_scale_t.v | 1,591 | module MODULE1;
reg [31:0] VAR4 [VAR1-1:0];
reg [31:0] VAR10 [VAR1-1:0];
reg [31:0] VAR7 [VAR1-1:0];
reg clk;
reg [23:0] VAR9;
reg [31:0] VAR6;
wire [31:0] VAR2;
VAR11 VAR8(
.clk(clk),
.VAR9(VAR9), .VAR6(VAR6),
.VAR2(VAR2));
parameter VAR3 = 41.0;
integer VAR5; | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_uitofp.v | 2,407 | module MODULE1(VAR2, VAR10,
VAR21, VAR14, VAR29,
VAR24, VAR7, VAR23);
parameter VAR12 = 32;
parameter VAR5 = 6;
parameter VAR19 = 64;
input VAR2, VAR10;
input [VAR12-1:0] VAR21;
input VAR14;
output VAR29;
output [VAR12-1:0] VAR24;
input VAR7;
output VAR23;
reg [VAR5-1:0] VAR20;
wire [VAR12-1:0] VAR15;
wire VAR17;
wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp.behavioral.v | 2,290 | module MODULE1 (
VAR8 ,
VAR1,
VAR12 ,
VAR13
);
output VAR8 ;
input VAR1;
input VAR12 ;
input VAR13 ;
supply1 VAR11;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR7 ;
wire VAR15 ;
reg VAR18 ;
wire VAR14 ;
wire VAR16 ;
wire VAR9 ;
wire VAR3;
wire VAR17 ;
wire VAR19 ;
wire VAR5 ;
wire VAR4 ;
not VAR10 (VAR15 , VAR3 );
VAR21 VAR... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/user_logic_if/user_dma_req_arbitrator.v | 4,758 | module MODULE1 #(
parameter VAR18 = 'd4,
parameter VAR5 = 'd32,
parameter VAR29 = 'd12,
parameter VAR4 = 'd8,
parameter VAR39 = 'd64,
parameter VAR26 = 'd5
)
(
input VAR2,
input VAR30,
input [VAR18-1:0] VAR9,
input [VAR5*VAR18-1:0] VAR25,
input [VAR29*VAR18-1:0] VAR35,
input [VAR4*VAR18-1 :0] VAR15,
output reg [VAR18-1... | mit |
walkthetalk/fsref | ip/s2mm/src/s2mm.v | 4,686 | module MODULE1 #
(
parameter integer VAR2 = 8,
parameter integer VAR6 = 12,
parameter integer VAR55 = 12,
parameter integer VAR5 = 12,
parameter integer VAR59 = 8,
parameter integer VAR66 = 16,
parameter integer VAR68 = 32,
parameter integer VAR20 = 32
)
(
input wire [VAR6-1:0] VAR51,
input wire [VAR55-1:0] VAR70,
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4/sky130_fd_sc_ms__nor4_2.v | 2,275 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR11 ,
VAR1 ,
VAR4 ,
VAR10,
VAR7,
VAR3 ,
VAR8
);
output VAR5 ;
input VAR2 ;
input VAR11 ;
input VAR1 ;
input VAR4 ;
input VAR10;
input VAR7;
input VAR3 ;
input VAR8 ;
VAR9 VAR6 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR3(VAR3),
.... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v | 8,787 | module MODULE1 #
(
parameter VAR3 = "none",
parameter integer VAR16 = 1,
parameter integer VAR30 = 32,
parameter integer VAR34 = 32,
parameter integer VAR21 = 0,
parameter integer VAR33 = 1,
parameter integer VAR20 = 1,
parameter integer VAR5 = 1
)
(
input wire VAR6,
input wire VAR27,
input wire VAR38,
input wire VAR10... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/26bit/ReCodeRKOA/RKOA_OPCHANGE.v | 4,100 | module MODULE1
(
input wire [VAR16-1:0] VAR22,
input wire [VAR16-1:0] VAR15,
output reg [2*VAR16-1:0] VAR11
);
wire [1:0] VAR24;
wire [3:0] VAR14;
assign VAR24 = 2'b00;
assign VAR14 = 4'b0000;
wire [VAR16/2-1:0] VAR2;
wire [VAR16/2:0] VAR9;
wire [VAR16/2-3:0] VAR3;
wire [VAR16/2-4:0] VAR17;
reg [4*(VAR16/2)-1:0] VAR7 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai_1.v | 2,424 | module MODULE1 (
VAR12 ,
VAR6 ,
VAR9 ,
VAR8 ,
VAR7 ,
VAR10 ,
VAR1,
VAR5,
VAR2 ,
VAR4
);
output VAR12 ;
input VAR6 ;
input VAR9 ;
input VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR1;
input VAR5;
input VAR2 ;
input VAR4 ;
VAR3 VAR11 (
.VAR12(VAR12),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v | 56,935 | module MODULE1 (
input wire VAR145, input wire VAR232, input wire VAR6, input wire [31:0] VAR202, output wire VAR12, input wire [4:0] VAR9, input wire [31:0] VAR42, input wire VAR41, output wire [255:0] VAR55, output wire VAR86, input wire VAR225, input wire [255:0] VAR166, output wire [26:0] VAR248, output wire VAR14,... | mit |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_texcache.v | 10,795 | module MODULE1 #(
parameter VAR45 = 13,
parameter VAR102 = 26
) (
input VAR95,
input VAR84,
output [VAR102-1:0] VAR20,
output reg VAR36,
input VAR38,
input [63:0] VAR76,
input VAR30,
output VAR3,
input VAR17,
output VAR13,
input [VAR102-1-1:0] VAR11,
input [VAR102-1-1:0] VAR105,
input [VAR102-1-1:0] VAR48,
input [VAR10... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha.behavioral.v | 1,511 | module MODULE1 (
VAR9,
VAR14 ,
VAR7 ,
VAR12
);
output VAR9;
output VAR14 ;
input VAR7 ;
input VAR12 ;
supply1 VAR5;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR3 ;
wire VAR1;
wire VAR4 ;
and VAR13 (VAR1, VAR7, VAR12 );
buf VAR2 (VAR9 , VAR1 );
xor VAR10 (VAR4 , VAR12, VAR7 );
buf VAR11 (VAR14 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3.pp.symbol.v | 1,295 | module MODULE1 (
input VAR1 ,
input VAR3 ,
input VAR4 ,
output VAR5 ,
input VAR8 ,
input VAR2,
input VAR7,
input VAR6
);
endmodule | apache-2.0 |
Chapna/TTCache | src/cache_ctl.v | 1,801 | module MODULE1 (enable, clk, VAR26, word, VAR10,
write, VAR17, VAR8, VAR20,
rst, VAR2, VAR13, VAR6,
VAR5, valid);
input clk;
input enable;
input [0:3] VAR26;
input [0:1] word;
input VAR10;
input write;
input [0:4] VAR17;
input [0:15] VAR8;
input VAR20;
input rst;
output reg VAR2;
output reg VAR13;
output reg [0:4] VAR6... | gpl-2.0 |
ptracton/pmodacl2 | behavioral/adxl362/adxl362_spi.v | 13,798 | module MODULE1 (
VAR62, address, VAR63, VAR16, write, VAR48,
VAR37, VAR64, VAR21, VAR12, VAR51, VAR10, rst
) ;
input wire VAR37;
input wire VAR64;
input wire VAR21;
output reg VAR62;
input wire VAR12;
output reg [5:0] address;
output reg [7:0] VAR63;
input wire [7:0] VAR51;
input wire [15:0] VAR10;
output reg VAR16;
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn_1.v | 2,444 | module MODULE2 (
VAR2,
VAR4 ,
VAR8 ,
VAR10 ,
VAR6 ,
VAR7 ,
VAR5 ,
VAR1
);
input VAR2;
input VAR4 ;
input VAR8 ;
output VAR10 ;
input VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR1 ;
VAR9 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODU... | apache-2.0 |
bunnie/novena-sd-fpga | novena-sd.srcs/sources_1/imports/romulator_ddr3.v | 36,309 | module MODULE1(
input wire clk,
input wire VAR61,
input wire VAR4,
input wire VAR64,
input wire VAR134,
output wire VAR46,
input wire VAR127,
input wire VAR87,
input wire [7:0] VAR122,
output wire [7:0] VAR103,
output wire VAR73,
input wire VAR114,
output wire VAR93,
output wire VAR31,
output reg VAR31,
output wire [2:... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_16/bsg_async/bsg_sync_sync.v | 3,615 | \
module MODULE2 \
(input VAR11 \
,input [VAR2-1:0] VAR19 \
,output [VAR2-1:0] VAR5 ); \
\
genvar VAR17; \
\
logic [VAR2-1:0] VAR12; \
\
assign VAR5 = VAR12; \
\
for (VAR17 = 0; VAR17 < VAR2; VAR17 = VAR17 + 1) \
begin : VAR4 \
VAR8 VAR6 \
(.VAR1 (VAR19[VAR17]) \
,.VAR15 (VAR11) \
,.VAR22 (1'b0) \
,.VAR14 (1'b0) \
,.VA... | bsd-3-clause |
marmolejo/zet | cores/ps2/rtl/ps2_mouse_datain.v | 5,048 | module MODULE1 (
input clk,
input reset,
input VAR14,
input VAR13,
input VAR10,
input VAR2,
input VAR9,
output reg [7:0] VAR12,
output reg VAR11 );
localparam VAR1 = 3'h0,
VAR15 = 3'h1,
VAR4 = 3'h2,
VAR16 = 3'h3,
VAR7 = 3'h4;
reg [3:0] VAR5;
reg [7:0] VAR6;
reg [2:0] VAR8;
reg [2:0] VAR3;
always @(posedge clk) begin
if... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fah/sky130_fd_sc_ls__fah.blackbox.v | 1,297 | module MODULE1 (
VAR4,
VAR5 ,
VAR7 ,
VAR1 ,
VAR2
);
output VAR4;
output VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR2 ;
supply1 VAR8;
supply0 VAR9;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/verilog/ANN_dadd_64ns_64ns_64_5_full_dsp.v | 1,912 | module MODULE1
VAR6 = 7,
VAR18 = 5,
VAR25 = 64,
VAR2 = 64,
VAR1 = 64
)(
input wire clk,
input wire reset,
input wire VAR24,
input wire [VAR25-1:0] VAR10,
input wire [VAR2-1:0] VAR4,
output wire [VAR1-1:0] dout
);
wire VAR27;
wire VAR21;
wire VAR20;
wire [63:0] VAR5;
wire VAR7;
wire [63:0] VAR13;
wire VAR12;
wire [63:0]... | gpl-3.0 |
disaderp/automatic-chainsaw | GPU/Font_ROM.v | 132,545 | module MODULE1(
input clk,
input [11:0] address,
output reg [7:0] out);
reg [7:0] MODULE1 [4095:0];
VAR1 begin : VAR2
MODULE1[0] <= 8'b00000000;
MODULE1[1] <= 8'b00000000;
MODULE1[2] <= 8'b00000000;
MODULE1[3] <= 8'b00000000;
MODULE1[4] <= 8'b00000000;
MODULE1[5] <= 8'b00000000;
MODULE1[6] <= 8'b00000000;
MODULE1[7] <=... | gpl-3.0 |
jameshegarty/rigel | generators/hardfloat/source/iNToRecFN.v | 5,334 | module
MODULE1#(parameter VAR19 = 1) (VAR1, in, VAR17, VAR15, VAR7, VAR8);
localparam VAR13 = VAR9(VAR19) + 1;
input VAR1;
input [(VAR19 - 1):0] in;
output VAR17;
output VAR15;
output signed [(VAR13 + 1):0] VAR7;
output [VAR19:0] VAR8;
localparam VAR10 = 1<<(VAR13 - 1);
assign VAR15 = VAR1 && in[VAR19 - 1];
wire [(VAR1... | mit |
benreynwar/fpga-sdrlib | verilog/fft/qa_stage.v | 5,098 | module MODULE1
parameter VAR60 = 32,
parameter VAR27 = 1
)
(
input wire clk,
input wire VAR63,
input wire [VAR60-1:0] VAR15,
input wire VAR1,
input wire [VAR27-1:0] VAR80,
input wire [VAR29-1:0] VAR21,
input wire VAR39,
output wire [VAR60-1:0] VAR19,
output wire VAR12,
output wire [VAR27-1:0] VAR54,
output wire [VAR29-... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_19.v | 16,187 | module MODULE1 (
clk,
reset,
VAR112,
VAR125,
VAR68,
VAR44,
VAR67
);
parameter VAR88 = 18;
parameter VAR69 = 19;
parameter VAR41 = 10;
localparam VAR129 = 25;
input clk;
input reset;
input VAR112;
input VAR125;
input [VAR88-1:0] VAR68; output VAR44;
output [VAR88-1:0] VAR67;
localparam VAR2 = 18; localparam VAR75 = 36; ... | mit |
orbancedric/DeepGate | other/convPrototype/DeepGATE_top.v | 6,059 | module MODULE1(
input clk,
input VAR1,
input VAR57,
output wire [7:0]VAR46,
input VAR60,
input VAR39,
input VAR14,
output reg VAR82,
output VAR20,
input VAR79,
input VAR75,
input VAR71,
output [3:0] VAR44,
input VAR3, output VAR54, input VAR77,
output VAR33,
output VAR66,
output VAR7,
output VAR69,
output VAR65,
output... | gpl-3.0 |
alexforencich/xfcp | lib/eth/rtl/arp.v | 17,469 | module MODULE1 #
(
parameter VAR123 = 8,
parameter VAR48 = (VAR123>8),
parameter VAR20 = (VAR123/8),
parameter VAR9 = 9,
parameter VAR31 = 4,
parameter VAR119 = 125000000*2,
parameter VAR101 = 125000000*30
)
(
input wire clk,
input wire rst,
input wire VAR24,
output wire VAR38,
input wire [47:0] VAR84,
input wire [47:0... | mit |
jotego/jt12 | hdl/jt03.v | 3,542 | module MODULE1(
input rst, input clk, input VAR36, input [7:0] din,
input addr,
input VAR37,
input VAR8,
output [7:0] dout,
output VAR7,
input [7:0] VAR9,
input [7:0] VAR1,
output [ 7:0] VAR10,
output [ 7:0] VAR13,
output [ 7:0] VAR5,
output signed [15:0] VAR19,
output [ 9:0] VAR4,
output signed [15:0] VAR32,
output VA... | gpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemTextures/MemTextures_stub.v | 1,252 | module MODULE1(VAR2, clk, VAR1)
;
input [7:0]VAR2;
input clk;
output [91:0]VAR1;
endmodule | gpl-3.0 |
hakehuang/pycpld | ips/ip/spi_master/spi_ctrl.v | 1,515 | module MODULE1(
clk,VAR5,VAR18,VAR7,VAR2,VAR11,VAR19,VAR13,VAR3,VAR17,VAR16
);
input clk,VAR5,VAR2;
input VAR3;
input VAR17;
output VAR18,VAR7,VAR11;
output VAR16;
input VAR19;
input VAR13;
wire VAR12;
wire VAR16;
reg VAR4;
reg VAR11;
reg[7:0] VAR8;
reg[7:0] VAR9;
reg VAR15;
always @(posedge clk or negedge VAR5) begin
... | mit |
Digilent/vivado-library | ip/Pmods/Pmod_Bridge_v1_1/src/pmod_concat.v | 7,190 | module MODULE1
(
VAR34,
VAR18,
VAR50,
VAR25,
VAR57,
VAR17,
VAR26,
VAR68,
VAR71,
VAR48,
VAR9,
VAR51,
VAR45,
VAR54,
VAR13,
VAR61,
VAR6,
VAR59,
VAR67,
VAR64,
VAR1,
VAR62,
VAR30,
VAR23,
VAR3,
VAR66,
VAR24,
VAR40,
VAR10,
VAR52,
VAR2,
VAR55,
VAR43,
VAR63,
VAR8,
VAR42,
VAR29,
VAR27,
VAR65,
VAR56,
VAR39,
VAR46,
VAR32,
VAR22,
V... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab3/array_io_prj/solution3/syn/verilog/array_io.v | 47,456 | module MODULE1 (
VAR236,
VAR13,
VAR61,
VAR54,
VAR64,
VAR171,
VAR233,
VAR162,
VAR111,
VAR222,
VAR113,
VAR9,
VAR79,
VAR51,
VAR144,
VAR133,
VAR183,
VAR52,
VAR204,
VAR169,
VAR174,
VAR119,
VAR116,
VAR63,
VAR197,
VAR188,
VAR24,
VAR47,
VAR143,
VAR91
);
parameter VAR115 = 12'd1;
parameter VAR165 = 12'd2;
parameter VAR201 = 12'... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi_1.v | 2,450 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR12 ,
VAR6 ,
VAR5 ,
VAR10 ,
VAR11,
VAR4,
VAR1 ,
VAR2
);
output VAR8 ;
input VAR3 ;
input VAR12 ;
input VAR6 ;
input VAR5 ;
input VAR10 ;
input VAR11;
input VAR4;
input VAR1 ;
input VAR2 ;
VAR7 VAR9 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/RAM16_s36_s36_altera.v | 11,211 | module MODULE1 (
VAR62,
VAR33,
VAR41,
VAR37,
VAR46,
VAR13,
VAR24,
VAR51,
VAR28,
VAR27,
VAR5,
VAR60);
input VAR62;
input VAR33;
input [8:0] VAR41;
input [8:0] VAR37;
input VAR46;
input VAR13;
input [31:0] VAR24;
input [31:0] VAR51;
input VAR28;
input VAR27;
output [31:0] VAR5;
output [31:0] VAR60;
tri0 VAR62;
tri0 VAR33... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o.symbol.v | 1,375 | module MODULE1 (
input VAR6,
input VAR4,
input VAR9,
input VAR1,
output VAR2
);
supply1 VAR7;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
oblivioncth/DE0-Verilog-Processor | src/reg_8x16bit.v | 4,771 | module MODULE1(
VAR43,
VAR22,
reset,
VAR4,
VAR32,
VAR30,
VAR13,
VAR55,
VAR72,
VAR29,
VAR1,
VAR71,
VAR40,
VAR12,
VAR26,
VAR31,
VAR7
);
input wire VAR43;
input wire VAR22;
input wire reset;
input wire [2:0] VAR4;
input wire [2:0] VAR32;
input wire [15:0] VAR30;
input wire [2:0] VAR13;
output wire [15:0] VAR55;
output wir... | mit |
csail-csg/recycle-bsv-lib | src/v/EHRU_2.v | 2,003 | module MODULE1 (
VAR11,
VAR10,
VAR6,
VAR12,
VAR9,
VAR4,
VAR3
);
parameter VAR8 = 1;
parameter VAR1 = 0;
input VAR11;
output [VAR8-1:0] VAR10;
input [VAR8-1:0] VAR6;
input VAR12;
output [VAR8-1:0] VAR9;
input [VAR8-1:0] VAR4;
input VAR3;
reg [VAR8-1:0] VAR7;
wire [VAR8-1:0] VAR13;
wire [VAR8-1:0] VAR5;
wire [VAR8-1:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_pg/sky130_fd_sc_hs__udp_dff_pr_pp_pg.symbol.v | 1,430 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR6,
input VAR2 ,
input VAR4 ,
input VAR1
);
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/standard_cc_module.v | 9,894 | module MODULE1
(
VAR10,
VAR18,
VAR5,
VAR9,
VAR8
);
output VAR10;
output VAR18;
input VAR5;
input VAR9;
input VAR8;
reg VAR10;
reg VAR18;
reg [0:7] VAR2;
reg [0:5] VAR15;
reg VAR11;
reg [0:11] VAR7;
reg VAR1;
reg [0:14] VAR3;
reg VAR17;
reg [0:10] VAR16;
reg VAR19;
wire VAR14;
wire VAR4;
wire VAR6;
wire VAR13;
always @(... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill_2.v | 1,840 | module MODULE1 (
VAR6,
VAR5,
VAR4 ,
VAR2
);
input VAR6;
input VAR5;
input VAR4 ;
input VAR2 ;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 ();
supply1 VAR6;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR2 ;
VAR1 VAR3 ();
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9361/axi_ad9361_dev_if_alt.v | 9,684 | module MODULE1 (
VAR24,
VAR50,
VAR21,
VAR51,
VAR52,
VAR64,
VAR33,
VAR62,
VAR59,
VAR19,
VAR56,
VAR15,
rst,
clk,
VAR35,
VAR5,
VAR45,
VAR7,
VAR41,
VAR9,
VAR17,
VAR53,
VAR42,
VAR65,
VAR13,
VAR67,
VAR61,
VAR39,
VAR3,
VAR55,
VAR54,
VAR12,
VAR18);
parameter VAR37 = 0;
parameter VAR40 = 0;
parameter VAR27 = "VAR30";
localparam... | gpl-3.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CORESPI/4.2.116/rtl/vlog/core/spi.v | 15,748 | module MODULE1( VAR13, VAR22, VAR36, VAR69, VAR76, VAR52, VAR80, VAR108, VAR84, VAR31,
VAR53, VAR38, VAR62, VAR29, VAR109, VAR94, VAR87, VAR104, VAR56 );
parameter VAR51 = 8;
parameter VAR2 = 4;
parameter VAR4 = 4;
parameter VAR30 = 7;
parameter VAR49 = 0;
parameter VAR54 = 0;
parameter VAR27 = 0;
parameter VAR105 = 0;... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.functional.pp.v | 1,520 | module MODULE1( VAR5, VAR7, VAR1, VAR10, VAR6, VAR19, VAR13 );
input VAR10, VAR6, VAR7, VAR5;
inout VAR19, VAR13;
output VAR1;
wire VAR15;
not VAR17( VAR15, VAR10 );
wire VAR11;
not VAR4( VAR11, VAR6 );
wire VAR16;
and VAR3( VAR16, VAR15, VAR11 );
wire VAR9;
not VAR20( VAR9, VAR7 );
wire VAR2;
not VAR8( VAR2, VAR5 );
w... | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/EXMEM_Stage.v | 6,014 | module MODULE1(
input VAR28,
input reset,
input VAR36,
input VAR48,
input VAR40,
input VAR67,
input VAR10,
input VAR38,
input VAR16, input VAR3, input VAR64,
input VAR41,
input VAR31,
input VAR44,
input VAR2,
input VAR50,
input VAR52,
input VAR51,
input VAR56,
input VAR9,
input [31:0] VAR61,
input VAR68,
input VAR43,
i... | lgpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/uart16550/uart_wb.v | 11,593 | module MODULE1 (clk, VAR5,
VAR15, VAR22, VAR3, VAR26, VAR16,
VAR17, VAR21, VAR14, VAR2, VAR13, VAR4, VAR8,
VAR1, VAR9 );
input clk;
input VAR5;
input VAR15;
input VAR22;
input VAR3;
input [3:0] VAR8;
input [VAR6-1:0] VAR16;
input [7:0] VAR21; output [7:0] VAR14;
reg [7:0] VAR14;
wire [7:0] VAR21;
reg [7:0] VAR12;
reg [... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.functional.v | 1,344 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
wire VAR1;
not VAR4 (VAR1, VAR5 );
buf VAR2 (VAR3 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a.behavioral.v | 1,930 | module MODULE1 (
VAR15 ,
VAR2 ,
VAR5 ,
VAR6 ,
VAR9 ,
VAR14,
VAR3
);
output VAR15 ;
input VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR9 ;
input VAR14;
input VAR3;
wire VAR9 VAR7 ;
wire VAR4 ;
wire VAR1;
or VAR13 (VAR7 , VAR5, VAR2 );
and VAR11 (VAR4 , VAR7, VAR6, VAR9 );
VAR12 VAR10 (VAR1, VAR4, VAR14, VAR3);
buf VAR8 (VA... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_async/bsg_async_fifo.v | 4,442 | module MODULE1 #(parameter VAR44( VAR25 )
, parameter VAR44( VAR11 )
, parameter VAR45 = 0)
(
input VAR42
, input VAR3
, input VAR41
, input [VAR11-1:0] VAR17
, output VAR38
, input VAR20
, input VAR23
, input VAR43
, output [VAR11-1:0] VAR29
, output VAR37
);
localparam VAR22 = 1 << VAR25;
logic [VAR25:0] VAR10;
logic... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3.behavioral.v | 1,396 | module MODULE1 (
VAR8,
VAR3,
VAR1,
VAR11
);
output VAR8;
input VAR3;
input VAR1;
input VAR11;
supply1 VAR2;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR5 ;
wire VAR9;
xnor VAR4 (VAR9, VAR3, VAR1, VAR11 );
buf VAR10 (VAR8 , VAR9 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_j_pack_out_gen.v | 8,543 | module MODULE1 (
VAR47, VAR43,
VAR24, VAR15,
VAR34, VAR39, VAR37, VAR68, VAR67,
VAR29, VAR23, VAR54,
clk, VAR36, VAR14, VAR17, VAR5
);
input VAR34;
input VAR39;
input VAR37;
input VAR68;
input VAR67;
input VAR29; input [3:0] VAR23; input VAR54;
output [2:0] VAR47;
output VAR43;
output [2:0] VAR24;
output VAR15;
input c... | gpl-2.0 |
theapi/de0-nano | memory/memory_init.v | 1,442 | module MODULE1(
input clk,
input reset,
output [7:0] out
);
reg [12:0] address;
reg VAR6, VAR15, VAR3;
wire [15:0] VAR14, VAR4, VAR9;
reg [15:0] VAR18;
reg [7:0] VAR13;
always @(posedge clk or posedge reset) begin
if (reset) begin
address <= 0;
VAR18 <= 16'b1111111111111111;
end else begin
address <= address + 13'd1;
V... | mit |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/ppu/ppu_vga.v | 9,365 | module MODULE1
(
input VAR9, input VAR19,
output VAR18, output VAR28, output [2:0] VAR1, output [2:0] VAR3, output [1:0] VAR10,
input [5:0] VAR33,
output [9:0] VAR27, output [9:0] VAR36, output [9:0] VAR32, output VAR8, output VAR26 );
localparam [9:0] VAR16 = 10'h280,
VAR14 = 10'h1E0;
localparam [9:0] VAR34 = 10'h100,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b.functional.pp.v | 1,998 | module MODULE1 (
VAR1 ,
VAR16 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR6,
VAR14,
VAR5 ,
VAR8
);
output VAR1 ;
input VAR16 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR6;
input VAR14;
input VAR5 ;
input VAR8 ;
wire VAR2 ;
wire VAR11 ;
wire VAR13;
not VAR10 (VAR2 , VAR16 );
nand VAR9 (VAR11 , VAR4, VAR3, VAR7, VAR2 );
VAR12 VAR15 ... | apache-2.0 |
jakubfi/mera400f | src/platform.v | 1,398 | module MODULE1(
input VAR16,
output VAR33,
input VAR22,
output VAR4,
output [7:0] VAR21,
output [7:0] VAR15,
output VAR24, VAR11, VAR17, VAR26, VAR29,
output [17:0] VAR30,
inout [15:0] VAR1,
output VAR28, VAR14, VAR25
);
localparam VAR23 = 50000000;
wire VAR8, VAR35, VAR18;
wire [0:15] VAR10;
wire [10:0] VAR32;
wire [0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai_1.v | 2,352 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR4 ,
VAR2 ,
VAR3 ,
VAR5,
VAR11,
VAR7 ,
VAR1
);
output VAR9 ;
input VAR10 ;
input VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR5;
input VAR11;
input VAR7 ;
input VAR1 ;
VAR8 VAR6 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR7(VAR7),
.... | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/jasons_v/QM_FIR.v | 6,536 | module MODULE1(
VAR11, VAR27, VAR12, VAR2, VAR16, VAR13,
VAR20,
VAR25, VAR18, VAR29, VAR8, VAR31, VAR1, VAR14, VAR32,
VAR23
);
parameter VAR9 = 16;
parameter VAR28 = 8;
parameter VAR39 = 32;
output signed [(VAR9-1):0] VAR11, VAR27, VAR12;
output signed [(VAR9-1):0] VAR2, VAR16, VAR13;
output VAR20;
input VAR25;
input V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15.pp.symbol.v | 1,322 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR6 ,
input VAR2,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4/sky130_fd_sc_hs__nor4.functional.v | 1,759 | module MODULE1 (
VAR6,
VAR11,
VAR1 ,
VAR13 ,
VAR10 ,
VAR8 ,
VAR7
);
input VAR6;
input VAR11;
output VAR1 ;
input VAR13 ;
input VAR10 ;
input VAR8 ;
input VAR7 ;
wire VAR9 ;
wire VAR5;
nor VAR4 (VAR9 , VAR13, VAR10, VAR8, VAR7 );
VAR12 VAR3 (VAR5, VAR9, VAR6, VAR11);
buf VAR2 (VAR1 , VAR5 );
endmodule | apache-2.0 |
argonnexraydetector/RoachFirmPy | ANLYellowBlocks/mkid_dacadc_4x/ise/mkiddac/mkid_dac_4x.v | 26,818 | module MODULE1(
input VAR124, input VAR139,
output VAR102, output VAR150,
output VAR155,
output VAR142,
output VAR103,
output VAR84,
output VAR37,
output VAR169,
output [15:0] VAR44, output [15:0] VAR77,
output [15:0] VAR157,
output [15:0] VAR83,
output VAR19,
output VAR162,
output VAR152,
output VAR45,
output VAR50,
i... | gpl-2.0 |
AquarHEAD/stopwatch | src/calc.v | 1,314 | module MODULE1(
input wire clk,
input wire VAR5, VAR13,
input wire VAR9, VAR12,
input wire VAR4, input wire[3:0] VAR6,
output wire[3:0] VAR11,
output wire[7:0] VAR8,
output wire VAR2,
output wire VAR3,
output wire VAR1,
output wire VAR10);
reg[15:0] VAR7; | mit |
jefg89/proyecto_final_prototipado | ProyectoFinal/SOC/synthesis/submodules/SoC_onchip_memory2_0.v | 2,916 | module MODULE1 (
address,
VAR27,
VAR29,
clk,
VAR19,
reset,
VAR17,
write,
VAR1,
VAR11
)
;
parameter VAR3 = "MODULE1.VAR4";
output [ 31: 0] VAR11;
input [ 14: 0] address;
input [ 3: 0] VAR27;
input VAR29;
input clk;
input VAR19;
input reset;
input VAR17;
input write;
input [ 31: 0] VAR1;
wire VAR14;
wire [ 31: 0] VAR11;
... | gpl-2.0 |
rakeshkadamati/MIPS-32-Bit-Verilog | alu.v | 1,838 | module MODULE1(VAR15,VAR19,VAR12,VAR11,VAR13,VAR2,clk);
input clk;
input [5:0] VAR15, VAR19;
input [31:0] VAR12, VAR11;
output [31:0] VAR13; reg [31:0] VAR13;
output VAR2;
reg VAR2;
wire [31:0] sum, VAR16, VAR3, VAR6;
VAR9 VAR1(VAR12,VAR11,VAR17,sum,1'b0);
VAR4 VAR10(VAR12,VAR11,VAR18,VAR16,1'b0);
VAR14 VAR5(VAR12,VAR1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_2.functional.pp.v | 1,386 | module MODULE1( VAR15, VAR14, VAR17, VAR13, VAR6, VAR12 );
input VAR13, VAR17, VAR15;
inout VAR6, VAR12;
output VAR14;
wire VAR16;
not VAR4( VAR16, VAR13 );
wire VAR2;
not VAR11( VAR2, VAR15 );
wire VAR10;
and VAR8( VAR10, VAR16, VAR2 );
wire VAR9;
not VAR1( VAR9, VAR17 );
wire VAR7;
and VAR3( VAR7, VAR9, VAR2 );
or VA... | apache-2.0 |
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