repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/saed_90/bsg_mem/bsg_mem_1r1w_sync.v | 3,268 | if (VAR44 == VAR33 && VAR12 == VAR41) \
begin: VAR7 \
VAR15 VAR43 \
(.VAR35 (VAR18) \
,.VAR10 (1'b0) \
,.VAR13 (1'b0) \
,.VAR25 (VAR26) \
,.VAR28 (VAR29) \
,.VAR38 (VAR32) \
,.VAR23 (~VAR36) \
,.VAR19 (1'b0) \
,.VAR21 (VAR5) \
,.VAR37 (VAR34) \
); \
end
module MODULE1 #(parameter VAR8(VAR12)
,parameter VAR8(VAR44)
,par... | bsd-3-clause |
alexforencich/verilog-ethernet | example/ML605/fpga_rgmii/rtl/fpga.v | 6,122 | module MODULE1 (
input wire VAR4,
input wire VAR25,
input wire reset,
input wire VAR96,
input wire VAR66,
input wire VAR39,
input wire VAR74,
input wire VAR76,
input wire [7:0] VAR84,
output wire VAR113,
output wire VAR67,
output wire VAR88,
output wire VAR40,
output wire VAR1,
output wire [7:0] VAR73,
input wire VAR11... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v | 18,798 | module MODULE1
VAR30 = 2,
VAR8 = 3,
VAR18 = 1,
VAR5 = 4
)
(
VAR6,
VAR28,
VAR23,
VAR20,
VAR14,
VAR11,
VAR33,
VAR1,
VAR19,
VAR32
);
localparam integer VAR21 = 2**VAR5; localparam VAR26 = 2;
localparam VAR22 = 2.5;
input VAR6;
input VAR28;
input [VAR5-1:0] VAR23;
input [VAR8-1:0] VAR20;
input [4:0] VAR14;
input [VAR18-1:0... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_pd_top.v | 16,205 | module MODULE1 #
(
parameter VAR53 = 100, parameter VAR33 = 3, parameter VAR3 = 8, parameter VAR34 = 16, parameter VAR73 = "VAR1", parameter VAR60 = 8, parameter VAR20 = "VAR11", parameter VAR32 = "VAR59", parameter VAR68 = "VAR69" )
(
input clk,
input rst,
input VAR43, output VAR47, input VAR16, input VAR38, output re... | lgpl-3.0 |
Elphel/x393_sata | x393/axi/axibram_write.v | 11,978 | module MODULE1 #(
parameter VAR65 = 10 )(
input VAR5, input VAR14,
input [31:0] VAR88, input VAR68, output VAR74, input [11:0] VAR73, input [ 3:0] VAR12, input [ 1:0] VAR69, input [ 1:0] VAR63, input [31:0] VAR64, input VAR11, output VAR41, input [11:0] VAR25, input VAR20, input [ 3:0] VAR93, output VAR61, input VAR53,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31a/sky130_fd_sc_ls__o31a.pp.blackbox.v | 1,368 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR3,
VAR1,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR3;
input VAR1;
input VAR4 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21bo/sky130_fd_sc_ls__a21bo.symbol.v | 1,388 | module MODULE1 (
input VAR1 ,
input VAR8 ,
input VAR3,
output VAR6
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_controlFlagsOut.v | 1,886 | module MODULE1 (
address,
clk,
VAR1,
VAR3,
VAR4
)
;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input clk;
input [ 1: 0] VAR1;
input VAR3;
wire VAR6;
wire [ 1: 0] VAR5;
wire [ 1: 0] VAR2;
reg [ 31: 0] VAR4;
assign VAR6 = 1;
assign VAR2 = {2 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR3)
begin
if (VAR3... | gpl-3.0 |
Tabrizian/GuessNumber | main.v | 2,506 | module MODULE1(VAR1,VAR16,VAR22,VAR12,VAR6,VAR15,VAR17,reset,VAR20,VAR18,VAR19,VAR23); input VAR1, VAR16, VAR22, VAR12, VAR6,reset;
reg[0:6] VAR5,VAR14,VAR9,VAR13,VAR24,b1,VAR11,VAR10,VAR4;
reg[0:3] VAR2,VAR21;
output reg VAR15,VAR17;
output reg VAR20,VAR18,VAR19;
reg VAR8,VAR7;
reg [0:3] VAR3;
output reg [0:3] VAR23; | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat.v | 25,216 | module MODULE1(
VAR75,
VAR20,
VAR106 ,
VAR104 ,
VAR62 ,
VAR21 ,
VAR230 ,
VAR36 ,
VAR142 ,
VAR84 ,
VAR46 ,
VAR234 ,
VAR196,
VAR171,
VAR9,
VAR216,
VAR5,
VAR176,
VAR45,
VAR12,
VAR26,
VAR113,
VAR148,
VAR145,
VAR193,
VAR10,
VAR38,
VAR92,
VAR172,
VAR175,
VAR76,
VAR22,
VAR197,
VAR35,
o0 ,
o1 ,
o2 ,
o3 ,
o4 ,
o5 ,
o6 ,
o7 ,
VA... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/clk_gen/clk_gen.v | 3,911 | module MODULE1
(
input VAR4,
output VAR1,
input reset
);
VAR2 VAR3
(
.VAR4(VAR4),
.VAR1(VAR1),
.reset(reset)
);
endmodule | gpl-3.0 |
Sponk/mips86 | src/opcode-buffer/OpcodeBuffer.v | 1,196 | module MODULE1
(
input wire clk,
input wire reset,
input wire [VAR3-1:0] VAR2,
input wire VAR7,
input wire [7:0] VAR10,
input wire VAR4,
output reg VAR9,
output reg [VAR11-1:0] VAR1,
output reg [VAR3-1:0] address,
output reg request
);
reg [7:0] VAR6[0:3];
reg [3:0] counter = 0;
reg [3:0] VAR5 = 0;
integer VAR8;
begin
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_1.functional.v | 1,585 | module MODULE1( VAR8, VAR4, VAR14, VAR13, VAR5 );
input VAR14, VAR8, VAR13, VAR5;
output VAR4;
wire VAR1;
not VAR2( VAR1, VAR14 );
wire VAR3;
not VAR7( VAR3, VAR13 );
wire VAR10;
not VAR9( VAR10, VAR5 );
wire VAR18;
and VAR17( VAR18, VAR1, VAR3, VAR10 );
wire VAR12;
not VAR11( VAR12, VAR8 );
wire VAR16;
and VAR6( VAR16... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill_diode/sky130_fd_sc_ls__fill_diode_2.v | 1,901 | module MODULE1 (
VAR1,
VAR3,
VAR4 ,
VAR5
);
input VAR1;
input VAR3;
input VAR4 ;
input VAR5 ;
VAR2 VAR6 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
VAR2 VAR6 ();
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_time.v | 1,911 | module MODULE1 (VAR13, reset, enable, VAR2, VAR14, VAR15);
parameter VAR17 = VAR22;
parameter VAR8 = 1;
parameter VAR19 = VAR3;
parameter VAR16 = VAR7;
parameter VAR21 = VAR12;
parameter VAR18 = VAR6;
parameter VAR11 = VAR1;
parameter VAR5 = VAR24;
parameter VAR20 = VAR10;
input VAR13, reset, enable;
input VAR2;
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtp/sky130_fd_sc_hd__dlrtp.pp.symbol.v | 1,434 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR7,
input VAR4 ,
input VAR6 ,
input VAR1 ,
input VAR8 ,
input VAR5
);
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/elink/dv/emesh_monitor.v | 2,013 | module MODULE1(
clk, reset, VAR6, VAR4, VAR1, VAR11,
VAR13, VAR16, VAR14, VAR9,
VAR2, VAR7
);
parameter VAR15 = 32;
parameter VAR3 = 32;
parameter VAR8 = "VAR10";
input clk;
input reset;
input VAR6;
input [31:0] VAR4;
input VAR1;
input VAR11;
input [1:0] VAR13;
input [3:0] VAR16;
input [VAR15-1:0] VAR14;
input [VAR3-1:... | gpl-3.0 |
hydai/Verilog-Practice | template/Mealy.v | 1,699 | module MODULE1 (
output out,
input in,
input clk,
input VAR1
);
parameter VAR2 = 2'b00;
parameter VAR4 = 2'b01;
parameter VAR6 = 2'b10;
parameter VAR5 = 2'b11;
reg state, VAR3;
reg out;
always @(posedge clk or negedge VAR1) begin
if (!VAR1) begin
state <= 0;
end else begin
state <= VAR3;
end
end
always @(*) begin
case(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufinv/sky130_fd_sc_ls__bufinv.functional.pp.v | 1,782 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR8,
VAR4,
VAR11 ,
VAR7
);
output VAR10 ;
input VAR6 ;
input VAR8;
input VAR4;
input VAR11 ;
input VAR7 ;
wire VAR2 ;
wire VAR1;
not VAR9 (VAR2 , VAR6 );
VAR5 VAR3 (VAR1, VAR2, VAR8, VAR4);
buf VAR12 (VAR10 , VAR1 );
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bwjx1c64a/DecWOp1.v | 15,655 | module MODULE1(
VAR39,
VAR100,
VAR105,
VAR113,
VAR46,
VAR47,
VAR26
);
parameter VAR12 = 1;
input VAR39;
input[23:0] VAR100;
output[6:0] VAR105;
output[6:0] VAR113;
output[6:0] VAR46;
output[31:0] VAR47;
output[7:0] VAR26;
reg[6:0] VAR80;
reg[6:0] VAR106;
reg[6:0] VAR35; reg[31:0] VAR69; reg[7:0] VAR90;
reg[7:0] VAR13;
... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/submidRecursiveKOA2.v | 5,303 | module MODULE1
(
input wire clk,
input wire [VAR29-1:0] VAR27,
input wire [VAR29-1:0] VAR19,
output reg [2*VAR29-1:0] VAR15
);
wire [1:0] VAR7;
wire [3:0] VAR11;
assign VAR7 = 2'b00;
assign VAR11 = 4'b0000;
wire [VAR29/2-1:0] VAR5;
wire [VAR29/2:0] VAR26;
wire [VAR29/2-3:0] VAR10;
wire [VAR29/2-4:0] VAR20;
reg [4*(VAR2... | gpl-3.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_gpu.v | 11,367 | module MODULE1 (
VAR20, VAR63, VAR5, VAR49,
VAR28, VAR6, VAR60, VAR72,
VAR15, VAR19,
VAR62,
VAR7,
VAR29, VAR25, VAR21,
VAR36, VAR4 );
output VAR20; output VAR63; output VAR5; output VAR49;
output [VAR33:0] VAR28; output [15:0] VAR6; output VAR60; output VAR72;
input VAR15; input VAR19;
input [VAR37:0] VAR62;
input [2:0... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3.pp.symbol.v | 1,314 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR8 ,
output VAR2 ,
input VAR3 ,
input VAR7,
input VAR5,
input VAR6
);
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/tlu/tlu_controller_core.v | 25,409 | module MODULE1
parameter VAR165 = 16,
parameter VAR185 = 8, parameter VAR196 = 17, parameter VAR129 = 8,
parameter VAR116 = 32
)
(
input wire VAR90,
input wire VAR186,
input wire [VAR165-1:0] VAR68,
input wire [7:0] VAR35,
input wire VAR144,
input wire VAR33,
output reg [7:0] VAR14,
input wire VAR170,
input wire VAR57,... | bsd-3-clause |
Ribeiro/sd2snes | verilog/sd2snes_cx4/main.v | 19,061 | module MODULE1(
input VAR23,
input [23:0] VAR169,
input VAR205,
input VAR56,
input VAR241,
inout [7:0] VAR202,
input VAR97,
input VAR287,
output VAR82,
output VAR79,
output VAR304,
input VAR158,
input [7:0] VAR16,
input VAR200,
input VAR89,
inout [15:0] VAR176,
output [22:0] VAR204,
output VAR86,
output VAR95,
output V... | gpl-2.0 |
chriswynnyk/american-put-verilog | american_put_stratix/src/fp_add_v1.v | 146,957 | module MODULE1
(
VAR6,
VAR5,
VAR10,
VAR2,
VAR7,
VAR1) ;
input VAR6;
input VAR5;
input VAR10;
input [54:0] VAR2;
input [5:0] VAR7;
output [54:0] VAR1;
reg [54:0] VAR11;
wire VAR3;
wire [31:0] VAR4;
wire [384:0] VAR9;
wire [5:0] VAR8; | apache-2.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/timer.v | 1,290 | module MODULE1 #(
parameter VAR1 = 33, parameter VAR3 = 12507 )
(
input VAR2, input VAR7,
output reg VAR6 );
reg [VAR1-1:0] VAR4;
reg VAR5;
wire VAR8;
assign VAR8 = VAR4[VAR1-1];
always @(posedge VAR2)
VAR4 <= VAR7 ? 0 : (VAR4 + VAR3);
always @(posedge VAR2)
VAR5 <= VAR7 ? 1'b0 : VAR8;
always @(posedge VAR2)
VAR6 <= VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3/sky130_fd_sc_hdll__nor3.symbol.v | 1,316 | module MODULE1 (
input VAR6,
input VAR3,
input VAR2,
output VAR5
);
supply1 VAR4;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31ai/sky130_fd_sc_hd__o31ai.symbol.v | 1,354 | module MODULE1 (
input VAR5,
input VAR4,
input VAR6,
input VAR7,
output VAR9
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | TGC_ROM_bb.v | 5,063 | module MODULE1 (
address,
VAR2,
VAR1);
input [6:0] address;
input VAR2;
output [7:0] VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4_2.v | 2,242 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR11 ,
VAR1 ,
VAR5 ,
VAR2,
VAR9,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR7 ;
input VAR11 ;
input VAR1 ;
input VAR5 ;
input VAR2;
input VAR9;
input VAR6 ;
input VAR8 ;
VAR3 VAR10 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR... | apache-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_experimental/solution1/impl/ip/hdl/verilog/contact_discovery_AXILiteS_s_axi.v | 22,975 | module MODULE1
VAR10 = 7,
VAR51 = 32
)(
input wire VAR1,
input wire VAR81,
input wire VAR40,
input wire [VAR10-1:0] VAR27,
input wire VAR14,
output wire VAR69,
input wire [VAR51-1:0] VAR62,
input wire [VAR51/8-1:0] VAR98,
input wire VAR63,
output wire VAR6,
output wire [1:0] VAR96,
output wire VAR25,
input wire VAR20,
... | gpl-3.0 |
dachdecker2/icoboard_ws2812b_display | top.v | 11,655 | module MODULE1 (
input VAR3,
VAR61, VAR97,
VAR58, VAR50, VAR44, VAR23,
output reg VAR83, VAR110, VAR87, VAR52, VAR91,
VAR120, VAR76, VAR122, VAR6,
VAR60, VAR35, VAR71, VAR134,
output [15:0] VAR119
);
/* wire [15:0] VAR84;
wire [15:0] VAR90;
wire [15:0] VAR75;
VAR89 #(
.VAR46(6'VAR85 101001),
.VAR54 (1'VAR85 0)
) VAR66 ... | gpl-3.0 |
hhuang25/uwaterloo_ece224 | ANT - Copy/button_pio.v | 1,793 | module MODULE1 (
address,
clk,
VAR6,
VAR5,
VAR2
)
;
output [ 3: 0] VAR2;
input [ 1: 0] address;
input clk;
input [ 3: 0] VAR6;
input VAR5;
wire VAR4;
wire [ 3: 0] VAR3;
wire [ 3: 0] VAR1;
reg [ 3: 0] VAR2;
assign VAR4 = 1;
assign VAR1 = {4 {(address == 0)}} & VAR3;
always @(posedge clk or negedge VAR5)
begin
if (VAR5 =... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_dp_maca_l.v | 4,144 | module MODULE1(
VAR16, VAR21, VAR24,
VAR5, VAR3, VAR13,
VAR31, VAR8, VAR10, VAR23,
VAR15, VAR26
);
output [129:0] VAR16; output VAR21;
output VAR24;
input VAR5; input VAR3; input VAR13; input VAR31; input VAR8;
input [129:0] VAR10;
input VAR23;
input VAR15;
input VAR26;
wire VAR14;
wire [129:0] VAR25;
wire [129:0] VAR2... | gpl-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T25-uart-rx/baudgen.v | 1,722 | module MODULE1
parameter VAR6 = VAR2
)
(input wire clk,
input wire VAR7,
output wire VAR5);
localparam VAR1 = VAR3(VAR6);
reg [VAR1-1:0] VAR4 = 0;
always @(posedge clk)
if (VAR7)
VAR4 <= (VAR4 == VAR6 - 1) ? 0 : VAR4 + 1;
else
VAR4 <= VAR6 - 1;
assign VAR5 = (VAR4 == 0) ? VAR7 : 0;
endmodule | gpl-2.0 |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | hex7seg.v | 3,123 | module MODULE1 (
input [3:0] VAR1,
output reg [6:0] VAR2
);
always @(*) begin
case(VAR1)
4'h0: VAR2 = 7'b1000000;
4'h1: VAR2 = 7'b1111001;
4'h2: VAR2 = 7'b0100100;
4'h3: VAR2 = 7'b0110000;
4'h4: VAR2 = 7'b0011001;
4'h5: VAR2 = 7'b0010010;
4'h6: VAR2 = 7'b0000010;
4'h7: VAR2 = 7'b1111000;
4'h8: VAR2 = 7'b0000000;
4'h9: ... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/ucb_bus_out.v | 4,469 | module MODULE1 (
VAR10, VAR16, VAR2,
clk, VAR3, VAR17, VAR11, VAR6, VAR20
);
parameter VAR18 = 32;
parameter VAR14 = 64;
input clk;
input VAR3;
output VAR10;
output [VAR18-1:0] VAR16;
input VAR17;
output VAR2;
input [VAR14+63:0] VAR11;
input [(VAR14+64)/VAR18-1:0] VAR6;
input VAR20;
wire VAR19;
wire [(VAR14+64)/VAR18-1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkinvkapwr/sky130_fd_sc_hd__lpflow_clkinvkapwr_2.v | 2,261 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR1,
VAR2 ,
VAR8 ,
VAR6 ,
VAR9
);
output VAR5 ;
input VAR3 ;
input VAR1;
input VAR2 ;
input VAR8 ;
input VAR6 ;
input VAR9 ;
VAR7 VAR4 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR5,
VAR3
);
output VAR5;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2_0.v | 2,086 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR2 ,
VAR9,
VAR3,
VAR8 ,
VAR1
);
output VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR9;
input VAR3;
input VAR8 ;
input VAR1 ;
VAR5 VAR4 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR6,
VAR7,
VAR2
);
output VAR6;
... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | whole_system/whole_system.v | 8,274 | module MODULE1( clk,
rst
);
input clk;
input rst;
wire VAR28; wire VAR53;
wire VAR35; wire VAR5; wire [3:0] VAR29;
wire [3:0] VAR2;
wire [15:0] VAR15;
wire [1:0] VAR32;
wire [1:0] VAR45;
wire VAR54; wire VAR30;
wire VAR14; wire VAR24; wire [3:0] VAR12;
wire [3:0] VAR20;
wire [15:0] VAR37;
wire [1:0] VAR1;
wire [1:0] VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b.blackbox.v | 1,303 | module MODULE1 (
VAR6 ,
VAR2,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR2;
input VAR8 ;
input VAR4 ;
supply1 VAR7;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tap/sky130_fd_sc_hdll__tap_1.v | 1,893 | module MODULE2 (
VAR1,
VAR4,
VAR3 ,
VAR5
);
input VAR1;
input VAR4;
input VAR3 ;
input VAR5 ;
VAR2 VAR6 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
VAR2 VAR6 ();
endmodule | apache-2.0 |
bruskajp/EE-316 | Project2/Vivado_NexysBoard/project_2b/project_2b.srcs/sources_1/ip/blk_mem_LUT/blk_mem_LUT_stub.v | 1,304 | module MODULE1(VAR4, VAR3, VAR1, VAR2)
;
input VAR4;
input VAR3;
input [3:0]VAR1;
output [15:0]VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222o/sky130_fd_sc_ls__a222o.blackbox.v | 1,419 | module MODULE1 (
VAR6 ,
VAR2,
VAR9,
VAR1,
VAR5,
VAR3,
VAR11
);
output VAR6 ;
input VAR2;
input VAR9;
input VAR1;
input VAR5;
input VAR3;
input VAR11;
supply1 VAR7;
supply0 VAR10;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sf_camera/rtl/wb_sf_camera.v | 14,963 | module MODULE1 #(
parameter VAR18 = 12
)(
input clk,
input rst,
output [31:0] VAR87,
input VAR104,
input VAR8,
input [3:0] VAR88,
input [31:0] VAR7,
input VAR102,
output reg VAR99,
output reg [31:0] VAR82,
input [31:0] VAR11,
output reg VAR112,
output VAR101,
output VAR71,
output VAR126,
output [3:0] VAR9,
output [31:0... | mit |
himansurathi/labCourseWork | VLSI lab/VLSI codes/boothMultiplier.v | 1,335 | module MODULE2(
input [3:0] VAR7,
input [3:0] VAR5,
output [7:0] VAR10,
input VAR15,
input reset
);
reg [3:0] VAR2, VAR4, VAR6;
reg VAR11;
reg [3:0] VAR12;
wire [3:0] sum, VAR9;
always @(posedge VAR15)
begin
if (reset) begin
VAR2 <= 4'b0;
VAR6 <= VAR7;
VAR4 <= VAR5;
VAR11 <= 1'b0;
VAR12 <= 3'b0;
end
else begin
case ({V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3.blackbox.v | 1,288 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_lsu.v | 7,718 | module MODULE1(
VAR10, VAR20, VAR11, VAR43, VAR41, VAR26, VAR35,
VAR16, VAR1, VAR18, VAR37, VAR45,
VAR30, VAR34, VAR13, VAR6, VAR17, VAR28,
VAR40, VAR14, VAR2, VAR39, VAR8
);
parameter VAR23 = VAR33;
parameter VAR38 = VAR22;
input [31:0] VAR10;
input [31:0] VAR20;
input [VAR42-1:0] VAR11;
input [VAR23-1:0] VAR43;
outpu... | gpl-2.0 |
ptracton/wb_soc_template | rtl/uart16550/bench/verilog/wb_mast.v | 10,947 | module MODULE1(clk, rst, VAR4, din, dout, VAR8, VAR11, sel, VAR5, ack, VAR1, VAR10);
input clk, rst;
output [31:0] VAR4;
input [31:0] din;
output [31:0] dout;
output VAR8, VAR11;
output [3:0] sel;
output VAR5;
input ack, VAR1, VAR10;
parameter VAR6 = 4096;
reg [31:0] VAR4;
reg [31:0] dout;
reg VAR8, VAR11;
reg [3:0] se... | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v2_0_bank_compare.v | 10,847 | module MODULE1 #
(parameter VAR70 = 3,
parameter VAR50 = 100,
parameter VAR36 = "8",
parameter VAR4 = 12,
parameter VAR69 = 8,
parameter VAR27 = "VAR1",
parameter VAR8 = 2,
parameter VAR72 = 4,
parameter VAR74 = 16)
(
VAR48, VAR59, VAR80, VAR76,
VAR32, VAR35, VAR12, VAR57, VAR20,
VAR46, VAR9, VAR81, VAR30, VAR34,
VAR52... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbp/sky130_fd_sc_hd__sdfbbp.symbol.v | 1,572 | module MODULE1 (
input VAR12 ,
output VAR2 ,
output VAR6 ,
input VAR11,
input VAR4 ,
input VAR5 ,
input VAR7 ,
input VAR3
);
supply1 VAR8;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn.behavioral.v | 1,314 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR8
);
output VAR3 ;
input VAR7 ;
input VAR8;
supply1 VAR5;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
notif0 VAR6 (VAR3 , VAR7, VAR8 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_rxeq_scan.v | 11,034 | module MODULE1
(
input VAR35,
input VAR11,
input [ 2:0] VAR15,
input VAR36,
input [ 3:0] VAR17,
input [17:0] VAR30,
input VAR1,
input [ 5:0] VAR16,
input [ 5:0] VAR5,
output VAR4,
output [17:0] VAR12,
output VAR22,
output VAR26,
output VAR21
);
reg [ 2:0] VAR14;
reg VAR23;
reg [ 3:0] VAR25;
reg [17:0] VAR10;
reg VAR29;... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux4/sky130_fd_sc_hd__mux4_2.v | 2,444 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR11 ,
VAR5 ,
VAR10 ,
VAR7 ,
VAR4 ,
VAR3,
VAR2,
VAR6 ,
VAR8
);
output VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR5 ;
input VAR10 ;
input VAR7 ;
input VAR4 ;
input VAR3;
input VAR2;
input VAR6 ;
input VAR8 ;
VAR13 VAR12 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR10(VAR10)... | apache-2.0 |
olajep/oh | src/aes/hdl/table.v | 14,744 | module MODULE2 (clk, state, VAR14, VAR8, VAR12, VAR16);
input clk;
input [31:0] state;
output [31:0] VAR14, VAR8, VAR12, VAR16;
wire [7:0] b0, b1, VAR4, VAR2;
assign {b0, b1, VAR4, VAR2} = state;
MODULE1
MODULE4 (clk, b0, {VAR14[23:0], VAR14[31:24]}),
VAR11 (clk, b1, {VAR8[15:0], VAR8[31:16]}),
VAR10 (clk, VAR4, {VAR12... | mit |
AngelTerrones/ADA | rtl/ada_exception.v | 18,967 | module MODULE1(
input clk, input rst, input [4:0] VAR80, input [4:0] VAR60, input [31:0] VAR24, input VAR4, input VAR39, input VAR55, input VAR1, input VAR44, input VAR88, input VAR76, input VAR14, input VAR52, input VAR84, input VAR43, input VAR71, input VAR83, input VAR5, input [31:0] VAR8, input [31:0] VAR3, input [... | mit |
kyzhai/NUNY | src/hardware/fail_new_bb.v | 5,016 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2.pp.blackbox.v | 1,238 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR1 ,
VAR3,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR3;
input VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb.pp.symbol.v | 1,229 | module MODULE1 (
input VAR1 ,
input VAR3,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
kDaniu/miaow | src/verilog/rtl/dispatcher/allocator.v | 18,380 | module MODULE1
(
VAR129, VAR34, VAR45,
VAR115, VAR31, VAR126,
VAR138, VAR15,
VAR136, VAR67,
VAR114, VAR149,
VAR113,
clk, rst, VAR131,
VAR135,
VAR65,
VAR101,
VAR24,
VAR132, VAR50,
VAR69, VAR100,
VAR23, VAR93, VAR18,
VAR27, VAR77, VAR112,
VAR133, VAR124, VAR102,
VAR7, VAR127
);
parameter VAR5 = 6;
parameter VAR63 = 6;
pa... | bsd-3-clause |
martinmiranda14/Digitales | Lab5/ss_a_7seg.v | 1,511 | module MODULE1(
input [3:0] VAR2,
output reg [7:0] VAR1
);
always @(*) begin
case(VAR2)
4'd0: VAR1=8'b00000011;
4'd1: VAR1=8'b10011111;
4'd2: VAR1=8'b00100101;
4'd3: VAR1=8'b00001101;
4'd4: VAR1=8'b10011001;
4'd5: VAR1=8'b01001001;
4'd6: VAR1=8'b01000001;
4'd7: VAR1=8'b00011111;
4'd8: VAR1=8'b00000001;
4'd9: VAR1=8'b00... | apache-2.0 |
8l/kestrel | 2/nexys2/uxa/ps2io/T_uxa_ps2.v | 7,105 | module MODULE1;
reg VAR1;
reg VAR10;
reg VAR9;
reg VAR8;
reg VAR12;
reg VAR11;
reg [9:8] VAR3;
wire VAR2;
wire VAR5;
wire VAR4;
wire [15:0] VAR13;
VAR6 VAR7 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR13(VAR13)
);
always b... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_2.functional.pp.v | 1,168 | module MODULE1( VAR1, VAR9, VAR8, VAR11, VAR7 );
input VAR9, VAR1;
inout VAR11, VAR7;
output VAR8;
wire VAR14;
not VAR4( VAR14, VAR1 );
wire VAR2;
and VAR12( VAR2, VAR14, VAR9 );
wire VAR5;
not VAR10( VAR5, VAR9 );
wire VAR3;
and VAR13( VAR3, VAR5, VAR1 );
or VAR6( VAR8, VAR2, VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtn/sky130_fd_sc_hd__dlrtn_2.v | 2,358 | module MODULE1 (
VAR6 ,
VAR7,
VAR4 ,
VAR10 ,
VAR5 ,
VAR9 ,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR7;
input VAR4 ;
input VAR10 ;
input VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR2 ;
VAR8 VAR3 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODU... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.behavioral.v | 1,098 | module MODULE1( VAR1, VAR4 );
input VAR1;
output VAR4;
VAR2 VAR5(.VAR1(VAR1),.VAR4(VAR4));
VAR2 VAR3(.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
asicguy/gplgpu | hdl/de3d/des_state.v | 3,234 | module MODULE1
(
input VAR16,
input VAR12,
input VAR17,
input VAR4,
input VAR3,
input VAR1,
input VAR2,
input VAR18,
input VAR5,
output reg VAR13,
output reg VAR8,
output reg [5:0] VAR14
);
reg VAR10;
reg VAR9;
always @ (posedge VAR16 or negedge VAR12) begin
if (!VAR12) begin
VAR14 <= 6'b000000;
VAR13 <= 1'b0;
VAR8 <= ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32ai/sky130_fd_sc_hd__o32ai.functional.pp.v | 2,191 | module MODULE1 (
VAR16 ,
VAR5 ,
VAR12 ,
VAR17 ,
VAR7 ,
VAR9 ,
VAR15,
VAR3,
VAR19 ,
VAR1
);
output VAR16 ;
input VAR5 ;
input VAR12 ;
input VAR17 ;
input VAR7 ;
input VAR9 ;
input VAR15;
input VAR3;
input VAR19 ;
input VAR1 ;
wire VAR11 ;
wire VAR4 ;
wire VAR20 ;
wire VAR18;
nor VAR2 (VAR11 , VAR17, VAR5, VAR12 );
nor V... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cpu/sprdma.v | 4,642 | module MODULE1
(
input wire VAR8, input wire VAR11, input wire [15:0] VAR16, input wire [ 7:0] VAR10, input wire [ 7:0] VAR3, input wire VAR21, output wire VAR17, output reg [15:0] VAR15, output reg [ 7:0] VAR1, output reg VAR19 );
localparam [1:0] VAR14 = 2'h0,
VAR12 = 2'h1,
VAR7 = 2'h2;
reg [ 1:0] VAR18, VAR13; reg [... | mit |
sh-chris110/chris | FPGA/uCos/system/synthesis/submodules/system_nios2_gen2_0_cpu_mult_cell.v | 8,024 | module MODULE1 (
VAR33,
VAR1,
VAR18,
clk,
VAR6,
VAR11,
VAR21,
VAR52
)
;
output [ 31: 0] VAR11;
output [ 31: 0] VAR21;
output [ 31: 0] VAR52;
input [ 31: 0] VAR33;
input [ 31: 0] VAR1;
input VAR18;
input clk;
input VAR6;
wire [ 31: 0] VAR11;
wire [ 31: 0] VAR21;
wire [ 31: 0] VAR52;
wire VAR22;
wire [ 31: 0] VAR10;
wire... | gpl-2.0 |
freecores/tcp_socket | precompiled/server.v | 332,997 | module MODULE1(VAR27,VAR23,VAR35,VAR2,VAR49,VAR11,clk,rst,VAR6,VAR43,VAR12,VAR30,VAR10,VAR36);
integer VAR1;
real VAR53;
input [15:0] VAR27;
input [15:0] VAR23;
input VAR35;
input VAR2;
input VAR49;
input VAR11;
input clk;
input rst;
output [15:0] VAR6;
output [15:0] VAR43;
output VAR12;
output VAR30;
output VAR10;
out... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_systeminit_top.v | 19,818 | module MODULE1 #
(
parameter VAR127 = "VAR141" ,
parameter VAR108 = 1 ,
parameter VAR82 = 1 ,
parameter VAR58 = 32 ,
parameter VAR15 = "VAR86.VAR45" ,
parameter VAR128 = "VAR12.VAR45" ,
parameter VAR6 = "VAR37.VAR45" ,
parameter VAR140 = "VAR72.VAR45" ,
parameter VAR96 = 5 , parameter VAR55 = 32 , parameter VAR88 = 0 ,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi.blackbox.v | 1,411 | module MODULE1 (
VAR7 ,
VAR4,
VAR9,
VAR3,
VAR8,
VAR10
);
output VAR7 ;
input VAR4;
input VAR9;
input VAR3;
input VAR8;
input VAR10;
supply1 VAR2;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
golfit/QcmPhaseDelayBoard | DecoderSerial.v | 1,174 | module MODULE1(clk,VAR1,VAR7);
parameter VAR3=8; parameter VAR2=256;
input [VAR3-1:0] VAR1;
input clk;
reg [VAR3-1:0] VAR6, VAR4;
reg [14:0] VAR5;
output [VAR3-1:0] VAR7; | mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_arb_rd.v | 3,764 | module MODULE1(
VAR2,
VAR24,
VAR23,
VAR9,
VAR4,
VAR7,
VAR5,
VAR27,
VAR21,
VAR28,
VAR6,
VAR8,
VAR25,
VAR17,
VAR3,
VAR1,
VAR13,
VAR11,
VAR19,
VAR22
);
input VAR2, VAR24;
input [VAR14-1:0] VAR23,VAR9;
input VAR4, VAR7;
input [VAR16-1:0] VAR21, VAR28;
input [VAR10:0] VAR5, VAR27;
output reg VAR25, VAR17;
output reg [VAR26-... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_axi_tx.v | 5,928 | module MODULE1
,parameter VAR50(VAR4)
,parameter VAR50(VAR88)
,parameter VAR18=VAR41
,parameter VAR50(VAR62)
,parameter VAR50(VAR70)
,parameter VAR50(VAR25)
,parameter VAR50(VAR47)
,parameter VAR23=VAR44(VAR41)
,parameter VAR1=(VAR25>>3)
,parameter VAR69=(VAR25/VAR4)
)
(
input VAR7
,input VAR35
,input VAR33
,output log... | bsd-3-clause |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_and.v | 4,340 | module MODULE1 #
(
parameter VAR13 = "VAR8"
)
(
input wire VAR7,
input wire VAR4,
output wire VAR1
);
generate
if ( VAR13 == "VAR12" ) begin : VAR3
assign VAR1 = VAR7 & VAR4;
end else begin : VAR10
VAR5 VAR6
(
.VAR9 (VAR1),
.VAR11 (VAR7),
.VAR2 (1'b0),
.VAR4 (VAR4)
);
end
endgenerate
endmodule | mit |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/niosII_system_nios2_qsys_0_jtag_debug_module_wrapper.v | 10,686 | module MODULE1 (
VAR25,
VAR48,
clk,
VAR22,
VAR32,
VAR8,
VAR18,
VAR36,
VAR49,
VAR51,
VAR38,
VAR10,
VAR56,
VAR9,
VAR21,
VAR44,
VAR54,
VAR57,
VAR7,
VAR29,
VAR50,
VAR17,
VAR41,
VAR43,
VAR39,
VAR35,
VAR46,
VAR28,
VAR60,
VAR4,
VAR20,
VAR13,
VAR55,
VAR45,
VAR11,
VAR42
)
;
output [ 37: 0] VAR50;
output VAR17;
output VAR41;
out... | apache-2.0 |
carstenbru/fpga-log | spartanmc/hardware/timestamp_gen/src/spmc_timestamp_gen.v | 6,379 | module MODULE1 #(
parameter VAR46 = 2, parameter VAR28 = 2, parameter VAR24 = 0, parameter VAR20 = 10'h0) (
input wire VAR40, input wire [17:0] VAR7, output wire [17:0] VAR39, input wire [9:0] VAR4, input wire VAR49, input wire VAR42,
input wire reset,
input wire [35:0] VAR13, input wire [35:0] VAR57,
input wire [VAR46... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b.symbol.v | 1,293 | module MODULE1 (
input VAR2,
input VAR4 ,
input VAR5 ,
input VAR1 ,
output VAR3
);
supply1 VAR7;
supply0 VAR6;
endmodule | apache-2.0 |
theapi/de0-nano | text/font_rom.v | 95,702 | module MODULE1 (clk, addr, VAR1);
input clk;
input [10:0] addr;
output [7:0] VAR1;
reg [7:0] VAR1;
always @ (posedge clk)
begin
case (addr)
11'h000: VAR1 = 8'b00000000; 11'h001: VAR1 = 8'b00000000; 11'h002: VAR1 = 8'b00000000; 11'h003: VAR1 = 8'b00000000; 11'h004: VAR1 = 8'b00000000; 11'h005: VAR1 = 8'b00000000; 11'h00... | mit |
Valakor/EE201-Text-Editor | text_editor_RAM.v | 1,262 | module MODULE1(
input clk,
input VAR2,
input write,
input [VAR1-1:0] VAR3,
input [VAR8-1:0] VAR9,
input [VAR1-1:0] VAR4,
output [VAR8-1:0] VAR10
);
parameter VAR8 = 8;
parameter VAR1 = 9;
parameter VAR6 = 1 << VAR1;
reg [VAR8-1:0] VAR5 [0:VAR6-1];
always @ (posedge clk, posedge VAR2) begin: VAR11
if (VAR2) begin: VAR2
... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/video_sys_Pixel_Scaler.v | 8,588 | module MODULE1 (
clk,
reset,
VAR5,
VAR17,
VAR7,
VAR27,
VAR23,
VAR32,
VAR25,
VAR11,
VAR20,
VAR34,
VAR15,
VAR31
);
parameter VAR13 = 29; parameter VAR19 = 1;
parameter VAR33 = 8; parameter VAR35 = 7; parameter VAR4 = 320;
parameter VAR16 = 4'b0000;
parameter VAR22 = 4'b0000;
parameter VAR24 = 8; parameter VAR1 = 320; par... | gpl-2.0 |
horia141/bachelor-thesis | prj/components/RegBank/RegBankP8.v | 10,041 | module MODULE1(VAR22,reset,VAR33,VAR14,VAR9,VAR29,VAR21,VAR32,VAR2,VAR34,VAR5,VAR26);
input wire VAR22;
input wire reset;
input wire [11:0] VAR33;
input wire VAR14;
output wire [7:0] VAR9;
output wire [7:0] VAR29;
output wire [7:0] VAR21;
output wire [7:0] VAR32;
output wire [7:0] VAR2;
output wire [7:0] VAR34;
output ... | mit |
tmolteno/TART | hardware/FPGA/tart_spi/bench/xilinx/RAMB16_S9_S36.v | 12,953 | module MODULE1(
VAR70, VAR64, VAR33, VAR61, VAR99, VAR59, VAR40, VAR38, VAR89,
VAR17, VAR101, VAR104, VAR10, VAR114, VAR97, VAR56, VAR39, VAR79
);
input [7:0] VAR70;
input VAR64;
input [10:0] VAR33;
input VAR61;
input VAR99;
input VAR59;
input VAR40;
output reg [7:0] VAR38;
output reg VAR89;
input [31:0] VAR17;
input [... | lgpl-3.0 |
Elphel/x353 | control/i2c_writeonly.v | 16,315 | module MODULE1 (VAR63, VAR32, VAR94, VAR54, sync, VAR46, VAR56, VAR47, VAR13, VAR81, VAR29); input VAR63;
input VAR32;
input [ 3:0] VAR94;
input [15:0] VAR54;
input sync;
output VAR46;
output VAR56;
output VAR47;
output VAR13;
output VAR81;
output [2:0] VAR29;
reg [3:0] VAR48; reg [3:0] VAR19;
reg [15:0] VAR89;
reg [15... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr.pp.symbol.v | 1,410 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR7,
input VAR6 ,
input VAR4 ,
input VAR1 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill/sky130_fd_sc_hs__fill_1.v | 1,840 | module MODULE2 (
VAR2,
VAR1,
VAR6 ,
VAR3
);
input VAR2;
input VAR1;
input VAR6 ;
input VAR3 ;
VAR5 VAR4 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR3 ;
VAR5 VAR4 ();
endmodule | apache-2.0 |
olajep/oh | src/aes/hdl/aes_128.v | 2,679 | module MODULE2(clk, state, VAR17, out);
input clk;
input [127:0] state, VAR17;
output [127:0] out;
reg [127:0] VAR64, VAR11;
wire [127:0] VAR26, VAR30, VAR45, VAR7, VAR23, VAR44, VAR5, VAR27, VAR54,
VAR43, VAR50, VAR1, VAR66, VAR51, VAR28, VAR24, VAR8, VAR42,
VAR22, VAR19, VAR3, VAR58, VAR25, VAR12, VAR13, VAR60, VAR47... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/NVMeHostController_v2_0_0/ba7abda2/src/pcie_hcmd_cq_fifo.v | 9,197 | module MODULE1 # (
parameter VAR46 = 35,
parameter VAR4 = 5
)
(
input clk,
input VAR67,
input VAR66,
input [VAR46-1:0] VAR23,
input [VAR46-1:0] VAR14,
output VAR48,
output VAR1,
input VAR81,
output [VAR46-1:0] VAR49,
output VAR21,
input VAR44,
input VAR64,
input VAR72,
input [VAR46-1:0] VAR31,
input [VAR46-1:0] VAR63,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.v | 2,270 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR7 ,
VAR8,
VAR6,
VAR10,
VAR3 ,
VAR2
);
output VAR1 ;
output VAR5 ;
input VAR7 ;
input VAR8;
input VAR6;
input VAR10;
input VAR3 ;
input VAR2 ;
VAR4 VAR9 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr.pp.blackbox.v | 1,414 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR4,
VAR2 ,
VAR3
);
output VAR5 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR4;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/hpdmc_datactl.v | 4,871 | module MODULE1(
input VAR10,
input VAR12,
input read,
input write,
input [3:0] VAR16,
output reg VAR17,
output reg VAR8,
output [3:0] VAR18,
output reg ack,
output reg VAR6,
output VAR19,
input VAR22,
input [1:0] VAR5
);
reg [2:0] VAR20;
always @(posedge VAR10) begin
if(VAR12) begin
VAR20 <= 3'd0;
VAR17 <= 1'b1;
end el... | lgpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_pll_0.v | 2,078 | module MODULE1(
input wire VAR2,
input wire rst,
output wire VAR28,
output wire VAR24
);
VAR56 #(
.VAR9("false"),
.VAR34("50.0 VAR30"),
.VAR46("VAR48"),
.VAR1(1),
.VAR11("200.000000 VAR30"),
.VAR58("0 VAR55"),
.VAR25(50),
.VAR17("0 VAR30"),
.VAR69("0 VAR55"),
.VAR42(50),
.VAR64("0 VAR30"),
.VAR6("0 VAR55"),
.VAR62(50),... | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkFTop_ml555.v | 35,104 | module MODULE1(VAR328,
VAR427,
VAR280,
VAR317,
VAR428,
VAR364,
VAR1,
VAR406,
VAR395,
VAR31,
VAR48,
VAR403,
VAR156,
VAR35,
VAR457);
input VAR328;
input VAR427;
input VAR280;
input VAR317;
input VAR428;
input [7 : 0] VAR364;
input [7 : 0] VAR1;
output [7 : 0] VAR406;
output [7 : 0] VAR395;
output [2 : 0] VAR31;
input VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s.symbol.v | 1,358 | module MODULE1 (
input VAR6,
output VAR5
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/vcr_flit_ctrl_dec.v | 11,086 | module MODULE1
(clk, reset, VAR22, VAR36, VAR40,
VAR35, VAR8);
parameter VAR24 = 2;
parameter VAR33 = 2;
localparam VAR10 = VAR24 * VAR33;
parameter VAR6 = 1;
localparam VAR43 = VAR10 * VAR6;
localparam VAR41 = VAR17(VAR43);
parameter VAR20 = 4;
parameter VAR30 = 2;
parameter VAR37 = 1;
parameter VAR29 = VAR31;
localpa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31oi/sky130_fd_sc_ms__a31oi.behavioral.v | 1,544 | module MODULE1 (
VAR8 ,
VAR1,
VAR10,
VAR3,
VAR6
);
output VAR8 ;
input VAR1;
input VAR10;
input VAR3;
input VAR6;
supply1 VAR14;
supply0 VAR11;
supply1 VAR7 ;
supply0 VAR5 ;
wire VAR4 ;
wire VAR2;
and VAR13 (VAR4 , VAR3, VAR1, VAR10 );
nor VAR12 (VAR2, VAR6, VAR4 );
buf VAR9 (VAR8 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32ai/sky130_fd_sc_hd__o32ai.blackbox.v | 1,392 | module MODULE1 (
VAR7 ,
VAR5,
VAR9,
VAR1,
VAR10,
VAR6
);
output VAR7 ;
input VAR5;
input VAR9;
input VAR1;
input VAR10;
input VAR6;
supply1 VAR8;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
YurongYou/MIPS_CPU | EX_MEM.v | 1,928 | module MODULE1 (
input clk,
input rst,
input VAR12,
input[VAR32-1:0] VAR22,
input[VAR35-1:0] VAR29,
input VAR10,
input VAR18,
input[VAR35-1:0] VAR44,
input[VAR35-1:0] VAR1,
input[VAR32-1:0] VAR43,
input[VAR35-1:0] VAR41,
input VAR42,
input VAR33,
input VAR3,
input VAR21,
input[VAR6-1:0] VAR2,
output[VAR32-1:0] VAR15,
o... | mpl-2.0 |
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