repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_ic_top_wrapper.v | 8,755 | module MODULE1(
clk, rst,
VAR43, VAR31, VAR15, VAR10, VAR33, VAR20, VAR3,
VAR42, VAR47, VAR13,
VAR23,
VAR6, VAR11, VAR32,
VAR40, VAR38,
VAR22, VAR25, VAR27, VAR14, VAR2,
VAR26, VAR17, VAR4,
VAR18, VAR19, VAR34
);
parameter VAR28 = VAR56;
input clk;
input rst;
output [VAR28-1:0] VAR43;
output [31:0] VAR31;
output VAR15;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbn/sky130_fd_sc_lp__dfbbn.behavioral.pp.v | 2,820 | module MODULE1 (
VAR28 ,
VAR27 ,
VAR1 ,
VAR17 ,
VAR8 ,
VAR9,
VAR16 ,
VAR13 ,
VAR2 ,
VAR20
);
output VAR28 ;
output VAR27 ;
input VAR1 ;
input VAR17 ;
input VAR8 ;
input VAR9;
input VAR16 ;
input VAR13 ;
input VAR2 ;
input VAR20 ;
wire VAR19 ;
wire VAR25 ;
wire VAR29 ;
wire VAR7 ;
wire VAR10 ;
wire VAR6;
wire VAR14 ;
re... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4b/sky130_fd_sc_ls__and4b.behavioral.pp.v | 1,988 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR9 ,
VAR8 ,
VAR3 ,
VAR14,
VAR10,
VAR11 ,
VAR4
);
output VAR7 ;
input VAR1 ;
input VAR9 ;
input VAR8 ;
input VAR3 ;
input VAR14;
input VAR10;
input VAR11 ;
input VAR4 ;
wire VAR12 ;
wire VAR6 ;
wire VAR13;
not VAR17 (VAR12 , VAR1 );
and VAR15 (VAR6 , VAR12, VAR9, VAR8, VAR3 );
VAR2 VAR5 ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_4.functional.v | 1,838 | module MODULE1( VAR16, VAR7, VAR23, VAR13, VAR6, VAR21, VAR10 );
input VAR6, VAR21, VAR10, VAR23, VAR16, VAR7;
output VAR13;
wire VAR5;
not VAR14( VAR5, VAR6 );
wire VAR17;
not VAR8( VAR17, VAR21 );
wire VAR3;
not VAR2( VAR3, VAR10 );
wire VAR22;
and VAR11( VAR22, VAR5, VAR17, VAR3 );
wire VAR24;
not VAR20( VAR24, VAR2... | apache-2.0 |
andykarpov/radio-86rk-wxeda | src/video/rambuffer.v | 10,608 | module MODULE1 (
VAR59,
VAR6,
VAR26,
VAR45,
VAR53,
VAR16,
VAR47,
VAR48,
VAR41);
input [16:0] VAR59;
input [16:0] VAR6;
input VAR26;
input [0:0] VAR45;
input [0:0] VAR53;
input VAR16;
input VAR47;
output [0:0] VAR48;
output [0:0] VAR41;
tri1 VAR26;
tri0 VAR16;
tri0 VAR47;
wire [0:0] VAR8;
wire [0:0] VAR24;
wire [0:0] VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32oi/sky130_fd_sc_hd__a32oi.functional.pp.v | 2,238 | module MODULE1 (
VAR6 ,
VAR12 ,
VAR9 ,
VAR19 ,
VAR18 ,
VAR3 ,
VAR17,
VAR16,
VAR1 ,
VAR15
);
output VAR6 ;
input VAR12 ;
input VAR9 ;
input VAR19 ;
input VAR18 ;
input VAR3 ;
input VAR17;
input VAR16;
input VAR1 ;
input VAR15 ;
wire VAR4 ;
wire VAR13 ;
wire VAR5 ;
wire VAR7;
nand VAR10 (VAR4 , VAR9, VAR12, VAR19 );
nand... | apache-2.0 |
DigitalLogicSummerTerm2015/mips-cpu-single-cycle | Control.v | 13,900 | module MODULE1(VAR14,VAR15,VAR1,VAR3,VAR9,VAR11,VAR7,
VAR5,VAR12,VAR6,VAR8,VAR4,VAR13,VAR10,VAR2);
output reg [2:0]VAR14;
output reg [1:0]VAR15;
output reg VAR1;
output reg VAR3;
output reg VAR9;
output reg [5:0]VAR11;
output reg VAR7;
output reg VAR5;
output reg VAR12;
output reg [1:0]VAR6;
output reg VAR8;
output reg... | mit |
Nrpickle/ECE272 | Lab5_TekBotSM/Section5_Top_tf.v | 1,113 | module MODULE1();
reg VAR3;
reg VAR6;
reg VAR1;
wire [3:0] VAR5;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5)
); | mit |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_register_64.v | 5,281 | module MODULE1 #
(
parameter VAR24 = 64,
parameter VAR23 = (VAR24/8)
)
(
input wire clk,
input wire rst,
input wire [VAR24-1:0] VAR12,
input wire [VAR23-1:0] VAR17,
input wire VAR13,
output wire VAR21,
input wire VAR5,
input wire VAR1,
output wire [VAR24-1:0] VAR19,
output wire [VAR23-1:0] VAR20,
output wire VAR8,
inpu... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/usbSerialInterfaceEngine.v | 11,297 | module MODULE1(
clk, rst,
VAR24,
VAR62,
VAR61,
VAR111,
VAR136,
VAR88,
VAR59,
VAR68,
VAR15,
VAR64,
VAR110,
VAR16,
VAR126,
VAR124,
VAR57,
VAR63,
VAR67,
VAR46
);
input clk, rst;
input [1:0] VAR24;
output VAR62;
output VAR67;
input VAR46;
output [1:0] VAR61;
output VAR111;
output VAR136;
output [1:0] VAR88;
output VAR59;
o... | gpl-3.0 |
racerxdl/LVDS-7-to-1-Serializer | src/maincore.v | 4,089 | module MODULE1(
input clk,
output VAR10,
output VAR26,
output VAR22,
output VAR38,
output VAR43,
output VAR3,
output VAR29,
output VAR6
);
parameter VAR18 = 1280;
parameter VAR15 = 800;
parameter VAR9 = 12;
parameter VAR39 = 192;
wire VAR44,VAR23,VAR24, VAR1;
reg [5:0] VAR7 = 0;
reg [5:0] VAR17 = 0;
reg [5:0] VAR40 = 0... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_8.behavioral.v | 1,101 | module MODULE1( VAR5, VAR3 );
input VAR5;
output VAR3;
VAR2 VAR1(.VAR5(VAR5),.VAR3(VAR3));
VAR2 VAR4(.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_altmemddr_0_full_mem_model.v | 24,309 | module MODULE1 (
VAR108,
VAR54,
VAR100,
VAR22,
VAR24,
VAR51,
VAR26
)
;
output [ 15: 0] VAR26;
input [ 15: 0] VAR108;
input [ 24: 0] VAR54;
input VAR100;
input [ 24: 0] VAR22;
input VAR24;
input VAR51;
reg [ 15: 0] VAR66 [33554431: 0];
wire [ 15: 0] VAR26;
reg [ 24: 0] VAR122;
always @(VAR54)
begin
VAR122 = VAR54;
end
a... | gpl-3.0 |
Seeed-Studio/DSOQuad_SourceCode | FPGA_V2.5/IO_Ctrl.v | 4,832 | module MODULE1( VAR21, VAR39, VAR10, VAR12, VAR35, VAR28, VAR7, VAR20, VAR1, VAR33, VAR17,
VAR30, VAR19, VAR6, VAR5, VAR34, VAR25,
VAR8, VAR38, VAR11, VAR14, VAR18, VAR31,
VAR9, VAR3, VAR22,
VAR15, VAR32, VAR26, VAR27, VAR23, VAR16 );
input VAR21; input VAR39; input VAR10; input VAR12; input [17:0]VAR35; input VAR28; i... | mit |
sirchuckalot/zet | cores/hpdmc_sdr16/rtl/hpdmc_busif.v | 1,440 | module MODULE1 #(
parameter VAR13 = 23
) (
input VAR7,
input VAR8,
input [VAR13-1:0] VAR11,
input VAR1,
input VAR2,
output VAR12,
output VAR10,
output VAR4,
output [VAR13-1-1:0] VAR6,
input VAR9,
input VAR3
);
reg VAR5;
assign VAR10 = VAR1 & VAR5;
assign VAR4 = VAR2;
assign VAR6 = VAR11[VAR13-1:1];
assign VAR12 = VAR3;... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_cx4/cx4_datram.v | 10,709 | module MODULE1 (
VAR51,
VAR25,
VAR30,
VAR47,
VAR13,
VAR56,
VAR8,
VAR24,
VAR28);
input [11:0] VAR51;
input [11:0] VAR25;
input VAR30;
input [7:0] VAR47;
input [7:0] VAR13;
input VAR56;
input VAR8;
output [7:0] VAR24;
output [7:0] VAR28;
tri1 VAR30;
tri0 VAR56;
tri0 VAR8;
wire [7:0] VAR60;
wire [7:0] VAR61;
wire [7:0] VA... | gpl-2.0 |
YosysHQ/yosys | techlibs/xilinx/ff_map.v | 4,943 | module \VAR15 (input VAR26, VAR40, VAR44, VAR34, output VAR3);
parameter VAR14 = 1'VAR31;
VAR8 #(.VAR11(VAR14)) VAR13 (.VAR26(VAR26), .VAR3(VAR3), .VAR40(VAR40), .VAR6(VAR44), .VAR23(VAR34));
wire VAR39 = 1;
endmodule
module \VAR43 (input VAR26, VAR40, VAR44, VAR34, output VAR3);
parameter VAR14 = 1'VAR31;
VAR27 #(.VAR... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlclkp/sky130_fd_sc_hs__dlclkp.blackbox.v | 1,223 | module MODULE1 (
VAR4,
VAR1,
VAR2
);
output VAR4;
input VAR1;
input VAR2 ;
supply1 VAR3;
supply0 VAR5;
endmodule | apache-2.0 |
mlohstroh/bubble-pushers | InstrDecod.v | 2,572 | module MODULE1(VAR7, VAR16, VAR17, VAR10, VAR15, VAR18, VAR13, VAR12, VAR6, VAR1, VAR8, VAR2, VAR5, VAR4);
input [31:0] VAR7; input [31:0] VAR16; input [31:0] VAR10; input [4:0] VAR15; input VAR17;
output [5:0] VAR18; output [5:0] VAR13; output [31:0] VAR12; output [31:0] VAR6; output [4:0] VAR1; output [4:0] VAR8; out... | gpl-3.0 |
gigglesninja/digital-system-design | spi/ipcore_dir/txreg.v | 13,640 | module MODULE1(
clk,
rst,
din,
VAR315,
VAR165,
dout,
VAR34,
VAR259
);
input clk;
input rst;
input [7 : 0] din;
input VAR315;
input VAR165;
output [7 : 0] dout;
output VAR34;
output VAR259;
VAR343 #(
.VAR59(0),
.VAR306(0),
.VAR113(0),
.VAR222(0),
.VAR199(0),
.VAR61(0),
.VAR214(0),
.VAR272(32),
.VAR322(1),
.VAR312(1),
.V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2.pp.symbol.v | 1,265 | module MODULE1 (
input VAR2 ,
input VAR4 ,
output VAR5 ,
input VAR1 ,
input VAR7,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | boards/xilinx-ml401/rtl/ddram.v | 4,133 | module MODULE1 #(
parameter VAR40 = 4'h0
) (
input VAR47,
input VAR90,
input [13:0] VAR22,
input VAR27,
input [31:0] VAR23,
output [31:0] VAR69,
input [VAR84-1:0] VAR52,
input VAR34,
input VAR50,
output VAR91,
input [7:0] VAR82,
input [63:0] VAR12,
output [63:0] VAR8,
output VAR65,
output VAR94,
input VAR1,
output VAR3... | lgpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/gpif/packet_reframer.v | 1,782 | module MODULE1
(input clk, input reset, input VAR6,
input [15:0] VAR9,
input VAR12,
output VAR4,
output [18:0] VAR11,
output VAR3,
input VAR8,
output reg state,
output VAR2,
output reg [15:0] VAR7);
localparam VAR10 = 0;
localparam VAR1 = 1;
always @(posedge clk)
if(reset | VAR6)
state <= VAR10;
else
if(VAR12 & VAR8)
c... | gpl-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_arb_mux.v | 13,315 | module MODULE1 #
(
parameter VAR60 = 4,
parameter VAR91 = 8,
parameter VAR2 = (VAR91>8),
parameter VAR76 = (VAR91/8),
parameter VAR85 = 0,
parameter VAR32 = 8,
parameter VAR82 = 0,
parameter VAR55 = 8,
parameter VAR88 = 1,
parameter VAR24 = 1,
parameter VAR71 = 0,
parameter VAR27 = 1
)
(
input wire clk,
input wire rst,... | mit |
cfib/bf2hw | lib/bambu_io_hw/bambu_getchar.v | 2,844 | module MODULE1 (input VAR4, input reset, input VAR11, output reg VAR1, output reg [7:0] VAR8, input [7:0] VAR19, input VAR30);
reg [7:0] VAR9;
reg VAR27;
wire [7:0] VAR26;
wire VAR17;
reg [7:0] VAR28;
reg VAR13;
wire VAR10;
VAR18 #(.VAR23(8))
VAR21 (.clk(VAR4), .reset(reset), .VAR20(VAR13), .VAR7(VAR27),
.VAR25(VAR17),... | gpl-3.0 |
ngoel9/progressive-learning-platform | reference/hw/verilog/arbiter.v | 6,537 | module MODULE1(rst, clk, VAR72, VAR107, VAR68, VAR91, VAR67, VAR78, int, VAR23, VAR49, VAR69, VAR109, VAR28, VAR18, VAR117, VAR103, VAR110, VAR1, VAR13, VAR88, VAR45, VAR17, VAR111, VAR54, VAR32, VAR7, VAR77, VAR89, VAR57, VAR2, VAR40);
input clk, rst, VAR23;
output int;
input [1:0] VAR91;
input [31:0] VAR72, VAR67;
in... | gpl-3.0 |
jeffkub/n64-cart-reader | old/n64cartridge/src/sdram/lfsr_count64.v | 2,243 | module MODULE1(
input VAR2,
input VAR4,
output reg VAR1);
reg [5:0] VAR3;
wire VAR5,VAR6;
xnor(VAR5,VAR3[5],VAR3[4]);
assign VAR6 = (VAR3 == 6'h20);
always @(posedge VAR2,posedge VAR4)
begin
if(VAR4) begin
VAR3 <= 0;
VAR1 <= 0;
end
else begin
VAR3 <= VAR6 ? 6'h0 : {VAR3[4:0],VAR5};
VAR1 <= VAR6;
end
end
endmodule | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/updateCRC16.v | 3,971 | module MODULE1 (VAR5, VAR7, VAR4, VAR1, ready, clk, rst);
input VAR5;
input VAR4;
input [7:0] VAR1;
input clk;
input rst;
output [15:0] VAR7;
output ready;
wire VAR5;
wire VAR4;
wire [7:0] VAR1;
wire clk;
wire rst;
reg [15:0] VAR7;
reg ready;
reg VAR3;
reg [7:0] VAR6;
reg [3:0] VAR2;
always @(posedge clk)
begin
if (rst... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_sdr.v | 4,147 | module MODULE1
,parameter VAR28(VAR35 )
,parameter VAR28(VAR8 )
,parameter VAR42 = 0
,parameter VAR26 = 1
,parameter VAR4 = 0
)
( input VAR14
, input VAR17
, input VAR16
, input VAR34
, input VAR23
, input VAR36
, input [VAR39-1:0] VAR24
, output VAR40
, output VAR31
, output [VAR39-1:0] VAR32
, input VAR15
, output VA... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_16/bsg_async/bsg_launch_sync_sync.v | 7,650 | \
module MODULE2 \
(input VAR23 \
,input VAR37 \
,input VAR32 \
,input [VAR35-1:0] VAR26 \
,output [VAR35-1:0] VAR28 \
,output [VAR35-1:0] VAR11 \
); \
\
genvar VAR25; \
\
logic [VAR35-1:0] VAR7; \
logic [VAR35-1:0] VAR10; \
\
assign VAR28 = VAR7; \
assign VAR11 = VAR10; \
\
VAR1 @(VAR3 VAR23) \
begin \
if (VAR37) \
VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi.behavioral.v | 2,139 | module MODULE1 (
VAR2 ,
VAR7,
VAR9,
VAR13 ,
VAR4 ,
VAR8,
VAR11
);
output VAR2 ;
input VAR7;
input VAR9;
input VAR13 ;
input VAR4 ;
input VAR8;
input VAR11;
wire VAR4 VAR14 ;
wire VAR4 VAR16 ;
wire VAR5 ;
wire VAR15;
and VAR12 (VAR14 , VAR13, VAR4 );
nor VAR1 (VAR16 , VAR7, VAR9 );
nor VAR6 (VAR5 , VAR16, VAR14 );
VAR10... | apache-2.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlconstant_0_1/RAT_xlconstant_0_1_stub.v | 1,169 | module MODULE1(dout)
;
output [1:0]dout;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a_1.v | 2,348 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR9 ,
VAR4 ,
VAR11 ,
VAR8,
VAR3,
VAR10 ,
VAR6
);
output VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR11 ;
input VAR8;
input VAR3;
input VAR10 ;
input VAR6 ;
VAR1 VAR2 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.... | apache-2.0 |
valptek/v586 | core_rtl/arithbox.v | 3,674 | module MODULE1 (VAR3,VAR13,VAR9,VAR16,VAR10,VAR1,VAR12,VAR14,VAR6,VAR4,VAR15,VAR8);
input [3:0] VAR3;
input [3:0] VAR13;
input [31:0] VAR6,VAR4;
output reg [31:0] VAR15;
input VAR9,VAR1;
output reg VAR16,VAR10,VAR12,VAR14,VAR8;
wire [4:0] VAR7,VAR5,VAR11,VAR2;
assign VAR7 = VAR6[3:0]+VAR4[3:0];
assign VAR5 = VAR6[3:0]+... | apache-2.0 |
plindstroem/oh | elink/hdl/emaxi.v | 19,062 | module MODULE1(
VAR109, VAR78, VAR67, VAR75, VAR21,
VAR90, VAR39, VAR65, VAR46,
VAR37, VAR107, VAR35, VAR16,
VAR100, VAR47, VAR25, VAR31, VAR110,
VAR4, VAR36, VAR20, VAR91, VAR55,
VAR59, VAR108, VAR80, VAR94,
VAR29, VAR61, VAR68, VAR81,
VAR84, VAR92, VAR9, VAR96, VAR50,
VAR40, VAR72, VAR24, VAR93, VAR13,
VAR43, VAR106,... | gpl-3.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_inferram.v | 15,956 | module MODULE1(clk, VAR16, VAR12, VAR11, VAR13, VAR21, VAR19, VAR22, VAR17);
parameter VAR1 = "VAR10";
parameter VAR3 = "VAR9";
parameter VAR2 = 1024;
parameter VAR20 = 10;
parameter VAR15 = 8;
parameter VAR18 = 4;
parameter VAR14 = 0;
input clk;
input [VAR18-1:0] VAR16;
input [VAR18-1:0] VAR12;
input [VAR20-1:0] VAR11... | mit |
hcabrera-/lancetfish | RTL/shared/verif/source.v | 6,171 | module MODULE1 #(
parameter VAR3 = 5,
parameter VAR17 = VAR9,
parameter VAR6 = 2,
parameter VAR7 = 0
)
(
input wire clk,
input wire VAR10,
output reg [VAR20-1:0] VAR16
);
localparam VAR8 = 65;
integer VAR11;
integer VAR12;
integer VAR15;
integer VAR19;
reg [12*8:0] VAR4;
reg [4*8:0] VAR22;
reg [7:0] VAR21;
reg [17:0] V... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/rx_buffer_fsm.v | 2,297 | module MODULE1 (
input VAR3,
input VAR2,
input VAR5,
input VAR4,
input VAR1,
output reg VAR8,
output reg VAR7,
output reg VAR6
);
always@(posedge VAR3 or negedge VAR2)
begin
if(!VAR2)
begin
VAR8 <= 1'b0;
VAR7 <= 1'b0;
VAR6 <= 1'b0;
end
else
begin
if(VAR5 == 1'b1 )
begin
VAR8 <= 1'b0;
VAR7 <= 1'b1;
VAR6 <= 1'b0;
end
els... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/BCHDecoderInputControl.v | 16,770 | module MODULE1
(
parameter VAR3 = 32 ,
parameter VAR14 = 32 ,
parameter VAR44 = 16 ,
parameter VAR60 = 2
)
(
VAR51 ,
VAR57 ,
VAR69 ,
VAR53 ,
VAR75 ,
VAR56 ,
VAR70 ,
VAR62 ,
VAR48 ,
VAR67 ,
VAR8 ,
VAR11 ,
VAR46 ,
VAR20 ,
VAR32 ,
VAR47 ,
VAR17 ,
VAR73 ,
VAR74 ,
VAR59 ,
VAR16 ,
VAR43 ,
VAR36 ,
VAR29 ,
VAR25 ,
VAR79 ,
VAR7... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController/src/pcie_tx_cmd_fifo.v | 4,947 | module MODULE1 # (
parameter VAR12 = 34,
parameter VAR47 = 5
)
(
input clk,
input VAR14,
input VAR40,
input [VAR12-1:0] VAR41,
output VAR43,
input VAR23,
output [VAR12-1:0] VAR26,
output VAR31
);
localparam VAR22 = 1;
reg [VAR47:0] VAR5;
reg [VAR47:0] VAR28;
wire [VAR47-1:0] VAR29;
reg [VAR47:0] VAR25;
assign VAR43 = ~... | gpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/ddr_ctrl_ip_alt_mem_ddrx_controller_top.v | 41,283 | module MODULE1(
clk,
VAR333,
VAR38,
VAR363,
VAR184,
VAR159,
VAR187,
VAR397,
VAR228,
VAR105,
VAR231,
VAR244,
VAR15,
VAR176,
VAR201,
VAR247,
VAR131,
VAR381,
VAR284,
VAR240,
VAR288,
VAR21,
VAR370,
VAR148,
VAR115,
VAR267,
VAR93,
VAR45,
VAR66,
VAR153,
VAR337,
VAR391,
VAR248,
VAR50,
VAR336,
VAR340,
VAR215,
VAR86,
VAR265,
VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4bb/sky130_fd_sc_hdll__nor4bb.pp.symbol.v | 1,342 | module MODULE1 (
input VAR6 ,
input VAR9 ,
input VAR5 ,
input VAR2 ,
output VAR3 ,
input VAR7 ,
input VAR4,
input VAR8,
input VAR1
);
endmodule | apache-2.0 |
Digilent/vivado-library | ip/Pmods/PmodDPG1_v1_0/src/PmodDPG1.v | 10,163 | module MODULE1
(VAR77,
VAR73,
VAR133,
VAR120,
VAR128,
VAR137,
VAR153,
VAR142,
VAR23,
VAR112,
VAR91,
VAR145,
VAR5,
VAR72,
VAR12,
VAR99,
VAR93,
VAR121,
VAR157,
VAR60,
VAR6,
VAR168,
VAR139,
VAR148,
VAR81,
VAR69,
VAR11,
VAR18,
VAR55,
VAR110,
VAR38,
VAR105,
VAR56,
VAR80,
VAR51,
VAR42,
VAR21,
VAR82,
VAR8,
VAR166,
VAR155,
VAR... | mit |
dhytxz/PolyPC | hardware/ip_repo/hapara_axis_barrier_1.0/hdl/hapara_axis_barrier_v1_0.v | 26,327 | module MODULE1 #
(
parameter integer VAR49 = 2,
parameter integer VAR18 = 32
)
(
input wire VAR58,
input wire VAR10,
input wire VAR46,
input wire [VAR18-1 : 0] VAR2,
output wire VAR33,
input wire VAR43,
input wire [VAR18-1 : 0] VAR61,
output wire VAR74,
input wire VAR14,
input wire [VAR18-1 : 0] VAR64,
output wire VAR9... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/Priority_Codec_32.v | 2,855 | module MODULE1(
input wire [25:0] VAR1,
output reg [4:0] VAR3
);
parameter VAR2 = 26;
always @(VAR1)
begin
if(~VAR1[25]) begin VAR3 = 5'b00000; end else if(~VAR1[24]) begin VAR3 = 5'b00001; end else if(~VAR1[23]) begin VAR3 = 5'b00010; end else if(~VAR1[22]) begin VAR3 = 5'b00011; end else if(~VAR1[21]) begin VAR3 = 5'... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,556 | module MODULE1
parameter VAR35 = 8,
VAR37 = 8,
VAR6 = 0,
VAR18 = 0,
VAR9 = 1,
VAR22 = 0,
VAR2 = 1,
VAR23 = 2,
VAR21 = 2,
VAR43 = 1,
VAR20 = VAR35 / VAR37,
VAR8 = VAR26(VAR20)
)
(
input VAR25,
input VAR5,
input VAR27,
input VAR38,
output VAR16,
input VAR11,
input [VAR35 - 1 : 0] VAR3,
input [VAR9 - 1 : 0] VAR29,
input [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxbp/sky130_fd_sc_hd__sedfxbp_2.v | 2,564 | module MODULE2 (
VAR9 ,
VAR13 ,
VAR3 ,
VAR12 ,
VAR7 ,
VAR10 ,
VAR4 ,
VAR1,
VAR6,
VAR8 ,
VAR5
);
output VAR9 ;
output VAR13 ;
input VAR3 ;
input VAR12 ;
input VAR7 ;
input VAR10 ;
input VAR4 ;
input VAR1;
input VAR6;
input VAR8 ;
input VAR5 ;
VAR2 VAR11 (
.VAR9(VAR9),
.VAR13(VAR13),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR7(VAR... | apache-2.0 |
davidlee80/miaow | src/verilog/rtl/dispatcher/gds_resource_table.v | 2,698 | module MODULE1 (
VAR10,
rst, clk, VAR8, VAR25,
VAR1, VAR17, VAR14,
VAR20
) ;
parameter VAR23 = 64;
parameter VAR13 = 6;
parameter VAR2 = 3;
parameter VAR15 = 6;
parameter VAR18 = 40;
parameter VAR7 = 10;
parameter VAR6 = 1024;
localparam VAR3 = 2**VAR2;
input rst, clk;
input VAR8, VAR25;
input [VAR13-1:0] VAR1;
input [... | bsd-3-clause |
lavingiasa/verilogTetris | tetris.v | 15,954 | module MODULE1( VAR73, VAR34, VAR50, VAR10, VAR52, VAR68, VAR8, VAR18,
VAR71, VAR22, VAR39, VAR49, VAR40, VAR2, VAR55, VAR17, VAR36, VAR41
);
input VAR73, VAR34;
input VAR50, VAR10;
input VAR52, VAR68, VAR8;
input VAR18;
output VAR71, VAR22;
output VAR39, VAR49, VAR40;
output reg [159:0] VAR2;
output reg [7:0] VAR55;
r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2.blackbox.v | 1,239 | module MODULE1 (
VAR3,
VAR4,
VAR1
);
output VAR3;
input VAR4;
input VAR1;
supply1 VAR2;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
egyp7/mor1kx | rtl/verilog/mor1kx_decode.v | 17,632 | module MODULE1
parameter VAR110 = 32,
parameter VAR61 = {{(VAR110-13){1'b0}},
parameter VAR108 = 5,
parameter VAR5 = "VAR129",
parameter VAR30 = "VAR129",
parameter VAR85 = "VAR129",
parameter VAR96 = "VAR23",
parameter VAR17 = "VAR64",
parameter VAR141 = "VAR23",
parameter VAR10 = "VAR23",
parameter VAR65 = "VAR129",
... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211ai/sky130_fd_sc_hdll__o211ai_1.v | 2,377 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR9 ,
VAR7 ,
VAR6 ,
VAR11,
VAR2,
VAR10 ,
VAR1
);
output VAR4 ;
input VAR5 ;
input VAR9 ;
input VAR7 ;
input VAR6 ;
input VAR11;
input VAR2;
input VAR10 ;
input VAR1 ;
VAR8 VAR3 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR10(VAR10),
.... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_pwm16_core.v | 12,430 | module MODULE1(
input VAR53,
input reset,
input VAR141,
input [31:0] VAR7,
output [31:0] VAR158,
input VAR33,
input [31:0] VAR13,
output [31:0] VAR155,
input VAR1,
input [31:0] VAR78,
output [31:0] VAR165,
input VAR109,
input [15:0] VAR5,
output [15:0] VAR160,
input VAR72,
input [15:0] VAR58,
output [15:0] VAR25,
input... | apache-2.0 |
thotypous/rtai-irq-latency | PCIe_HW/de4_pcie_top.v | 1,599 | module MODULE1(
input VAR28,
input VAR11,
input VAR4,
input [3:0] VAR29,
output [3:0] VAR25,
output [7:0] VAR14,
output [35:0] VAR8
);
wire [16:0] VAR5;
wire [ 3:0] VAR26;
VAR1 VAR24 (
.VAR23(VAR28),
.VAR30(VAR5),
.VAR7(VAR26)
);
VAR9 VAR19 (
.VAR27 (VAR28),
.VAR18 (VAR11),
.VAR22 (VAR4),
.VAR21 (VAR29[0]),
.VAR17 (VAR... | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_mc_phy_wrapper.v | 66,958 | module MODULE1 #
(
parameter VAR378 = 100, parameter VAR243 = 2500, parameter VAR96 = "VAR72", parameter VAR390 = "VAR315", parameter VAR165 = "VAR31", parameter VAR71 = "VAR404",
parameter VAR339 = 4, parameter VAR220 = 1, parameter VAR336 = 3, parameter VAR141 = 1, parameter VAR38 = 1, parameter VAR321 = 1, parameter... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi_4.v | 2,261 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR4 ,
VAR10 ,
VAR3,
VAR6,
VAR9 ,
VAR1
);
output VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR10 ;
input VAR3;
input VAR6;
input VAR9 ;
input VAR1 ;
VAR8 VAR2 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/ddr2_infrastructure.v | 12,437 | module MODULE1 #
(
parameter VAR83 = 3000,
parameter VAR117 = "VAR99",
parameter VAR76 = "VAR54",
parameter VAR87 = 1
)
(
input VAR126,
input VAR43,
input VAR34,
input VAR58,
input VAR41,
input VAR89,
output VAR59,
output VAR107,
output VAR125,
output VAR98,
input VAR101,
input VAR133,
output VAR39,
output VAR55,
outpu... | mit |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/Verilog_Source/Macros/serdes_n_to_1_s8_diff.v | 8,828 | module MODULE1 (VAR43, VAR17, reset, VAR37, VAR35, VAR20, VAR12) ;
parameter integer VAR41 = 8 ; parameter integer VAR27 = 16 ;
input VAR43 ; input VAR17 ; input reset ; input VAR37 ; input [(VAR27*VAR41)-1:0] VAR35 ; output [VAR27-1:0] VAR20 ; output [VAR27-1:0] VAR12 ;
wire [VAR27:0] VAR28 ; wire [VAR27:0] VAR15 ; wi... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtp/sky130_fd_sc_hs__sdfrtp.symbol.v | 1,474 | module MODULE1 (
input VAR5 ,
output VAR7 ,
input VAR6,
input VAR4 ,
input VAR3 ,
input VAR8
);
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
juan199/Lab_Digitales | exp2/IMUL16.v | 2,734 | module MODULE1 # (parameter VAR1 = 2)
(
input wire [VAR1-1:0] VAR14,
input wire [VAR1-1:0] VAR17,
output wire [2*VAR1-1:0] VAR12
);
wire [VAR1-1:0] VAR7 [VAR1-2:0]; wire[VAR1-1:0] VAR4 [VAR1-1:0]; genvar VAR15, VAR6;
assign VAR12[0]=VAR14[0]&VAR17[0]; assign VAR4[0][VAR1-1]=1'b0;
generate
for(VAR15=0; VAR15<VAR1-1;VAR1... | lgpl-3.0 |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/gleichmann/miscellaneous/postponer.v | 2,317 | module MODULE1 (
VAR3, VAR22, VAR23, VAR5, VAR12, VAR19,
VAR7, VAR6, VAR4, VAR10,
VAR8, VAR17, VAR2, VAR21, VAR15, VAR18, VAR16, VAR13,
VAR14, VAR11
) ;
parameter VAR1 = 32;
parameter VAR20 = 32;
parameter VAR9 = 1;
input VAR8, VAR17, VAR2, VAR21;
input [VAR1-1:0] VAR15;
input [1:0] VAR18;
input [2:0] VAR16, VAR13;
inp... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_video_clipper_add.v | 6,837 | module MODULE1 (
clk,
reset,
VAR3,
VAR2,
VAR31,
VAR27,
VAR4,
VAR13,
VAR14,
VAR15,
VAR22,
VAR24,
VAR19,
VAR6
);
parameter VAR1 = 15; parameter VAR25 = 0;
parameter VAR9 = 640; parameter VAR37 = 480; parameter VAR38 = 9; parameter VAR11 = 8;
parameter VAR26 = 0;
parameter VAR10 = 0;
parameter VAR30 = 0;
parameter VAR33 =... | mit |
skyfex/svo-raycaster | raycaster2/raycast_slave.v | 10,563 | module MODULE1
(
VAR48,
VAR55,
VAR40, VAR5,
VAR17, VAR19, VAR60,
VAR27, VAR24,
VAR22, VAR45, VAR10, VAR14,
VAR21,
VAR4,
VAR31, VAR58, VAR23, VAR64,
VAR30,
VAR35,
VAR7,
VAR6,
VAR59, VAR51,
VAR56
);
input VAR48;
input VAR55;
input [7:0] VAR40;
input [7:0] VAR5;
input VAR17;
input VAR19;
input VAR60;
input [2:0] VAR27;
in... | mit |
GSejas/Karatsuba_FPU | FPGA_FLOW/Cordic/CORDIC_FUNCIONAL_Viv/CORDIC_FUNCIONAL_Viv.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/FPU_Interface_and_NaN/NaN_mod_32.v | 1,497 | module MODULE1
(
input wire [1:0] VAR3,
input wire [31:0] VAR1,
input wire [31:0] VAR4,
output reg VAR2
);
always @*
begin
case(VAR3)
2'b00:
begin
if((VAR1 == 32'h7f800000) && (VAR4 == 32'h7f800000))
VAR2 = 1'b1;
end
else if((VAR1 == 32'hff800000) && (VAR4 == 32'hff800000))
VAR2 = 1'b1;
end
else if((VAR1 == 32'h7f80000... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo.functional.pp.v | 2,043 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR12 ,
VAR9,
VAR1,
VAR4,
VAR13 ,
VAR14
);
output VAR2 ;
input VAR3 ;
input VAR12 ;
input VAR9;
input VAR1;
input VAR4;
input VAR13 ;
input VAR14 ;
wire VAR11 ;
wire VAR10 ;
wire VAR7;
nand VAR8 (VAR11 , VAR12, VAR3 );
nand VAR5 (VAR10 , VAR9, VAR11 );
VAR15 VAR16 (VAR7, VAR10, VAR1, VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4.behavioral.pp.v | 1,837 | module MODULE1 (
VAR5 ,
VAR15 ,
VAR9 ,
VAR2 ,
VAR14 ,
VAR10,
VAR12,
VAR11 ,
VAR4
);
output VAR5 ;
input VAR15 ;
input VAR9 ;
input VAR2 ;
input VAR14 ;
input VAR10;
input VAR12;
input VAR11 ;
input VAR4 ;
wire VAR6 ;
wire VAR13;
and VAR1 (VAR6 , VAR15, VAR9, VAR2, VAR14 );
VAR3 VAR8 (VAR13, VAR6, VAR10, VAR12);
buf VAR... | apache-2.0 |
open-power/snap | actions/hdl_helloworld/hw/hdl/action_wrapper.v | 18,654 | module MODULE1 #(
parameter VAR143 = 4,
parameter VAR5 = 33,
parameter VAR20 = 512,
parameter VAR55 = 1,
parameter VAR33 = 1,
parameter VAR25 = 1,
parameter VAR42 = 1,
parameter VAR18 = 1,
parameter VAR84 = 32,
parameter VAR96 = 32,
parameter VAR83 = 1,
parameter VAR152 = 64,
parameter VAR69 = 512,
parameter VAR34 = 8,... | apache-2.0 |
wyvernSemi/vproc | f_VProc.v | 4,496 | module MODULE1 (VAR6, VAR4, VAR16, VAR19, VAR18, VAR20, VAR5, VAR12, VAR15, VAR2, VAR22, VAR9);
input VAR6;
input VAR12;
input VAR5;
input VAR22;
input [3:0] VAR9;
input [2:0] VAR15;
input [31:0] VAR20;
output [31:0] VAR4, VAR18;
output VAR16;
output VAR19;
output VAR2;
integer VAR3;
integer VAR23;
integer VAR1;
intege... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_ground_hvc_wpad/sky130_fd_io__top_ground_hvc_wpad.behavioral.v | 1,099 | module MODULE1 ( VAR4, VAR11, VAR1
);
inout VAR4;
inout VAR11;
inout VAR1;
supply1 VAR15;
supply1 VAR13;
supply0 VAR16;
supply0 VAR9;
supply1 VAR17;
supply1 VAR5;
supply1 VAR8;
supply1 VAR3;
supply1 VAR12;
supply1 VAR10;
supply1 VAR7;
supply1 VAR6;
supply0 VAR18;
supply0 VAR19;
supply0 VAR14;
supply0 VAR2;
assign VAR9 ... | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/verilog/rc4_old.v | 2,769 | module MODULE1(ready, VAR2, clk, rst, VAR6, VAR1);
parameter VAR3 = 8;
output reg ready; output reg [7:0] VAR2;
input clk;
input rst;
input [7:0] VAR6; input VAR1;
reg [7:0] VAR9[0:VAR3-1];
reg [3:0] state;
reg [7:0] VAR8[0:255];
reg [7:0] VAR10;
reg [7:0] VAR7;
reg [7:0] VAR5;
reg [7:0] VAR4; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b_1.v | 2,000 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR1 ,
VAR2,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR2;
input VAR4;
VAR6 VAR3 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR7 ,
VAR5 ,
VAR1
);
output VAR7 ;
input VAR5 ;
input VAR1;
supply1 VAR2;
supply0 VAR4;
VAR6 VAR3... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/md.v | 2,981 | module MODULE1 (
clk ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR13 ,
VAR2 ,
VAR11 ,
VAR6 ,
VAR8 ,
VAR12 ,
VAR9 ,
VAR10 ,
VAR14
);
input clk ; input VAR7 ; output [1:0] VAR3 ; output [1:0] VAR4 ; output [1:0] VAR13 ; input VAR2 ; input [4:0] VAR11 ; input [VAR5*32-1:0] VAR6 ; output VAR8 ;
output [20:0] VAR12; output [((2^VAR1)^2)*6-1:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd/sky130_fd_sc_hd__tapvgnd.functional.v | 1,097 | module MODULE1 ();
endmodule | apache-2.0 |
dries007/Basys3 | FPGA-Z/FPGA-Z.ip_user_files/ip/Mem/Mem_stub.v | 1,285 | module MODULE1(VAR1, VAR6, VAR4, VAR5, VAR2, VAR3)
;
input VAR1;
input VAR6;
input [0:0]VAR4;
input [16:0]VAR5;
input [7:0]VAR2;
output [7:0]VAR3;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2.functional.pp.v | 1,827 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR2 ,
VAR11,
VAR12,
VAR1 ,
VAR9
);
output VAR4 ;
input VAR6 ;
input VAR2 ;
input VAR11;
input VAR12;
input VAR1 ;
input VAR9 ;
wire VAR13 ;
wire VAR3;
xnor VAR8 (VAR13 , VAR6, VAR2 );
VAR7 VAR5 (VAR3, VAR13, VAR11, VAR12);
buf VAR10 (VAR4 , VAR3 );
endmodule | apache-2.0 |
bkboggy/MIPS | MEM_WB.v | 1,188 | module MODULE1(
input clk,
input [1:0] VAR1,
input [31:0] VAR4,
input [31:0] VAR2,
input [4:0] VAR3,
output reg [1:0] VAR8,
output reg [31:0] VAR5,
output reg [31:0] VAR7,
output reg [4:0] VAR6);
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b.behavioral.pp.v | 1,971 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR11 ,
VAR12 ,
VAR13,
VAR5,
VAR9 ,
VAR1
);
output VAR8 ;
input VAR2 ;
input VAR11 ;
input VAR12 ;
input VAR13;
input VAR5;
input VAR9 ;
input VAR1 ;
wire VAR16 ;
wire VAR15 ;
wire VAR3;
not VAR4 (VAR16 , VAR2 );
nand VAR10 (VAR15 , VAR11, VAR16, VAR12 );
VAR14 VAR7 (VAR3, VAR15, VAR13, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4/sky130_fd_sc_hs__nand4.behavioral.v | 1,738 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR12 ,
VAR2 ,
VAR13 ,
VAR10,
VAR6
);
output VAR8 ;
input VAR9 ;
input VAR12 ;
input VAR2 ;
input VAR13 ;
input VAR10;
input VAR6;
wire VAR4 ;
wire VAR11;
nand VAR7 (VAR4 , VAR13, VAR2, VAR12, VAR9 );
VAR3 VAR5 (VAR11, VAR4, VAR10, VAR6);
buf VAR1 (VAR8 , VAR11 );
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/timer/timer.v | 5,395 | module MODULE1 (
input wire clk,
input wire reset,
input wire VAR12,
input wire VAR5,
input wire VAR20,
input wire [VAR17] addr,
input wire [VAR10] VAR13,
output reg [VAR10] VAR2,
output reg VAR8,
output reg irq
);
reg VAR11;
reg VAR6;
reg [VAR10] VAR14;
reg [VAR10] counter;
wire VAR15 = ((VAR6 == VAR16) && (counter ==... | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_input_if.v | 9,812 | module MODULE1
VAR3 = 64,
VAR42 = 8,
VAR6 = 33,
VAR28 = 3,
VAR71 = 1,
VAR17 = 2,
VAR5 = "VAR32"
)
(
VAR84,
VAR62,
VAR18,
VAR83,
VAR12,
VAR81,
VAR22,
VAR74,
VAR41,
VAR76,
VAR48,
VAR2,
VAR54,
VAR67,
VAR7,
VAR4,
VAR82,
VAR80,
VAR21,
VAR72,
VAR65,
VAR43,
VAR31,
VAR57,
VAR66,
VAR8,
VAR19,
VAR25,
VAR58,
VAR9,
VAR53,
VAR27,
V... | gpl-3.0 |
gajjanag/6111_Project | src/accel_lut.v | 222,177 | module MODULE1(input clk, input[11:0] VAR1, output reg[75:0] VAR2);
always @(posedge clk) begin
case (VAR1)
12'd0: VAR2 = 76'd166903815503556664320;
12'd1: VAR2 = 76'd166903815503556664320;
12'd2: VAR2 = 76'd166903815503556664320;
12'd3: VAR2 = 76'd166903815503556664320;
12'd4: VAR2 = 76'd166903815503556664320;
12'd5: ... | gpl-3.0 |
manili/Pipelined_6502 | Effective_Address.v | 24,785 | module MODULE1(
VAR32,
VAR63,
VAR46,
VAR60,
VAR45,
VAR25,
VAR26,
VAR54,
VAR38,
VAR21,
VAR68,
VAR59,
VAR39,
VAR61,
VAR33,
VAR37,
VAR30,
VAR31,
VAR53,
VAR41
,VAR69
);
input wire VAR32;
input wire VAR63;
input wire VAR46;
input wire VAR60;
input wire [1:0] VAR45;
input wire [7:0] VAR25;
input wire [7:0] VAR26;
input wire ... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/TriState.v | 1,625 | module MODULE1
(
VAR5,
VAR3,
VAR4, VAR1
);
parameter VAR2 = 1;
input VAR4;
input [VAR2-1:0] VAR1;
output [VAR2-1:0] VAR5;
inout [VAR2-1:0] VAR3;
assign VAR3 = (VAR4) ? VAR1 : { VAR2 { 1'VAR6 } };
assign VAR5 = VAR3;
endmodule | lgpl-3.0 |
os-cillation/easyfpga-soc | easy_cores/spi/fifo4.v | 4,345 | module MODULE1(clk, rst, VAR8, din, VAR6, dout, VAR5, VAR4, VAR3);
parameter VAR10 = 8;
input clk, rst;
input VAR8;
input [VAR10:1] din;
input VAR6; output [VAR10:1] dout;
input VAR5; output VAR4, VAR3;
reg [VAR10:1] VAR2[0:3];
reg [1:0] VAR12; reg [1:0] VAR1; wire [1:0] VAR7; wire [1:0] VAR11; wire VAR4, VAR3;
reg VAR... | gpl-3.0 |
jameshegarty/rigel | platform/verilator/RAMB16_S36_S36.v | 3,540 | module MODULE1(
input VAR4,
input VAR58,
input VAR70,
input VAR25,
input [8:0] VAR26,
input [31:0] VAR49,
input [3:0] VAR38,
output [31:0] VAR47,
input VAR21,
input VAR3,
input VAR60,
input VAR66,
input [8:0] VAR48,
input [31:0] VAR2,
input [3:0] VAR65,
output [31:0] VAR83);
parameter VAR16 = "VAR11";
parameter VAR37 =... | mit |
CospanDesign/python | game/panda/panda_path/example_project/rtl/bus/interconnect/wishbone_mem_interconnect.v | 3,386 | module MODULE1 (
input clk,
input rst,
input VAR21,
input VAR22,
input VAR1,
input [3:0] VAR2,
input [31:0] VAR17,
input [31:0] VAR14,
output reg [31:0] VAR4,
output reg VAR10,
output reg VAR3,
output VAR12,
output VAR15,
output VAR11,
output [3:0] VAR16,
input VAR9,
output [31:0] VAR20,
input [31:0] VAR8,
output [31:0... | mit |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_systeminit_dmg.v | 7,078 | module MODULE1
parameter VAR46 = "VAR25" ,
parameter VAR11 = 4 , parameter VAR52 = 16 , parameter VAR24 = "VAR9.VAR33"
) (
input [VAR11-1 : 0] VAR55 ,
input clk ,
input VAR48 ,
output [31 : 0] VAR51
);
VAR30 #(
.VAR39 (VAR11 ),
.VAR13 ("0" ),
.VAR54 (VAR52),
.VAR46 (VAR46 ),
.VAR37 (1 ),
.VAR41 (0 ),
.VAR31 (0 ),
.VAR2... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s0_jtag_debug_module_sysclk.v | 6,946 | module MODULE1 (
clk,
VAR33,
VAR6,
VAR16,
VAR12,
VAR15,
VAR3,
VAR25,
VAR2,
VAR8,
VAR28,
VAR5,
VAR9,
VAR30,
VAR20,
VAR31,
VAR23,
VAR24,
VAR21
)
;
output [ 37: 0] VAR15;
output VAR3;
output VAR25;
output VAR2;
output VAR8;
output VAR28;
output VAR5;
output VAR9;
output VAR30;
output VAR20;
output VAR31;
output VAR23;
out... | gpl-2.0 |
Separius/DigitalLogicDesign-FixedPoint-LnComputation | CA6_Quartus/frac_rom_bb.v | 4,967 | module MODULE1 (
address,
VAR2,
VAR1);
input [3:0] address;
input VAR2;
output [7:0] VAR1;
tri1 VAR2;
endmodule | gpl-3.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/arriagx_dmem.v | 7,448 | module MODULE1 (
address,
VAR7,
VAR4,
VAR10,
VAR47,
VAR41,
VAR8);
input [9:0] address;
input [1:0] VAR7;
input VAR4;
input VAR10;
input [15:0] VAR47;
input VAR41;
output [15:0] VAR8;
tri1 [1:0] VAR7;
tri1 VAR4;
tri1 VAR10;
wire [15:0] VAR55;
wire [15:0] VAR8 = VAR55[15:0];
VAR30 VAR27 (
.VAR29 (VAR4),
.VAR6 (VAR41),
.V... | bsd-3-clause |
kyzhai/NUNY | src/hardware/pizza.v | 6,352 | module MODULE1 (
address,
VAR45,
VAR11);
input [11:0] address;
input VAR45;
output [11:0] VAR11;
tri1 VAR45;
wire [11:0] VAR29;
wire [11:0] VAR11 = VAR29[11:0];
VAR34 VAR47 (
.VAR2 (address),
.VAR28 (VAR45),
.VAR22 (VAR29),
.VAR3 (1'b0),
.VAR52 (1'b0),
.VAR33 (1'b1),
.VAR13 (1'b0),
.VAR19 (1'b0),
.VAR27 (1'b1),
.VAR38 ... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/axi_basic_rx.v | 8,365 | module MODULE1 #(
parameter VAR34 = 128, parameter VAR16 = "VAR21", parameter VAR24 = "VAR10", parameter VAR23 = "VAR10", parameter VAR22 = 1,
parameter VAR18 = (VAR34 == 128) ? 2 : 1, parameter VAR1 = VAR34 / 8 ) (
output [VAR34-1:0] VAR15, output VAR26, input VAR30, output [VAR1-1:0] VAR25, output VAR28, output [21:0... | lgpl-3.0 |
freecores/eco32 | fpga/src/rom/rom.v | 2,755 | module MODULE1(clk, reset,
en, wr, VAR5, addr,
VAR8, VAR4,
VAR11, VAR7, VAR1, VAR6, VAR9, VAR2, VAR10);
input clk;
input reset;
input en;
input wr;
input [1:0] VAR5;
input [20:0] addr;
output reg [31:0] VAR8;
output reg VAR4;
output VAR11;
output VAR7;
output VAR1;
output VAR6;
output VAR9;
output [19:0] VAR2;
input [1... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.functional.pp.v | 1,702 | module MODULE1( VAR18, VAR4, VAR10, VAR2, VAR1, VAR11, VAR17, VAR5 );
input VAR11, VAR1, VAR4, VAR18, VAR2;
inout VAR17, VAR5;
output VAR10;
wire VAR21;
not VAR13( VAR21, VAR11 );
wire VAR6;
not VAR20( VAR6, VAR1 );
wire VAR8;
and VAR14( VAR8, VAR21, VAR6 );
wire VAR16;
not VAR23( VAR16, VAR4 );
wire VAR7;
not VAR19( V... | apache-2.0 |
ptracton/pmodacl2 | soc/xilinx/RAM32M.v | 13,611 | module MODULE1 #(
parameter VAR22 = "VAR3",
parameter [63:0] VAR33 = 64'h0000000000000000,
parameter [63:0] VAR10 = 64'h0000000000000000,
parameter [63:0] VAR47 = 64'h0000000000000000,
parameter [63:0] VAR26 = 64'h0000000000000000,
parameter [0:0] VAR42 = 1'b0
)(
output [1:0] VAR44,
output [1:0] VAR38,
output [1:0] VAR... | mit |
amrmorsey/Digital-Design-Project | DES_main.v | 2,237 | module MODULE1(
clk,
rst,
select,
VAR52,
VAR4,
VAR10
);
input clk;
input rst;
input select;
input [64:1] VAR4;
output [64:1] VAR10;
input [64:1] VAR52;
wire [32:1] VAR68, VAR71;
VAR63 VAR56(VAR52, VAR71, VAR68,select);
wire [48:1] VAR28,VAR13,VAR2,VAR24,VAR36,VAR27,VAR8,VAR60,VAR49,VAR7,VAR54,VAR32,VAR74,VAR29,VAR47,VA... | gpl-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_s00_regslice_0/synth/zc702_s00_regslice_0.v | 15,525 | module MODULE1 (
VAR60,
VAR98,
VAR92,
VAR41,
VAR66,
VAR79,
VAR86,
VAR13,
VAR100,
VAR17,
VAR46,
VAR1,
VAR42,
VAR62,
VAR9,
VAR70,
VAR28,
VAR112,
VAR54,
VAR36,
VAR63,
VAR61,
VAR49,
VAR35,
VAR57,
VAR109,
VAR8,
VAR93,
VAR99,
VAR53,
VAR96,
VAR7,
VAR102,
VAR29,
VAR78,
VAR43,
VAR68,
VAR12,
VAR22,
VAR55,
VAR77,
VAR94,
VAR20,
VA... | mit |
alankarkotwal/lca-processor | pipeline/pc_forwarding.v | 1,624 | module MODULE1(clk,VAR19,VAR28,VAR20,VAR12,VAR25,VAR3);
parameter VAR14 = 6'b000000;
parameter VAR22 = 6'b001000;
parameter VAR32 = 6'b000010;
parameter VAR4 = 6'b000001;
parameter VAR18 = 4'b0001;
parameter VAR8 = 6'b001010;
parameter VAR16 = 6'b001001;
parameter VAR5 = 4'b0011;
parameter VAR23 = 4'b0100;
parameter VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai_4.v | 2,457 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR12 ,
VAR5 ,
VAR10 ,
VAR7 ,
VAR8,
VAR3,
VAR9 ,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR12 ;
input VAR5 ;
input VAR10 ;
input VAR7 ;
input VAR8;
input VAR3;
input VAR9 ;
input VAR2 ;
VAR11 VAR6 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(... | apache-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/pixelq_op_Mat2AXIvideo.v | 17,912 | module MODULE1 (
VAR26,
VAR43,
VAR6,
VAR86,
VAR90,
VAR47,
VAR68,
VAR18,
VAR29,
VAR48,
VAR3,
VAR83,
VAR34,
VAR40,
VAR69,
VAR16,
VAR7,
VAR94,
VAR9,
VAR93,
VAR19,
VAR65,
VAR56,
VAR84,
VAR77,
VAR82,
VAR13,
VAR39,
VAR23,
VAR57,
VAR30,
VAR44,
VAR59,
VAR24,
VAR75,
VAR72,
VAR35,
VAR67,
VAR85
);
parameter VAR8 = 1'b1;
parameter... | gpl-2.0 |
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