repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3/sky130_fd_sc_ms__and3_1.v | 2,164 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR9 ,
VAR6 ,
VAR3,
VAR8,
VAR5 ,
VAR10
);
output VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR3;
input VAR8;
input VAR5 ;
input VAR10 ;
VAR2 VAR4 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
mbus/mbus | releases/mbus_example-v1.2/verilog/timer.v | 2,692 | module MODULE1
(
VAR5,
VAR1,
VAR6,
VAR10,
VAR4,
VAR9,
VAR3,
VAR11
);
input VAR5;
input VAR1;
input VAR6;
input [7:0] VAR4;
input VAR10;
input VAR9;
output reg [7:0] VAR3;
output reg VAR11;
reg [7:0] VAR8;
reg VAR2;
always @* begin
if (~VAR1) begin
VAR8 <= 8'h00;
end
else if (VAR6) begin
if (VAR3 == VAR4) begin
if (VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfsbp/sky130_fd_sc_ls__sdfsbp.behavioral.v | 2,922 | module MODULE1 (
VAR1 ,
VAR30 ,
VAR33 ,
VAR8 ,
VAR12 ,
VAR6 ,
VAR29
);
output VAR1 ;
output VAR30 ;
input VAR33 ;
input VAR8 ;
input VAR12 ;
input VAR6 ;
input VAR29;
supply1 VAR13;
supply0 VAR24;
supply1 VAR22 ;
supply0 VAR14 ;
wire VAR7 ;
wire VAR19 ;
wire VAR25 ;
reg VAR21 ;
wire VAR15 ;
wire VAR9 ;
wire VAR11 ;
wir... | apache-2.0 |
lab1-ufba/Genius | rom_botao_bb.v | 5,058 | module MODULE1 (
address,
VAR2,
VAR1);
input [6:0] address;
input VAR2;
output [20:0] VAR1;
tri1 VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a.functional.pp.v | 2,171 | module MODULE1 (
VAR8 ,
VAR10,
VAR9,
VAR17 ,
VAR12 ,
VAR2,
VAR6,
VAR15 ,
VAR3
);
output VAR8 ;
input VAR10;
input VAR9;
input VAR17 ;
input VAR12 ;
input VAR2;
input VAR6;
input VAR15 ;
input VAR3 ;
wire VAR11 ;
wire VAR7 ;
wire VAR4 ;
wire VAR13;
nand VAR19 (VAR11 , VAR9, VAR10 );
or VAR16 (VAR7 , VAR12, VAR17 );
and ... | apache-2.0 |
SymbiFlow/sphinxcontrib-hdl-diagrams | docs/code/verilog/carry4-bits.v | 1,266 | module MODULE1(output [3:0] VAR9, VAR11, input VAR1, VAR3, input [3:0] VAR7, VAR15);
wire VAR5 = VAR1 | VAR3;
VAR16 VAR2 (.VAR11(VAR9[0]), .VAR1(VAR5), .VAR7(VAR7[0]), .VAR15(VAR15[0]));
VAR16 VAR13 (.VAR11(VAR9[1]), .VAR1(VAR9[0]), .VAR7(VAR7[1]), .VAR15(VAR15[1]));
VAR16 VAR12 (.VAR11(VAR9[2]), .VAR1(VAR9[1]), .VAR7(... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_pcie_pipe_misc.v | 8,531 | module MODULE1 #
(
parameter VAR29 = 0, parameter VAR27 = 1 )
(
input wire VAR28 , input wire VAR24 , input wire VAR18 , input wire VAR11 , input wire [2:0] VAR31 , input wire VAR16 ,
output wire VAR23 , output wire VAR13 , output wire VAR19 , output wire VAR10 , output wire [2:0] VAR21 , output wire VAR9 ,
input wire ... | mit |
ridecore/ridecore | src/fpga/pipeline_if.v | 2,647 | module MODULE1
(
input wire clk,
input wire reset,
input wire [VAR7-1:0] VAR10,
output wire VAR3,
output wire [VAR7-1:0] VAR30,
output wire [VAR14-1:0] VAR33,
output wire [VAR14-1:0] VAR26,
output wire VAR32,
input wire VAR5,
input wire [VAR7-1:0] VAR13,
input wire [VAR7-1:0] VAR27,
input wire VAR20,
input wire [VAR2-1... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111oi/sky130_fd_sc_ls__a2111oi_4.v | 2,461 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR7 ,
VAR11 ,
VAR9 ,
VAR2 ,
VAR4,
VAR12,
VAR1 ,
VAR6
);
output VAR10 ;
input VAR8 ;
input VAR7 ;
input VAR11 ;
input VAR9 ;
input VAR2 ;
input VAR4;
input VAR12;
input VAR1 ;
input VAR6 ;
VAR3 VAR5 (
.VAR10(VAR10),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3_0.v | 2,175 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR10 ,
VAR8 ,
VAR9,
VAR3,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR4 ;
input VAR10 ;
input VAR8 ;
input VAR9;
input VAR3;
input VAR2 ;
input VAR1 ;
VAR5 VAR6 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
DougFirErickson/parallella-hw | fpga/ip/xilinx/fifo_async_103x16/fifo_async_103x16/fifo_async_103x16_stub.v | 1,493 | module MODULE1(rst, VAR2, VAR1, din, VAR7, VAR4, dout, VAR5, VAR3, VAR6)
;
input rst;
input VAR2;
input VAR1;
input [102:0]din;
input VAR7;
input VAR4;
output [102:0]dout;
output VAR5;
output VAR3;
output VAR6;
endmodule | gpl-3.0 |
drichmond/riffa | fpga/xilinx/ac701/AC701_Gen2x4If128/hdl/AC701_Gen2x4If128.v | 20,974 | module MODULE1
parameter VAR69 = 4,
parameter VAR16 = 128,
parameter VAR14 = 256,
parameter VAR183 = 5
)
(output [(VAR69 - 1) : 0] VAR156,
output [(VAR69 - 1) : 0] VAR72,
input [(VAR69 - 1) : 0] VAR52,
input [(VAR69 - 1) : 0] VAR37,
output [3:0] VAR114,
input VAR180,
input VAR49,
input VAR122
);
wire VAR88;
wire VAR173... | bsd-3-clause |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_leds_pio_0.v | 2,228 | module MODULE1 (
address,
VAR3,
clk,
VAR7,
VAR5,
VAR8,
VAR2,
VAR9
)
;
output [ 7: 0] VAR2;
output [ 31: 0] VAR9;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR7;
input VAR5;
input [ 31: 0] VAR8;
wire VAR6;
reg [ 7: 0] VAR1;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR4;
wire [ 31: 0] VAR9;
assign VAR6 = 1;
assign VAR4 ... | gpl-3.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/megacells/fifo_1kx16_bb.v | 5,864 | module MODULE1 (
VAR6,
VAR1,
VAR2,
VAR5,
VAR9,
VAR7,
VAR10,
VAR3,
VAR4,
VAR8);
input VAR6;
input VAR1;
input [15:0] VAR2;
input VAR5;
input VAR9;
output VAR7;
output VAR10;
output VAR3;
output [15:0] VAR4;
output [9:0] VAR8;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbn/sky130_fd_sc_ms__dlrbn.pp.blackbox.v | 1,436 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR9,
VAR5 ,
VAR3 ,
VAR4 ,
VAR1 ,
VAR6 ,
VAR8
);
output VAR2 ;
output VAR7 ;
input VAR9;
input VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2.blackbox.v | 1,288 | module MODULE1 (
VAR3,
VAR6
);
output VAR3;
input VAR6;
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_arb_rd.v | 3,763 | module MODULE1(
VAR27,
VAR11,
VAR15,
VAR7,
VAR28,
VAR9,
VAR5,
VAR21,
VAR4,
VAR10,
VAR23,
VAR1,
VAR3,
VAR24,
VAR25,
VAR12,
VAR17,
VAR8,
VAR2,
VAR18
);
input VAR27, VAR11;
input [VAR19-1:0] VAR15,VAR7;
input VAR28, VAR9;
input [VAR13-1:0] VAR4, VAR10;
input [VAR22:0] VAR5, VAR21;
output reg VAR3, VAR24;
output reg [VAR20... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_2.v | 2,583 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR1 ,
VAR11 ,
VAR7 ,
VAR9,
VAR2 ,
VAR10 ,
VAR3 ,
VAR5
);
output VAR4 ;
input VAR6 ;
input VAR1 ;
input VAR11 ;
input VAR7 ;
input VAR9;
input VAR2 ;
input VAR10 ;
input VAR3 ;
input VAR5 ;
VAR12 VAR8 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR2(... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_video_resizer/rtl/axi_video_resizer.v | 15,391 | module MODULE1 #(
parameter VAR14 = 1,
parameter VAR40 = 1,
parameter VAR13 = 9,
parameter VAR79 = 4,
parameter VAR29 = 32,
parameter VAR109 = (VAR29 / 8),
parameter VAR27 = 24,
parameter VAR128 = 1280,
parameter VAR5 = 720,
parameter VAR26 = VAR128 * VAR5,
parameter VAR130 = 1280,
parameter VAR18 = 720,
parameter VAR1... | mit |
aj-michael/Digital-Systems | Lab6-Part1/ControllerI2C.v | 3,507 | module MODULE1(VAR22,VAR26,VAR29,VAR2,VAR30,VAR16,VAR27,VAR14,VAR5,VAR18);
input VAR22, VAR26, VAR29, VAR2;
output reg VAR30, VAR16, VAR27, VAR14, VAR5, VAR18;
parameter VAR12 = 3'd0;
parameter VAR9 = 3'd1;
parameter VAR19 = 3'd2;
parameter VAR10 = 3'd3;
parameter VAR1 = 3'd4;
parameter VAR23 = 3'd5;
parameter VAR20 = ... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9467/axi_ad9467_channel.v | 5,558 | module MODULE1(
VAR25,
VAR62,
VAR54,
VAR56,
VAR36,
VAR49,
VAR34,
VAR55,
VAR51,
VAR24,
VAR8,
VAR65,
VAR29,
VAR19,
VAR44,
VAR63,
VAR45,
VAR31,
VAR12);
parameter VAR11 = 0;
input VAR25;
input VAR62;
input [15:0] VAR54;
input VAR56;
output [15:0] VAR36;
output VAR49;
output VAR34;
output VAR55;
output VAR51;
input VAR24;
i... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfstp/sky130_fd_sc_hs__sdfstp.symbol.v | 1,462 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR8,
input VAR7 ,
input VAR5 ,
input VAR4
);
supply1 VAR6;
supply0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/decap/sky130_fd_sc_ms__decap.functional.v | 1,039 | module MODULE1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311a/sky130_fd_sc_ms__o311a.behavioral.pp.v | 2,053 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR13 ,
VAR16 ,
VAR12 ,
VAR11 ,
VAR2,
VAR1,
VAR8 ,
VAR6
);
output VAR7 ;
input VAR9 ;
input VAR13 ;
input VAR16 ;
input VAR12 ;
input VAR11 ;
input VAR2;
input VAR1;
input VAR8 ;
input VAR6 ;
wire VAR5 ;
wire VAR15 ;
wire VAR18;
or VAR17 (VAR5 , VAR13, VAR9, VAR16 );
and VAR10 (VAR15 , VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.behavioral.pp.v | 2,375 | module MODULE1( VAR8, VAR10, VAR6, VAR4, VAR7, VAR5, VAR9 );
input VAR7, VAR4, VAR10, VAR8;
inout VAR5, VAR9;
output VAR6;
VAR3 VAR1(.VAR8(VAR8),.VAR10(VAR10),.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5),.VAR9(VAR9));
VAR3 VAR2(.VAR8(VAR8),.VAR10(VAR10),.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5),.VAR9(VAR9)); | apache-2.0 |
efabless/openlane | designs/md5/src/md5.v | 11,550 | module MODULE1(clk,reset,VAR49,VAR34,VAR45,VAR32,VAR8);
input clk;
input reset;
input VAR49;
output VAR34;
input VAR45;
input [127:0] VAR32;
output [127:0] VAR8;
reg VAR34, VAR9;
reg [127:0] VAR8, VAR16;
reg [5:0] VAR10, VAR25;
reg [43:0] VAR50;
reg [31:0] VAR31,VAR35,VAR44,VAR47,VAR19, VAR13,VAR37, VAR48, VAR17;
reg [... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_1/zqynq_lab_1_design_axi_gpio_1_1_stub.v | 2,420 | module MODULE1(VAR11, VAR7, VAR8,
VAR18, VAR5, VAR9, VAR15, VAR13, VAR6,
VAR16, VAR2, VAR17, VAR10, VAR4, VAR3,
VAR12, VAR19, VAR1, VAR14, VAR20, VAR21)
;
input VAR11;
input VAR7;
input [8:0]VAR8;
input VAR18;
output VAR5;
input [31:0]VAR9;
input [3:0]VAR15;
input VAR13;
output VAR6;
output [1:0]VAR16;
output VAR2;
inp... | mit |
cpulabs/mist1032isa | src/dps/sci/dps_uart.v | 5,941 | module MODULE1(
input wire VAR32,
input wire VAR24,
input wire [3:0] VAR18,
input wire VAR38,
input wire VAR54,
input wire VAR10,
output wire VAR45,
input wire [7:0] VAR25,
output wire [3:0] VAR17,
output wire VAR47,
input wire VAR46,
input wire VAR14,
input wire VAR4,
output wire VAR23,
output wire [7:0] VAR21,
output... | bsd-2-clause |
saiedhk/WhirlpoolHashEngine | whirlpool_wcipher_round.v | 9,605 | module MODULE1 (
output [0:511] VAR192,
input [0:511] VAR74,
input [0:511] VAR115
);
wire [7:0] VAR99, VAR5, VAR245, VAR111, VAR260, VAR207, VAR198, VAR191,
VAR83, VAR223, VAR208, VAR268, VAR25, VAR90, VAR203, VAR167,
VAR161, VAR137, VAR11, VAR64, VAR249, VAR173, VAR26, VAR159,
VAR105, VAR149, VAR38, VAR53, VAR91, VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp.behavioral.v | 2,923 | module MODULE1 (
VAR25,
VAR28 ,
VAR27 ,
VAR18 ,
VAR5 ,
VAR24 ,
VAR19 ,
VAR11 ,
VAR10
);
input VAR25;
input VAR28 ;
input VAR27 ;
output VAR18 ;
output VAR5 ;
input VAR24 ;
input VAR19 ;
input VAR11 ;
input VAR10 ;
wire VAR9 ;
wire VAR8 ;
wire VAR29 ;
reg VAR30 ;
wire VAR23 ;
wire VAR21 ;
wire VAR2 ;
wire VAR3;
wire VAR... | apache-2.0 |
gyurco/ZX_Spectrum-128K_MIST | mouse.v | 2,097 | module MODULE1
(
input VAR7,
input reset,
input [24:0] VAR12,
input [2:0] addr,
output sel,
output [7:0] dout
);
assign dout = VAR1;
assign sel = VAR10;
reg [1:0] VAR6;
reg VAR13;
reg [11:0] VAR9;
reg [11:0] VAR5;
wire [11:0] VAR8 = VAR9 + {{4{VAR12[4]}},VAR12[15:8]};
wire [11:0] VAR11 = VAR5 + {{4{VAR12[5]}},VAR12[23:... | gpl-2.0 |
AbhishekShah212/School_Projects | ELEN232/pset5/FullAdder.v | 1,772 | module MODULE1(
input [3:0] VAR17,
input [3:0] VAR18,
input VAR16,
output [3:0] VAR19,
output VAR12
);
wire VAR20, VAR15, VAR4;
VAR7 VAR3 (
.VAR17(VAR17[0]),
.VAR18(VAR18[0] ^ VAR16), .VAR19(VAR19[0]),
.VAR5(VAR20),
.VAR8(VAR16)
);
VAR7 VAR11 (
.VAR17(VAR17[1]),
.VAR18(VAR18[1] ^ VAR16),
.VAR19(VAR19[1]),
.VAR5(VAR15),... | mit |
mamijaz/RISC-V | src/riscv_pipeline/write_back/MULTIPLEXER_2_TO_1.v | 1,126 | module MODULE1 #(
parameter VAR6 = 32
) (
input [VAR6 - 1 : 0] VAR5 ,
input [VAR6 - 1 : 0] VAR4 ,
input VAR1 ,
output [VAR6 - 1 : 0] VAR3
);
reg [VAR6 - 1 : 0] VAR2;
always@(*)
begin
case(VAR1)
1'b0:
begin
VAR2 = VAR5;
end
1'b1:
begin
VAR2 = VAR4;
end
endcase
end
assign VAR3 = VAR2;
endmodule | bsd-2-clause |
ashikpoojari/NIDS-Wu-Manber | Wu_Manber_register.v | 1,654 | module MODULE1 #(parameter VAR5=8)
(input clk,
input reset,
input VAR4,
input VAR3,
input [VAR5-1:0] VAR2,
output reg [VAR5-1:0] VAR1);
always @ (posedge clk) begin
if(VAR4 || reset)
VAR1 <= 0;
end
else if(VAR3) begin
VAR1 <= VAR2;
end
end
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_4.behavioral.pp.v | 1,164 | module MODULE1( VAR3, VAR7, VAR4, VAR6 );
input VAR3;
inout VAR4, VAR6;
output VAR7;
VAR2 VAR5(.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6));
VAR2 VAR1(.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6)); | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_nios2_qsys_0.v | 5,818 | module MODULE1 (
input wire clk, input wire VAR1, input wire VAR9, output wire [18:0] VAR22, output wire [3:0] VAR17, output wire VAR8, input wire [31:0] VAR23, input wire VAR25, output wire VAR6, output wire [31:0] VAR26, output wire VAR21, output wire [18:0] VAR18, output wire VAR3, input wire [31:0] VAR13, input wir... | gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_s_r_channel.v | 26,077 | module MODULE1
parameter VAR107 = 32'hffffffff,
parameter VAR176 = 32'h00000000,
parameter VAR20 = 1 ,
parameter VAR134 = 0 ,
parameter VAR14 = 1 ,
parameter VAR59 = 8 ,
parameter VAR44 = 32 ,
parameter VAR37 = 1 ,
parameter VAR78 = 0
) (
input VAR58 ,
input VAR120 ,
input [VAR14-1:0] VAR34 ,
input [31:0] VAR3 ,
input ... | gpl-3.0 |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_interconnect_model.v | 16,899 | module MODULE1 (
VAR15,
VAR218,
VAR40,
VAR7,
VAR21,
VAR170,
VAR128,
VAR30,
VAR222,
VAR33,
VAR17,
VAR60,
VAR214,
VAR260,
VAR190,
VAR78,
VAR125,
VAR235,
VAR223,
VAR51,
VAR54,
VAR245,
VAR146,
VAR28,
VAR144,
VAR203,
VAR83,
VAR229,
VAR232,
VAR180,
VAR57,
VAR204,
VAR208,
VAR130,
VAR273,
VAR142,
VAR163,
VAR151,
VAR98,
VAR162,... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_axi_basic_top.v | 10,999 | module MODULE1 #(
parameter VAR4 = 128, parameter VAR59 = "VAR43", parameter VAR53 = "VAR61", parameter VAR57 = "VAR61", parameter VAR28 = 1,
parameter VAR8 = (VAR4 == 128) ? 2 : 1, parameter VAR11 = VAR4 / 8 ) (
input [VAR4-1:0] VAR9, input VAR2, output VAR24, input [VAR11-1:0] VAR50, input VAR10, input [3:0] VAR31,
o... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111a/sky130_fd_sc_ls__o2111a.pp.blackbox.v | 1,427 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR10 ,
VAR1 ,
VAR6,
VAR8,
VAR5 ,
VAR4
);
output VAR9 ;
input VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR10 ;
input VAR1 ;
input VAR6;
input VAR8;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/6d8f288943408fbb/zynq_design_1_rst_ps7_0_100M_1_stub.v | 1,880 | module MODULE1(VAR8, VAR7, VAR4,
VAR1, VAR2, VAR5, VAR6, VAR3,
VAR10, VAR9)
;
input VAR8;
input VAR7;
input VAR4;
input VAR1;
input VAR2;
output VAR5;
output [0:0]VAR6;
output [0:0]VAR3;
output [0:0]VAR10;
output [0:0]VAR9;
endmodule | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_p_src_rows_V_2_loc_channel.v | 3,043 | module MODULE2 (
clk,
VAR1,
VAR24,
VAR9,
VAR27);
parameter VAR25 = 32'd12;
parameter VAR15 = 32'd2;
parameter VAR21 = 32'd3;
input clk;
input [VAR25-1:0] VAR1;
input VAR24;
input [VAR15-1:0] VAR9;
output [VAR25-1:0] VAR27;
reg[VAR25-1:0] VAR5 [0:VAR21-1];
integer VAR7;
always @ (posedge clk)
begin
if (VAR24)
begin
for ... | gpl-3.0 |
Tommydag/CAN-Bus-Controller | CRC.v | 9,782 | module MODULE1(
input [63:0] VAR3,
input VAR1,
output [14:0] VAR4,
input rst,
input clk);
reg [14:0] VAR2 ,VAR5 ;
assign VAR4[14:0] = VAR2[14:0];
always @(*) begin
VAR5[0] = VAR2[0] ^ VAR2[2] ^ VAR2[3] ^ VAR2[8] ^ VAR2[9] ^ VAR2[12] ^ VAR2[13] ^ VAR2[14] ^ VAR3[0] ^ VAR3[1] ^ VAR3[2] ^ VAR3[3] ^ VAR3[4] ^ VAR3[6] ^ VAR... | mit |
sigilance/paper-processor | 4-bit/paper.v | 2,581 | module MODULE1;
reg VAR29 = 1'b0; reg VAR20 = 1'b1; reg VAR26 = 1'b0; reg VAR22 = 1'b1;
wire VAR24, VAR4, VAR8, VAR16;
assign VAR24 = VAR29; assign VAR4 = VAR20; assign VAR8 = VAR26; assign VAR16 = VAR22;
wire [1:0] VAR2; wire [3:0] VAR27;
wire VAR33, VAR15, VAR30, VAR7;
wire [1:0] VAR12; wire [1:0] VAR32, VAR17; wire ... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcjesdadc1/common/fmcjesdadc1_spi.v | 4,604 | module MODULE1 (
VAR14,
VAR16,
VAR11,
VAR8,
VAR10);
localparam VAR5 = 8'h00;
localparam VAR4 = 8'h84;
localparam VAR1 = 8'h80;
localparam VAR15 = 8'h81;
localparam VAR17 = 8'h82;
localparam VAR3 = 8'h83;
input VAR14;
input VAR16;
input VAR11;
output VAR8;
inout VAR10;
reg [ 7:0] VAR9 = 'd0;
reg [ 5:0] VAR2 = 'd0;
reg V... | gpl-3.0 |
kramble/FPGA-Litecoin-Miner | experimental/ZTEX/ztex_ufm1_15b1_litecoin.v | 4,608 | module MODULE1 (VAR80, reset, VAR6, VAR30, VAR63, VAR61, VAR71, VAR57, VAR21, read, write);
input VAR80, reset, VAR6, VAR30, VAR63, VAR61, VAR71, VAR57, VAR21;
input [7:0] read;
output [7:0] write;
reg [3:0] VAR38, VAR41;
reg VAR47, VAR8, VAR23;
reg VAR11, VAR2, VAR18;
reg [4:0] VAR37;
reg [671:0] VAR15, VAR36;
reg [95... | gpl-3.0 |
mshaklunov/mips_onemore | rtl/mips_alu.v | 5,528 | module MODULE1 (
input clk,
input rst,
input[2:0] VAR34,
input VAR20,
input VAR11,
input VAR21,
input VAR27,
input VAR3,
input[31:0] VAR14,
input[31:0] VAR32,
output reg[31:0] VAR19,
output VAR9,
output[31:0] VAR7,
output[31:0] VAR33,
output[63:0] VAR26
);
wire[31:0] VAR8;
wire[31:0] VAR25;
wire[31:0] VAR13;
wire[31:0]... | mit |
MeshSr/onetswitch45 | ons45-app52-ref_ofshw/vivado/onets_7045_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_aggr.v | 12,282 | module MODULE1
parameter VAR33=VAR8/8,
parameter VAR5 = 2,
parameter VAR19 = 2,
parameter VAR30 = 4,
parameter VAR63 = 8
)
( output reg [VAR8-1:0] VAR15,
output reg [VAR33-1:0] VAR32,
output reg VAR6,
input VAR58,
input [VAR8-1:0] VAR7,
input [VAR33-1:0] VAR12,
input VAR11,
output VAR13,
input [VAR8-1:0] VAR27,
input [... | lgpl-2.1 |
hydai/Verilog-Practice | DigitalDesign/hw1/hw1_101062124/hw1_A/hw1_A.v | 1,155 | module MODULE1 (
input [15:0] VAR10,
input [6:0] VAR9,
input clk,
input VAR8,
output reg [15:0] VAR12,
output reg [15:0] VAR1,
output reg [15:0] VAR6,
output reg [15:0] VAR5
);
reg [15:0] VAR7;
reg [15:0] VAR2, VAR11, VAR3, VAR4;
always @(posedge clk or negedge VAR8) begin
if (!VAR8) begin
VAR12 <= 0;
VAR1 <= 0;
VAR6 <... | mit |
davidjabon/AXI-Peripheral-Library | Four_Digit_Seven_Segment_Display_2.0/hdl/Four_Digit_Seven_Segment_Display_v2_0.v | 2,476 | module MODULE1 #
(
parameter integer VAR48 = 32,
parameter integer VAR51 = 4
)
(
output wire [6:0] VAR3,
output wire VAR50,
output wire [3:0] VAR6,
input wire VAR26,
input wire VAR44,
input wire [VAR51-1 : 0] VAR23,
input wire [2 : 0] VAR5,
input wire VAR13,
output wire VAR35,
input wire [VAR48-1 : 0] VAR40,
input wire... | gpl-2.0 |
airin711/Verilog-caches | 8way_4word.v | 25,165 | module MODULE1(clk,
rst,
VAR34,
VAR41,
VAR49,
VAR52,
VAR59,
VAR56,
VAR43,
VAR63,
VAR29,
VAR45,
VAR18,
VAR26,
VAR11,
VAR60,
VAR70,
VAR46,
VAR39,
VAR8,
VAR24,
VAR20,
VAR30,
VAR58);
parameter VAR69 = 9;
input wire clk, rst;
input wire [24:0] VAR34;
input wire [3:0] VAR41;
input wire [31:0] VAR49;
input wire VAR52, VAR59;
... | mit |
zhangly/azpr_cpu | rtl/cpu/rtl/bus_if.v | 5,676 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR9, input wire VAR10, output reg VAR26,
input wire [VAR21] addr, input wire VAR13, input wire VAR14, input wire [VAR27] VAR7, output reg [VAR27] VAR28,
input wire [VAR27] VAR29, output wire [VAR21] VAR4, output reg VAR16, output wire VAR33, output wire [VA... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/dotp_wrapper_sv.v | 2,324 | module MODULE1 (
VAR13,
VAR22,
VAR25,
VAR8,
VAR6,
VAR11,
VAR19, VAR26, VAR5, VAR1,
b0, b1, VAR12, VAR16,
VAR3
);
input VAR13;
input VAR22;
input VAR25;
input VAR8;
output VAR6;
output VAR11;
input [511:0] VAR19;
input [511:0] VAR26;
input [511:0] VAR5;
input [511:0] VAR1;
input [511:0] b0;
input [511:0] b1;
input [511:... | mit |
eSedano/vrudy | rtl/vrudy_top.v | 4,334 | module MODULE1 (
input wire clk,
input wire VAR6,
input wire [15:0] VAR4,
output wire [15:0] VAR19,
output wire [7:0] VAR9,
output wire VAR18
);
VAR1 VAR14 (
.clk ( clk ),
.VAR6 ( VAR6 ),
.VAR3 ( VAR3 ),
.VAR12 ( VAR12 ),
.VAR22 ( VAR22 ),
.VAR7 ( VAR7 ),
.VAR11 ( VAR11 ),
.VAR16 ( VAR16 ),
.VAR20 ( VAR20 ),
.VAR21 ( V... | mit |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_uart_0.v | 26,956 | module MODULE1 (
VAR69,
VAR82,
clk,
VAR45,
VAR53,
VAR56,
VAR87,
VAR86,
VAR9,
VAR79,
VAR94,
VAR39,
VAR75
)
;
output VAR79;
output VAR94;
output VAR39;
output VAR75;
input [ 15: 0] VAR69;
input VAR82;
input clk;
input VAR45;
input VAR53;
input VAR56;
input VAR87;
input [ 7: 0] VAR86;
input VAR9;
reg VAR78;
reg [ 15: 0] V... | gpl-2.0 |
gyurco/ZX_Spectrum-128K_MIST | sys/osd.v | 5,986 | module MODULE1 (
input VAR52,
input VAR55,
input VAR43,
input VAR13,
input VAR3,
input [1:0] VAR27,
input [5:0] VAR56,
input [5:0] VAR1,
input [5:0] VAR30,
input VAR54,
input VAR50,
output [5:0] VAR25,
output [5:0] VAR31,
output [5:0] VAR44
);
parameter VAR24 = 11'd0;
parameter VAR21 = 11'd0;
parameter VAR49 = 3'd0;
pa... | gpl-2.0 |
Rod2693rm/netfpga-firewal-ddos | src/tcam_bl/tcam_bl.v | 4,027 | module MODULE1(
clk,
VAR10,
VAR45,
VAR44,
din,
VAR33,
VAR27,
VAR39,
VAR1,
VAR23);
input clk;
input [31 : 0] VAR10;
input [31 : 0] VAR45;
input [31 : 0] VAR44;
input [31 : 0] din;
input VAR33;
input [10 : 0] VAR27;
output VAR39;
output VAR1;
output [2047 : 0] VAR23;
VAR17 #(
.VAR43(2),
.VAR34(32),
.VAR14(32),
.VAR22(32)... | gpl-3.0 |
Canaan-Creative/MM | verilog/superkdf9/components/twi/twi.v | 10,289 | module MODULE1(
input VAR47 ,
input VAR10 ,
input VAR48 , input VAR67 ,
input VAR57 ,
input VAR45 , input [2:0] VAR77 , input [1:0] VAR30 , input [5:0] VAR105 ,
input [31:0] VAR58 ,
input [3:0] VAR73 ,
output reg VAR79 ,
output VAR65 , output VAR44 , output [31:0] VAR19 ,
output VAR60 ,
input VAR99 ,
output VAR9 ,
outp... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfsbp/sky130_fd_sc_hd__dfsbp_2.v | 2,377 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR4 ,
VAR5 ,
VAR7,
VAR3 ,
VAR8 ,
VAR1 ,
VAR10
);
output VAR2 ;
output VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR7;
input VAR3 ;
input VAR8 ;
input VAR1 ;
input VAR10 ;
VAR11 VAR9 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VA... | apache-2.0 |
cpulabs/mist1032isa | src/core/execute/execute_adder_calc.v | 10,057 | module MODULE1(
input wire [4:0] VAR24,
input wire VAR41, input wire [31:0] VAR5,
input wire [31:0] VAR27,
input wire VAR25,
input wire [31:0] VAR36,
input wire [31:0] VAR29,
input wire [31:0] VAR37,
input wire [31:0] VAR17,
input wire [31:0] VAR6,
input wire [31:0] VAR28,
output wire VAR35,
output wire [31:0] VAR43,
o... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai.pp.symbol.v | 1,391 | module MODULE1 (
input VAR9,
input VAR1,
input VAR4 ,
input VAR2 ,
output VAR6 ,
input VAR5 ,
input VAR7,
input VAR8,
input VAR3
);
endmodule | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_s0_mm_interconnect_0_avalon_st_adapter.v | 6,182 | module MODULE1 #(
parameter VAR14 = 34,
parameter VAR24 = 0,
parameter VAR13 = 34,
parameter VAR6 = 0,
parameter VAR21 = 0,
parameter VAR3 = 0,
parameter VAR19 = 1,
parameter VAR22 = 1,
parameter VAR7 = 0,
parameter VAR9 = 34,
parameter VAR4 = 0,
parameter VAR15 = 1,
parameter VAR17 = 0,
parameter VAR1 = 1,
parameter V... | gpl-3.0 |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | FSM.v | 6,865 | module MODULE1
(
input wire clk,rst, input wire VAR1, input wire [3:0] VAR12,
input wire [3:0] VAR10,
output reg [3:0]VAR7, output reg [3:0]VAR18 );
wire [3:0] VAR13;
VAR20 VAR11 (
.VAR16(VAR1),
.VAR5(VAR12),
.VAR22(VAR10),
.VAR14(VAR13)
);
localparam [3:0]
VAR15 = 4'b0000,
VAR19 = 4'b0001, VAR8 = 4'b0010, VAR6 = 4'b00... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_107.v | 1,477 | module MODULE1 (
VAR11,
VAR2
);
input [31:0] VAR11;
output [31:0]
VAR2;
wire [31:0]
VAR13,
VAR10,
VAR7,
VAR3,
VAR9,
VAR5,
VAR6,
VAR12;
assign VAR13 = VAR11;
assign VAR12 = VAR6 << 3;
assign VAR3 = VAR13 << 2;
assign VAR5 = VAR9 << 3;
assign VAR6 = VAR13 + VAR5;
assign VAR9 = VAR7 - VAR3;
assign VAR7 = VAR10 - VAR13;
as... | mit |
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_txethmac.v | 17,254 | module MODULE1 (VAR22, VAR50, VAR47, VAR15, VAR87, VAR73, VAR84,
VAR20, VAR25, VAR57, VAR44, VAR59, VAR81, VAR24, VAR86, VAR36,
VAR80, VAR11, VAR89, VAR74, VAR27, VAR90,
VAR7, VAR40, VAR33, VAR88, VAR37, VAR18, VAR66, VAR38,
VAR5, VAR75, VAR13, VAR19, VAR34,
VAR61, VAR42, VAR28, VAR1
);
parameter VAR2 = 1;
input VAR22;... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp.symbol.v | 1,395 | module MODULE1 (
input VAR2 ,
output VAR7 ,
input VAR8,
input VAR4
);
supply1 VAR6;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3_4.v | 2,047 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR3 ,
VAR6 ,
VAR5,
VAR8
);
output VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR5;
input VAR8;
VAR4 VAR2 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR7,
VAR1,
VAR3,
VAR6
);
output VAR7;
input VAR1;
input VAR3;
in... | apache-2.0 |
MarcoVogt/basil | firmware/modules/fei4_rx/decode_8b10b.v | 6,103 | module MODULE1 (VAR44, VAR35, VAR58, VAR30, VAR56, VAR47) ;
input wire [9:0] VAR44 ;
input wire VAR35 ;
output wire [8:0] VAR58 ;
output wire VAR30 ;
output wire VAR56 ;
output wire VAR47 ;
wire VAR11 = VAR44[0] ;
wire VAR68 = VAR44[1] ;
wire VAR38 = VAR44[2] ;
wire VAR32 = VAR44[3] ;
wire VAR24 = VAR44[4] ;
wire VAR31... | bsd-3-clause |
andrzej-r/wb_sseg_ctrl | rtl/sseg_ctrl.v | 4,592 | module MODULE1
parameter VAR9 = 8,
parameter VAR14 = 8
)
(
input VAR8,
input VAR4,
input VAR21,
input VAR22,
input [15:0] VAR6,
input [7:0] VAR20,
input [VAR9*VAR14-1:0] VAR5,
output [VAR14-1:0] VAR11,
output [VAR9-1:0] VAR19,
output VAR16
);
reg [15:0] VAR12;
wire VAR1 = (VAR22 & VAR12 == 16'b0);
always @(posedge VAR8... | bsd-2-clause |
AndreaCorallo/KPU | rtl/wishbone/slaves/uart/wb_uart.v | 18,689 | module MODULE1 (
input clk,
input rst,
input VAR24,
input VAR51,
input [3:0] VAR20,
input [31:0] VAR54,
input VAR4,
output reg VAR21,
output reg [31:0] VAR30,
input [31:0] VAR62,
output VAR63,
input VAR44,
input VAR64,
output VAR31,
input VAR41,
output VAR10,
output reg VAR12
);
reg [31:0] VAR58;
reg [31:0] VAR68;
wire... | gpl-3.0 |
ultraembedded/riscv | core/riscv/riscv_regfile.v | 15,006 | module MODULE1
parameter VAR71 = 0
)
(
input VAR30
,input VAR24
,input [ 4:0] VAR29
,input [ 31:0] VAR27
,input [ 4:0] VAR37
,input [ 4:0] VAR59
,output [ 31:0] VAR80
,output [ 31:0] VAR45
);
generate
if (VAR71)
begin: VAR21
VAR70
VAR86
(
.VAR30(VAR30)
,.VAR24(VAR24)
,.VAR29(VAR29)
,.VAR27(VAR27)
,.VAR49(VAR37)
,.VAR58... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and3/sky130_fd_sc_hvl__and3.symbol.v | 1,278 | module MODULE1 (
input VAR3,
input VAR1,
input VAR6,
output VAR4
);
supply1 VAR8;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen_new/sky130_fd_io__top_refgen_new.blackbox.v | 2,463 | module MODULE1 (
VAR13 ,
VAR21 ,
VAR3 ,
VAR4 ,
VAR19 ,
VAR18 ,
VAR15 ,
VAR10 ,
VAR12 ,
VAR22,
VAR20 ,
VAR7 ,
VAR24 ,
VAR25 ,
VAR2 ,
VAR1 ,
VAR27
);
output VAR13 ;
output VAR21 ;
inout VAR3 ;
inout VAR4 ;
inout VAR19 ;
input VAR18 ;
input VAR15 ;
input VAR10 ;
input VAR12 ;
input VAR22;
input [2:0] VAR20 ;
input VAR7 ;
... | apache-2.0 |
mbus/mbus | releases/mbus_example-v1.2/verilog/mbus_ctrl.v | 4,968 | module MODULE1(
input VAR3,
input VAR36,
input VAR26,
output VAR13,
input VAR27,
output reg VAR8,
input [VAR37-1:0] VAR21
);
parameter VAR38 = 0;
parameter VAR5 = 3;
parameter VAR15 = 4;
parameter VAR11 = 1;
parameter VAR19 = 2;
parameter VAR24 = 5;
parameter VAR17 = 7;
parameter VAR9 = 6;
parameter VAR29 = 8;
paramete... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_counter.v | 3,252 | module MODULE1
(
enable, VAR5, VAR6,
VAR7,
VAR4,
VAR13,
VAR1,
VAR8,
VAR11,
VAR12,
VAR10,
VAR3
);
parameter VAR2=0; parameter VAR9=65536;
input logic VAR5;
input logic VAR6;
input logic enable;
input logic [31:0] VAR7;
input logic [31:0] VAR4;
input logic VAR1;
input logic [31:0] VAR13;
output logic [31:0] VAR8;
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/maj3/sky130_fd_sc_hd__maj3.symbol.v | 1,284 | module MODULE1 (
input VAR7,
input VAR6,
input VAR5,
output VAR8
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/Lab6/Lab6.v | 1,373 | module MODULE1( VAR4, VAR12, VAR6, VAR3, VAR23, clk, VAR11);
output [3:0] VAR4;
output [8:0] VAR12;
output [3:0] VAR6;
input [3:0] VAR3;
input [1:0] VAR23;
input clk;
input VAR11;
wire VAR24;
wire VAR19;
wire [3:0] VAR25;
wire [3:0] VAR20,VAR21;
wire [3:0] VAR10,VAR13;
wire [1:0] VAR26;
wire VAR17;
VAR14 VAR5(VAR24, cl... | mit |
cr88192/bgbtech_bjx1core | bjx1c32b/DecOp2.v | 11,005 | module MODULE1(
clk,
VAR27,
VAR8,
VAR61,
VAR31,
VAR17,
VAR46,
VAR35,
VAR28
);
input clk; input[31:0] VAR27; input[15:0] VAR8;
output[6:0] VAR61;
output[6:0] VAR31;
output[6:0] VAR17;
output[31:0] VAR46;
output[3:0] VAR35;
output[7:0] VAR28;
reg VAR21;
reg VAR47;
reg[7:0] VAR15;
reg[15:0] VAR45;
reg[6:0] VAR22;
reg[6:0]... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/ip/ip_2/synth/bd_350b_slot_0_aw_0.v | 4,561 | module MODULE1 (
VAR45,
VAR44,
dout
);
input wire [0 : 0] VAR45;
input wire [0 : 0] VAR44;
output wire [1 : 0] dout;
VAR64 #(
.VAR15(1),
.VAR2(1),
.VAR5(1),
.VAR4(1),
.VAR35(1),
.VAR54(1),
.VAR63(1),
.VAR49(1),
.VAR16(1),
.VAR50(1),
.VAR6(1),
.VAR41(1),
.VAR51(1),
.VAR37(1),
.VAR53(1),
.VAR46(1),
.VAR39(1),
.VAR3(1),
.... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_cop.v | 13,276 | module MODULE1
(
VAR55, VAR53,
VAR4, VAR51, VAR44, VAR45,
VAR14, VAR31, VAR50, VAR58,
VAR57,
VAR6, VAR36, VAR3, VAR33,
VAR17, VAR35, VAR43, VAR9,
VAR1,
VAR42, VAR19, VAR32, VAR22,
VAR24, VAR62, VAR10, VAR46,
VAR15,
VAR61, VAR25, VAR54, VAR13,
VAR27, VAR16, VAR59, VAR49,
VAR40
);
parameter VAR20 = 32'hd0000000;
paramete... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpadv2/sky130_fd_io__top_power_hvc_wpadv2.behavioral.v | 1,103 | module MODULE1 ( VAR1, VAR11, VAR4
);
inout VAR1;
inout VAR11;
inout VAR4;
supply1 VAR7;
supply1 VAR6;
supply0 VAR10;
supply1 VAR13;
supply1 VAR15;
supply1 VAR17;
supply1 VAR9;
supply1 VAR18;
supply1 VAR5;
supply1 VAR12;
supply1 VAR3;
supply1 VAR16;
supply0 VAR19;
supply0 VAR14;
supply0 VAR8;
supply0 VAR20;
tran VAR2 (... | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/AUDIO_DAC.v | 8,754 | module MODULE1 ( VAR41,VAR17,
VAR46,VAR42,
VAR5,VAR47,
VAR20,
VAR13,
VAR34,
VAR25,
VAR10,
VAR48 );
parameter VAR39 = 18432000; parameter VAR14 = 48000; parameter VAR24 = 16; parameter VAR9 = 2;
parameter VAR32 = 48;
parameter VAR40 = 1048576; parameter VAR6 = 4194304; parameter VAR45 = 262144;
parameter VAR21= 20; para... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1.pp.symbol.v | 1,387 | module MODULE1 (
input [3:0] VAR7 ,
output VAR3 ,
input [3:0] VAR1 ,
input VAR4 ,
input VAR2,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
Nrpickle/ECE272 | Lab4_SmartTekbotRemote_WORKING/Section4_Verilog.v | 1,141 | module MODULE1(
input VAR29,
input VAR12,
input VAR3,
input VAR14,
input VAR27,
output VAR21,
output VAR18,
output VAR17,
output VAR10
);
wire VAR9;
wire VAR15;
wire VAR35;
wire VAR2;
wire VAR8;
wire VAR5;
wire VAR20;
wire VAR4;
supply0 VAR19;
assign VAR4 = VAR14 & VAR27;
MODULE3 VAR28(.VAR29(VAR29), .VAR13(VAR9));
MOD... | mit |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_fdest.v | 3,950 | module MODULE1 #(
parameter VAR18 = 26
) (
input VAR3,
input VAR21,
output [VAR18-1:0] VAR15,
output reg VAR10,
input VAR17,
input [63:0] VAR9,
input VAR5,
output VAR11,
input VAR14,
input VAR6,
output reg VAR16,
input [15:0] VAR7,
input [VAR18-1-1:0] VAR4,
output VAR8,
input VAR23,
output reg [15:0] VAR1,
output [VAR1... | lgpl-3.0 |
AbhishekShah212/School_Projects | ELEN232/pset1/Problem4.v | 1,299 | module MODULE1(
input VAR3,
input VAR4,
input VAR1,
input VAR2,
input VAR5,
output VAR6
);
assign VAR6 = (~VAR3 & ~VAR4 & ~VAR1 & VAR2 & ~VAR5) | (~VAR3 & ~VAR4 & ~VAR1 & VAR2 & VAR5) | (~VAR3 & ~VAR4 & VAR1 & ~VAR2 & VAR5) | (~VAR3 & ~VAR4 & VAR1 & VAR2 & VAR5) | (~VAR3 & VAR4 & ~VAR1 & ~VAR2 & VAR5) | (~VAR3 & VAR4 &... | mit |
Cognoscan/BoostDSP | verilog/src/iirFilters/BiquadCascade.v | 4,775 | module MODULE1 #(
parameter VAR1 = 18, parameter VAR20 = 18, parameter VAR24 = 0, parameter VAR15 = 0, parameter VAR16 = 0, parameter VAR14 = 0, parameter VAR6 = 0, parameter VAR3 = 0 )
(
input clk, input rst, input VAR23, input signed [VAR1-1:0] VAR19, output reg VAR18, output signed [VAR1-1:0] VAR28 );
localparam VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111o/sky130_fd_sc_ls__a2111o.blackbox.v | 1,394 | module MODULE1 (
VAR7 ,
VAR9,
VAR4,
VAR1,
VAR5,
VAR10
);
output VAR7 ;
input VAR9;
input VAR4;
input VAR1;
input VAR5;
input VAR10;
supply1 VAR2;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlxtp/sky130_fd_sc_lp__srdlxtp.symbol.v | 1,383 | module MODULE1 (
input VAR7 ,
output VAR8 ,
input VAR3 ,
input VAR9
);
supply1 VAR2;
supply1 VAR5 ;
supply0 VAR1 ;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtn/sky130_fd_sc_ms__dfrtn.behavioral.pp.v | 2,391 | module MODULE1 (
VAR10 ,
VAR17 ,
VAR15 ,
VAR19,
VAR7 ,
VAR4 ,
VAR5 ,
VAR18
);
output VAR10 ;
input VAR17 ;
input VAR15 ;
input VAR19;
input VAR7 ;
input VAR4 ;
input VAR5 ;
input VAR18 ;
wire VAR13 ;
wire VAR1 ;
wire VAR20 ;
reg VAR8 ;
wire VAR2 ;
wire VAR9;
wire VAR6 ;
wire VAR21 ;
wire VAR12 ;
wire VAR3 ;
not VAR14 (... | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/video/video_render.v | 4,021 | module MODULE1(
input wire clk,
input wire [63:0] VAR22,
input wire VAR8,
input wire VAR10,
input wire VAR19, input wire VAR20,
input wire VAR11,
input wire VAR16,
input wire [ 2:0] VAR5,
output wire [ 3:0] VAR9,
input wire [10:0] VAR1,
input wire [ 7:0] VAR15,
input wire VAR18,
input wire VAR12,
input wire VAR14, inpu... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_093.v | 1,617 | module MODULE1 (
VAR11,
VAR10
);
input [31:0] VAR11;
output [31:0]
VAR10;
wire [31:0]
VAR9,
VAR7,
VAR13,
VAR2,
VAR14,
VAR16,
VAR1,
VAR3,
VAR4,
VAR6,
VAR12;
assign VAR9 = VAR11;
assign VAR1 = VAR14 + VAR16;
assign VAR7 = VAR9 << 7;
assign VAR13 = VAR9 + VAR7;
assign VAR3 = VAR13 << 7;
assign VAR2 = VAR13 << 4;
assign VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbn/sky130_fd_sc_lp__dlxbn.symbol.v | 1,368 | module MODULE1 (
input VAR1 ,
output VAR8 ,
output VAR3 ,
input VAR6
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22oi/sky130_fd_sc_ls__a22oi.behavioral.v | 1,641 | module MODULE1 (
VAR6 ,
VAR2,
VAR15,
VAR16,
VAR3
);
output VAR6 ;
input VAR2;
input VAR15;
input VAR16;
input VAR3;
supply1 VAR11;
supply0 VAR10;
supply1 VAR7 ;
supply0 VAR9 ;
wire VAR1 ;
wire VAR8 ;
wire VAR13;
nand VAR4 (VAR1 , VAR15, VAR2 );
nand VAR5 (VAR8 , VAR3, VAR16 );
and VAR14 (VAR13, VAR1, VAR8);
buf VAR12 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i.symbol.v | 1,308 | module MODULE1 (
input VAR5,
input VAR3,
output VAR2 ,
input VAR4
);
supply1 VAR1;
supply0 VAR6;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/top_ctrl.v | 18,366 | module MODULE1(
clk ,
VAR52 ,
VAR34 ,
VAR26 ,
VAR15 ,
VAR1 ,
VAR24 ,
VAR8 ,
VAR56 ,
VAR54 ,
VAR18 ,
VAR25 ,
VAR12 ,
VAR29 ,
VAR38 ,
VAR4 ,
VAR40 ,
VAR9 ,
VAR30 ,
VAR57 ,
VAR53 ,
VAR59 ,
VAR21 ,
VAR32 ,
VAR35 ,
VAR39 ,
VAR14 ,
VAR6 ,
VAR22
);
localparam VAR48 = 00 ,
VAR28 = 01 ,
VAR41 = 02 ,
VAR55 = 03 ,
VAR49 = 04 ,
VA... | gpl-3.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/Delay.v | 1,654 | module MODULE3(
input [31:0] VAR4,
output [31:0] VAR5,
input VAR2
);
reg [31:0]VAR3 [1:0];
reg VAR1;
always @(posedge VAR2)
begin
VAR3[0] <= VAR4;
VAR3[1] <= VAR3[0];
end
assign VAR5 = VAR3[1];
endmodule
module MODULE2(
input [31:0] VAR4,
output [31:0] VAR5,
input VAR2
);
reg [31:0]VAR3 ;
always @(posedge VAR2)
begin
V... | gpl-3.0 |
davidjabon/Verilog | Quadrature_Decoder/quadrature_encoder.v | 1,736 | module MODULE1(
input clk,
input reset,
input VAR3,
input VAR2,
output VAR8,
output [31:0] VAR6
);
reg [2:0] VAR7;
reg [2:0] VAR4;
reg VAR1=1'b0;
reg [31:0] VAR5=0;
always @(posedge clk)
begin
VAR7 <= {VAR7[1:0],VAR3};
VAR4 <= {VAR4[1:0],VAR2};
end
always @(posedge clk or posedge reset)
begin
if (reset == 1'b1) begin
{... | gpl-2.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v | 10,409 | module MODULE1 (
VAR54, VAR48, VAR29,
VAR11, VAR3, VAR25, VAR46, VAR32, VAR28, VAR2, VAR10, VAR44, VAR7 );
output VAR54; output VAR48; output [15:0] VAR29;
input [3:0] VAR11; input [3:0] VAR3; input VAR25; input [15:0] VAR46; input VAR32; input VAR28; input [15:0] VAR2; input VAR10; input [1:0] VAR44; input [15:0] VAR7... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32oi/sky130_fd_sc_ls__a32oi.pp.blackbox.v | 1,467 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR6 ,
VAR10 ,
VAR8 ,
VAR4 ,
VAR9,
VAR1,
VAR3 ,
VAR7
);
output VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR10 ;
input VAR8 ;
input VAR4 ;
input VAR9;
input VAR1;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
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