repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2b/sky130_fd_sc_hdll__and2b.symbol.v | 1,299 | module MODULE1 (
input VAR5,
input VAR2 ,
output VAR3
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/tx_fct_counter.v | 5,449 | module MODULE1(
input VAR14,
input VAR10,
input VAR6,
input VAR11,
input VAR12,
output reg [5:0] VAR1
);
reg [2:0] VAR5;
reg [2:0] VAR4;
reg [2:0] VAR13;
reg [2:0] VAR9;
reg [5:0] VAR8;
reg VAR7;
reg VAR3;
reg VAR2;
always@(posedge VAR11 or negedge VAR3)
begin
if(!VAR3)
begin
VAR2 <= 1'b0;
end
else if(VAR10)
begin
VAR2... | gpl-3.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/WB_PS2.v | 59,755 | module MODULE3(
input VAR114, input VAR31, input [15:0] VAR16, output [15:0] VAR117, input VAR145, input VAR45, input [ 2:1] VAR132, input [ 1:0] VAR89, input VAR133, output VAR20, output VAR73, output VAR103,
inout VAR85, inout VAR3, inout VAR68, inout VAR147 );
wire [7:0] VAR26 = VAR89[0] ? VAR16[7:0] : VAR16[15:8]; ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputisolatch/sky130_fd_sc_lp__inputisolatch.functional.pp.v | 1,836 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR14,
VAR4 ,
VAR6 ,
VAR3 ,
VAR12
);
output VAR10 ;
input VAR5 ;
input VAR14;
input VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR12 ;
wire VAR9 ;
wire VAR7;
wire VAR11 ;
VAR8 VAR1 VAR13 (VAR9 , VAR5, VAR14, , VAR4, VAR6);
buf VAR2 (VAR10 , VAR9 );
endmodule | apache-2.0 |
ptracton/pmodacl2 | soc/wb_uart/uart_rfifo.v | 11,758 | module MODULE1 (clk,
VAR18, VAR43, VAR46,
VAR36, VAR1, VAR10,
VAR19,
VAR6,
VAR8,
VAR25
);
parameter VAR17 = VAR27;
parameter VAR32 = VAR15;
parameter VAR38 = VAR31;
parameter VAR29 = VAR5;
input clk;
input VAR18;
input VAR36;
input VAR1;
input [VAR17-1:0] VAR43;
input VAR8;
input VAR25;
output [VAR17-1:0] VAR46;
output... | mit |
neale/CS-program | 474-VLSI/Lab_4/db/frame_rate_altpll1.v | 4,352 | module MODULE1
(
clk,
VAR45,
VAR16) ;
output [4:0] clk;
input [1:0] VAR45;
output VAR16;
tri0 [1:0] VAR45;
wire [4:0] VAR24;
wire VAR41;
wire VAR37;
VAR21 VAR30
(
.VAR19(),
.clk(VAR24),
.VAR3(),
.VAR18(VAR41),
.VAR11(VAR41),
.VAR45(VAR45),
.VAR16(VAR37),
.VAR35(),
.VAR15(),
.VAR22(),
.VAR42(),
.VAR8()
,
.VAR10(1'b0),
.... | unlicense |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.functional.v | 3,002 | module MODULE1( VAR18, VAR26, VAR6, VAR9, VAR29, VAR17, VAR14 );
input VAR14, VAR17, VAR9, VAR29, VAR6, VAR26;
output VAR18;
wire VAR21;
not VAR34( VAR21, VAR14 );
wire VAR13;
not VAR32( VAR13, VAR9 );
wire VAR31;
not VAR4( VAR31, VAR6 );
wire VAR36;
and VAR22( VAR36, VAR21, VAR13, VAR31 );
wire VAR19;
not VAR30( VAR19... | apache-2.0 |
INTI-CMNB/Lattuino_IP_Core | Work/lattuino_1_bl_2.v | 2,366 | module MODULE1
parameter VAR9=16, parameter VAR8=0, parameter VAR2=13 )
(
input VAR4,
input [VAR2-1:0] VAR10,
output [VAR9-1:0] VAR5,
input VAR7,
input [VAR9-1:0] VAR6
);
localparam VAR1=2**VAR2;
reg [VAR2-1:0] VAR3;
reg [VAR9-1:0] VAR11[0:VAR1-1]; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3b/sky130_fd_sc_hd__nor3b.pp.symbol.v | 1,341 | module MODULE1 (
input VAR6 ,
input VAR7 ,
input VAR1 ,
output VAR5 ,
input VAR4 ,
input VAR2,
input VAR3,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi.functional.pp.v | 2,413 | module MODULE1 (
VAR15 ,
VAR3 ,
VAR22 ,
VAR16 ,
VAR2 ,
VAR1 ,
VAR8 ,
VAR13,
VAR10,
VAR21 ,
VAR17
);
output VAR15 ;
input VAR3 ;
input VAR22 ;
input VAR16 ;
input VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR13;
input VAR10;
input VAR21 ;
input VAR17 ;
wire VAR5 ;
wire VAR11 ;
wire VAR6 ;
wire VAR14 ;
wire VAR9;
nand VAR12... | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_rxeq_scan.v | 14,810 | module MODULE1 #
(
parameter VAR47 = "VAR11", parameter VAR50 = "VAR39", parameter VAR25 = 1, parameter VAR40 = 22'd3125000, parameter VAR36 = 22'd2083333 )
(
input VAR29,
input VAR7,
input [ 1:0] VAR41,
input [ 2:0] VAR10,
input VAR24,
input [ 3:0] VAR4,
input [17:0] VAR16,
input VAR23,
input [ 5:0] VAR17,
input [ 5:0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32oi/sky130_fd_sc_hs__a32oi.functional.pp.v | 2,139 | module MODULE1 (
VAR14,
VAR1,
VAR8 ,
VAR18 ,
VAR9 ,
VAR11 ,
VAR7 ,
VAR15
);
input VAR14;
input VAR1;
output VAR8 ;
input VAR18 ;
input VAR9 ;
input VAR11 ;
input VAR7 ;
input VAR15 ;
wire VAR7 VAR4 ;
wire VAR7 VAR10 ;
wire VAR12 ;
wire VAR16;
nand VAR5 (VAR4 , VAR9, VAR18, VAR11 );
nand VAR17 (VAR10 , VAR15, VAR7 );
an... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo.pp.symbol.v | 1,385 | module MODULE1 (
input VAR3 ,
input VAR4 ,
input VAR1,
output VAR8 ,
input VAR6 ,
input VAR7,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/soc_system_bb.v | 5,101 | module MODULE1 (
VAR10,
VAR7,
VAR60,
VAR11,
VAR70,
VAR9,
VAR44,
VAR17,
VAR23,
VAR3,
VAR27,
VAR12,
VAR21,
VAR42,
VAR52,
VAR49,
VAR30,
VAR68,
VAR48,
VAR5,
VAR14,
VAR65,
VAR53,
VAR50,
VAR15,
VAR58,
VAR46,
VAR19,
VAR25,
VAR63,
VAR35,
VAR61,
VAR59,
VAR20,
VAR37,
VAR34,
VAR45,
VAR16,
VAR33,
VAR54,
VAR57,
VAR38,
VAR31,
VAR41,... | mit |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_fifo64to256.v | 1,980 | module MODULE1 #(
parameter VAR12 = 2
) (
input VAR11,
input VAR15,
output VAR1,
input VAR8,
input [63:0] VAR14,
output VAR2,
input VAR6,
output [255:0] rd
);
reg [63:0] VAR16[0:(1 << VAR12)-1];
reg [63:0] VAR7[0:(1 << VAR12)-1];
reg [63:0] VAR3[0:(1 << VAR12)-1];
reg [63:0] VAR5[0:(1 << VAR12)-1];
reg [VAR12+2:0] VAR1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp_1.v | 2,591 | module MODULE1 (
VAR11 ,
VAR8 ,
VAR1 ,
VAR9 ,
VAR4 ,
VAR7,
VAR2 ,
VAR6 ,
VAR12 ,
VAR10
);
output VAR11 ;
input VAR8 ;
input VAR1 ;
input VAR9 ;
input VAR4 ;
input VAR7;
input VAR2 ;
input VAR6 ;
input VAR12 ;
input VAR10 ;
VAR3 VAR5 (
.VAR11(VAR11),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2... | apache-2.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/Loop_loop_height_kbM.v | 1,187 | module MODULE1 (
VAR7, VAR1, VAR5, clk);
parameter VAR3 = 8;
parameter VAR2 = 8;
parameter VAR6 = 256;
input[VAR2-1:0] VAR7;
input VAR1;
output reg[VAR3-1:0] VAR5;
input clk;
reg [VAR3-1:0] VAR4[0:VAR6-1];
begin
begin | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_convert_to_ieee_double.v | 1,564 | module MODULE1(VAR11, VAR6, VAR4, VAR7, VAR3, VAR10, VAR1, VAR2, VAR9, VAR8, enable);
input VAR11, VAR6;
input [55:0] VAR4;
input [11:0] VAR7;
input VAR3;
output [63:0] VAR10;
input VAR1, VAR9, enable;
output VAR2, VAR8;
parameter VAR5 = 1;
assign VAR2 = VAR1;
assign VAR8 = VAR9;
generate
if (VAR5 == 0)
assign VAR10 = ... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq_issue.v | 17,393 | module MODULE1 (
VAR129, VAR126, VAR115, VAR39,
VAR83, VAR71, VAR77, VAR34,
clk, VAR144, VAR35, VAR33, VAR41, VAR1,
VAR125, VAR66, VAR89, VAR42, VAR118,
VAR82, VAR79, VAR132
);
input clk;
input VAR144;
input VAR35;
input VAR33;
input VAR41;
input [1:0] VAR1;
input VAR125;
input [VAR97-1:0] VAR66;
output VAR129;
input [... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w.v | 3,166 | module MODULE1
, parameter VAR6(VAR16)
, parameter VAR6(VAR13)
, parameter VAR28 = "VAR2"
)
(input VAR22
, input VAR7
, input VAR18
, input VAR15
, input [VAR16-1:0] VAR38
, input [VAR13-1:0] VAR14
, input VAR36
, input [VAR16-1:0] VAR21
, output logic [VAR13-1:0] VAR3
, output logic VAR32
);
localparam VAR27 = VAR17(V... | bsd-3-clause |
bkboggy/MIPS | ID_EX.v | 1,770 | module MODULE1(
input clk,
input [1:0] VAR3,
input [2:0] VAR1,
input [3:0] VAR16,
input [31:0] VAR6, VAR18, VAR20, VAR12,
input [4:0] VAR19, VAR17,
output reg [1:0] VAR8,
output reg [2:0] VAR4,
output reg [3:0] VAR14,
output reg [31:0] VAR11, VAR13, VAR15, VAR2,
output reg [4:0] VAR9, VAR5,
input [4:0] VAR7,
output reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtp/sky130_fd_sc_ms__sdfrtp.blackbox.v | 1,444 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR8 ,
VAR2 ,
VAR9 ,
VAR1
);
output VAR7 ;
input VAR10 ;
input VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR1;
supply1 VAR6;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_bridge_v1_08_a/hdl/verilog/radio_bridge.v | 11,263 | module MODULE1
(
VAR61,
VAR32,
VAR14,
VAR99,
VAR26,
VAR12,
VAR65,
VAR29,
VAR38,
VAR60,
VAR62,
VAR21,
VAR84,
VAR81,
VAR25,
VAR19,
VAR44,
VAR13,
VAR89,
VAR92,
VAR22,
VAR93,
VAR88,
VAR49,
VAR42,
VAR98,
VAR20,
VAR40,
VAR53,
VAR105,
VAR97,
VAR69,
VAR57,
VAR50,
VAR90,
VAR72,
VAR59,
VAR55,
VAR86,
VAR68,
VAR30,
VAR16,
VAR94,
V... | bsd-2-clause |
ludisu13/Estructuras2 | tarea45/ALU.v | 5,245 | module MODULE1(
input wire[15:0] VAR6,
input wire[7:0] VAR2,
input wire [7:0] VAR4,
output reg VAR3,
output wire[7:0] VAR13,
output reg VAR11,
output reg VAR8,
output reg VAR9, VAR1,
output reg [9:0] VAR12,
output reg VAR10,VAR7
);
reg [8:0]VAR5;
assign VAR13=VAR5;
always @ ( * )
begin
case(VAR6[15:10])
begin
VAR5=VAR2... | gpl-3.0 |
8l/soc | backends/small1/hw/rtl/core.v | 25,172 | module MODULE1(
input clk, input rst,
output reg [31:0] VAR47,
output reg VAR161,
input [31:0] VAR11,
input VAR93,
input [31:0] VAR59, input VAR170, input VAR61,
output VAR119, output VAR44, output [31:0] VAR101, output [31:0] VAR111,
input irq, input [3:0] VAR34, output VAR118, output VAR130,
output reg [31:0] VAR134,... | mit |
jameshegarty/rigel | generators/hardfloat/source/mulAddRecFN.v | 20,359 | module
MODULE1#(
parameter VAR72 = 3, parameter VAR34 = 3
) (
VAR63,
VAR116,
VAR48,
VAR29,
VAR134,
VAR105,
VAR124,
VAR114,
VAR111,
VAR76,
VAR95,
VAR68,
VAR13
);
input [(VAR9 - 1):0] VAR63;
input [1:0] VAR116;
input [(VAR72 + VAR34):0] VAR48;
input [(VAR72 + VAR34):0] VAR29;
input [(VAR72 + VAR34):0] VAR134;
input [2:0]... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encoder_ip_export/src/encoder_axi_s_v1_0.v | 2,615 | module MODULE1 #
(
parameter integer VAR16 = 32,
parameter integer VAR52 = 5
)
(
output wire [VAR16-1:0] VAR30,
output wire [VAR16-1:0] VAR12,
output wire [VAR16-1:0] VAR18,
output wire VAR38,
input wire VAR43,
input wire VAR25,
input wire VAR53,
input wire [VAR52-1 : 0] VAR41,
input wire [2 : 0] VAR32,
input wire VAR3... | gpl-3.0 |
seyedmaysamlavasani/GorillaPP | apps/k-means/build/verilog/types_float_double_grp_fu_100_ACMP_dsqrt_4.v | 1,141 | module MODULE1(
clk,
reset,
VAR9,
VAR7,
VAR3,
VAR4,
VAR10);
input clk;
input reset;
input VAR9;
output VAR7;
input[64 - 1:0] VAR3;
input[64 - 1:0] VAR4;
output[64 - 1:0] VAR10;
MODULE2 MODULE1(
.clk(clk),
.VAR2(VAR9),
.VAR5(VAR7),
.VAR1(VAR3),
.VAR8(VAR10));
endmodule
module MODULE2(
clk,
VAR2,
VAR5,
VAR1,
VAR8);
input... | bsd-3-clause |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_ecc_encoder.v | 9,649 | module MODULE1 #
( parameter
VAR15 = 40,
VAR19 = 8,
VAR27 = 0,
VAR10 = 7,
VAR29 = 7,
VAR16 = 1
)
(
VAR28,
VAR22,
VAR3,
VAR14,
VAR9,
VAR7,
VAR24,
VAR21,
VAR18
);
localparam VAR26 = (VAR15 > 8) ? (VAR15 - VAR19) : (VAR15);
input VAR28;
input VAR22;
input [VAR10 - 1 : 0] VAR3;
input [VAR29 - 1 : 0] VAR14;
input [VAR16 - 1... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/common/up_axi.v | 8,736 | module MODULE1 #(
parameter VAR36 = 14,
parameter VAR21 = 16) (
input VAR2,
input VAR6,
input VAR31,
input [(VAR21-1):0] VAR28,
output VAR12,
input VAR20,
input [31:0] VAR4,
input [ 3:0] VAR11,
output VAR5,
output VAR13,
output [ 1:0] VAR17,
input VAR24,
input VAR22,
input [(VAR21-1):0] VAR37,
output VAR42,
output VAR3... | mit |
Jside/nova1 | nova_disa.v | 5,888 | module MODULE1(clk, VAR62, VAR5, VAR4);
input clk;
input VAR62;
input [0:15] VAR5;
input [0:14] VAR4;
wire [0:1] VAR26;
wire [0:2] VAR54;
wire [0:1] VAR24;
wire [0:5] VAR33;
assign VAR26 = VAR5[VAR63];
assign VAR54 = VAR5[VAR31];
assign VAR24 = VAR5[VAR48];
assign VAR33 = VAR5[VAR21];
wire [0:3] VAR67;
wire [0:1] VAR17... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b.pp.symbol.v | 1,284 | module MODULE1 (
input VAR7 ,
input VAR4 ,
output VAR3 ,
input VAR2 ,
input VAR1,
input VAR5,
input VAR6
);
endmodule | apache-2.0 |
Cognoscan/BoostDSP | verilog/src/miscFilters/HaarFilter.v | 7,302 | module MODULE1 #(
parameter VAR1 = 4, parameter VAR3 = 18, parameter VAR4 = 16, parameter VAR2 = 16 )
(
input clk, input rst, input en, input signed [VAR4-1:0] VAR6, output reg [VAR1:0] VAR7, output reg [VAR2*(VAR1+1)-1:0] VAR5 ); | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/DNAMapper_top.v | 29,164 | module MODULE1
parameter VAR110 = 128,
parameter VAR77 = 256,
parameter VAR206 = 5
)
(output [(VAR70 - 1) : 0] VAR208,
output [(VAR70 - 1) : 0] VAR53,
input [(VAR70 - 1) : 0] VAR117,
input [(VAR70 - 1) : 0] VAR176,
input VAR107,
input VAR170,
input VAR65,
input VAR124 );
wire VAR202;
wire VAR57;
wire VAR132;
wire VAR15... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor3/sky130_fd_sc_lp__xnor3.symbol.v | 1,289 | module MODULE1 (
input VAR3,
input VAR1,
input VAR6,
output VAR5
);
supply1 VAR8;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv.blackbox.v | 1,371 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR6 ;
supply0 VAR4 ;
supply1 VAR1;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/16-way_2-tree/src/riffa/cross_domain_signal.v | 2,909 | module MODULE1 (
input VAR8, input VAR1, output VAR11, input VAR6, output VAR2, input VAR4 );
VAR3 VAR7 (.VAR9(VAR6), .VAR12(VAR1), .VAR10(VAR2));
VAR3 VAR5 (.VAR9(VAR8), .VAR12(VAR4), .VAR10(VAR11));
endmodule | mit |
Pylonight/MIPS-CPU | cpu/Arithmetic_Logic_Unit.v | 1,548 | module MODULE1(
output [15 : 0] VAR3,
input [4 : 0] VAR1,
input [15 : 0] VAR2,
input [15 : 0] VAR5
);
wire [1 : 0] VAR4;
assign VAR4 = {VAR2[15], VAR5[15]};
assign VAR3 =
(VAR1 == 0) ? VAR2 :
(VAR1 == 1) ? VAR5 :
(VAR1 == 2) ? (VAR2+VAR5) :
(VAR1 == 3) ? (VAR2-VAR5) :
(VAR1 == 4) ? (VAR2&VAR5) :
(VAR1 == 5) ? (VAR2|VAR... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/Dispatcher.v | 39,358 | module MODULE1
(
parameter VAR291 = 32 ,
parameter VAR248 = 32 ,
parameter VAR56 = 16 ,
parameter VAR242 = 4 ,
parameter VAR305 = 64 ,
parameter VAR317 = 256
)
(
VAR312 ,
VAR174 ,
VAR77 ,
VAR211 ,
VAR86 ,
VAR23 ,
VAR1 ,
VAR233 ,
VAR75 ,
VAR265 ,
VAR311 ,
VAR318 ,
VAR91 ,
VAR276 ,
VAR137 ,
VAR160 ,
VAR161 ,
VAR104 ,
VAR... | gpl-3.0 |
hcabrera-/lancetfish | RTL/nic/des_nic/rtl/des_nic_input_control_unit.v | 5,576 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR12,
input wire VAR11,
input wire VAR18,
output wire VAR13,
output wire VAR9,
output wire [VAR7:0] VAR3
);
localparam VAR10 = 2'b00;
localparam VAR8 = 2'b01;
localparam VAR14 = 2'b10;
localparam VAR6 = 1'b1;
localparam VAR15 = 1'b0;
reg [VAR7:0] VAR16;
wir... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/sctag_cpx_rptr_0.v | 1,918 | module MODULE1 (
VAR2,
VAR1
);
output [163:0] VAR2;
input [163:0] VAR1;
assign VAR2 = VAR1;
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/xilinx_v6es_pcie_wrapper.v | 15,249 | module MODULE1
(
VAR103, VAR9, VAR14, VAR93,
VAR16, VAR35, VAR99, VAR72,
VAR94, VAR26, VAR43, VAR70, VAR90,
VAR41, VAR96, VAR7, VAR63, VAR51,
VAR100, VAR79, VAR17, VAR46, VAR12,
VAR83, VAR44, VAR68,
VAR59, VAR97,
VAR66, VAR34,
VAR6, VAR55, VAR30,
VAR98, VAR22, VAR2, VAR19,
VAR101, VAR88, VAR91,
VAR37, VAR28, VAR95,
VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp.functional.pp.v | 1,875 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR10 ,
VAR2,
VAR1,
VAR15,
VAR12 ,
VAR3
);
output VAR6 ;
output VAR4 ;
input VAR10 ;
input VAR2;
input VAR1;
input VAR15;
input VAR12 ;
input VAR3 ;
wire VAR13 ;
wire VAR8;
wire VAR5 ;
VAR16 VAR9 VAR7 (VAR13 , VAR10, VAR2, , VAR1, VAR15);
buf VAR14 (VAR6 , VAR13 );
not VAR11 (VAR4 , VAR13... | apache-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_slow_clock_generator.v | 7,439 | module MODULE1 (
clk,
reset,
VAR3,
VAR8,
VAR2,
VAR5,
VAR4,
VAR1
);
parameter VAR6 = 10;
input clk;
input reset;
input VAR3;
output reg VAR8;
output reg VAR2;
output reg VAR5;
output reg VAR4;
output reg VAR1;
reg [VAR6:1] VAR7;
always @(posedge clk)
begin
if (reset)
VAR7 <= 'h0;
end
else if (VAR3)
VAR7 <= VAR7 + 1;
end... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd.blackbox.v | 1,183 | module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2.behavioral.v | 1,340 | module MODULE1 (
VAR9,
VAR10,
VAR6
);
output VAR9;
input VAR10;
input VAR6;
supply1 VAR1;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR2 ;
wire VAR8;
or VAR4 (VAR8, VAR6, VAR10 );
buf VAR3 (VAR9 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2.behavioral.pp.v | 1,827 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR10 ,
VAR7,
VAR1,
VAR5 ,
VAR8
);
output VAR3 ;
input VAR9 ;
input VAR10 ;
input VAR7;
input VAR1;
input VAR5 ;
input VAR8 ;
wire VAR4 ;
wire VAR11;
xnor VAR12 (VAR4 , VAR9, VAR10 );
VAR2 VAR6 (VAR11, VAR4, VAR7, VAR1);
buf VAR13 (VAR3 , VAR11 );
endmodule | apache-2.0 |
dhesant/elec4320 | Lab2/keytofrequency.v | 2,018 | module MODULE1( VAR20, clk, VAR1 );
input[4:0] VAR20;
input clk;
output [12:0] VAR1;
reg [12:0] VAR7;
always @ (posedge clk)
case (VAR20)
0: VAR7 <= 0; 1: VAR7 <= 'VAR16; 2: VAR7 <= 'VAR13; 3: VAR7 <= 'VAR3; 4: VAR7 <= 'VAR23; 5: VAR7 <= 'VAR24; 6: VAR7 <= 'VAR6; 7: VAR7 <= 'VAR21; 8: VAR7 <= 'VAR17; 9: VAR7 <= 'VAR12;... | mit |
mamijaz/RISC-V | src/riscv_instruction_cache/DUAL_PORT_MEMORY.v | 3,022 | module MODULE1 #(
parameter VAR12 = 512 ,
parameter VAR13 = 512 ,
parameter VAR15 = "VAR8" ,
parameter VAR14 = ""
) (
input VAR7 ,
input [VAR1(VAR13-1) - 1 : 0] VAR3 ,
input [VAR12-1 : 0] VAR11 ,
input VAR4 ,
input [VAR1(VAR13-1)-1 : 0] VAR2 ,
input VAR10 ,
output [VAR12-1 : 0] VAR9
);
reg [VAR12 - 1 : 0] memory [VAR13... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcin/sky130_fd_sc_ms__fahcin.behavioral.v | 1,848 | module MODULE1 (
VAR21,
VAR23 ,
VAR4 ,
VAR14 ,
VAR16
);
output VAR21;
output VAR23 ;
input VAR4 ;
input VAR14 ;
input VAR16 ;
supply1 VAR10;
supply0 VAR9;
supply1 VAR13 ;
supply0 VAR11 ;
wire VAR5 ;
wire VAR6;
wire VAR17 ;
wire VAR12 ;
wire VAR15 ;
wire VAR20;
not VAR22 (VAR5 , VAR16 );
xor VAR3 (VAR6, VAR4, VAR14, VAR... | apache-2.0 |
fpgaminer/fpgaminer-vanitygen | fpgaminer_vanitygen_top.v | 4,633 | module MODULE1 (
input clk
);
wire VAR53;
VAR12 VAR50 (
.VAR65 (clk),
.VAR1 (VAR53)
);
wire reset;
wire [255:0] VAR34, VAR21;
wire [159:0] VAR44, VAR57;
VAR13 # (.VAR51 (256), .VAR62 ("VAR10")) VAR37 (.clk (VAR53), .VAR15 (), .VAR39 (VAR34));
VAR13 # (.VAR51 (256), .VAR62 ("VAR36")) VAR29 (.clk (VAR53), .VAR15 (), .VAR... | gpl-3.0 |
mosukiton/mipsprocessor | Mips_single_cycle.srcs/sources_1/new/memoryaccess.v | 1,716 | module MODULE1(
output [31:0] VAR17, VAR6, VAR8,
output [4:0] VAR12,
output VAR11, VAR18, VAR3,
input [31:0] VAR5, VAR9, VAR20,
input [4:0] VAR16,
input VAR1, VAR7, VAR19, VAR4, VAR2, clk
);
VAR14 VAR13(
.VAR21( VAR17 ),
.VAR15( VAR9 ),
.VAR22( VAR5 ),
.VAR10( VAR7 ),
.clk( clk )
);
assign VAR3 = VAR1 & VAR2;
assign VA... | gpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/rm_hdr.v | 3,720 | module MODULE1
parameter VAR23 = 64,
parameter VAR5 = VAR23/8
)
(
VAR20,
VAR22,
VAR13,
VAR4,
VAR18,
VAR8,
VAR17,
VAR12,
reset,
clk
);
input [VAR23-1:0] VAR20;
input [VAR5-1:0] VAR22;
input VAR13;
output VAR4;
output [VAR23-1:0] VAR18;
output [VAR5-1:0] VAR8;
output reg VAR17;
input VAR12;
input reset;
input clk;
functi... | apache-2.0 |
plindstroem/oh | elink/hdl/erx_fifo.v | 5,493 | module MODULE1 (
VAR37, VAR7, VAR31, VAR34, VAR35,
VAR20, VAR9, VAR24, VAR1,
VAR38, VAR14, VAR21, VAR18, VAR27, VAR22,
VAR32, VAR17, VAR5, VAR23,
VAR39, VAR26, VAR36
);
parameter VAR6 = 32;
parameter VAR13 = 32;
parameter VAR2 = 104;
parameter VAR25 = 6;
parameter VAR10 = 12'h800;
input VAR38;
input VAR14;
input VAR21;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.pp.blackbox.v | 1,273 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR6,
VAR5,
VAR3 ,
VAR1
);
output VAR4 ;
input VAR2 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_rdwr_data_tmg.v | 128,460 | module MODULE1
VAR5 = 2,
VAR76 = 8,
VAR56 = 1,
VAR144 = 1,
VAR128 = 6,
VAR177 = 1,
VAR169 = 10,
VAR1 = 0,
VAR15 = 0,
VAR180 = 2,
VAR73 = 1,
VAR9 = 1
)
(
VAR185,
VAR48,
VAR160,
VAR36,
VAR184,
VAR67,
VAR58,
VAR146, VAR163,
VAR127,
VAR21,
VAR186,
VAR40,
VAR46,
VAR10, VAR18,
VAR24,
VAR136,
VAR38,
VAR84,
VAR14,
VAR27,
VAR17... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_2.v | 2,339 | module MODULE2 (
VAR2 ,
VAR5 ,
VAR9 ,
VAR10 ,
VAR1 ,
VAR6 ,
VAR4,
VAR8
);
output VAR2 ;
input VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR1 ;
input VAR6 ;
input VAR4;
input VAR8;
VAR7 VAR3 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODUL... | apache-2.0 |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/controller.v | 9,308 | module MODULE1 (reset, clk, VAR39, VAR33, VAR38, VAR5,
VAR16, VAR27, VAR4,
VAR25, VAR3, VAR23, VAR30,
VAR42, VAR44, VAR19, VAR21, VAR11,
VAR28, VAR2, VAR22);
parameter VAR14 = 9'b000000001;
parameter VAR40 = 9'b000000010;
parameter VAR41 = 9'b000000100;
parameter VAR8 = 9'b000001000;
parameter VAR43 = 9'b000010000;
par... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b_1.v | 2,234 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR8 ,
VAR2 ,
VAR4,
VAR9,
VAR5 ,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR4;
input VAR9;
input VAR5 ;
input VAR6 ;
VAR10 VAR3 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE2 (... | apache-2.0 |
Cognoscan/BoostLogic | verilog/src/receivers/Rx8b10b.v | 9,153 | module MODULE1 #(
parameter VAR1 = 10'b0011111010, parameter VAR23 = 10'b1100000101, parameter VAR6 = 1'b1, parameter VAR4 = 8, parameter VAR7 = 4 )
(
input clk, input rst, input VAR15, input VAR27, input VAR14, output VAR8, output VAR11, output VAR22, output VAR34, output [7:0] VAR29 );
parameter integer VAR25 = VAR2(... | apache-2.0 |
jobisoft/jTDC | modules/counter/dsp_multioption_counter.v | 4,513 | module MODULE1 (VAR29, VAR58, reset, VAR38);
parameter VAR30 = 1;
parameter VAR52 = 1;
input VAR29;
input VAR58;
input reset;
output [31:0] VAR38;
wire [47:0] VAR20;
wire VAR15;
wire [1:0] VAR46 = 2'b11; wire [1:0] VAR19 = 2'b10;
wire VAR18;
wire VAR49;
generate
if (VAR30 == 0) assign VAR18 = VAR58; else
if (VAR30 == 1... | gpl-3.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/hls_saturation_endEe.v | 1,311 | module MODULE1(
input [20 - 1:0] VAR4,
input [16 - 1:0] VAR8,
input [27 - 1:0] VAR18,
output [36 - 1:0] dout);
wire signed [25 - 1:0] VAR16;
wire signed [18 - 1:0] VAR1;
wire signed [48 - 1:0] VAR3;
wire signed [43 - 1:0] VAR9;
wire signed [48 - 1:0] VAR5;
assign VAR16 = (VAR4);
assign VAR1 = (VAR8);
assign VAR3 = (VAR... | mit |
richard42/CoCo3FPGA | FIFO_READ_bb.v | 6,161 | module MODULE1 (
VAR9,
VAR7,
VAR3,
VAR5,
VAR8,
VAR2,
VAR1,
VAR4,
VAR6);
input VAR9;
input [7:0] VAR7;
input VAR3;
input VAR5;
input VAR8;
input VAR2;
output [7:0] VAR1;
output VAR4;
output VAR6;
tri0 VAR9;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2b/sky130_fd_sc_hd__nand2b_1.v | 2,147 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR1 ,
VAR7,
VAR5,
VAR9 ,
VAR2
);
output VAR3 ;
input VAR6 ;
input VAR1 ;
input VAR7;
input VAR5;
input VAR9 ;
input VAR2 ;
VAR8 VAR4 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR3 ,
VAR6,
VAR1
);
output VAR3 ... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/axi_basic_rx_null_gen.v | 15,673 | module MODULE1 # (
parameter VAR21 = 128, parameter VAR25 = 1,
parameter VAR7 = VAR21 / 8 ) (
input [VAR21-1:0] VAR27, input VAR30, input VAR23, input VAR29, input [21:0] VAR28,
output VAR18, output VAR11, output [VAR7-1:0] VAR34, output VAR37, output reg [4:0] VAR5,
input VAR36, input VAR14 );
localparam VAR24 = (VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b.blackbox.v | 1,326 | module MODULE1 (
VAR5 ,
VAR4,
VAR1 ,
VAR8 ,
VAR7
);
output VAR5 ;
input VAR4;
input VAR1 ;
input VAR8 ;
input VAR7 ;
supply1 VAR3;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2.functional.v | 1,759 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR6,
VAR4
);
output VAR5 ;
input VAR10 ;
input VAR6;
input VAR4;
wire VAR7 ;
wire VAR2;
not VAR3 (VAR7 , VAR10 );
VAR9 VAR8 (VAR2, VAR7, VAR6, VAR4);
buf VAR1 (VAR5 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22ai/sky130_fd_sc_hs__o22ai.functional.pp.v | 2,060 | module MODULE1 (
VAR8,
VAR14,
VAR5 ,
VAR1 ,
VAR17 ,
VAR7 ,
VAR11
);
input VAR8;
input VAR14;
output VAR5 ;
input VAR1 ;
input VAR17 ;
input VAR7 ;
input VAR11 ;
wire VAR11 VAR15 ;
wire VAR11 VAR10 ;
wire VAR2 ;
wire VAR12;
nor VAR13 (VAR15 , VAR7, VAR11 );
nor VAR4 (VAR10 , VAR1, VAR17 );
or VAR16 (VAR2 , VAR10, VAR15 ... | apache-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/7-uart/fifo.v | 2,521 | module MODULE1
VAR2 = 8, VAR15 = 4 )
(
input wire clk, reset,
input wire wr, rd,
input wire [VAR2-1:0] VAR6,
output wire VAR9, VAR10,
output wire [VAR2-1:0] VAR13
);
reg [VAR2-1:0] VAR8 [0:2**VAR15-1]; reg [VAR15-1:0] VAR3, VAR7, VAR18;
reg [VAR15-1:0] VAR12, VAR17, VAR16;
reg VAR1, VAR5, VAR4, VAR14;
wire VAR11;
alway... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a_lp.v | 2,456 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR1 ,
VAR10 ,
VAR2 ,
VAR4 ,
VAR5,
VAR11,
VAR12 ,
VAR6
);
output VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR10 ;
input VAR2 ;
input VAR4 ;
input VAR5;
input VAR11;
input VAR12 ;
input VAR6 ;
VAR3 VAR9 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(V... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_qspi_media.v | 15,073 | module MODULE1(
input VAR136,
input reset,
output VAR63,
input VAR96,
output VAR141,
output VAR129,
input VAR152,
output VAR156,
output VAR105,
input VAR62,
output VAR85,
output VAR91,
input VAR164,
output VAR57,
output VAR74,
output VAR38,
input [11:0] VAR55,
input VAR19,
input VAR113,
input [7:0] VAR99,
input [7:0] V... | apache-2.0 |
hhuang25/uwaterloo_ece224 | Lab1/pio_egmenable.v | 2,113 | module MODULE1 (
address,
VAR2,
clk,
VAR5,
VAR4,
VAR1,
VAR6,
VAR9
)
;
output VAR6;
output VAR9;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR5;
input VAR4;
input VAR1;
wire VAR7;
reg VAR3;
wire VAR6;
wire VAR8;
wire VAR9;
assign VAR7 = 1;
assign VAR8 = {1 {(address == 0)}} & VAR3;
always @(posedge clk or nege... | mit |
jmassucco17/full_mips | processor/SingleCycleDatapath/InstructionMemory.v | 1,318 | module MODULE1(input VAR2,
input VAR3,
input[31:0] address,
output [31:0] VAR1);
reg[31:0] VAR4[255:0];
integer VAR5;
always @(posedge VAR3, negedge VAR2)
if (VAR3) begin
for (VAR5 = 0; VAR5 < 256; VAR5 = VAR5 + 1)
VAR4[VAR5] = 0;
VAR4[0] = 32'h00220018; VAR4[1] = 32'h0041001A; VAR4[2] = 32'h00001810; VAR4[3] = 32'h000... | mit |
sam-falvo/remex | example/rtl/bottleneck.v | 3,752 | module MODULE1(
input [63:0] VAR6,
input VAR59,
input [63:0] VAR17,
input VAR61,
input [1:0] VAR73,
input VAR25,
input VAR50,
output VAR13,
output [63:0] VAR19,
output VAR24,
output [63:0] VAR67,
output VAR53,
output VAR65,
output VAR47,
output VAR48,
output VAR72,
output [15:0] VAR33,
input VAR64,
input [15:0] VAR52,
... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor3/sky130_fd_sc_lp__xnor3.pp.symbol.v | 1,295 | module MODULE1 (
input VAR6 ,
input VAR5 ,
input VAR1 ,
output VAR2 ,
input VAR4 ,
input VAR7,
input VAR8,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtn/sky130_fd_sc_hd__dlxtn.behavioral.v | 1,947 | module MODULE1 (
VAR4 ,
VAR16 ,
VAR5
);
output VAR4 ;
input VAR16 ;
input VAR5;
supply1 VAR12;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR15 ;
wire VAR2 ;
wire VAR11 ;
wire VAR9;
wire VAR6 ;
reg VAR14 ;
wire VAR3 ;
not VAR17 (VAR2 , VAR9 );
VAR7 VAR1 (VAR11 , VAR6, VAR2, VAR14, VAR12, VAR8);
buf VAR13 (VAR4 , VAR11 );
as... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_sub_inputs.v | 2,238 | module MODULE1 (
address,
VAR8,
clk,
VAR4,
VAR1,
VAR9,
VAR5,
VAR2
)
;
output [ 8: 0] VAR5;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR4;
input VAR1;
input [ 31: 0] VAR9;
wire VAR7;
reg [ 8: 0] VAR6;
wire [ 8: 0] VAR5;
wire [ 8: 0] VAR3;
wire [ 31: 0] VAR2;
assign VAR7 = 1;
assign VAR3 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlrtp/sky130_fd_sc_hvl__dlrtp.behavioral.pp.v | 2,448 | module MODULE1 (
VAR12 ,
VAR7,
VAR15 ,
VAR19 ,
VAR11 ,
VAR17 ,
VAR22 ,
VAR4
);
output VAR12 ;
input VAR7;
input VAR15 ;
input VAR19 ;
input VAR11 ;
input VAR17 ;
input VAR22 ;
input VAR4 ;
wire VAR14 ;
reg VAR8 ;
wire VAR6 ;
wire VAR13 ;
wire VAR2 ;
wire VAR23 ;
wire VAR9;
wire VAR1 ;
wire VAR18 ;
not VAR10 (VAR14 , VA... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_read_valid_selector.v | 2,299 | module MODULE1(
VAR7,
VAR21,
VAR11,
VAR18,
VAR10,
VAR20
);
parameter VAR5 = "";
localparam VAR15 = 2**VAR5;
input VAR7;
input VAR21;
input [VAR15-1:0] VAR11;
input [VAR5-1:0] VAR18;
output VAR10;
output VAR20;
wire [VAR15-1:0] VAR13;
reg [VAR15-1:0] VAR22;
reg VAR10;
reg VAR17;
reg VAR20;
wire [VAR15-1:0] VAR4;
VAR6 VA... | lgpl-3.0 |
8l/kestrel | 2/nexys2/uxa/ps2io/T_uxa_ps2_busctl.v | 3,547 | module MODULE1;
reg VAR7;
reg VAR10;
reg VAR11;
reg VAR9;
reg VAR3;
reg VAR4;
wire VAR8;
wire VAR12;
wire VAR2;
wire VAR1;
VAR6 VAR5 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR1(VAR1)
);
always begin
VAR7 = ~VAR7;
end | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/vfabric_shl.v | 2,386 | module MODULE1(VAR10, VAR6,
VAR26, VAR8, VAR28,
VAR2, VAR4, VAR23,
VAR29, VAR13, VAR12);
parameter VAR16 = 32;
parameter VAR24= 5;
parameter VAR11 = 64;
input VAR10, VAR6;
input [VAR16-1:0] VAR26;
input [VAR24-1:0] VAR2;
input VAR8, VAR4;
output VAR28, VAR23;
output [VAR16-1:0] VAR29;
output VAR12;
input VAR13;
wire [V... | mit |
lbl-cal/StanfordNoC | router/src/clib/c_scatter.v | 2,705 | module MODULE1
(VAR10, VAR2, VAR7);
parameter VAR6 = 32;
function integer VAR4(input [0:VAR6-1] VAR3);
integer VAR1;
begin
VAR4 = 0;
for(VAR1 = 0; VAR1 < VAR6; VAR1 = VAR1 + 1)
VAR4 = VAR4 + VAR3[VAR1];
end
endfunction
parameter [0:VAR6-1] VAR9 = {VAR6{1'b1}};
localparam VAR11 = VAR4(VAR9);
input [0:VAR11-1] VAR10;
inp... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.pp.blackbox.v | 1,198 | module MODULE1 (
VAR3,
VAR1,
VAR2 ,
VAR4
);
input VAR3;
input VAR1;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22ai/sky130_fd_sc_hvl__o22ai.pp.blackbox.v | 1,397 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR8 ,
VAR7 ,
VAR2 ,
VAR5,
VAR9,
VAR6 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR5;
input VAR9;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
hcabrera-/lancetfish | RTL/router/rtl/outport_scheduler_control_unit.v | 7,176 | module MODULE1 #(
parameter VAR10 = VAR12
)
(
input wire clk,
input wire reset,
input wire VAR7,
input wire VAR3,
output wire VAR14,
output wire VAR30,
output wire VAR24,
output wire VAR21
);
localparam VAR27 = (VAR10 == VAR6) ? 1 : VAR29/5;
localparam VAR23 = VAR11(VAR27);
localparam VAR2 = VAR11(VAR18);
localparam VA... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/paula_audio_mixer.v | 2,036 | module MODULE1 (
input clk, input VAR14,
input [7:0] VAR3, input [7:0] VAR11, input [7:0] VAR12, input [7:0] VAR16, input [6:0] VAR7, input [6:0] VAR18, input [6:0] VAR20, input [6:0] VAR4, output reg [14:0]VAR10, output reg [14:0]VAR9 );
wire [14-1:0] VAR13, VAR17, VAR6, VAR5;
VAR15 VAR21
(
.VAR8(VAR3),
.VAR1({ (VAR7[... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3.functional.v | 1,344 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
wire VAR1;
not VAR2 (VAR1, VAR4 );
buf VAR5 (VAR3 , VAR1 );
endmodule | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | contador_AD_SS_T_2dig.v | 4,716 | module MODULE1
(
input wire clk,
input wire reset,
input wire [3:0] VAR9,
input wire VAR1,
input wire VAR3,
output wire [7:0] VAR10
);
localparam VAR6 = 6; reg [VAR6-1:0] VAR8, VAR2;
wire [VAR6-1:0] VAR7;
reg [3:0] VAR5, VAR4;
always@(posedge clk, posedge reset)
begin
if(reset)
begin
VAR8 <= 6'b0;
end
else
begin
VAR8 <... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp_4.v | 2,220 | module MODULE1 (
VAR6,
VAR8 ,
VAR7 ,
VAR5 ,
VAR2 ,
VAR3
);
input VAR6;
input VAR8 ;
input VAR7 ;
output VAR5 ;
input VAR2 ;
input VAR3 ;
VAR4 VAR1 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6,
VAR8 ,
VAR7 ,
VAR5
);
input VAR6;
input VAR8 ;
input VAR7 ... | apache-2.0 |
DigitalLogicSummerTerm2015/mips-cpu-pipeline | ppcpu/EXMEMreg.v | 1,136 | module MODULE1(clk,VAR5,VAR10,VAR8,VAR7,VAR18,VAR11,VAR12,VAR20,VAR14,VAR17,
VAR6,VAR2,VAR19,VAR16,VAR1,VAR13,VAR9,VAR3,VAR15,VAR4);
input clk;
input [4:0] VAR5;
input [4:0] VAR10;
input [31:0] VAR8;
input [31:0] VAR7;
input [31:0] VAR18;
input [1:0] VAR11;
input VAR12;
input VAR20;
input VAR14;
input [1:0] VAR17;
outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.v | 2,377 | module MODULE2 (
VAR11 ,
VAR3 ,
VAR4 ,
VAR10 ,
VAR8,
VAR1 ,
VAR7 ,
VAR2 ,
VAR9
);
output VAR11 ;
output VAR3 ;
input VAR4 ;
input VAR10 ;
input VAR8;
input VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR9 ;
VAR5 VAR6 (
.VAR11(VAR11),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai_2.v | 2,352 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR9 ,
VAR10 ,
VAR11 ,
VAR8,
VAR7,
VAR4 ,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR10 ;
input VAR11 ;
input VAR8;
input VAR7;
input VAR4 ;
input VAR5 ;
VAR2 VAR6 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.... | apache-2.0 |
jairov4/accel-oil | solution_virtex5_plb/syn/verilog/sample_iterator_next.v | 6,005 | module MODULE1 (
VAR40,
VAR13,
VAR6,
VAR48,
VAR46,
VAR22,
VAR23,
VAR17,
VAR18,
VAR25,
VAR10,
VAR39,
VAR20,
VAR26,
VAR36,
VAR14,
VAR45,
VAR44,
VAR32
);
parameter VAR24 = 1'b1;
parameter VAR34 = 1'b0;
parameter VAR5 = 2'b00;
parameter VAR1 = 2'b1;
parameter VAR8 = 2'b10;
parameter VAR9 = 2'b11;
parameter VAR15 = 32'b1;
p... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3b/sky130_fd_sc_ms__and3b_4.v | 2,218 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR10 ,
VAR8 ,
VAR9,
VAR3,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR7 ;
input VAR10 ;
input VAR8 ;
input VAR9;
input VAR3;
input VAR1 ;
input VAR4 ;
VAR6 VAR2 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.functional.v | 1,390 | module MODULE1( VAR7, VAR6, VAR11, VAR12, VAR5 );
input VAR5, VAR12, VAR11, VAR7;
output VAR6;
wire VAR13;
not VAR10( VAR13, VAR5 );
wire VAR8;
not VAR4( VAR8, VAR12 );
wire VAR2;
not VAR1( VAR2, VAR11 );
wire VAR3;
not VAR9( VAR3, VAR7 );
or VAR14( VAR6, VAR13, VAR8, VAR2, VAR3 );
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/sa1_mult.v | 4,607 | module MODULE1 (
VAR12,
VAR7,
VAR6,
VAR14);
input VAR12;
input [15:0] VAR7;
input [15:0] VAR6;
output [31:0] VAR14;
wire [31:0] VAR16;
wire [31:0] VAR14 = VAR16[31:0];
VAR18 VAR2 (
.VAR12 (VAR12),
.VAR7 (VAR7),
.VAR6 (VAR6),
.VAR14 (VAR16),
.VAR1 (1'b0),
.VAR20 (1'b1),
.VAR10 (1'b0),
.sum (1'b0));
VAR2.VAR4 = "VAR5=5"... | gpl-2.0 |
Raamakrishnan/MyProc | MyProc2/Reg.v | 1,569 | module MODULE1(
input wire clk, input wire [VAR12 - 1:0] VAR11,
input wire [VAR12 - 1:0] VAR22,
output wire [VAR8 - 1:0] VAR10,
output wire [VAR8 - 1:0] VAR16,
output reg VAR19, output reg VAR17, input wire VAR1,
input wire VAR20,
input wire [VAR12 - 1:0] VAR21,
input wire [VAR8 -1 :0] VAR7,
input wire VAR6,
input wire... | mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/system/synthesis/submodules/system_acl_iface_acl_kernel_interface.v | 60,109 | module MODULE1 (
input wire VAR58, input wire VAR40, output wire VAR311, output wire [31:0] VAR248, output wire VAR189, input wire [0:0] VAR149, input wire [31:0] VAR118, input wire [13:0] VAR50, input wire VAR283, input wire VAR6, input wire [3:0] VAR361, input wire VAR291, input wire VAR66, input wire [63:0] VAR258, ... | mit |
charcole/Z3 | altera/altpll0_bb.v | 11,072 | module MODULE1 (
VAR1,
VAR3,
VAR2);
input VAR1;
output VAR3;
output VAR2;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.symbol.v | 1,332 | module MODULE1 (
input VAR2 ,
output VAR1,
input VAR4 ,
input VAR3
);
endmodule | apache-2.0 |
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