repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2_4.v | 2,075 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR8 ,
VAR9,
VAR6,
VAR7 ,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR8 ;
input VAR9;
input VAR6;
input VAR7 ;
input VAR1 ;
VAR5 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR2,
VAR4,
VAR8
);
output VAR2;
... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_035.v | 1,598 | module MODULE1 (
VAR14,
VAR13
);
input [31:0] VAR14;
output [31:0]
VAR13;
wire [31:0]
VAR6,
VAR12,
VAR1,
VAR10,
VAR16,
VAR11,
VAR3,
VAR5,
VAR15,
VAR9,
VAR4;
assign VAR6 = VAR14;
assign VAR4 = VAR3 + VAR9;
assign VAR15 = VAR5 - VAR6;
assign VAR5 = VAR6 << 7;
assign VAR11 = VAR6 << 8;
assign VAR10 = VAR6 << 2;
assign VAR... | mit |
dvanmali/Superscalar_Pipeline_Processor | mainmem.v | 1,787 | module MODULE1(clk, VAR12,VAR1, address, VAR13,VAR6,VAR4, VAR2, VAR10, VAR14, VAR5, VAR7, VAR15, VAR8);
input clk, VAR6,VAR4, VAR12,VAR1, VAR2, VAR8;
input [31:0] address,VAR13;
input [127:0] VAR14;
input [19:0] VAR10;
input [127:0] VAR7;
output reg [127:0] VAR5;
output reg [127:0] VAR15;
reg VAR16;
reg [127:0] memory[... | apache-2.0 |
SymbiFlow/yosys | techlibs/intel/common/altpll_bb.v | 14,300 | module MODULE1
( VAR291,
VAR306,
VAR142,
VAR165,
VAR52,
VAR124,
VAR55,
VAR139,
VAR82,
VAR204,
VAR38,
VAR290,
VAR300,
VAR288,
VAR242,
VAR156,
VAR166,
VAR129,
VAR40,
clk,
VAR227,
VAR146,
VAR299,
VAR131,
VAR174,
VAR245,
VAR113,
VAR127,
VAR80,
VAR261,
VAR219,
VAR321,
VAR312,
VAR167,
VAR200,
VAR119,
VAR68,
VAR309,
VAR235,
V... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp.symbol.v | 1,338 | module MODULE1 (
input VAR6 ,
input VAR4 ,
input VAR1,
output VAR5
);
supply1 VAR8;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
csail-csg/connectal | verilog/altera/BRAM2.v | 3,660 | module MODULE1(VAR5,
VAR8,
VAR17,
VAR2,
VAR21,
VAR19,
VAR14,
VAR1,
VAR9,
VAR22,
VAR11,
VAR6
);
parameter VAR4 = 0;
parameter VAR12 = 1;
parameter VAR7 = 1;
parameter VAR3 = 1;
input VAR5;
input VAR8;
input VAR17;
input [VAR12-1:0] VAR2;
input [VAR7-1:0] VAR21;
output [VAR7-1:0] VAR19;
input VAR14;
input VAR1;
input VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill.blackbox.v | 1,170 | module MODULE1 ();
supply1 VAR2;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/pc2.v | 1,413 | module MODULE1(
input [0:55] VAR1,
output [0:47] VAR2
);
assign VAR2 = {VAR1[13], VAR1[16], VAR1[10], VAR1[23], VAR1[0], VAR1[4], VAR1[2], VAR1[27], VAR1[14], VAR1[5], VAR1[20], VAR1[9], VAR1[22], VAR1[18], VAR1[11], VAR1[3], VAR1[25], VAR1[7], VAR1[15], VAR1[6], VAR1[26], VAR1[19], VAR1[12], VAR1[1], VAR1[40], VAR1[51... | gpl-3.0 |
samyk/proxmark3 | fpga/hi_get_trace.v | 4,091 | module MODULE1(
VAR11,
VAR9, VAR8, VAR19,
VAR14, VAR10, VAR3
);
input VAR11;
input [7:0] VAR9;
input VAR8;
input [2:0] VAR19;
output VAR14, VAR10, VAR3;
reg [6:0] VAR16;
always @(negedge VAR11)
begin
VAR16 <= VAR16 + 1;
end
reg [2:0] VAR18;
always @(negedge VAR11)
begin
if (VAR18 == 3'd7)
VAR18 <= 3'd0;
end
else
VAR18 ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ba/sky130_fd_sc_hd__o21ba.pp.symbol.v | 1,383 | module MODULE1 (
input VAR7 ,
input VAR3 ,
input VAR5,
output VAR1 ,
input VAR6 ,
input VAR2,
input VAR8,
input VAR4
);
endmodule | apache-2.0 |
dekuNukem/FAP_Z80 | FAP_modules/video_card/FPGA_code/src/mojo_top.v | 2,531 | module MODULE1(
input clk,
input VAR18,
input VAR8,
output[7:0]VAR17,
output VAR34,
input VAR21,
input VAR40,
input VAR39,
output [3:0] VAR45,
input VAR7, output VAR13, input VAR30,
output VAR14,
output VAR24,
output VAR29,
output VAR23,
output [12:0] VAR4,
inout [7:0] VAR6,
output [12:0] VAR31,
inout [7:0] VAR49,
outp... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_tse_rgmii_module.v | 8,713 | module MODULE1 ( VAR37,
VAR50,
VAR32,
VAR41,
VAR5,
VAR53,
VAR55,
VAR25,
VAR57,
VAR26,
VAR31,
VAR43,
VAR2,
VAR45,
VAR42,
VAR1,
VAR24,
VAR52,
VAR48,
VAR56,
VAR15,
VAR21,
VAR27
);
parameter VAR20 = 3;
output [ 3: 0] VAR45;
output [ 7: 0] VAR42;
output [ 3: 0] VAR1;
output VAR24;
output VAR52;
output VAR48;
output VAR56;
o... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi_2.v | 2,457 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR6 ,
VAR7 ,
VAR12 ,
VAR1 ,
VAR8,
VAR11,
VAR9 ,
VAR5
);
output VAR3 ;
input VAR10 ;
input VAR6 ;
input VAR7 ;
input VAR12 ;
input VAR1 ;
input VAR8;
input VAR11;
input VAR9 ;
input VAR5 ;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR8... | apache-2.0 |
titorgalaxy/Titor | rtl/verilog/unused/Sign_Ext_Imm.v | 1,323 | module MODULE1 (
VAR3,
VAR2,
enable
);
output [VAR6-1:0] VAR3;
input [VAR6-1:0] VAR2;
input enable;
VAR1 VAR7(
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR4),
.VAR8(enable)
);
endmodule | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_21.v | 16,089 | module MODULE3 (
clk,
reset,
VAR12,
VAR62,
VAR104,
VAR131,
VAR41
);
parameter VAR30 = 18;
parameter VAR119 = 21;
parameter VAR2 = 11;
localparam VAR29 = 22;
input clk;
input reset;
input VAR12;
input VAR62;
input [VAR30-1:0] VAR104; output VAR131;
output [VAR30-1:0] VAR41;
localparam VAR3 = 18; localparam VAR106 = 36; ... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/ddr2_phy_ctl_io.v | 9,767 | module MODULE1 #
(
parameter VAR27 = 2,
parameter VAR68 = 1,
parameter VAR37 = 10,
parameter VAR12 = 1,
parameter VAR2 = 0,
parameter VAR15 = 1,
parameter VAR36 = 1,
parameter VAR58 = 14,
parameter VAR8 = 1
)
(
input VAR35,
input VAR29,
input VAR52,
input VAR54,
input [VAR58-1:0] VAR22,
input [VAR27-1:0] VAR24,
input V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai.pp.symbol.v | 1,417 | module MODULE1 (
input VAR8 ,
input VAR1 ,
input VAR10 ,
input VAR6 ,
input VAR4 ,
output VAR9 ,
input VAR2 ,
input VAR7,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp.functional.v | 1,693 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR8 ,
VAR1
);
output VAR4 ;
output VAR11 ;
input VAR8 ;
input VAR1;
wire VAR9 ;
wire VAR6;
wire VAR3 ;
VAR2 VAR12 VAR7 (VAR9 , VAR8, VAR1 );
buf VAR5 (VAR4 , VAR9 );
not VAR10 (VAR11 , VAR9 );
endmodule | apache-2.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/stratix2_pmem.v | 7,466 | module MODULE1 (
address,
VAR29,
VAR14,
VAR41,
VAR44,
VAR46,
VAR27);
input [11:0] address;
input [1:0] VAR29;
input VAR14;
input VAR41;
input [15:0] VAR44;
input VAR46;
output [15:0] VAR27;
tri1 [1:0] VAR29;
tri1 VAR14;
tri1 VAR41;
wire [15:0] VAR42;
wire [15:0] VAR27 = VAR42[15:0];
VAR6 VAR13 (
.VAR30 (VAR14),
.VAR19 ... | bsd-3-clause |
James534/SubZero | SubZero/fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_sysid.v | 1,408 | module MODULE1 (
address,
VAR3,
VAR1,
VAR2
)
;
output [ 31: 0] VAR2;
input address;
input VAR3;
input VAR1;
wire [ 31: 0] VAR2;
assign VAR2 = address ? 1435703700 : 0;
endmodule | mit |
aap/pdp6 | verilog/memif.v | 1,589 | module MODULE1(
input wire clk,
input wire reset,
input wire [1:0] VAR12,
input wire VAR5,
input wire VAR18,
input wire [31:0] VAR13,
output reg [31:0] VAR14,
output wire VAR16,
output wire [17:0] VAR11,
output reg VAR6,
output reg VAR4,
output wire [35:0] VAR1,
input wire [35:0] VAR8,
input wire VAR2
);
reg [17:0] add... | mit |
m-labs/milkymist | cores/tmu2/rtl/tmu2_divider17.v | 1,501 | module MODULE1(
input VAR3,
input VAR8,
input VAR6,
input [16:0] VAR4,
input [16:0] VAR9,
output ready,
output [16:0] VAR7,
output [16:0] VAR5
);
reg [33:0] VAR1;
assign VAR5 = VAR1[33:17];
assign VAR7 = VAR1[16:0];
reg [4:0] counter;
assign ready = (counter == 5'd0);
reg [16:0] VAR10;
wire [17:0] VAR2 = VAR1[33:16] - ... | lgpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/dbg_if_model.v | 15,211 | module MODULE1(
VAR32, VAR18, VAR17, VAR43, VAR34,
VAR23, VAR12, VAR39, VAR42, VAR41,
VAR16, VAR31, VAR1, VAR29, VAR40,
VAR13, VAR21, VAR19, VAR36, VAR7, VAR30,
VAR38, VAR27,
VAR11, VAR20, VAR37, VAR5, VAR22, VAR35,
VAR3, VAR44, VAR45, VAR33
);
parameter VAR28 = 1;
input VAR32; input VAR18; input VAR17; input VAR43; ou... | gpl-3.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_one_db_load/solution1/impl/verilog/contact_discoverycud.v | 1,805 | module MODULE1 (VAR9, VAR5, VAR4, VAR12, VAR1, VAR2, VAR11, VAR7, clk);
parameter VAR8 = 8;
parameter VAR10 = 19;
parameter VAR3 = 480000;
input[VAR10-1:0] VAR9;
input VAR5;
input[VAR8-1:0] VAR4;
input VAR12;
output reg[VAR8-1:0] VAR1;
input[VAR10-1:0] VAR2;
input VAR11;
output reg[VAR8-1:0] VAR7;
input clk;
reg [VAR8-... | gpl-3.0 |
alexforencich/xfcp | example/S10MX_DK/fpga/rtl/eth_xcvr_phy_wrapper.v | 5,234 | module MODULE1 (
input wire VAR85,
input wire VAR96,
input wire VAR59,
input wire VAR38,
input wire VAR31,
input wire VAR35,
output wire VAR24,
output wire VAR33,
output wire VAR22,
output wire VAR69,
output wire VAR2,
output wire VAR10,
input wire VAR26,
input wire VAR80,
output wire VAR82,
input wire VAR20,
output wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2/sky130_fd_sc_hs__mux2.pp.blackbox.v | 1,242 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR2 ,
VAR1 ,
VAR3,
VAR6
);
output VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR3;
input VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o.pp.blackbox.v | 1,368 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR5 ,
VAR1 ,
VAR8 ,
VAR4 ,
VAR6,
VAR3
);
output VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR6;
input VAR3;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_018bits.v | 1,917 | module MODULE2 (
clk,
VAR6, VAR1, VAR4, VAR27, VAR33, VAR30, VAR14, VAR22,
sum,
);
input clk;
input [VAR18+0-1:0] VAR6, VAR1, VAR4, VAR27, VAR33, VAR30, VAR14, VAR22;
output [VAR18 :0] sum;
reg [VAR18 :0] sum;
wire [VAR18+3-1:0] VAR32;
wire [VAR18+2-1:0] VAR5, VAR3;
wire [VAR18+1-1:0] VAR34, VAR24, VAR7, VAR13;
reg [VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3b/sky130_fd_sc_hs__or3b.functional.v | 1,871 | module MODULE1 (
VAR4,
VAR7,
VAR12 ,
VAR9 ,
VAR6 ,
VAR14
);
input VAR4;
input VAR7;
output VAR12 ;
input VAR9 ;
input VAR6 ;
input VAR14 ;
wire VAR3 ;
wire VAR8 ;
wire VAR1;
not VAR11 (VAR3 , VAR14 );
or VAR13 (VAR8 , VAR6, VAR9, VAR3 );
VAR2 VAR10 (VAR1, VAR8, VAR4, VAR7);
buf VAR5 (VAR12 , VAR1 );
endmodule | apache-2.0 |
OrganicMonkeyMotion/fpga_experiments | bmax10/Bemicro_m10_embedded_lab_14_0/bemicro_m10_embedded_lab_14_0/ip/i2c_opencores/i2c_master_byte_ctrl.v | 10,547 | module MODULE1 (
clk, rst, VAR23, VAR32, VAR3, VAR41, VAR17, read, write, VAR39, din,
VAR24, VAR11, dout, VAR8, VAR1, VAR20, VAR9, VAR34, VAR10, VAR21, VAR31 );
input clk; input rst; input VAR23; input VAR32;
input [15:0] VAR3;
input VAR41;
input VAR17;
input read;
input write;
input VAR39;
input [7:0] din;
output VAR2... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.blackbox.v | 1,496 | module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
wire VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
supply1 VAR4 ;
endmodule | apache-2.0 |
johan92/yafpgatetris | ip_cores/ps2_keyboard/PS2_Controller.v | 8,089 | module MODULE1 #(parameter VAR13 = 0) (
VAR4,
reset,
VAR29,
VAR2,
VAR35, VAR14,
VAR31,
VAR16,
VAR10,
VAR19 );
input VAR4;
input reset;
input [7:0] VAR29;
input VAR2;
inout VAR35;
inout VAR14;
output VAR31;
output VAR16;
output [7:0] VAR10;
output VAR19;
wire [7:0] VAR9;
wire VAR24, VAR5, VAR30;
generate
if(VAR13) begin... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s.pp.symbol.v | 1,358 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR1 ,
input VAR5,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_pnmon.v | 4,533 | module MODULE1 (
VAR2,
VAR4,
VAR8,
VAR11,
VAR16,
VAR17);
parameter VAR14 = 16;
localparam VAR6 = VAR14 - 1;
input VAR2;
input VAR4;
input [VAR6:0] VAR8;
input [VAR6:0] VAR11;
output VAR16;
output VAR17;
reg VAR12 = 'd0;
reg VAR1 = 'd0;
reg VAR3 = 'd0;
reg VAR17 = 'd0;
reg VAR16 = 'd0;
reg [ 3:0] VAR13 = 'd0;
wire VAR10... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4/sky130_fd_sc_hd__nand4_4.v | 2,253 | module MODULE2 (
VAR9 ,
VAR2 ,
VAR3 ,
VAR11 ,
VAR8 ,
VAR5,
VAR10,
VAR1 ,
VAR7
);
output VAR9 ;
input VAR2 ;
input VAR3 ;
input VAR11 ;
input VAR8 ;
input VAR5;
input VAR10;
input VAR1 ;
input VAR7 ;
VAR6 VAR4 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_2.behavioral.pp.v | 1,174 | module MODULE1( VAR6, VAR4, VAR7, VAR2 );
input VAR6;
inout VAR7, VAR2;
output VAR4;
VAR1 VAR5(.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2));
VAR1 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2)); | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_gmultp2_32x32.v | 4,878 | module MODULE1 ( VAR2, VAR3, VAR11, VAR9, VAR5 );
input [VAR4-1:0] VAR2;
input [VAR4-1:0] VAR3;
input VAR11;
input VAR9;
output [VAR1-1:0] VAR5;
reg [VAR1-1:0] VAR10;
reg [VAR1-1:0] VAR8;
integer VAR6;
integer VAR7;
always @(VAR2)
VAR6 <= VAR2;
always @(VAR3)
VAR7 <= VAR3;
always @(posedge VAR11 or posedge VAR9)
if (VA... | gpl-2.0 |
davidkoltak/tawas-core | ip/rcn/rtl/avalon2rcn.v | 2,446 | module MODULE1
(
input VAR20,
input VAR8,
output VAR6,
input [21:0] VAR4,
input VAR14,
input VAR23,
input [3:0] VAR5,
input [31:0] VAR19,
output [31:0] VAR15,
output VAR12,
input [68:0] VAR13,
output [68:0] VAR11
);
parameter VAR18 = 6'h3F;
reg [68:0] VAR22;
reg [68:0] VAR21;
reg [2:0] VAR1;
reg [2:0] VAR10;
reg [2:0] ... | mit |
somethingnew2-0/CS552-CPU | RoadRunner/provided_modules/clk_and_rst_n.v | 1,202 | module MODULE1;
parameter VAR7=1;
parameter VAR9=5;
parameter VAR4=100000;
reg clk, VAR11;
wire VAR3;
wire [15:0] VAR2;
integer VAR8;
VAR6 VAR1 (.clk(clk), .VAR11(VAR11), .VAR10(VAR3), .VAR5(VAR2));
VAR12 clk = VAR7;
always #VAR9 clk <= ~clk;
begin
begin
begin
begin | mit |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/imports/imports/sources_1/imports/Chapter11/ctrl.v | 1,541 | module MODULE1(
input wire rst,
input wire[31:0] VAR12,
input wire[VAR2] VAR3,
input wire VAR6,
input wire VAR9,
input wire VAR8,
output reg[VAR2] VAR5,
output reg VAR13,
output reg[5:0] VAR11
);
always @ (*) begin
if(rst == VAR7) begin
VAR11 <= 6'b000000;
VAR13 <= 1'b0;
VAR5 <= VAR1;
end else if(VAR12 != VAR1) begin
V... | gpl-3.0 |
zYeoman/32BIT-MIPS-CPU | Single/InstructionMem.v | 5,767 | module MODULE1 (
input [31:0] addr,
output reg [31:0] VAR1
);
parameter VAR3 = 128;
parameter VAR2 = 7;
always @ (*)
case (addr[VAR2+1:2])
7'd0: VAR1 = 32'h08000003;
7'd1: VAR1 = 32'h0800004b;
7'd2: VAR1 = 32'h08000002;
7'd3: VAR1 = 32'h20080014;
7'd4: VAR1 = 32'h01000008;
7'd5: VAR1 = 32'h3c104000;
7'd6: VAR1 = 32'h20... | gpl-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_asg.v | 16,343 | module MODULE1 (
output [ 14-1: 0] VAR12 , output [ 14-1: 0] VAR33 , input VAR64 , input VAR81, input VAR84 , input VAR60 , output [ 2-1: 0] VAR74,
input VAR23 ,
output [ 14-1: 0] VAR63,
input [ 32-1: 0] VAR65 , input [ 32-1: 0] VAR67 , input [ 4-1: 0] VAR19 , input VAR35 , input VAR57 , output reg [ 32-1: 0] VAR24 , o... | mit |
mgohde/MiniMicroII | RevisionB/ALU.v | 2,470 | module MODULE1(
VAR14,
VAR6,
VAR1,
VAR16,
VAR11,
out,
VAR18
);
input [3:0] VAR14;
input [7:0] VAR6;
input [15:0] VAR1;
input [15:0] VAR16;
output [7:0] VAR11;
output [15:0] out;
output VAR18;
wire [15:0] VAR5;
wire [16:0] VAR2;
wire [16:0] VAR17;
wire [15:0] VAR3;
wire [15:0] VAR4;
wire [15:0] VAR8;
wire [15:0] VAR15;
... | bsd-2-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/rtl_model/rom_1p.v | 2,832 | module MODULE1 (
clk ,
VAR8 ,
VAR3 ,
VAR10 ,
VAR6
);
parameter VAR1 = 32;
parameter VAR9 = 8;
input clk; input VAR8; input VAR3; input [VAR9-1:0] VAR10; output [VAR1-1:0] VAR6;
reg [VAR1-1:0] VAR5[(1<<VAR9)-1:0];
reg [VAR1-1:0] VAR7;
always @(posedge clk) begin
if (!VAR8)
VAR7 <= VAR5[VAR10];
end
else
VAR7 <= 'VAR4;
en... | gpl-3.0 |
fbalakirev/red-pitaya-notes | projects/red_pitaya_0_92/red_pitaya_pid_block.v | 5,021 | module MODULE1 #(
parameter VAR2 = 12 ,
parameter VAR4 = 18 ,
parameter VAR3 = 10
)
(
input VAR11 , input VAR19 , input [ 14-1: 0] VAR10 , output [ 14-1: 0] VAR13 ,
input [ 14-1: 0] VAR8 , input [ 14-1: 0] VAR16 , input [ 14-1: 0] VAR24 , input [ 14-1: 0] VAR23 , input VAR6 );
reg [ 15-1: 0] VAR15 ;
always @(posedge VA... | mit |
CeesWolfs/ceespu | src/intr/int_controller.v | 1,113 | module MODULE1(
input VAR1,
input VAR3,
input [2:0] VAR7,
input VAR4,
output reg VAR5 = 0,
output reg [1:0] VAR8 = 0
);
reg VAR2 = 0;
reg [2:0] VAR6 = 0;
always @(posedge VAR1) begin
if (VAR7[1]) begin
VAR6[1] <= 1;
end
if (VAR7[2]) begin
VAR6[2] <= 1;
end
if (VAR2) begin
if (VAR4) begin
VAR2 <= 0;
VAR6[VAR8] <= 0;
VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.functional.v | 1,384 | module MODULE1( VAR6, VAR15, VAR16, VAR17, VAR14, VAR19, VAR13 );
input VAR13, VAR19, VAR6, VAR16, VAR15, VAR14;
output VAR17;
wire VAR7;
not VAR2( VAR7, VAR15 );
wire VAR3;
not VAR12( VAR3, VAR14 );
wire VAR10;
and VAR20( VAR10, VAR7, VAR3, VAR13 );
wire VAR18;
and VAR1( VAR18, VAR3, VAR19, VAR15 );
wire VAR5;
and VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2.blackbox.v | 1,256 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
CeesWolfs/ceespu | src/gpu/ceespu_font_mem.v | 7,558 | module MODULE1 (
input clk,
input [6:0] VAR37,
input [3:0] VAR27,
input [2:0] VAR3,
output wire VAR75
);
VAR44 VAR58 (
.VAR61(clk),
.VAR26(1'b1),
.VAR35(1'b0),
.VAR33({VAR37[6:1], ~VAR37[0], VAR27, ~VAR3}),
.VAR38(1'b0),
.VAR69(1'b0),
.VAR46(VAR75)
);
endm... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_encode.v | 1,677 | module MODULE1
, parameter VAR15 = VAR4(VAR16)
)
(
input [VAR11(VAR16, 2):0] VAR10
, output logic [VAR15-1:0] VAR13
);
if (VAR16 == 1) begin: VAR12
assign VAR13 = 1'b0;
end
else begin: VAR6
for (genvar VAR8 = 0; VAR8 < VAR15; VAR8++) begin: VAR14
if (VAR8 == 0) begin: VAR2
assign VAR13[VAR15-1] = VAR10[0];
end
else beg... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s.functional.pp.v | 1,868 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR11,
VAR6,
VAR9 ,
VAR4
);
output VAR7 ;
input VAR10 ;
input VAR11;
input VAR6;
input VAR9 ;
input VAR4 ;
wire VAR2 ;
wire VAR1;
buf VAR3 (VAR2 , VAR10 );
VAR12 VAR8 (VAR1, VAR2, VAR11, VAR6);
buf VAR5 (VAR7 , VAR1 );
endmodule | apache-2.0 |
thinkoco/de1_soc_opencl | de10_nano_sharedonly_hdmi/ip/i2c/I2C_Controller.v | 2,478 | module MODULE1 (
input VAR9,
input [23:0]VAR18,
input VAR21,
input VAR13,
input VAR7,
inout VAR1,
output VAR22,
output VAR3,
output VAR16
);
wire VAR10 ;
assign VAR1 = VAR10?1'VAR8 :0 ;
VAR2 VAR15(
.VAR17 ( VAR13),
.VAR14 ( VAR9),
.VAR21 ( VAR21 ),
.VAR5 ( VAR3 ),
.VAR12 ( VAR16 ),
.VAR6 ( 2 ), .VAR20 ( VAR1 ), .VAR10 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_lp__udp_isolatch_pp_pkg_sn.symbol.v | 1,525 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR1 ,
input VAR5 ,
input VAR6,
input VAR4 ,
input VAR7
);
endmodule | apache-2.0 |
HFoxtail/Mu80 | trunk/icarus.v | 1,728 | module MODULE1;
reg clk;
reg VAR8;
wire [3:0] VAR6;
reg [7:0] VAR3;
wire [7:0] VAR2;
wire [19:0] address;
wire VAR12;
wire [15:0] VAR13;
wire [7:0] VAR4; wire [7:0] VAR9; wire VAR7;
wire [2:0] VAR1;
VAR8 VAR11(VAR8, VAR3, VAR2, address, VAR12, VAR6, VAR13, VAR4, VAR9, VAR7);
VAR10 VAR5(VAR7, VAR13, VAR4, VAR9, VAR1);
a... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3_m.v | 2,150 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR1 ,
VAR9 ,
VAR7,
VAR5,
VAR8 ,
VAR4
);
output VAR3 ;
input VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR7;
input VAR5;
input VAR8 ;
input VAR4 ;
VAR2 VAR10 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE2 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_pr_pp_pkg_sn/sky130_fd_sc_hs__udp_dlatch_pr_pp_pkg_sn.blackbox.v | 1,546 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR8 ,
VAR3 ,
VAR2 ,
VAR6,
VAR1 ,
VAR4 ,
VAR7
);
output VAR5 ;
input VAR9 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
input VAR6;
input VAR1 ;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.convolution.ok/db/ip/soc_design/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1500949681 : 255;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1n/sky130_fd_sc_lp__inputiso1n.functional.v | 1,359 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR5;
wire VAR2;
not VAR3 (VAR2 , VAR5 );
or VAR6 (VAR4 , VAR1, VAR2 );
endmodule | apache-2.0 |
jhol/butterflylogic | rtl/sram_interface.v | 7,425 | module MODULE1 #(
parameter VAR3 = 6*1024, parameter VAR8 = 13, parameter VAR20 = 32 )(
input wire clk,
input wire rst,
input wire VAR5,
input wire [3:0] VAR15,
input wire write,
input wire VAR18,
input wire [VAR20-1:0] VAR6,
input wire VAR11,
output reg VAR10,
output reg [3:0] VAR7,
output wire [VAR20-1:0] VAR14
);
re... | gpl-2.0 |
joaocarlos/udlx-verilog | rtl/execute/alu.v | 6,833 | module MODULE1
parameter VAR2 = 'd32,
parameter VAR4 = 6,
parameter VAR14 = 6,
parameter VAR22 = 'd32,
parameter VAR28 = 4
)
(
input clk,
input VAR35,
input en,
input [VAR2-1:0] VAR26, input [VAR2-1:0] VAR11, input [VAR4-1:0] VAR16, input [VAR14-1:0] VAR5, input [VAR22-1:0] VAR36,
output reg VAR37,
output [VAR2-1:0] VA... | lgpl-3.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/riffa/rx_port_requester_mux.v | 6,428 | module MODULE1 (
input VAR1,
input VAR16,
input VAR3, input [9:0] VAR28, input [63:0] VAR24, output VAR29,
input VAR18, input [9:0] VAR25, input [63:0] VAR2, output VAR8,
input VAR14, input [9:0] VAR15, input [63:0] VAR9, output VAR10,
output VAR27, input VAR19, output [1:0] VAR31, output [63:0] VAR20, output [9:0] VAR... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v | 7,052 | module MODULE1 (VAR12, VAR17, VAR10, VAR4, VAR18, VAR1, VAR6, VAR19,
VAR3, VAR16, VAR22, VAR20, VAR11, VAR13,
VAR15
);
input VAR12;
input VAR17;
input VAR10;
input VAR4;
input VAR18;
input VAR6;
input VAR1;
input VAR19;
input VAR3;
input VAR16;
output [1:0] VAR22;
output VAR20;
output VAR15;
output VAR11;
output VAR13;... | gpl-2.0 |
Gurint/EPC-Gen2-RFID-Tag-Baseband-Processor | cmd_buf.v | 2,623 | module MODULE1
(
output reg [7:0]VAR6,
output [51:0]VAR4,
output VAR7,
output VAR12,
output VAR10,
input VAR1,
input VAR8,
input VAR17,
input sync
);
parameter VAR9 = 8'b00001100;
parameter VAR3 = 8'b00001101;
parameter VAR18 = 8'b00111000;
parameter VAR13 = 8'b00111001;
parameter VAR14 = 8'b00111010;
parameter VAR5 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor2/sky130_fd_sc_hs__xnor2_1.v | 2,005 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR7 ,
VAR2,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR2;
input VAR1;
VAR6 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3,
VAR5,
VAR7
);
output VAR3;
input VAR5;
input VAR7;
supply1 VAR2;
supply0 VAR1;
VAR6 VAR4 (
.... | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/ciaa.v | 16,052 | module MODULE1
(
input clk, input VAR37,
input VAR17,
input VAR9, input rd, input wr, input reset, input [3:0] VAR69, input [7:0] VAR60, output [7:0] VAR99, input VAR78, input VAR46, output irq, input [7:2] VAR50, output [3:0] VAR49, output VAR87, inout VAR20, inout VAR40, input VAR67, input VAR45,
input VAR22,
input [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/edfxbp/sky130_fd_sc_lp__edfxbp.functional.pp.v | 2,082 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR1 ,
VAR10 ,
VAR17 ,
VAR14,
VAR12,
VAR13 ,
VAR3
);
output VAR4 ;
output VAR11 ;
input VAR1 ;
input VAR10 ;
input VAR17 ;
input VAR14;
input VAR12;
input VAR13 ;
input VAR3 ;
wire VAR15 ;
wire VAR6;
VAR7 VAR18 (VAR6, VAR15, VAR10, VAR17 );
VAR9 VAR2 VAR5 (VAR15 , VAR6, VAR1, , VAR14, VA... | apache-2.0 |
Murailab-arch/magukara | boards/ecp3versa/rtl/ipexpress/ecp3/pciex1/pcie_eval/models/ecp3/rx_gear.v | 6,134 | module MODULE1 #(
parameter VAR13 = 14
)
(
input wire VAR20 , input wire VAR10 , input wire VAR1 ,
input wire VAR2, input wire [VAR13-1:0] VAR7 ,
output wire [VAR13*2-1:0] VAR3 );
reg [1:0] VAR15 ; reg [1:0] VAR18 ; reg VAR16 ;
reg [VAR13-1:0] VAR8 ; reg [VAR13-1:0] VAR12 ;
integer VAR17 ;
integer VAR9 ;
reg [VAR13-1:0... | gpl-3.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_srl_fifo_64.v | 4,021 | module MODULE1 #
(
parameter VAR5 = 64,
parameter VAR14 = (VAR5/8),
parameter VAR3 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR5-1:0] VAR17,
input wire [VAR14-1:0] VAR12,
input wire VAR6,
output wire VAR25,
input wire VAR31,
input wire VAR1,
output wire [VAR5-1:0] VAR8,
output wire [VAR14-1:0] VAR4,
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.blackbox.v | 1,420 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR1 ,
VAR2,
VAR4 ,
VAR5
);
output VAR3 ;
input VAR6 ;
input VAR1 ;
input VAR2;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/phy/phy_rddata_sync.v | 23,750 | module MODULE1 #
(
parameter VAR3 = 100, parameter VAR71 = 64, parameter VAR19 = 8, parameter VAR64 = 8, parameter VAR53 = 4, parameter VAR61 = 4, parameter VAR52 = 4, parameter VAR47 = 4, parameter VAR14 = 32'h03020100, parameter VAR36 = 32'h07060504, parameter VAR31 = 0, parameter VAR22 = 0 )
(
input clk,
input [3:0]... | lgpl-3.0 |
olajep/oh | src/common/hdl/oh_iddr.v | 1,317 | module MODULE1 #(parameter VAR4 = 1 )
(
input clk, input VAR3, input [VAR4-1:0] din, output reg [VAR4-1:0] VAR1, output reg [VAR4-1:0] VAR2 );
reg [VAR4-1:0] VAR5;
reg [VAR4-1:0] VAR6;
always @ (posedge clk)
if(VAR3)
VAR5[VAR4-1:0] <= din[VAR4-1:0];
always @ (negedge clk)
VAR6[VAR4-1:0] <= din[VAR4-1:0];
always @ (pose... | mit |
sirchuckalot/zet | cores/vga/rtl/fml/vga_fifo.v | 8,385 | module MODULE1 (
clk,
VAR17,
VAR6,
VAR3,
VAR9,
VAR19,
VAR4,
VAR14,
VAR11,
VAR12,
VAR13,
VAR10
);
parameter VAR8 = 3; parameter VAR16 = 8;
input clk; input VAR17; input VAR6;
input VAR3; input VAR9; input [VAR16:1] VAR19; output [VAR16:1] VAR4;
output [VAR8:0] VAR14;
output VAR11; output VAR12;
output VAR13; output VAR1... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_Onchip_Memory.v | 3,968 | module MODULE1 (
address,
VAR10,
VAR24,
clk,
VAR25,
reset,
write,
VAR23,
VAR16
)
;
parameter VAR30 = "../MODULE1.VAR29";
output [ 31: 0] VAR16;
input [ 11: 0] address;
input [ 3: 0] VAR10;
input VAR24;
input clk;
input VAR25;
input reset;
input write;
input [ 31: 0] VAR23;
wire [ 31: 0] VAR16;
wire VAR4;
assign VAR4 = ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrbp/sky130_fd_sc_hd__sdfrbp_1.v | 2,695 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR10 ,
VAR12 ,
VAR11 ,
VAR8 ,
VAR2,
VAR6 ,
VAR5 ,
VAR7 ,
VAR4
);
output VAR1 ;
output VAR3 ;
input VAR10 ;
input VAR12 ;
input VAR11 ;
input VAR8 ;
input VAR2;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR4 ;
VAR9 VAR13 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR12(VAR12),
.VAR11(... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.behavioral.pp.v | 1,495 | module MODULE1( VAR6, VAR2, VAR1, VAR3, VAR7 );
input VAR2, VAR6;
inout VAR3, VAR7;
output VAR1;
VAR4 VAR8(.VAR6(VAR6),.VAR2(VAR2),.VAR1(VAR1),.VAR3(VAR3),.VAR7(VAR7));
VAR4 VAR5(.VAR6(VAR6),.VAR2(VAR2),.VAR1(VAR1),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2/sky130_fd_sc_ls__or2.behavioral.pp.v | 1,774 | module MODULE1 (
VAR13 ,
VAR12 ,
VAR4 ,
VAR2,
VAR11,
VAR6 ,
VAR7
);
output VAR13 ;
input VAR12 ;
input VAR4 ;
input VAR2;
input VAR11;
input VAR6 ;
input VAR7 ;
wire VAR3 ;
wire VAR8;
or VAR1 (VAR3 , VAR4, VAR12 );
VAR10 VAR5 (VAR8, VAR3, VAR2, VAR11);
buf VAR9 (VAR13 , VAR8 );
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/cic_interp.v | 2,581 | module MODULE1
(input VAR19,
input reset,
input enable,
input [7:0] VAR12,
input VAR3,
input VAR18,
input [VAR17-1:0] VAR15,
output reg [VAR17-1:0] VAR11);
integer VAR14;
localparam VAR7 = (VAR1-1)*VAR8;
wire [VAR17+VAR7-1:0] VAR2;
reg [VAR17+VAR7-1:0] VAR9 [0:VAR1-1];
reg [VAR17+VAR7-1:0] VAR10 [0:VAR1-1];
reg [VAR17+... | gpl-2.0 |
yunqu/PYNQ | boards/ip/fsm_io_switch_1.1/hdl/fsm_io_switch_v1_1_S_AXI.v | 23,131 | module MODULE1 #
(
parameter VAR9 = 20,
parameter VAR58 = 0,
parameter integer VAR118 = 32,
parameter integer VAR43 = 5
)
(
input [VAR9-1:0] VAR38,
input [3:0] VAR17,
output [VAR9-1:0] VAR78,
output [7:0]VAR20,
input [VAR9-1:0] VAR6,
output [VAR9-1:0] VAR33,
input wire VAR64,
input wire VAR50,
input wire [VAR43-1 : 0] ... | bsd-3-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_controller/motor_driver.v | 10,123 | module MODULE1
parameter VAR13 = 11,
localparam VAR63 = VAR13 - 1
)
(
input VAR47,
input VAR36,
input VAR56,
input VAR52,
input VAR30, input VAR34, input [2:0] VAR62,
input [VAR63:0] VAR29,
output VAR22,
output VAR35,
output VAR37,
output VAR20,
output VAR42,
output VAR19
);
reg VAR23;
reg [ 3:0] VAR41;
reg [15:0] VAR2... | gpl-3.0 |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_gen_reset.v | 4,864 | module MODULE1(
VAR37,
VAR41,
VAR13,
VAR19,
VAR35,
VAR15,
VAR6,
VAR16,
VAR20,
VAR34,
VAR24,
VAR18,
VAR22,
VAR21,
VAR5,
VAR39,
VAR40,
VAR29,
VAR11,
VAR42,
VAR32,
VAR45,
VAR30,
VAR46,
VAR27,
VAR4,
VAR26,
VAR12,
VAR7,
VAR17,
VAR43,
VAR1,
VAR44,
VAR28
);
input VAR37;
input VAR41;
input VAR19;
input VAR35;
input VAR15;
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2.pp.symbol.v | 1,302 | module MODULE1 (
input VAR6 ,
input VAR2 ,
output VAR7 ,
input VAR5 ,
input VAR3,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2b/sky130_fd_sc_ls__or2b.functional.pp.v | 1,924 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR10 ,
VAR5,
VAR11,
VAR14 ,
VAR13
);
output VAR2 ;
input VAR1 ;
input VAR10 ;
input VAR5;
input VAR11;
input VAR14 ;
input VAR13 ;
wire VAR15 ;
wire VAR7 ;
wire VAR12;
not VAR3 (VAR15 , VAR10 );
or VAR9 (VAR7 , VAR15, VAR1 );
VAR6 VAR4 (VAR12, VAR7, VAR5, VAR11);
buf VAR8 (VAR2 , VAR12 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.symbol.v | 1,338 | module MODULE1 (
input VAR7 ,
input VAR6 ,
input VAR1,
output VAR5
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
marmolejo/zet | cores/flash/flash8_r2.v | 3,665 | module MODULE1 (
input VAR5,
input VAR9,
input [15:0] VAR16,
output reg [15:0] VAR10,
input VAR6,
input VAR17,
input [ 1:0] VAR3,
input VAR13,
input VAR18,
output reg VAR11,
output reg [22:0] VAR14,
input [ 7:0] VAR12,
output VAR21,
output reg VAR1,
output reg VAR7,
output VAR2
);
wire VAR22;
wire VAR4;
wire VAR20;
reg... | gpl-3.0 |
rfotino/consolite-hardware | proj/ipcore_dir/s6_lpddr_ram/user_design/rtl/mcb_controller/mcb_soft_calibration.v | 57,110 | module MODULE1 # (
parameter VAR19 = 10'd512, parameter VAR120 = "VAR15", parameter VAR111 = "VAR74", parameter VAR205 = 1'b0, parameter VAR253 = 1'b0, parameter VAR54 = 1'b1, parameter VAR28 = "VAR222"
)
(
input wire VAR230, input wire VAR153, output reg VAR33,
input wire VAR172, input wire VAR189,
input wire VAR143,
... | mit |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/fpgaTop_ml555.v | 1,094 | module MODULE1(
input wire VAR1, input wire VAR7, input wire VAR19, input wire VAR10, input wire VAR8, output wire [7:0] VAR18, output wire [7:0] VAR2,
input wire [7:0] VAR17,
input wire [7:0] VAR4,
output wire [2:0] VAR12, input wire VAR9, output wire VAR6 );
VAR5 VAR13(
.VAR1 (VAR1),
.VAR7 (VAR7),
.VAR19 (VAR19),
.VA... | lgpl-3.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_spram_128x32.v | 7,595 | module MODULE1(
VAR17, VAR28, VAR16,
clk, rst, VAR18, VAR6, VAR24, addr, VAR3, VAR23
);
parameter VAR21 = 7;
parameter VAR4 = 32;
input VAR17;
input [VAR5 - 1:0] VAR16;
output VAR28;
input clk; input rst; input VAR18; input VAR6; input VAR24; input [VAR21-1:0] addr; input [VAR4-1:0] VAR3; output [VAR4-1:0] VAR23;
VAR19... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.functional.pp.v | 1,864 | module MODULE1( VAR6, VAR21, VAR22, VAR2, VAR14, VAR18, VAR12, VAR8, VAR16 );
input VAR14, VAR18, VAR12, VAR22, VAR21, VAR6;
inout VAR8, VAR16;
output VAR2;
wire VAR17;
not VAR4( VAR17, VAR14 );
wire VAR5;
not VAR25( VAR5, VAR18 );
wire VAR3;
not VAR9( VAR3, VAR12 );
wire VAR13;
and VAR24( VAR13, VAR17, VAR5, VAR3 );
w... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/ui_top.v | 13,780 | module MODULE1 #
(
parameter VAR53 = 100,
parameter VAR51 = 256,
parameter VAR74 = 32,
parameter VAR1 = 3,
parameter VAR35 = 12,
parameter VAR3 = 5,
parameter VAR38 = "VAR28",
parameter VAR69 = "VAR28",
parameter VAR33 = "VAR2",
parameter VAR10 = 4,
parameter VAR66 = 2,
parameter VAR36 = 16,
parameter VAR60 = "VAR13"
)... | mit |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_stub.v | 1,298 | module MODULE1(VAR2, VAR1, VAR3)
;
input [9:0]VAR2;
output [17:0]VAR1;
input VAR3;
endmodule | mit |
andykarpov/radio-86rk-wxeda | src/rom/biossd.v | 6,468 | module MODULE1 (
address,
VAR43,
VAR33);
input [11:0] address;
input VAR43;
output [7:0] VAR33;
tri1 VAR43;
wire [7:0] VAR3;
wire [7:0] VAR33 = VAR3[7:0];
VAR15 VAR11 (
.VAR13 (VAR43),
.VAR47 (address),
.VAR18 (VAR3),
.VAR4 (1'b0),
.VAR50 (1'b0),
.VAR9 (1'b1),
.VAR32 (1'b0),
.VAR40 (1'b0),
.VAR45 (1'b1),
.VAR51 (1'b1),... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill.behavioral.v | 1,110 | module MODULE1 ();
supply1 VAR4;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
yahniukov/FIFO_Verilog | src/design/fifo.v | 2,950 | module MODULE1 ( VAR31, VAR29, VAR3, VAR18, VAR15, VAR33, VAR24, VAR5, VAR16, reset );
parameter VAR9 = 1;
parameter VAR8 = 8;
localparam VAR13 = VAR12(VAR8);
input wire [VAR9 - 1 : 0] VAR31;
input wire VAR29, VAR3;
output wire [VAR9 - 1 : 0] VAR18;
input wire VAR15, VAR33;
output wire VAR24;
output wire VAR5, VAR16;
i... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a_0.v | 2,348 | module MODULE2 (
VAR11 ,
VAR2 ,
VAR6 ,
VAR8 ,
VAR5 ,
VAR7,
VAR1,
VAR4 ,
VAR10
);
output VAR11 ;
input VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR7;
input VAR1;
input VAR4 ;
input VAR10 ;
VAR9 VAR3 (
.VAR11(VAR11),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VA... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/synth/design_1_xbar_1.v | 19,518 | module MODULE1 (
VAR66,
VAR85,
VAR70,
VAR20,
VAR99,
VAR12,
VAR98,
VAR9,
VAR17,
VAR3,
VAR131,
VAR88,
VAR67,
VAR84,
VAR5,
VAR65,
VAR55,
VAR123,
VAR58,
VAR63,
VAR25,
VAR120,
VAR80,
VAR100,
VAR72,
VAR56,
VAR101,
VAR31,
VAR32,
VAR93,
VAR122,
VAR44,
VAR91,
VAR103,
VAR76,
VAR37,
VAR45,
VAR75,
VAR69,
VAR81,
VAR23,
VAR27,
VAR51... | gpl-3.0 |
myriadrf/A2300 | hdl/wca/WcaWriteFifo8W32R.v | 1,805 | module MODULE1(
input wire reset,
input wire VAR10, input wire VAR5, output wire [31:0] out,
output wire VAR8, output wire VAR13,
input wire [11:0] VAR2, inout wire [7:0] VAR3 );
parameter VAR9 = 0;
wire VAR1 = (VAR9 == VAR2[11:4]) & VAR2[2];
wire VAR6 = VAR1 & VAR2[1];
VAR11 VAR12 (
.rst(reset), .VAR4(VAR2[0]), .VAR10... | gpl-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v | 57,364 | module MODULE1 #
(
parameter VAR353 = 100,
parameter VAR343 = "135", parameter VAR401 = 64,
parameter VAR61 = "VAR53",
parameter VAR362 = "0", parameter VAR142 = 3, parameter VAR225 = 2, parameter VAR294 = "8", parameter VAR133 = "VAR16", parameter VAR372 = "VAR368", parameter VAR333 = 1, parameter VAR205 = 5,
paramete... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtp/sky130_fd_sc_ls__dfrtp.behavioral.v | 2,202 | module MODULE1 (
VAR11 ,
VAR10 ,
VAR5 ,
VAR18
);
output VAR11 ;
input VAR10 ;
input VAR5 ;
input VAR18;
supply1 VAR3;
supply0 VAR12;
supply1 VAR16 ;
supply0 VAR20 ;
wire VAR4 ;
wire VAR21 ;
reg VAR9 ;
wire VAR19 ;
wire VAR14;
wire VAR15 ;
wire VAR2 ;
wire VAR6 ;
wire VAR8 ;
not VAR17 (VAR21 , VAR14 );
VAR1 VAR13 (VAR4 ... | apache-2.0 |
ThotIP/async_fifo | src/vlog/fifomem_dp.v | 2,839 | module MODULE1
parameter VAR12 = 8, parameter VAR15 = 4, parameter VAR20 = "VAR24" ) (
input wire VAR3,
input wire [VAR12-1:0] VAR2,
output wire [VAR12-1:0] VAR16,
input wire [VAR15-1:0] VAR9,
input wire VAR8,
input wire VAR7,
input wire VAR6,
input wire [VAR12-1:0] VAR11,
output wire [VAR12-1:0] VAR23,
input wire [VAR... | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v | 25,631 | module MODULE1
(
VAR1,
VAR28,
VAR34,
VAR4,
VAR23
);
parameter VAR32 = 8; parameter VAR17 = 16;
parameter VAR31 = 4'h0; parameter VAR26 = 4'h1; parameter VAR36 = 4'h2; parameter VAR5 = 4'h3; parameter VAR8 = 4'h4; parameter VAR15 = 4'h5; parameter VAR2 = 4'h8; parameter VAR9 = 4'h9; parameter VAR13 = 4'h6; parameter VAR... | lgpl-3.0 |
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