repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
peteasa/oh | src/common/dv/dv_driver.v | 4,055 | module MODULE1 #( parameter VAR29 = 1, parameter VAR14 = 32, parameter VAR22 = 104, parameter VAR30 = 12, parameter VAR27 = "none", parameter VAR20 = 1, parameter VAR21 = 16 )
(
input VAR2,
input VAR5,
input VAR9,
input VAR28, input [VAR30-1:0] VAR6, input [VAR29-1:0] VAR12,
input [VAR29*VAR22-1:0] VAR23,
input [VAR29-... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi.behavioral.v | 1,544 | module MODULE1 (
VAR12 ,
VAR9,
VAR3,
VAR8,
VAR5
);
output VAR12 ;
input VAR9;
input VAR3;
input VAR8;
input VAR5;
supply1 VAR11;
supply0 VAR14;
supply1 VAR13 ;
supply0 VAR4 ;
wire VAR7 ;
wire VAR10;
and VAR2 (VAR7 , VAR8, VAR9, VAR3 );
nor VAR1 (VAR10, VAR5, VAR7 );
buf VAR6 (VAR12 , VAR10 );
endmodule | apache-2.0 |
YosysHQ/yosys | techlibs/gowin/brams_map.v | 9,019 | function [255:0] VAR51; \
input integer VAR147; \
integer VAR84; \
for (VAR84 = 0; VAR84 < 32; VAR84 = VAR84 + 1) begin \
VAR51[VAR84*8+:8] = VAR88[(VAR147 * 32 + VAR84) * 9+:8]; \
end \
endfunction \
function [287:0] VAR14; \
input integer VAR147; \
VAR14 = VAR88[VAR147 * 288+:288]; \
endfunction \
.VAR27(VAR141('h00)... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor2/sky130_fd_sc_hd__xor2.behavioral.v | 1,381 | module MODULE1 (
VAR6,
VAR4,
VAR1
);
output VAR6;
input VAR4;
input VAR1;
supply1 VAR2;
supply0 VAR7;
supply1 VAR10 ;
supply0 VAR8 ;
wire VAR3;
xor VAR5 (VAR3, VAR1, VAR4 );
buf VAR9 (VAR6 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfstp/sky130_fd_sc_hd__sdfstp_4.v | 2,511 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR3 ,
VAR5 ,
VAR7 ,
VAR6,
VAR11 ,
VAR8 ,
VAR4 ,
VAR2
);
output VAR9 ;
input VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR6;
input VAR11 ;
input VAR8 ;
input VAR4 ;
input VAR2 ;
VAR10 VAR12 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR11(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand2/sky130_fd_sc_hvl__nand2.blackbox.v | 1,243 | module MODULE1 (
VAR2,
VAR6,
VAR5
);
output VAR2;
input VAR6;
input VAR5;
supply1 VAR4;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_1.v | 2,258 | module MODULE1 (
VAR5 ,
VAR6,
VAR9 ,
VAR7 ,
VAR8 ,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR6;
input VAR9 ;
input VAR7 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
VAR4 VAR1 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR5 ,
VAR6,
VAR9
);
output VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai.pp.symbol.v | 1,376 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR6 ,
input VAR4 ,
output VAR9 ,
input VAR3 ,
input VAR7,
input VAR8,
input VAR5
);
endmodule | apache-2.0 |
revaldinho/opc | system/blackice/system_32.v | 4,619 | module MODULE1 (
input VAR58,
output VAR16,
output VAR38,
output VAR45,
output VAR42,
input VAR25,
input VAR60,
input VAR49,
input VAR30,
input VAR69,
input VAR44,
output VAR1,
output VAR17,
output VAR6,
output [17:0] VAR10,
inout [15:0] VAR40,
input VAR21,
output VAR7);
parameter VAR35 = 50000000;
parameter VAR19 = 11... | gpl-3.0 |
ptracton/UART_ECHO | rtl/fifo.v | 6,762 | module MODULE1 (
VAR13, VAR7, VAR9,
VAR11, VAR10, VAR20, VAR17, VAR2, VAR3, VAR16
) ;
parameter VAR1 = 32; parameter VAR5 = 3; parameter VAR6 = 2 ** VAR5;
input VAR11; input VAR10; input VAR20; input VAR17; input [VAR1 - 1:0] VAR2; input VAR3; input VAR16;
output [VAR1 - 1:0] VAR13; output VAR7; output VAR9;
reg VAR9;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxtp/sky130_fd_sc_lp__dfxtp.behavioral.pp.v | 1,788 | module MODULE1 (
VAR15 ,
VAR2 ,
VAR6 ,
VAR4,
VAR12,
VAR8 ,
VAR13
);
output VAR15 ;
input VAR2 ;
input VAR6 ;
input VAR4;
input VAR12;
input VAR8 ;
input VAR13 ;
wire VAR9 ;
reg VAR3 ;
wire VAR14 ;
wire VAR11;
wire VAR7 ;
VAR1 VAR5 (VAR9 , VAR14, VAR11, VAR3, VAR4, VAR12);
assign VAR7 = ( VAR4 === 1'b1 );
buf VAR10 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o.behavioral.pp.v | 2,231 | module MODULE1 (
VAR3 ,
VAR16,
VAR12,
VAR10 ,
VAR6 ,
VAR18,
VAR19,
VAR17 ,
VAR9
);
output VAR3 ;
input VAR16;
input VAR12;
input VAR10 ;
input VAR6 ;
input VAR18;
input VAR19;
input VAR17 ;
input VAR9 ;
wire VAR15 ;
wire VAR7 ;
wire VAR13 ;
wire VAR1;
and VAR11 (VAR15 , VAR10, VAR6 );
nor VAR4 (VAR7 , VAR16, VAR12 );
o... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_adcfifo/axi_adcfifo_wr.v | 14,794 | module MODULE1 (
VAR12,
VAR61,
VAR63,
VAR82,
VAR83,
VAR79,
VAR40,
VAR81,
VAR99,
VAR18,
VAR15,
VAR92,
VAR41,
VAR57,
VAR28,
VAR50,
VAR7,
VAR65,
VAR90,
VAR17,
VAR89,
VAR38,
VAR93,
VAR85,
VAR62,
VAR25,
VAR88,
VAR48,
VAR21,
VAR98,
VAR67,
VAR4,
VAR33,
VAR47,
VAR34);
parameter VAR29 = 512;
parameter VAR2 = 2;
parameter VAR22 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi.functional.pp.v | 2,260 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR15 ,
VAR3 ,
VAR7 ,
VAR6 ,
VAR9,
VAR14,
VAR13 ,
VAR16
);
output VAR12 ;
input VAR1 ;
input VAR15 ;
input VAR3 ;
input VAR7 ;
input VAR6 ;
input VAR9;
input VAR14;
input VAR13 ;
input VAR16 ;
wire VAR8 ;
wire VAR10 ;
wire VAR2 ;
wire VAR11;
nand VAR4 (VAR8 , VAR15, VAR1, VAR3 );
nand VA... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_clk_gen/bsg_clk_gen_osc.v | 6,735 | module MODULE1
import VAR23::VAR13;
(
input VAR13 VAR5
,input VAR13 VAR22
,input VAR27
,output VAR35
);
wire VAR32;
wire VAR20 = ~VAR27;
VAR30 VAR19;
wire VAR17;
wire VAR24, VAR26;
VAR3
,.VAR4(1)
) VAR29
(.VAR5(VAR5)
,.VAR34(VAR19)
);
VAR3
,.VAR4(1)
) VAR11
(.VAR5(VAR22)
,.VAR34(VAR17)
);
wire VAR12, VAR21;
wire VAR33;... | bsd-3-clause |
Tsung-Wei/OpenTimer | benchmark/c499/c499.v | 14,553 | module MODULE1 (
VAR3,
VAR16,
VAR302,
VAR12,
VAR290,
VAR172,
VAR24,
VAR132,
VAR149,
VAR167,
VAR160,
VAR70,
VAR328,
VAR71,
VAR39,
VAR207,
VAR87,
VAR158,
VAR366,
VAR159,
VAR113,
VAR179,
VAR229,
VAR29,
VAR321,
VAR193,
VAR136,
VAR192,
VAR344,
VAR349,
VAR168,
VAR208,
VAR300,
VAR295,
VAR143,
VAR354,
VAR196,
VAR378,
VAR28,
VA... | gpl-3.0 |
parallella/oh | common/hdl/oh_crc.v | 1,364 | module MODULE1 #( parameter VAR5 = "VAR9", parameter VAR8 = 8) (
input [VAR8-1:0] VAR6, input [VAR7-1:0] VAR1, output [VAR7-1:0] VAR3 );
localparam VAR7 = 32;
generate
if(VAR5=="VAR9")
begin
if(VAR8==8)
VAR10 VAR4(
.VAR3 (VAR3[31:0]),
.VAR6 (VAR6[7:0]),
.VAR1 (VAR1[31:0]));
end
else if(VAR8==64)
VAR2 VAR4(
.VAR3 (VAR3[... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai.pp.symbol.v | 1,387 | module MODULE1 (
input VAR7 ,
input VAR9 ,
input VAR6 ,
input VAR2 ,
input VAR8 ,
output VAR5 ,
input VAR10 ,
input VAR3,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
fpgasystems/caribou | hw/src/nukv/nukv_predicate_eval.v | 11,345 | module MODULE1 #(
parameter VAR39 = 512,
parameter VAR31 = 96,
parameter VAR37 = 1,
parameter VAR38 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR31+VAR39-1:0] VAR11,
input wire VAR32,
input wire VAR47,
output reg VAR30,
input wire [VAR39-1:0] VAR20,
input wire VAR40,
input wire VAR18,
input wire VAR43,
output... | gpl-3.0 |
samyk/proxmark3 | fpga/min_max_tracker.v | 2,395 | module MODULE1(input clk, input [7:0] VAR7, input [7:0] VAR1,
output [7:0] VAR6, output [7:0] VAR5);
reg [7:0] VAR2 = 255;
reg [7:0] VAR4 = 0;
reg [7:0] VAR8 = 255;
reg [7:0] VAR3 = 0;
reg [1:0] state = 0;
always @(posedge clk)
begin
case (state)
0: begin
if (VAR3 >= ({1'b0, VAR7} + VAR1))
state <= 2;
end
else if (VAR7... | gpl-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/decoder_axi_modules/decoder_axi_m_v1_0.v | 5,819 | module MODULE1 #
(
parameter integer VAR13 = 16,
parameter integer VAR94 = 1,
parameter integer VAR53 = 32,
parameter integer VAR73 = 32,
parameter integer VAR4 = 0,
parameter integer VAR116 = 0,
parameter integer VAR97 = 0,
parameter integer VAR100 = 0,
parameter integer VAR76 = 0
)
(
output wire [31:0] VAR35,
output ... | gpl-3.0 |
Arlet/vga16 | async_fifo.v | 1,276 | module MODULE1(
input VAR16,
input [17:0] in,
input wr,
output VAR11,
input VAR27,
output [17:0] out,
input rd,
output VAR15 );
reg [10:0] heada = 0;
reg [10:0] headab = 0;
reg [10:0] headb = 0;
reg [10:0] VAR23 = 0;
reg [10:0] VAR2 = 0;
reg [10:0] VAR3 = 0;
wire [10:0] VAR1 = (heada - VAR3);
assign VAR11 = (VAR1 >= 11... | lgpl-2.1 |
oddball/genMem | rtl/twoPortMem.v | 4,543 | module MODULE1 (
VAR9,
VAR12,
VAR13,
VAR3,
VAR8,
VAR4,
VAR11,
VAR7);
parameter VAR1 = 32;
parameter VAR10 = 8;
parameter VAR2 = 0;
parameter VAR5 = 1;
localparam VAR6 =VAR14(VAR1);
input [VAR6-1:0] VAR9;
input VAR12;
input [VAR5-1:0] VAR13;
input [VAR10-1:0] VAR3;
input [VAR6-1:0] VAR8;
input VAR4;
input VAR11;
output ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3/sky130_fd_sc_ms__or3.functional.pp.v | 1,801 | module MODULE1 (
VAR5 ,
VAR13 ,
VAR14 ,
VAR12 ,
VAR6,
VAR9,
VAR3 ,
VAR7
);
output VAR5 ;
input VAR13 ;
input VAR14 ;
input VAR12 ;
input VAR6;
input VAR9;
input VAR3 ;
input VAR7 ;
wire VAR1 ;
wire VAR2;
or VAR8 (VAR1 , VAR14, VAR13, VAR12 );
VAR10 VAR4 (VAR2, VAR1, VAR6, VAR9);
buf VAR11 (VAR5 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ebufn/sky130_fd_sc_hs__ebufn.functional.v | 1,764 | module MODULE1 (
VAR10,
VAR9,
VAR5 ,
VAR8 ,
VAR3
);
input VAR10;
input VAR9;
output VAR5 ;
input VAR8 ;
input VAR3;
wire VAR11 ;
wire VAR1;
VAR7 VAR4 (VAR11 , VAR8, VAR10, VAR9 );
VAR7 VAR6 (VAR1, VAR3, VAR10, VAR9 );
bufif0 VAR2 (VAR5 , VAR11, VAR1);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a.behavioral.v | 1,662 | module MODULE1 (
VAR6 ,
VAR11,
VAR3,
VAR8,
VAR5,
VAR16
);
output VAR6 ;
input VAR11;
input VAR3;
input VAR8;
input VAR5;
input VAR16;
supply1 VAR10;
supply0 VAR14;
supply1 VAR15 ;
supply0 VAR2 ;
wire VAR12 ;
wire VAR1 ;
wire VAR13;
or VAR4 (VAR12 , VAR5, VAR8 );
or VAR7 (VAR1 , VAR3, VAR11 );
and VAR9 (VAR13, VAR12, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp.functional.pp.v | 1,881 | module MODULE1 (
VAR13 ,
VAR9 ,
VAR6 ,
VAR4,
VAR7 ,
VAR8 ,
VAR5 ,
VAR3
);
output VAR13 ;
input VAR9 ;
input VAR6 ;
input VAR4;
input VAR7 ;
input VAR8 ;
input VAR5 ;
input VAR3 ;
wire VAR11;
wire VAR14;
not VAR2 (VAR14 , VAR4 );
VAR10 VAR1 VAR12 (VAR11 , VAR6, VAR9, VAR14, , VAR7, VAR8);
buf VAR15 (VAR13 , VAR11 );
end... | apache-2.0 |
chasingegg/Computer_Systems | CS334_computer organization lab/source/lab3_alu/alu.v | 1,545 | module MODULE1(
output VAR2,
output [31:0] VAR4,
input [31:0] VAR5,
input [31:0] VAR1,
input [3:0] VAR3
);
reg VAR2;
reg [31:0] VAR4;
always @ (VAR5 or VAR1 or VAR3)
begin
if(VAR3 == 4'b0010) VAR4 = VAR5 + VAR1;
end
else if(VAR3 == 4'b0110) begin
VAR4 = VAR5 - VAR1;
if(VAR4 == 0)
VAR2 = 1;
end
else
VAR2 = 0;
end
else i... | mit |
alexforencich/verilog-ethernet | rtl/gmii_phy_if.v | 4,067 | module MODULE1 #
(
parameter VAR13 = "VAR26",
parameter VAR36 = "VAR14",
parameter VAR40 = "VAR43"
)
(
input wire clk,
input wire rst,
output wire VAR37,
output wire VAR44,
output wire [7:0] VAR16,
output wire VAR31,
output wire VAR2,
output wire VAR4,
output wire VAR6,
input wire [7:0] VAR29,
input wire VAR32,
input w... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/src/v/bsg_wormhole_stream_control.v | 3,968 | module MODULE1
, parameter [VAR4-1:0] VAR3(VAR35)
)
(input VAR31
, input VAR17
, input [VAR4-1:0] VAR12
, input VAR36
, output VAR30
, output VAR5
);
enum logic {VAR15, VAR7} VAR25, VAR32;
wire VAR26 = (VAR32 == VAR15);
wire VAR18 = (VAR32 == VAR7);
assign VAR30 = VAR26;
assign VAR5 = VAR18;
wire [VAR4-1:0] VAR14 = VAR... | bsd-3-clause |
elleandroculia/dflow-doc | tech/osu035/osu035_stdcells.v | 24,007 | module MODULE1 (VAR1, VAR2, VAR3);
input VAR1 ;
input VAR2 ;
output VAR3 ;
and (VAR3, VAR1, VAR2); | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor3/sky130_fd_sc_hd__xor3_2.v | 2,199 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR5 ,
VAR6 ,
VAR8,
VAR9,
VAR3 ,
VAR7
);
output VAR10 ;
input VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR9;
input VAR3 ;
input VAR7 ;
VAR1 VAR4 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
esonghori/TinyGarbled | circuit_synthesis/stack_machine/stackMachine.v | 1,724 | module MODULE1
parameter VAR1=8, parameter VAR9=8 )
(
clk,
rst,
VAR2,
VAR4,
VAR8
);
input clk;
input rst;
input signed [VAR1-1:0] VAR2;
input [2:0] VAR4;
output reg signed [VAR1-1:0] VAR8;
reg signed [VAR1-1:0] alu;
reg signed [VAR1-1:0] VAR7[VAR9-1:0];
reg VAR3;
reg VAR6;
reg VAR5;
integer VAR10;
always@
begin
if(VAR3... | gpl-3.0 |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/data_select.v | 1,943 | module MODULE1(
VAR1,
VAR5,
VAR3,
VAR2,
VAR4,
sel
);
input [15:0] VAR1;
input [15:0] VAR5;
input [15:0] VAR3;
input [7:0] VAR2;
input [1:0] sel;
output [15:0] VAR4;
reg [15:0] VAR4;
always @(sel, VAR1, VAR5, VAR3, VAR2) begin
case (sel)
2'b00 : VAR4 <= VAR1;
2'b01 : VAR4 <= VAR5;
2'b10 : VAR4 <= VAR3;
2'b11 : VAR4 <= {... | mit |
eSedano/vrudy | rtl/ctrl_top.v | 5,762 | module MODULE1 (
input wire clk,
input wire VAR21,
input wire [1:0] VAR12,
input wire VAR4,
output reg VAR11,
output reg VAR8,
output reg VAR17,
output reg VAR2,
output reg VAR15,
output reg VAR9,
output reg VAR7,
output reg [1:0] VAR6,
output reg VAR13,
output reg VAR16,
output reg VAR20
);
localparam VAR3 = 3'b000;
l... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2_8.v | 2,102 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR2 ,
VAR9,
VAR6,
VAR7 ,
VAR8
);
output VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR9;
input VAR6;
input VAR7 ;
input VAR8 ;
VAR4 VAR5 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR1,
VAR3,
VAR2
);
output VAR1;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi.blackbox.v | 1,334 | module MODULE1 (
VAR2 ,
VAR6,
VAR4,
VAR8
);
output VAR2 ;
input VAR6;
input VAR4;
input VAR8;
supply1 VAR1;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_4.behavioral.v | 3,689 | module MODULE1( VAR19, VAR21, VAR6, VAR31 );
input VAR19, VAR21, VAR6;
output VAR31;
reg VAR9;
VAR32 VAR26(.VAR19(VAR19),.VAR21(VAR21),.VAR6(VAR6),.VAR31(VAR31),.VAR9(VAR9));
VAR32 VAR23(.VAR19(VAR19),.VAR21(VAR21),.VAR6(VAR6),.VAR31(VAR31),.VAR9(VAR9));
not VAR8(VAR15,VAR21);
and VAR11(VAR16,VAR6,VAR15);
and VAR18(VAR... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/generic/adapter_bram_2_axi_stream.v | 6,458 | module MODULE1 #(
parameter VAR3 = 32,
parameter VAR17 = 8,
parameter VAR33 = VAR3 / 8,
parameter VAR7 = 0,
parameter VAR22 = 1
)(
input clk,
input rst,
input [VAR22 - 1:0] VAR34,
input VAR20,
input [VAR17 - 1:0] VAR29,
output reg [VAR17 - 1:0] VAR28,
input [VAR3 - 1:0] VAR21,
output [VAR22 - 1:0] VAR26,
input VAR16,
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b.blackbox.v | 1,331 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR2 ,
VAR4
);
output VAR3 ;
input VAR7 ;
input VAR2 ;
input VAR4;
supply1 VAR8;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_common_avalon_mm_master.v | 3,279 | module MODULE1
( VAR8,
reset,
VAR6,
VAR47,
VAR32,
VAR13,
VAR28,
VAR37,
VAR49,
VAR18,
VAR41,
VAR21,
addr,
VAR11,
VAR20,
VAR5,
VAR27,
VAR54,
write,
VAR48,
read,
VAR43);
parameter VAR44 = 16;
parameter VAR36 = 16;
parameter VAR46 = 11;
parameter VAR56 = 1;
parameter VAR45 = 1;
parameter VAR33 = 8;
parameter VAR7 = 8;
para... | mit |
SeanZarzycki/openSPARC-FPU | project/src/fpu_rptr_groups_hier.v | 56,765 | module MODULE1 ( VAR106, VAR92, VAR2, VAR95, VAR23,
VAR50, VAR44, VAR70,
VAR100, VAR42, VAR33,
VAR55, VAR7, VAR18,
VAR63, VAR26, VAR41,
VAR19, VAR65, VAR75,
VAR11, VAR48, VAR9, VAR68, VAR53, VAR25,
VAR117, VAR80, VAR32, VAR109, VAR37,
VAR86, VAR13, VAR89,
VAR99, VAR36, VAR4, VAR77,
VAR82, VAR81, VAR57, VAR85,
VAR103, V... | gpl-3.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_gt_rx_valid_filter_7x.v | 9,124 | module MODULE1 #(
parameter VAR19 = 28,
parameter VAR44 = 1
)
(
output [1:0] VAR3,
output [15:0] VAR6,
output VAR26,
output VAR17,
output [ 2:0] VAR5,
output VAR15,
input [1:0] VAR21,
input [15:0] VAR25,
input VAR1,
input VAR45,
input [ 2:0] VAR34,
input VAR13,
input VAR38,
input VAR27,
input VAR22,
input VAR7
);
local... | gpl-2.0 |
eda-globetrotter/PicenoDecoders | extra_credit/spare/build1/decoder.v | 1,236 | module MODULE1 (VAR2,VAR3);
output reg [14:0] VAR2;
input [10:0] VAR4;
reg [3:0] VAR1;
always @(*)
begin
VAR1[0]=VAR4[0]^VAR4[1]^VAR4[3]^VAR4[4]^VAR4[6]^VAR4[8]^VAR4[10];
VAR1[1]=((VAR4[0]^VAR4[2])^(VAR4[3]^VAR4[5]))^((VAR4[6]^VAR4[9])^VAR4[10]);
VAR1[2]=((VAR4[1]^VAR4[2])^(VAR4[3]^VAR4[7]))^((VAR4[8]^VAR4[9])^VAR4[10]... | mit |
m-labs/milkymist | cores/bt656cap/rtl/bt656cap_burstmem.v | 1,141 | module MODULE1(
input VAR9,
input VAR8,
input [2:0] VAR4,
input [31:0] VAR1,
input [1:0] VAR5,
output [63:0] rd
);
reg [31:0] VAR6[0:3];
reg [31:0] VAR2;
always @(posedge VAR9) begin
if(VAR8 & ~VAR4[0])
VAR6[VAR4[2:1]] <= VAR1;
VAR2 <= VAR6[VAR5];
end
reg [31:0] VAR3[0:3];
reg [31:0] VAR7;
always @(posedge VAR9) begin
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.v | 2,174 | module MODULE2 (
VAR3,
VAR4 ,
VAR2 ,
VAR1 ,
VAR7
);
output VAR3;
input VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR7 ;
VAR6 VAR5 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR3,
VAR4
);
output VAR3;
input VAR4 ;
supply1 VAR2;
supply1 VAR1 ;
supply0 VAR7 ;
VAR6 VAR5 (
.... | apache-2.0 |
racerxdl/LVDS-7-to-1-Serializer | src/serializer.v | 2,432 | module MODULE1(
input clk,
input VAR16,
input VAR11,
input [6:0] VAR4,
input rst,
output out
);
reg [6:0] buffer [1:0]; reg [1:0] VAR3 = 0;
reg VAR2 = 0;
reg [2:0] VAR18 = 0;
reg VAR6 = 0;
reg VAR20 = 0;
VAR1 #(
.VAR7("VAR17") ) VAR12 (
.VAR10(out), .VAR9(VAR16), .VAR8(VAR11), .VAR13(1'b1), .VAR5(VAR3[0]), .VAR19(VAR3[... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxtp/sky130_fd_sc_ms__edfxtp.symbol.v | 1,424 | module MODULE1 (
input VAR4 ,
output VAR7 ,
input VAR3 ,
input VAR8
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn.functional.pp.v | 1,872 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR4,
VAR13,
VAR3,
VAR12 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR4;
input VAR13;
input VAR3;
input VAR12 ;
input VAR6 ;
wire VAR10 ;
wire VAR9;
VAR11 VAR7 (VAR10 , VAR5, VAR13, VAR3 );
VAR11 VAR2 (VAR9, VAR4, VAR13, VAR3 );
notif0 VAR8 (VAR1 , VAR10, VAR9);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a.behavioral.v | 1,508 | module MODULE1 (
VAR6 ,
VAR9,
VAR1,
VAR12
);
output VAR6 ;
input VAR9;
input VAR1;
input VAR12;
supply1 VAR7;
supply0 VAR11;
supply1 VAR13 ;
supply0 VAR2 ;
wire VAR8 ;
wire VAR3;
or VAR5 (VAR8 , VAR1, VAR9 );
and VAR4 (VAR3, VAR8, VAR12 );
buf VAR10 (VAR6 , VAR3 );
endmodule | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/verilog/ANN_dadd_64ns_64ns_64_5_full_dsp.v | 1,912 | module MODULE1
VAR6 = 6,
VAR9 = 5,
VAR25 = 64,
VAR22 = 64,
VAR3 = 64
)(
input wire clk,
input wire reset,
input wire VAR20,
input wire [VAR25-1:0] VAR2,
input wire [VAR22-1:0] VAR27,
output wire [VAR3-1:0] dout
);
wire VAR24;
wire VAR26;
wire VAR4;
wire [63:0] VAR21;
wire VAR15;
wire [63:0] VAR12;
wire VAR8;
wire [63:0... | gpl-3.0 |
petrmikheev/miksys | verilog/SHIFT_bb.v | 3,310 | module MODULE1 (
VAR2,
VAR1,
VAR4,
VAR3);
input [15:0] VAR2;
input VAR1;
input [3:0] VAR4;
output [15:0] VAR3;
endmodule | gpl-3.0 |
spesialstyrker/boula | gen/PCIe/example_design/xilinx_pcie_2_0_ep_v6.v | 17,939 | module MODULE1 # (
parameter VAR103 = "VAR21",
parameter VAR79 = 64, parameter VAR101 = VAR79 / 8 )
(
output [0:0] VAR76,
output [0:0] VAR89,
input [0:0] VAR128,
input [0:0] VAR94,
output VAR114,
output VAR66,
output VAR13,
input VAR24,
input VAR41,
input VAR109
);
wire VAR29;
wire VAR5;
wire VAR91;
wire [5:0] VAR97;
w... | gpl-2.0 |
lbl-cal/StanfordNoC | router/src/rtr_flit_buffer.v | 15,909 | module MODULE1
(clk, reset, VAR97, VAR100, VAR105, VAR37, VAR67,
VAR68, VAR2, VAR29, VAR30, VAR71, VAR64,
VAR23, VAR46, VAR49, VAR13, VAR10);
parameter VAR34 = 4;
parameter VAR74 = 32;
parameter VAR77 = 64;
parameter VAR25 = 8;
parameter VAR94 = VAR15;
parameter VAR12 = 1;
parameter VAR65 = 0;
parameter VAR16 = VAR43;
... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_psa_pp_pkg_sn/sky130_fd_sc_hs__udp_dlatch_psa_pp_pkg_sn.symbol.v | 1,590 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR6 ,
input VAR5 ,
input VAR9 ,
input VAR8 ,
input VAR4,
input VAR7 ,
input VAR3
);
endmodule | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/Bluetooth/UART_top.v | 2,299 | module MODULE1(clk,VAR8,VAR3,VAR18,VAR24,VAR23,VAR28,VAR2);
input clk,VAR8,VAR24;
input [7:0] VAR23;
input VAR3; output VAR18;
output VAR28;
output [7:0] VAR2;
wire VAR14,VAR11;
wire VAR16,VAR5;
wire VAR30,VAR26;
wire [7:0] VAR15;
VAR6 VAR13(
.VAR10(VAR26),
.VAR4(VAR30),
.VAR9(VAR8),
.VAR29(clk)
);
VAR21 VAR27( .clk(VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai.blackbox.v | 1,397 | module MODULE1 (
VAR2 ,
VAR1,
VAR4,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR1;
input VAR4;
input VAR6 ;
input VAR5 ;
supply1 VAR3;
supply0 VAR9;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
chebykinn/university | circuitry/lab4/src/hdl/ram_wb/ram_wb.v | 1,429 | module MODULE1 #(
parameter VAR9 = 32'h0000ffff,
parameter VAR16 = 32'h00001000) (
input [31:0] VAR14,
output [31:0] VAR6,
input [31:0] VAR4,
input VAR21,
input [3:0] VAR15,
input VAR1,
input VAR7,
output reg VAR2,
input [2:0] VAR5,
input VAR18,
input VAR8);
wire [31:0] VAR19;
assign VAR19[31:24] = VAR15[3] ? VAR14[31:... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_lvds_clk.v | 3,283 | module MODULE1 (
VAR9,
VAR12,
clk);
parameter VAR17 = 0;
localparam VAR2 = 0;
localparam VAR8 = 1;
input VAR9;
input VAR12;
output clk;
wire VAR3;
VAR10 VAR16 (
.VAR14 (VAR9),
.VAR11 (VAR12),
.VAR13 (VAR3));
generate
if (VAR17 == VAR8) begin
VAR15 #(.VAR19("VAR7")) VAR6 (
.VAR1 (1'b0),
.VAR4 (1'b1),
.VAR14 (VAR3),
.VAR... | gpl-3.0 |
kigawas/MipsCPU | CPU/led.v | 1,227 | module MODULE1 (
input [15:0] VAR8,
input clk,
input VAR2,
output reg [6:0] VAR4,
output reg [3:0] VAR9,
output wire VAR5
);
wire [1:0] VAR6;
reg [3:0] VAR3;
wire [3:0] VAR1;
reg [19:0] VAR7;
assign VAR5 = 1;
assign VAR6[0] = VAR7[18]; assign VAR6[1] = VAR7[17];
assign VAR1 = 4'b1111; always @ ( * ) begin
case (VAR6)
2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtn/sky130_fd_sc_hd__dfrtn.functional.pp.v | 2,024 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR6 ,
VAR5,
VAR14 ,
VAR13 ,
VAR7 ,
VAR17
);
output VAR8 ;
input VAR2 ;
input VAR6 ;
input VAR5;
input VAR14 ;
input VAR13 ;
input VAR7 ;
input VAR17 ;
wire VAR3 ;
wire VAR12 ;
wire VAR4;
not VAR16 (VAR12 , VAR5 );
not VAR15 (VAR4, VAR2 );
VAR11 VAR10 VAR1 (VAR3 , VAR6, VAR4, VAR12, , VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a_4.v | 2,322 | module MODULE2 (
VAR2 ,
VAR10 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR11,
VAR1,
VAR8 ,
VAR4
);
output VAR2 ;
input VAR10 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR11;
input VAR1;
input VAR8 ;
input VAR4 ;
VAR7 VAR9 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.... | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/uart/uart.v | 3,386 | module MODULE1 (
input wire clk,
input wire reset,
input wire VAR19,
input wire VAR20,
input wire VAR17,
input wire [VAR5] addr,
input wire [VAR14] VAR8,
output wire [VAR14] VAR22,
output wire VAR7,
output wire VAR1,
output wire VAR21,
input wire VAR6,
output wire VAR10
);
wire VAR13;
wire VAR23;
wire [VAR15] VAR16;
wi... | apache-2.0 |
qeedquan/fpga | de2-115/ledhex/ledhex.v | 1,989 | module MODULE1
(
input wire [3:0] VAR12,
input wire clk,
output reg [VAR2-1:0] VAR11,
output reg [VAR8*7-1:0] VAR18
);
task VAR9();
integer VAR14;
for (VAR14 = 0; VAR14 < VAR8*7; VAR14 = VAR14 + 1) begin
VAR18[VAR14] = 1;
end
endtask
task VAR16(input integer VAR3, input integer VAR15);
reg [7:0] VAR6;
integer VAR14;
be... | mit |
dtysky/FPGA-Imaging-Library | LocalFilter/ErosionDilationBin/HDL/ErosionDilationBin.srcs/sources_1/new/ErosionDilationBin.v | 4,530 | module MODULE1(
clk,
VAR12,
VAR4,
VAR18,
VAR7,
VAR16,
VAR2,
VAR3);
parameter[0 : 0] VAR1 = 0;
parameter[3 : 0] VAR6 = 3;
parameter VAR17 = 3;
input clk;
input VAR12;
input VAR4;
input[VAR6 * VAR6 - 1 : 0] VAR18;
input VAR7;
input [VAR6 * VAR6 - 1 : 0] VAR16;
output VAR2;
output VAR3;
reg[VAR19 - 1 : 0] VAR5;
reg[3 : 0]... | lgpl-2.1 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_jid_to_yid.v | 5,224 | module MODULE1 (
VAR25, VAR5, VAR24, VAR1, VAR9, VAR34,
VAR20, VAR32, VAR10, VAR14, VAR7, VAR28, VAR6, VAR35,
clk, VAR13
);
input [3:0] VAR20;
output [9:0] VAR25;
output VAR5;
input [3:0] VAR32;
output [9:0] VAR24;
output VAR1;
output VAR9;
input VAR10;
input [9:0] VAR14;
output [3:0] VAR34;
input VAR7;
input [3:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211o/sky130_fd_sc_hs__a211o.pp.blackbox.v | 1,336 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR2 ,
VAR1,
VAR3
);
output VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR1;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbp/sky130_fd_sc_hd__dlxbp.pp.symbol.v | 1,358 | module MODULE1 (
input VAR3 ,
output VAR4 ,
output VAR7 ,
input VAR5,
input VAR6 ,
input VAR2,
input VAR8,
input VAR1
);
endmodule | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | crc_16/peripheral_crc_16.v | 1,974 | module MODULE1 (clk , rst , din , VAR2 , addr , rd , wr, dout );
input clk;
input rst;
input [15:0]din;
input VAR2;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
reg [4:0] VAR6;
reg [31:0] VAR1=0;
reg VAR8=0;
wire [15:0] VAR5;
wire VAR4;
always @(*) begin case (addr)
4'h0:begin VAR6 = (VAR2 && wr) ? 5'b00... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1.symbol.v | 1,357 | module MODULE1 (
input VAR2,
output VAR6
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_vector_to_stream_converter_single.v | 7,342 | module MODULE1(
VAR11, VAR4, VAR3, VAR13,
VAR9, VAR5, VAR18,
VAR19, VAR7, VAR14, VAR10);
parameter VAR20 = 32;
input VAR11, VAR4, VAR3, VAR19, VAR14, VAR13;
input [VAR20-1:0] VAR9;
input [VAR20-1:0] VAR5;
output [VAR20-1:0] VAR18;
output VAR7;
output VAR10;
reg [VAR20-1:0] VAR16 ;
reg [VAR20-1:0] VAR1 ;
reg VAR6 ;
wire... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2b/sky130_fd_sc_ms__and2b.pp.blackbox.v | 1,287 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR5 ,
VAR1,
VAR7,
VAR2 ,
VAR4
);
output VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
ptracton/Picoblaze | Picoblaze/UART_and_PicoTerm/ML605_design/uart6_ml605.v | 12,479 | module MODULE1 ( input VAR67,
input VAR12,
input VAR39,
output VAR46 );
wire VAR9;
wire clk;
wire [11:0] address;
wire [17:0] VAR36;
wire VAR28;
reg [7:0] VAR56;
wire [7:0] VAR63;
wire [7:0] VAR49;
wire VAR25;
wire VAR57;
wire VAR50;
wire interrupt;
wire VAR18;
wire VAR29;
wire VAR15;
wire VAR8;
wire [7:0] VAR68;
wire ... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_full.v | 4,537 | module MODULE1
,parameter VAR29(VAR8)
,parameter VAR21 = 0
,parameter VAR2 = 0
)
(input VAR10
,input VAR13
,input VAR14
,output logic VAR12
,input [VAR18-1:0] VAR24
,output logic [VAR8-1:0][VAR18-1:0] VAR31
,output logic VAR17
,input VAR20
);
localparam VAR35 = VAR1(VAR8);
logic [VAR8-1:0][VAR18-1:0] VAR9;
if (VAR21 ==... | bsd-3-clause |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_altpll_1.v | 11,301 | module MODULE1
(
VAR7,
VAR9,
VAR5,
VAR8) ;
input VAR7;
input VAR9;
input [0:0] VAR5;
output [0:0] VAR8;
tri0 VAR7;
tri1 VAR9;
reg [0:0] VAR3;
reg [0:0] VAR6;
reg [0:0] VAR2;
wire VAR1;
wire VAR10;
wire VAR4; | gpl-2.0 |
Feuerwerk/fpgaNES | audio_pll/audio_pll_0002.v | 2,162 | module MODULE1(
input wire VAR52,
input wire rst,
output wire VAR16,
output wire VAR18
);
VAR55 #(
.VAR3("false"),
.VAR39("50.0 VAR50"),
.VAR20("VAR61"),
.VAR45(1),
.VAR12("11.288888 VAR50"),
.VAR17("0 VAR32"),
.VAR57(50),
.VAR59("0 VAR50"),
.VAR9("0 VAR32"),
.VAR2(50),
.VAR68("0 VAR50"),
.VAR48("0 VAR32"),
.VAR4(50),
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtn/sky130_fd_sc_hd__dlxtn_1.v | 2,204 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR2,
VAR4 ,
VAR7 ,
VAR3 ,
VAR8
);
output VAR9 ;
input VAR5 ;
input VAR2;
input VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR8 ;
VAR6 VAR1 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR9 ,
VAR5 ,
VAR2
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4/sky130_fd_sc_hdll__nand4_2.v | 2,269 | module MODULE2 (
VAR8 ,
VAR10 ,
VAR11 ,
VAR9 ,
VAR2 ,
VAR7,
VAR3,
VAR6 ,
VAR1
);
output VAR8 ;
input VAR10 ;
input VAR11 ;
input VAR9 ;
input VAR2 ;
input VAR7;
input VAR3;
input VAR6 ;
input VAR1 ;
VAR5 VAR4 (
.VAR8(VAR8),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.... | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ddr3_source/clocking/mig_7series_v1_9_iodelay_ctrl.v | 10,172 | module MODULE1 #
(
parameter VAR30 = 100,
parameter VAR45 = "VAR27",
parameter VAR46 = "VAR16",
parameter VAR2 = "VAR16",
parameter VAR48 = "VAR44",
parameter VAR23 = 1,
parameter VAR34 = "VAR33"
)
(
input VAR8,
input VAR41,
input VAR11,
input VAR4,
output VAR37,
output VAR10,
output VAR19,
output VAR12,
output VAR43,
... | gpl-2.0 |
kielfriedt/ece472 | lab4/mux2.v | 1,046 | module MODULE1( sel, VAR2, VAR1, VAR3 );
parameter VAR4=32;
input sel;
input [VAR4-1:0] VAR2, VAR1;
output [VAR4-1:0] VAR3;
assign VAR3 = sel ? VAR1 : VAR2;
endmodule | gpl-3.0 |
colinww/spi-core-generator | templates/spi_top_template.v | 3,280 | module MODULE1(
VAR15, VAR18, VAR29,
VAR19, VAR24,
VAR16, VAR33, VAR34, VAR20, VAR26);
input VAR16;
input VAR33;
output VAR15;
output VAR18;
output VAR29;
input VAR34;
input VAR20;
input VAR26;
inout VAR19;
inout [36:0] VAR24;
wire VAR11;
wire VAR22;
wire [2:0] VAR25;
wire [7:0] VAR31;
wire [7:0] VAR5;
assign VAR15 = V... | gpl-3.0 |
liqimai/ZPC | PersonalComputer/MainBoard.v | 5,537 | module MODULE1(
input clk,
input VAR5,
input[4:0] VAR8,
output[31:0] VAR2,
output[31:0] VAR12,
output[31:0] VAR3,
output[31:0] VAR15,
output VAR6, output VAR10, output VAR13,
output VAR14,
output VAR4,
input VAR7,
input VAR1,
input VAR9,
output VAR11
);
reg clk;
reg VAR5;
reg[4:0] VAR8;
reg VAR7;
reg VAR1; | gpl-2.0 |
rfotino/consolite-hardware | src/input_handler.v | 1,199 | module MODULE1
(
input clk,
input [5:0] VAR8,
input [7:0] VAR5,
input [7:0] VAR9,
input [7:0] VAR11,
input [7:0] VAR7,
input [7:0] VAR10,
input [11:0] VAR6,
input [11:0] VAR1,
input [11:0] VAR14,
input [11:0] VAR12,
input [11:0] VAR16,
input [11:0] VAR15,
input [11:0] VAR4,
input [11:0] VAR13,
output reg [VAR3-1:0] VAR... | mit |
trivoldus28/pulsarch-verilog | verif/env/cmp/sparc_pipe_flow.v | 34,501 | module MODULE1 (clk);
input clk;
integer VAR10;
reg [31:0] VAR20;
reg [31:0] VAR21;
reg [8*6:0] VAR17;
reg [8*6:0] VAR12;
reg [8*6:0] VAR14;
reg [8*6:0] VAR2;
reg [8*6:0] VAR15;
reg [8*6:0] VAR19;
reg [8*80:0] VAR16;
reg [47:0] VAR9 [63:0];
reg [31:0] VAR3 [63:0];
reg [63:0] VAR13;
reg [5:0] VAR11;
reg [5:0] VAR18;
reg... | gpl-2.0 |
elegabriel/myzju | junior1/CA/LAB/lab6/lab6_gxl_3120102146/code/StallControlLogic.v | 2,819 | module MODULE1(
VAR11,VAR9,VAR16,VAR29,
VAR6, VAR5,
VAR22
);
input wire [4:0] VAR11, VAR9;
input wire [5:0] VAR16, VAR29;
input wire [4:0] VAR6;
input wire VAR5;
output wire VAR22;
wire VAR13, VAR12;
wire VAR27, VAR26, VAR14, VAR4, VAR30; wire VAR3,VAR17,VAR28,VAR18,VAR1,VAR24,VAR7,VAR21; wire VAR20,VAR8,VAR19,VAR25,VA... | gpl-2.0 |
orbancedric/DeepGate | other/Mojo Projects/Mojo-SDRAM/src/spi_slave.v | 1,344 | module MODULE1(
input clk,
input rst,
input VAR14,
input VAR12,
output VAR10,
input VAR5,
output VAR20,
input [7:0] din,
output [7:0] dout
);
reg VAR4, VAR6;
reg VAR15, VAR2;
reg VAR18, VAR23;
reg VAR11, VAR22;
reg [7:0] VAR7, VAR21;
reg VAR1, VAR9;
reg [2:0] VAR13, VAR3;
reg [7:0] VAR16, VAR17;
reg VAR19, VAR8;
assign... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2_16.v | 2,119 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR1 ,
VAR3,
VAR4,
VAR2 ,
VAR9
);
output VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR3;
input VAR4;
input VAR2 ;
input VAR9 ;
VAR5 VAR6 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR8,
VAR7,
VAR1
);
output VAR8;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtn/sky130_fd_sc_ms__dlrtn.behavioral.v | 2,404 | module MODULE1 (
VAR22 ,
VAR23,
VAR1 ,
VAR7
);
output VAR22 ;
input VAR23;
input VAR1 ;
input VAR7 ;
supply1 VAR11;
supply0 VAR3;
supply1 VAR18 ;
supply0 VAR8 ;
wire VAR10 ;
wire VAR19 ;
reg VAR16 ;
wire VAR2 ;
wire VAR21 ;
wire VAR20 ;
wire VAR12;
wire VAR9 ;
wire VAR17 ;
wire VAR14 ;
wire VAR24 ;
not VAR4 (VAR10 , VA... | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/prior_enc.v | 4,515 | module MODULE1 (
VAR4,
VAR9,
VAR8
);
parameter VAR3 = 64;
parameter VAR1 = VAR11(VAR3);
input [VAR3-1:0] VAR4;
output [VAR1-1:0] VAR9;
output VAR8;
reg [VAR1-1:0] VAR9;
reg VAR8;
reg [VAR1-1:0] VAR6;
integer VAR7, VAR2;
always @(*)
begin
VAR2 = 0;
for (VAR7=0; VAR7 < VAR3; VAR7=VAR7+1)
if (VAR4[VAR7] == 1'b1)
VAR2 = VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.v | 2,461 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR5 ,
VAR2 ,
VAR11 ,
VAR6 ,
VAR10,
VAR12,
VAR7 ,
VAR8
);
output VAR1 ;
input VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR11 ;
input VAR6 ;
input VAR10;
input VAR12;
input VAR7 ;
input VAR8 ;
VAR9 VAR3 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR10(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo_4.v | 2,334 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR6 ,
VAR4,
VAR1,
VAR10,
VAR7 ,
VAR2
);
output VAR8 ;
input VAR9 ;
input VAR6 ;
input VAR4;
input VAR1;
input VAR10;
input VAR7 ;
input VAR2 ;
VAR5 VAR3 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE2 ... | apache-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/bidir_reg.v | 1,121 | module MODULE1
( inout wire [15:0] VAR4,
input wire [15:0] VAR3,
input wire [15:0] VAR1 );
assign VAR4[0] = VAR3[0] ? VAR1[0] : 1'VAR2;
assign VAR4[1] = VAR3[1] ? VAR1[1] : 1'VAR2;
assign VAR4[2] = VAR3[2] ? VAR1[2] : 1'VAR2;
assign VAR4[3] = VAR3[3] ? VAR1[3] : 1'VAR2;
assign VAR4[4] = VAR3[4] ? VAR1[4] : 1'VAR2;
assi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22oi/sky130_fd_sc_hdll__a22oi.pp.symbol.v | 1,384 | module MODULE1 (
input VAR7 ,
input VAR5 ,
input VAR6 ,
input VAR4 ,
output VAR9 ,
input VAR8 ,
input VAR2,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf.functional.pp.v | 1,746 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR5,
VAR8,
VAR10 ,
VAR4
);
output VAR11 ;
input VAR7 ;
input VAR5;
input VAR8;
input VAR10 ;
input VAR4 ;
wire VAR9 ;
wire VAR12;
buf VAR6 (VAR9 , VAR7 );
VAR1 VAR2 (VAR12, VAR9, VAR5, VAR8);
buf VAR3 (VAR11 , VAR12 );
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/generic/template.v | 1,562 | module MODULE1 (
input clk,
input rst
);
localparam VAR1 = 32'h00000000;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3b/sky130_fd_sc_hd__nand3b.behavioral.pp.v | 1,971 | module MODULE1 (
VAR16 ,
VAR15 ,
VAR7 ,
VAR8 ,
VAR13,
VAR6,
VAR3 ,
VAR9
);
output VAR16 ;
input VAR15 ;
input VAR7 ;
input VAR8 ;
input VAR13;
input VAR6;
input VAR3 ;
input VAR9 ;
wire VAR2 ;
wire VAR5 ;
wire VAR1;
not VAR14 (VAR2 , VAR15 );
nand VAR12 (VAR5 , VAR7, VAR2, VAR8 );
VAR10 VAR11 (VAR1, VAR5, VAR13, VAR6);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi.pp.blackbox.v | 1,474 | module MODULE1 (
VAR5 ,
VAR1,
VAR2,
VAR3 ,
VAR6 ,
VAR7,
VAR9,
VAR8 ,
VAR4
);
output VAR5 ;
input VAR1;
input VAR2;
input VAR3 ;
input VAR6 ;
input VAR7;
input VAR9;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_dp_macc_l.v | 4,810 | module MODULE1(
VAR8, VAR24, VAR36,
VAR16, VAR33, VAR27,
VAR14, VAR10, VAR31,
VAR21, VAR19, VAR5, VAR28, VAR7
);
output [149:0] VAR8; output VAR24;
output VAR36;
input VAR16; input VAR33; input VAR27; input VAR14; input VAR10; input [149:0] VAR31; input [149:0] VAR21;
input [149:0] VAR19;
input VAR5;
input VAR28;
input... | gpl-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/ip/Binary_VGA_Controller/hdl/Img_RAM.v | 9,298 | module MODULE1 (
VAR45,
VAR31,
VAR61,
VAR6,
VAR26,
VAR3,
VAR59);
input [0:0] VAR45;
input VAR31;
input [18:0] VAR61;
input [15:0] VAR6;
input VAR26;
input VAR3;
output [7:0] VAR59;
wire [7:0] VAR41;
wire [7:0] VAR59 = VAR41[7:0];
VAR35 VAR39 (
.VAR52 (VAR31),
.VAR19 (VAR26),
.VAR43 (VAR3),
.VAR54 (VAR61),
.VAR58 (VAR6)... | gpl-3.0 |
AmeerAbdelhadi/Binary-to-BCD-Converter | bin2bcd.v | 10,122 | module MODULE1
integer VAR4,VAR3;
always @(VAR5) begin
for(VAR4 = 0; VAR4 <= VAR2+(VAR2-4)/3; VAR4 = VAR4+1) VAR1[VAR4] = 0; VAR1[VAR2-1:0] = VAR5; for(VAR4 = 0; VAR4 <= VAR2-4; VAR4 = VAR4+1) for(VAR3 = 0; VAR3 <= VAR4/3; VAR3 = VAR3+1) if (VAR1[VAR2-VAR4+4*VAR3 -: 4] > 4) VAR1[VAR2-VAR4+4*VAR3 -: 4] = VAR1[VAR2-VAR4+... | bsd-3-clause |
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