repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2.functional.pp.v | 1,690 | module MODULE1 (
VAR7,
VAR1,
VAR10 ,
VAR4 ,
VAR9
);
input VAR7;
input VAR1;
output VAR10 ;
input VAR4 ;
input VAR9 ;
wire VAR11 ;
wire VAR6;
nand VAR5 (VAR11 , VAR9, VAR4 );
VAR8 VAR2 (VAR6, VAR11, VAR7, VAR1);
buf VAR3 (VAR10 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai_4.v | 2,361 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR11 ,
VAR2 ,
VAR6 ,
VAR5,
VAR4,
VAR8 ,
VAR1
);
output VAR7 ;
input VAR10 ;
input VAR11 ;
input VAR2 ;
input VAR6 ;
input VAR5;
input VAR4;
input VAR8 ;
input VAR1 ;
VAR3 VAR9 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/cpu.v | 85,541 | module MODULE1 (
input wire VAR15, input wire VAR317, input wire VAR275,
input wire VAR138, input wire VAR110, input wire VAR13,
input wire [ 7:0] din, output wire [ 7:0] dout, output wire [15:0] VAR319, output reg VAR209,
input wire [ 3:0] VAR303, input wire [ 7:0] VAR335, input wire VAR234, output reg [ 7:0] VAR231, ... | mit |
bluespec/Flute | builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkNear_Mem_IO.v | 48,083 | module MODULE1(VAR202,
VAR139,
VAR194,
VAR174,
VAR142,
VAR209,
VAR204,
VAR169,
VAR234,
VAR141,
VAR183,
VAR10,
VAR226,
VAR216,
VAR56,
VAR147,
VAR21,
VAR189,
VAR51,
VAR231,
VAR87,
VAR74);
input VAR202;
input VAR139;
input VAR194;
output VAR174;
input VAR142;
output VAR209;
input [63 : 0] VAR204;
input [63 : 0] VAR169;
in... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_LVT_SS_210930.v | 73,172 | module MODULE1 (VAR13, VAR14, VAR6, VAR3);
output VAR13;
input VAR14, VAR6, VAR3;
reg VAR8;
wire VAR1, VAR4;
wire VAR16, VAR10, VAR15;
wire VAR11;
not (VAR16, VAR1);
not (VAR15, VAR6);
VAR5 (VAR11, VAR4, VAR16, VAR15);
VAR9 (VAR10, VAR8, VAR4, VAR16, VAR15, VAR11);
buf (VAR13, VAR10);
wire VAR7, VAR2, VAR12;
and (VAR7,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2.blackbox.v | 1,239 | module MODULE1 (
VAR4,
VAR2,
VAR1
);
output VAR4;
input VAR2;
input VAR1;
supply1 VAR6;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
CospanDesign/nysa-sata | rtl/phy/oob_controller.v | 10,794 | module MODULE1 (
input rst, input clk,
input VAR21, output reg VAR31, output reg VAR4,
output reg VAR25, output reg VAR9, input VAR8,
input VAR6, input VAR37,
input [31:0] VAR27,
input [3:0] VAR30,
input VAR33,
input VAR20,
input VAR2,
output reg [31:0] VAR11,
output reg VAR34,
output reg VAR5,
output [3:0] VAR13
);
pa... | mit |
tmatsuya/milkymist-ml401 | cores/minimac/rtl/minimac_tx.v | 3,604 | module MODULE1(
input VAR28,
input VAR6,
input VAR30,
input VAR35,
input [29:0] VAR36,
input [1:0] VAR21,
output reg VAR20,
output [31:0] VAR15,
output VAR33,
output VAR12,
input VAR16,
input [31:0] VAR17,
input VAR9,
output VAR26,
output [3:0] VAR3
);
reg VAR24;
assign VAR33 = VAR24;
assign VAR12 = VAR24;
assign VAR15... | lgpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_nco_0_0/ip_design_nco_0_0_stub.v | 2,663 | module MODULE1(VAR16,
VAR9, VAR17, VAR4,
VAR3, VAR1, VAR11,
VAR2, VAR15, VAR8,
VAR5, VAR19, VAR6,
VAR10, VAR13, VAR18,
VAR12, VAR14, VAR7)
;
input [5:0]VAR16;
input VAR9;
output VAR17;
input [31:0]VAR4;
input [3:0]VAR3;
input VAR1;
output VAR11;
output [1:0]VAR2;
output VAR15;
input VAR8;
input [5:0]VAR5;
input VAR19;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2.behavioral.v | 1,358 | module MODULE1 (
VAR10,
VAR9,
VAR8
);
output VAR10;
input VAR9;
input VAR8;
supply1 VAR1;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR6 ;
wire VAR2;
nor VAR3 (VAR2, VAR9, VAR8 );
buf VAR5 (VAR10 , VAR2 );
endmodule | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/ictlb.v | 3,639 | module MODULE1(
input clk
,input reset
,input VAR43
,output VAR28
,input VAR34 VAR41
,input VAR15
,output VAR33
,input VAR36 VAR32
,output VAR8
,input VAR4
,output VAR23 VAR50
,output VAR25
,input VAR48
,output VAR42 VAR18
,input VAR51
,output VAR14
,input VAR31 VAR10
,input VAR39
,output VAR26
,input VAR30 VAR52
,outp... | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/vfabric_sincos.v | 2,591 | module MODULE1(VAR14, VAR11,
VAR7, VAR6, VAR25,
VAR18, VAR13, VAR2,
VAR3, VAR20, VAR5);
parameter VAR15 = 32;
parameter VAR21 = 37;
parameter VAR1 = 64;
input VAR14, VAR11;
input [VAR15-1:0] VAR7;
input VAR6;
output VAR25;
output [VAR15-1:0] VAR18, VAR3;
output VAR13, VAR20;
input VAR2, VAR5;
reg [VAR21-1:0] VAR31;
wir... | mit |
makestuff/comm-fpga | fx2/verilog/comm_fpga_fx2.v | 9,142 | module
MODULE1(
input wire VAR10, input wire VAR35, output reg VAR5,
output reg VAR32, inout wire[7:0] VAR9,
output wire VAR13, input wire VAR4,
output wire VAR17, input wire VAR18, output reg VAR38,
output wire[6:0] VAR7,
output wire[7:0] VAR24, output reg VAR39, input wire VAR22,
input wire[7:0] VAR12, input wire VAR... | gpl-3.0 |
ncos/Xilinx-Verilog | INTERFACES/src/CAN/can_qsampler.v | 2,648 | module MODULE1
(
input wire VAR7, input wire VAR1, inout wire VAR6, input wire din, output reg dout, output reg VAR5, output reg VAR9, output reg sync );
parameter VAR4 = 20; parameter VAR10 = 15;
reg VAR3 = 1'b0; reg [63:0] VAR8 = 64'd0;
reg VAR2;
always @(posedge VAR7) begin
VAR2 <= VAR6;
if (VAR8 == VAR10) begin
dou... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/controller/bank_common.v | 17,771 | module MODULE1 #
(
parameter VAR17 = 100,
parameter VAR78 = 2,
parameter VAR2 = 1,
parameter VAR77 = 4,
parameter VAR33 = 2,
parameter VAR5 = 0,
parameter VAR62 = 44,
parameter VAR107 = 2,
parameter VAR89 = 4,
parameter VAR3 = 5,
parameter VAR113 = 64
)
(
VAR66, VAR108, VAR44, VAR58,
VAR46, VAR57, VAR28, VAR71, VAR26,
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbn/sky130_fd_sc_lp__dlrbn.blackbox.v | 1,405 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR1,
VAR7 ,
VAR4
);
output VAR9 ;
output VAR8 ;
input VAR1;
input VAR7 ;
input VAR4 ;
supply1 VAR2;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o.pp.symbol.v | 1,431 | module MODULE1 (
input VAR4 ,
input VAR9 ,
input VAR6 ,
input VAR2 ,
input VAR7 ,
output VAR5 ,
input VAR10 ,
input VAR8,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/normMult.v | 4,956 | module MODULE1(
input clk,
input VAR17,
input [1:0] VAR8,
input signed [17:0] VAR21,
input signed [15:0] VAR6,
input signed [13:0] VAR13,
output reg signed [15:0] dout = 16'VAR22,
output reg VAR11 = 1'b0
);
parameter VAR23 = 1; parameter VAR20 = 5; parameter VAR19 = 23;
parameter VAR2 = 4;
reg signed [15:0] VAR10 = 16'... | gpl-3.0 |
Giako68/SD_RAM_VIDEO | SDRAM.v | 9,001 | module MODULE1
( input VAR22,
output VAR61,
output reg [4:0] VAR5,
output reg [1:0] VAR43,
output reg [1:0] VAR64,
output reg [12:0] VAR51,
inout [15:0] VAR37,
input [23:0] VAR52,
input [15:0] VAR16,
input [1:0] VAR4,
output reg [15:0] VAR57,
input VAR46,
input VAR31,
output reg VAR58,
input [10:0] VAR55,
input VAR45,
... | gpl-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_iwb_biu.v | 15,381 | module MODULE1(
clk, rst, VAR45,
VAR37, VAR5, VAR40, VAR30, VAR43, VAR4,
VAR48, VAR12, VAR19, VAR22, VAR8, VAR32,
VAR46,
VAR26, VAR35,
VAR25, VAR20, VAR9, VAR44, VAR7, VAR2, VAR11,
VAR14, VAR23, VAR17
);
parameter VAR42 = VAR41;
parameter VAR21 = VAR41;
input clk; input rst; input [1:0] VAR45;
input VAR37; input VAR5; ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand3/sky130_fd_sc_hvl__nand3.pp.symbol.v | 1,290 | module MODULE1 (
input VAR2 ,
input VAR3 ,
input VAR5 ,
output VAR4 ,
input VAR7 ,
input VAR6,
input VAR8,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311ai/sky130_fd_sc_ls__o311ai.symbol.v | 1,380 | module MODULE1 (
input VAR4,
input VAR9,
input VAR8,
input VAR6,
input VAR5,
output VAR7
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.v | 2,119 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR1,
VAR6,
VAR5 ,
VAR4
);
output VAR8 ;
input VAR7 ;
input VAR1;
input VAR6;
input VAR5 ;
input VAR4 ;
VAR3 VAR2 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR8,
VAR7
);
output VAR8;
input VAR7;
supply1 VAR1;
supply0 VAR6;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4_6.v | 2,291 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR8 ,
VAR10 ,
VAR5 ,
VAR11,
VAR2,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR10 ;
input VAR5 ;
input VAR11;
input VAR2;
input VAR4 ;
input VAR1 ;
VAR9 VAR6 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR4(VAR4),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtp/sky130_fd_sc_ms__dlxtp.pp.blackbox.v | 1,301 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR7,
VAR2,
VAR5,
VAR6 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR7;
input VAR2;
input VAR5;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/buffers/TxFifoBI.v | 5,449 | module MODULE1 (
address, VAR3, VAR15,
VAR10,
VAR18,
VAR16,
VAR2,
VAR12,
VAR4,
VAR6,
VAR11,
VAR13,
VAR1
);
input [2:0] address;
input VAR3;
input VAR15;
input VAR10;
input VAR18;
input VAR16;
input [7:0] VAR12;
output [7:0] VAR4;
output VAR6;
output VAR11;
output VAR13;
input [15:0] VAR1;
input VAR2;
wire [2:0] address... | gpl-3.0 |
parallella/oh | xilibs/dv/PLLE2_BASE.v | 3,606 | module MODULE1 (
VAR15, VAR25, VAR16, VAR26, VAR10, VAR28, VAR8,
VAR45,
VAR4, VAR14, VAR21, VAR12
);
parameter VAR32 = 0;
parameter VAR43 = 1;
parameter VAR23 = 0;
parameter VAR6 = 10;
parameter VAR34 = 1;
parameter VAR27 = 0;
parameter VAR18 = 0;
parameter VAR40 = 1;
parameter VAR29 = 0.5;
parameter VAR3 = 0;
paramete... | mit |
sh-chris110/chris | FPGA/chris.convolution.ok/db/ip/soc_design/submodules/soc_design_Sys_Timer.v | 5,000 | module MODULE1 (
address,
VAR15,
clk,
VAR13,
VAR7,
VAR23,
irq,
VAR19
)
;
output irq;
output [ 15: 0] VAR19;
input [ 2: 0] address;
input VAR15;
input clk;
input VAR13;
input VAR7;
input [ 15: 0] VAR23;
wire VAR10;
wire VAR1;
reg VAR3;
wire VAR18;
reg VAR11;
wire VAR17;
wire [ 16: 0] VAR20;
reg VAR2;
wire VAR4;
wire VAR... | gpl-2.0 |
jkanasu/utl | lab14eve16/asic/j01b_carryLookAheadAdder.v | 3,027 | module MODULE1(VAR5,VAR3,VAR6,VAR1,VAR7);
output [3:0]VAR5;
output VAR3;
input [3:0]VAR6,VAR1;
input VAR7;
wire [3:0]VAR8,VAR4; wire [4:0]VAR2;
assign VAR2[0] = VAR7;
assign VAR5[0] = VAR6[0] ^ VAR1[0] ^ VAR2[0];
assign VAR2[1] = ( ( VAR6[0] & VAR1[0] ) | ( ( VAR6[0] ^ VAR1[0] ) & VAR2[0] ) );
assign VAR5[1] = VAR6[1] ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2a/sky130_fd_sc_ls__o2bb2a_2.v | 2,398 | module MODULE1 (
VAR6 ,
VAR8,
VAR1,
VAR9 ,
VAR4 ,
VAR5,
VAR7,
VAR11 ,
VAR10
);
output VAR6 ;
input VAR8;
input VAR1;
input VAR9 ;
input VAR4 ;
input VAR5;
input VAR7;
input VAR11 ;
input VAR10 ;
VAR2 VAR3 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR10(... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_axi_basic_tx.v | 9,979 | module MODULE1 #(
parameter VAR15 = 128, parameter VAR13 = "VAR27", parameter VAR42 = "VAR24", parameter VAR25 = "VAR24", parameter VAR19 = 1,
parameter VAR35 = (VAR15 == 128) ? 2 : 1, parameter VAR26 = VAR15 / 8 ) (
input [VAR15-1:0] VAR12, input VAR40, output VAR30, input [VAR26-1:0] VAR43, input VAR1, input [3:0] VA... | mit |
trander1/Queues-and-Adders | Verilog Files/synthesis_lifo_top.v | 4,887 | (VAR18<=4)?2:\
(VAR18<=8)?3:\
(VAR18<=16)?4:\
(VAR18<=32)?5:\
(VAR18<=64)?6:\
(VAR18<=128)?7:\
(VAR18<=256)?8:\
-1
module MODULE1(
VAR22, VAR14, VAR10,
VAR24, reset,
clk
);
parameter VAR23 = 4;
parameter VAR7 = 4;
parameter VAR26 = 2;
parameter VAR17 = VAR23+VAR26; parameter VAR12 = 'b0;
parameter VAR25 = VAR15(VAR7);
... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/vfabric_fcmp.v | 4,758 | module MODULE1(VAR33, VAR1,
VAR31, VAR10, VAR26,
VAR39, VAR41, VAR24,
VAR13, VAR22, VAR42,
VAR37);
parameter VAR36 = 32;
parameter VAR40 = 3;
parameter VAR17 = 4;
parameter VAR4 = 64;
input VAR33, VAR1;
input [VAR36-1:0] VAR31;
input [VAR36-1:0] VAR39;
input VAR10, VAR41;
output VAR26, VAR24;
output VAR13;
output VAR22... | mit |
ncos/Xilinx-Verilog | SINGEN/src/SPI/spi_slave.v | 1,398 | module MODULE1#
(
parameter integer VAR7 = 15 )
(
input wire VAR4,
input wire VAR8,
input wire VAR1,
output wire VAR2,
input wire VAR10,
input wire VAR12,
input wire [VAR7-1:0] VAR13,
output reg [VAR7-1:0] VAR5
);
reg [VAR7-1:0] VAR6 = 0;
reg [VAR7-1:0] VAR3 = 0;
reg VAR9 = 1'b0;
assign VAR2 = VAR3[VAR7-1];
wire VAR11;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s_1.v | 2,033 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR3,
VAR2
);
output VAR4 ;
input VAR6 ;
input VAR3;
input VAR2;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR3;
supply0 VAR2;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fah/sky130_fd_sc_hd__fah.behavioral.pp.v | 2,616 | module MODULE1 (
VAR12,
VAR19 ,
VAR24 ,
VAR11 ,
VAR4 ,
VAR10,
VAR5,
VAR8 ,
VAR23
);
output VAR12;
output VAR19 ;
input VAR24 ;
input VAR11 ;
input VAR4 ;
input VAR10;
input VAR5;
input VAR8 ;
input VAR23 ;
wire VAR3 ;
wire VAR26 ;
wire VAR1 ;
wire VAR14 ;
wire VAR2 ;
wire VAR16 ;
wire VAR13;
xor VAR21 (VAR3 , VAR24, VA... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/bch_shared_kes-1.0.1/d_KES_top.v | 38,577 | module MODULE1
(
input wire VAR32,
input wire VAR174,
input wire VAR64,
input wire [3:0] VAR44,
input wire VAR35,
input wire VAR69,
input wire VAR168,
input wire VAR124,
input wire VAR79,
output reg VAR7,
output wire VAR143,
output wire VAR71,
output reg [3:0] VAR156,
output reg VAR147,
output reg VAR22,
output reg [VA... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_30.v | 22,258 | module MODULE5 (
clk,
reset,
VAR33,
VAR38,
VAR10,
VAR57,
VAR42
);
parameter VAR3 = 18;
parameter VAR102 = 30;
parameter VAR125 = 15;
localparam VAR49 = 36;
input clk;
input reset;
input VAR33;
input VAR38;
input [VAR3-1:0] VAR10; output VAR57;
output [VAR3-1:0] VAR42;
localparam VAR54 = 18; localparam VAR181 = 36; loca... | mit |
pwwu/FPGA | VGAbased/vga_sync.v | 4,129 | module MODULE1
(
input wire clk, reset,
output wire VAR2, VAR23, VAR15, VAR27,
output wire [9:0] VAR14, VAR18
);
localparam VAR8 = 640; localparam VAR20 = 48 ; localparam VAR19 = 16 ; localparam VAR6 = 96 ; localparam VAR22 = 480; localparam VAR25 = 10; localparam VAR26 = 33; localparam VAR5 = 2;
reg VAR24;
wire VAR4;
... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9361/axi_ad9361_rx_pnmon.v | 12,295 | module MODULE1 (
VAR4,
VAR11,
VAR19,
VAR18,
VAR41,
VAR28,
VAR26);
parameter VAR32 = 0;
parameter VAR21 = 0;
localparam VAR29 = 0;
localparam VAR33 = 1;
localparam VAR15 = 2;
localparam VAR20 = 3;
input VAR4;
input VAR11;
input [11:0] VAR19;
input [11:0] VAR18;
input [ 3:0] VAR41;
output VAR28;
output VAR26;
reg VAR12 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3/sky130_fd_sc_ls__nor3.blackbox.v | 1,288 | module MODULE1 (
VAR4,
VAR1,
VAR5,
VAR3
);
output VAR4;
input VAR1;
input VAR5;
input VAR3;
supply1 VAR7;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211o/sky130_fd_sc_hs__a211o.symbol.v | 1,331 | module MODULE1 (
input VAR2,
input VAR1,
input VAR5,
input VAR6,
output VAR4
);
supply1 VAR3;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tap/sky130_fd_sc_lp__tap.functional.pp.v | 1,189 | module MODULE1 (
VAR3,
VAR2,
VAR4 ,
VAR1
);
input VAR3;
input VAR2;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1.functional.pp.v | 3,155 | module MODULE1 (
VAR16 ,
VAR8 ,
VAR17 ,
VAR12,
VAR9,
VAR22 ,
VAR21
);
output VAR16 ;
input [3:0] VAR8 ;
input [3:0] VAR17 ;
input VAR12;
input VAR9;
input VAR22 ;
input VAR21 ;
wire VAR1;
wire VAR4;
wire VAR6;
wire VAR23;
wire VAR7;
wire VAR19;
wire VAR18;
wire VAR26;
VAR27 VAR28 (VAR1, VAR8[0], VAR12, VAR9 );
VAR27 VA... | apache-2.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GDAN8M8P4_syn.v | 8,426 | module MODULE1 ( VAR155, VAR21, VAR313, VAR281 );
input [15:0] VAR21;
input [15:0] VAR313;
output [16:0] VAR281;
input VAR155;
wire VAR119, VAR299, VAR269, VAR16, VAR245, VAR215, VAR176, VAR62, VAR234, VAR54, VAR322, VAR32, VAR143, VAR270,
VAR311, VAR293, VAR24, VAR134, VAR195, VAR20, VAR1, VAR150, VAR17, VAR289, VAR32... | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v | 12,157 | module MODULE1 #
(
parameter VAR44 = 4096,
parameter VAR28 = 8,
parameter VAR41 = (VAR28>8),
parameter VAR26 = (VAR28/8),
parameter VAR7 = 8,
parameter VAR43 = (VAR7>8),
parameter VAR30 = (VAR7/8),
parameter VAR2 = 0,
parameter VAR3 = 8,
parameter VAR15 = 0,
parameter VAR10 = 8,
parameter VAR48 = 1,
parameter VAR42 = 1... | mit |
ptracton/vscale_soc | rtl/uart16550-1.5.4/bench/verilog/uart_wb_utilities.v | 13,298 | module MODULE1;
task VAR53;
input [VAR18-1:0] VAR45;
reg [3:0] VAR8;
reg VAR31 VAR55;
reg VAR49 VAR46;
integer VAR11;
integer VAR15;
integer VAR33;
reg VAR37;
begin
VAR8 = 4'hF;
VAR15 = 4;
VAR33 = 1;
VAR37 = 1'b0;
VAR2 = VAR11;
VAR65 = VAR15;
VAR4 = (VAR33 == 1);
VAR52 = VAR37;
if (VAR12 !== 1'b1)
begin
end
if (VAR... | mit |
pavel-demin/red-pitaya-notes | projects/red_pitaya_0_92/bus_clk_bridge.v | 3,535 | module MODULE1
(
input VAR9 , input VAR24 , input [ 32-1: 0] VAR14 , input [ 32-1: 0] VAR22 , input [ 4-1: 0] VAR13 , input VAR2 , input VAR1 , output [ 32-1: 0] VAR4 , output VAR27 , output VAR11 ,
input VAR3 , input VAR17 , output reg [ 32-1: 0] VAR18 , output reg [ 32-1: 0] VAR25 , output VAR15 , output VAR5 , input... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/verilog/aesl_mux_load_7_3_x_s.v | 13,878 | module MODULE1 (
VAR69,
VAR83,
VAR85,
VAR75,
VAR23,
VAR49,
VAR20,
VAR34,
VAR16,
VAR10,
VAR84,
VAR40,
VAR67,
VAR33,
VAR80,
VAR68,
VAR15,
VAR76,
VAR88,
VAR73,
VAR47,
VAR79,
VAR27,
VAR50,
VAR55,
VAR70,
VAR45,
VAR74,
VAR43,
VAR26,
VAR51,
VAR17,
VAR57,
VAR12,
VAR29,
VAR39,
VAR94,
VAR77,
VAR9,
VAR28,
VAR63,
VAR22,
VAR5,
VAR3... | mit |
klaNath/synth1 | spi_rx.v | 1,134 | module MODULE1(
clk,
VAR8,
VAR13,
VAR12,
VAR3,
VAR5,
VAR9,
VAR2);
input wire clk, VAR8, VAR13, VAR12, VAR3;
output wire VAR2;
output wire [7:0] VAR5, VAR9;
reg [15:0] VAR4, VAR6, VAR7;
reg [3:0] VAR1;
reg [2:0] VAR11;
wire VAR10;
assign VAR10 = &VAR1;
assign VAR5 = VAR7[15:8];
assign VAR9 = VAR7[7:0];
assign VAR2 = VAR... | lgpl-3.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/ClockDiv.v | 4,421 | module MODULE1(VAR14, VAR13, VAR4, VAR3);
parameter VAR8 = 2 ; parameter VAR10 = 1 ; parameter VAR5 = 3 ;
parameter VAR1 = 0;
input VAR14; input VAR13;
output VAR4; output VAR3;
reg [ VAR8 -1 : 0 ] VAR11 ;
reg VAR4 ;
wire [VAR8-1:0] VAR2 ;
wire [VAR8-1:0] VAR6 ;
assign VAR3 = VAR11[VAR8-1] ;
assign VAR2 = VAR5 ;
assign... | gpl-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/v7_ethernet_controller_top.v | 7,130 | module MODULE1 #(parameter VAR21 = 48'h001F293A10FD,VAR16 = 48'hAABBCCDDEEFF,VAR62 = 16'd1024,VAR29=48'hAABBCCDDEEFF)
(
input VAR13,
input VAR1,
output VAR73,
input VAR30, input VAR55, output VAR69, output VAR8, input VAR52, input VAR7,
output VAR46,
output VAR19,
input VAR35,
output VAR10,
output VAR12,
output VAR2,
i... | mit |
asicguy/gplgpu | hdl/generic/gen_pipe.v | 2,036 | module MODULE1
parameter VAR1 = 9'd32,
VAR2 = 5'd4
)
(
input clk,
input [VAR1 -1 :0] din,
output [VAR1 -1 :0] dout
);
reg [VAR1 - 1:0] VAR3 [VAR2 - 1:0];
reg [9:0] VAR4;
always @(posedge clk) begin
for(VAR4=(VAR2[9:0] - 10'h1); VAR4!=10'h0; VAR4=VAR4-10'h1)
VAR3[VAR4] <= VAR3[VAR4-10'h1];
VAR3[0] <= din;;
end
assign do... | gpl-3.0 |
zhangly/azpr_cpu | rtl/cpu/rtl/id_reg.v | 4,205 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR20] VAR33, input wire [VAR31] VAR34, input wire [VAR31] VAR36, input wire VAR13, input wire [VAR25] VAR26, input wire [VAR31] VAR21, input wire [VAR19] VAR1, input wire [VAR40] VAR4, input wire VAR2, input wire [VAR5] VAR17,
input wire VAR8, input wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1.blackbox.v | 1,296 | module MODULE1 (
VAR7,
VAR4,
VAR6
);
output VAR7;
input [7:0] VAR4;
input [7:0] VAR6;
supply1 VAR2;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4.pp.symbol.v | 1,330 | module MODULE1 (
input VAR3 ,
input VAR4 ,
input VAR8 ,
input VAR2 ,
output VAR9 ,
input VAR1 ,
input VAR7,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab02/lab02/Code/IOCore/Port/GPIO_IO.v | 1,121 | module MODULE1(input clk, input rst, input VAR2, input VAR6, input [31:0] VAR8, output reg[1:0] VAR7, output [15:0] VAR1, output wire VAR9, output wire VAR4, output wire VAR5, output wire VAR3, output reg[13:0] VAR10 );
endmodule | gpl-3.0 |
Tsung-Wei/OpenTimer | benchmark/s386/s386.v | 13,132 | module MODULE1 (
VAR49,
VAR304,
VAR108,
VAR22,
VAR284,
VAR100,
VAR137,
VAR326,
VAR261,
VAR189,
VAR369,
VAR55,
VAR283,
VAR246,
VAR234,
VAR347);
input VAR49;
input VAR304;
input VAR108;
input VAR22;
input VAR284;
input VAR100;
input VAR137;
input VAR326;
input VAR261;
output VAR189;
output VAR369;
output VAR55;
output VA... | gpl-3.0 |
freecores/altor32 | rtl/cpu/altor32_dcache_mem_if.v | 20,177 | module MODULE1
(
input VAR19 ,
input VAR34 ,
input [31:0] VAR14 ,
input [31:0] VAR29 ,
output reg [31:0] VAR26 ,
input VAR17 ,
input VAR31 ,
input [31:0] VAR33 ,
input VAR27 ,
input [3:0] VAR35 ,
output reg VAR4 ,
output reg [31:2] VAR22 ,
output reg [31:0] VAR20 ,
input [31:0] VAR6 ,
output reg VAR7 ,
output reg [31:0... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211o/sky130_fd_sc_hs__a211o.functional.v | 1,924 | module MODULE1 (
VAR6,
VAR13,
VAR15 ,
VAR12 ,
VAR9 ,
VAR10 ,
VAR1
);
input VAR6;
input VAR13;
output VAR15 ;
input VAR12 ;
input VAR9 ;
input VAR10 ;
input VAR1 ;
wire VAR1 VAR14 ;
wire VAR4 ;
wire VAR2;
and VAR8 (VAR14 , VAR12, VAR9 );
or VAR7 (VAR4 , VAR14, VAR1, VAR10 );
VAR3 VAR5 (VAR2, VAR4, VAR6, VAR13);
buf VAR1... | apache-2.0 |
davidjabon/AXI-Peripheral-Library | Eight_Digit_Seven_Segment_Display_2.0/src/seven_segment_leds_x_8.v | 2,639 | module MODULE1(
input [31:0] VAR4,
input [7:0] VAR7,
input clk,
output reg [6:0] VAR3,
output reg VAR6,
output reg [7:0] VAR2
);
wire [2:0] counter;
reg [3:0] VAR1;
reg [20:0] VAR5;
assign counter = VAR5[20:18];
always @(posedge clk)
case(counter)
0: {VAR1, VAR6} = {VAR4[3:0], ~VAR7[0]};
1: {VAR1, VAR6} = {VAR4[7:4], ~... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.functional.pp.v | 1,702 | module MODULE1( VAR5, VAR11, VAR20, VAR21, VAR8, VAR17, VAR1, VAR18 );
input VAR8, VAR17, VAR11, VAR5, VAR21;
inout VAR1, VAR18;
output VAR20;
wire VAR6;
not VAR7( VAR6, VAR8 );
wire VAR19;
not VAR12( VAR19, VAR17 );
wire VAR14;
and VAR15( VAR14, VAR6, VAR19 );
wire VAR23;
not VAR3( VAR23, VAR11 );
wire VAR2;
not VAR10... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2_0.v | 2,117 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR5 ,
VAR4,
VAR3,
VAR8 ,
VAR2
);
output VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR8 ;
input VAR2 ;
VAR9 VAR6 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR1,
VAR7,
VAR5
);
output VAR1;
... | apache-2.0 |
zambreno/RCL | sccCyGraph/verilog/cae_clock.v | 2,727 | module MODULE1 (
input clk,
input VAR20,
input VAR5,
output VAR8,
output VAR43,
output VAR33
);
generate if (VAR9 == 0) begin : VAR42
assign VAR8 = clk;
assign VAR43 = 1'b1;
assign VAR33 = VAR20;
end else begin : VAR18
wire VAR10;
VAR2 VAR54 (.VAR31(VAR8), .VAR1(VAR10));
if (VAR7 == "hc-1") begin : VAR3
VAR13 #(
.VAR49... | apache-2.0 |
Ribeiro/sd2snes | verilog/sd2snes_obc1/mcu_cmd.v | 12,579 | module MODULE1(
input clk,
input VAR35,
input VAR44,
input [7:0] VAR47,
input [7:0] VAR48,
output [2:0] VAR51,
output VAR20,
output VAR8,
output VAR19,
input VAR11,
output [7:0] VAR50,
input [7:0] VAR17,
output [7:0] VAR37,
input [31:0] VAR4,
input [2:0] VAR15,
output [23:0] VAR9,
output [23:0] VAR5,
output [23:0] VAR3... | gpl-2.0 |
VCTLabs/DE1_SOC_Linux_FB | ip/TERASIC_AUDIO/AUDIO_IF.v | 6,601 | module MODULE1(
VAR8,
VAR39,
VAR27,
VAR6,
VAR32,
VAR12,
VAR3,
VAR20,
VAR4,
VAR19,
VAR9,
VAR7,
VAR23
);
input VAR8;
input VAR39;
input [2:0] VAR27;
input VAR6;
output [15:0] VAR32;
input VAR12;
input [15:0] VAR3;
input VAR20;
input VAR4;
output VAR19;
input VAR9;
input VAR7;
output VAR23;
reg [15:0] VAR28;
reg VAR24;
wi... | epl-1.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_clock_converter_v2_1/hdl/verilog/axi_clock_converter_v2_1_axic_sync_clock_converter.v | 10,399 | module MODULE1 # (
parameter VAR7 = "VAR27",
parameter integer VAR28 = 32,
parameter integer VAR21 = 1,
parameter integer VAR51 = 1 ,
parameter integer VAR52 = 0 )
(
input wire VAR29,
input wire VAR11,
input wire VAR4,
input wire VAR2,
input wire [VAR28-1:0] VAR13,
input wire VAR44,
output wire VAR12,
input wire VAR49,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_p_pp_pg_n.blackbox.v | 1,428 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR1,
VAR5 ,
VAR2
);
output VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR1;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
grindars/bfcore | GenericCounter.v | 1,152 | module MODULE1 (
VAR8,
VAR7,
VAR5,
VAR4,
VAR2,
VAR3,
VAR6
);
parameter VAR1 = 8;
input VAR8;
input VAR7;
input [VAR1 - 1:0] VAR5;
output reg [VAR1 - 1:0] VAR4;
input VAR2;
input VAR3;
input VAR6;
always @ (posedge VAR8)
if(VAR7)
VAR4 <= 0;
else if(VAR2)
begin
if(VAR3)
VAR4 <= VAR5;
end
else if(VAR6)
VAR4 <= VAR4 - 1;
e... | gpl-3.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/sm_timer_64/sm_timer_64.v | 3,125 | module MODULE1
(
output wire VAR3 ,
input wire VAR9 ,
input wire [31 : 0] VAR6 ,
input wire VAR11 ,
output wire VAR16 ,
output wire [31 : 0] VAR8 ,
input wire VAR13 ,
input wire VAR5
);
localparam VAR24 = 8'b00000001; localparam VAR26 = 8'b00000010; localparam VAR15 = 8'b00000100; localparam VAR23 = 8'b00001000; localp... | bsd-3-clause |
velizarefremov/Rijndael | aesmain.v | 6,167 | module MODULE1(
output [127:0] out,
output ready,
output [3:0] VAR5,
input [127:0] in,
input [127:0] VAR14,
input VAR33,
input clk,
input reset
);
wire [127:0] VAR19;
wire [127:0] VAR28;
wire [127:0] VAR25;
wire [127:0] VAR35;
wire [127:0] VAR8;
wire [127:0] VAR41;
wire [127:0] VAR51;
wire [127:0] VAR10;
wire [127:0] V... | gpl-2.0 |
bluespec/Flute | builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkCSR_MIE.v | 3,367 | module MODULE1(VAR12,
VAR8,
VAR17,
VAR3,
VAR22,
VAR14,
VAR4,
VAR20);
input VAR12;
input VAR8;
input VAR17;
output [63 : 0] VAR3;
input [27 : 0] VAR22;
input [63 : 0] VAR14;
input VAR4;
output [63 : 0] VAR20;
wire [63 : 0] VAR20, VAR3;
reg [11 : 0] VAR15;
wire [11 : 0] VAR2;
wire VAR7;
wire VAR6,
VAR1,
VAR5,
VAR16;
wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b.behavioral.pp.v | 1,988 | module MODULE1 (
VAR15 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR13 ,
VAR2,
VAR14,
VAR17 ,
VAR4
);
output VAR15 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR13 ;
input VAR2;
input VAR14;
input VAR17 ;
input VAR4 ;
wire VAR5 ;
wire VAR16 ;
wire VAR10;
not VAR6 (VAR5 , VAR1 );
and VAR12 (VAR16 , VAR5, VAR9, VAR3, VAR13 );
VAR11 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp.functional.v | 1,206 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR4;
notif1 VAR3 (VAR2 , VAR1, VAR4 );
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/alt_mem_ddrx_wdata_path.v | 50,682 | module MODULE1
parameter
VAR197 = 16,
VAR43 = 8,
VAR249 = 1,
VAR236 = 5,
VAR255 = 4,
VAR144 = 1,
VAR99 = 1,
VAR10 = 8,
VAR2 = 10,
VAR158 = 2,
VAR250 = 1,
VAR245 = 0,
VAR229 = 1,
VAR87 = 8,
VAR172 = 5,
VAR86 = 1,
VAR171 = 1,
VAR225 = 1,
VAR84 = 1,
VAR1 = 8
)
(
VAR79,
VAR174,
VAR178,
VAR115,
VAR73,
VAR22,
VAR66,
VAR252,
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.v | 2,175 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR9,
VAR1,
VAR4 ,
VAR7 ,
VAR8
);
output VAR5 ;
input VAR2 ;
input VAR9;
input VAR1;
input VAR4 ;
input VAR7 ;
input VAR8 ;
VAR3 VAR6 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR5 ,
VAR2 ,
VAR9
);
output VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo.behavioral.v | 1,587 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR11 ,
VAR4
);
output VAR2 ;
input VAR9 ;
input VAR11 ;
input VAR4;
supply1 VAR12;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR10 ;
wire VAR1 ;
wire VAR3;
nand VAR7 (VAR1 , VAR11, VAR9 );
nand VAR13 (VAR3, VAR4, VAR1);
buf VAR6 (VAR2 , VAR3 );
endmodule | apache-2.0 |
jakubfi/mera400f | src/msg_cmd_dec.v | 1,105 | module MODULE1(
input [0:7] VAR10,
output VAR22, VAR2, in, VAR21, VAR13, VAR20, en,
output VAR17, VAR1, VAR12, VAR24
);
wire [0:10] VAR15;
always @ (*) begin
case (VAR10)
{ VAR5, VAR11, 3'b110 } : VAR15 = 11'b10000000000;
{ VAR5, VAR9, 3'b111 } : VAR15 = 11'b01000000000;
{ VAR5, VAR14, 3'b101 } : VAR15 = 11'b0010000000... | gpl-2.0 |
Marcoslz22/Tercer_Proyecto | font_rom.v | 96,061 | module MODULE1
(
input wire VAR3,
input wire [10:0] addr,
output reg [7:0] VAR2
);
reg [10:0] VAR1;
always @(posedge VAR3)
VAR1 <= addr;
always @*
case (VAR1)
11'h000: VAR2 = 8'b00000000; 11'h001: VAR2 = 8'b00000000; 11'h002: VAR2 = 8'b00000000; 11'h003: VAR2 = 8'b00000000; 11'h004: VAR2 = 8'b00000000; 11'h005: VAR2 = ... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado-hls/pointer_basic/proj_pointer_basic/solution2/impl/verilog/pointer_basic.v | 6,500 | module MODULE1 (
VAR7,
VAR32,
VAR42,
VAR17,
VAR25,
VAR36,
VAR2,
VAR35,
VAR1,
VAR43,
VAR5,
VAR19,
VAR10,
VAR15,
VAR24,
VAR28,
VAR12,
VAR23,
VAR13,
interrupt
);
parameter VAR31 = 3'd1;
parameter VAR40 = 3'd2;
parameter VAR30 = 3'd4;
parameter VAR22 = 32;
parameter VAR41 = 5;
parameter VAR21 = 32;
parameter VAR16 = (32 / ... | mit |
osrf/wandrr | firmware/motor_controller/fpga/usb_crc5.v | 2,639 | module MODULE1(
input [10:0] VAR5,
input VAR6,
output [4:0] VAR2,
input rst,
input clk);
reg [4:0] VAR7,VAR3;
assign VAR2 = ~VAR7;
always @;
wire [4:0] VAR4 = ~VAR2; VAR1 begin
rst <= 1'b0;
VAR6 <= 1'b0;
wait(clk);
wait(~clk);
rst <= 1'b1;
wait(clk);
wait(~clk);
rst <= 1'b0;
wait(clk);
wait(~clk);
VAR5 <= 11'b100000000... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_master_0.v | 21,599 | module MODULE1 #(
parameter VAR11 = 0,
parameter VAR18 = 50000,
parameter VAR36 = 2
) (
input wire VAR25, input wire VAR33, output wire [31:0] VAR41, input wire [31:0] VAR20, output wire VAR44, output wire VAR37, output wire [31:0] VAR5, input wire VAR28, input wire VAR4, output wire [3:0] VAR26, output wire VAR38 );
w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decapkapwr/sky130_fd_sc_lp__decapkapwr.functional.pp.v | 1,251 | module MODULE1 (
VAR2,
VAR1 ,
VAR4 ,
VAR5 ,
VAR3
);
input VAR2;
input VAR1 ;
input VAR4 ;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/Arty/fpga/rtl/fpga.v | 5,699 | module MODULE1 (
input wire clk,
input wire VAR13,
input wire [3:0] VAR85,
input wire [3:0] VAR1,
output wire VAR50,
output wire VAR7,
output wire VAR22,
output wire VAR115,
output wire VAR96,
output wire VAR110,
output wire VAR12,
output wire VAR4,
output wire VAR86,
output wire VAR35,
output wire VAR84,
output wire V... | mit |
sharebrained/medusa | hdl/medusa_cape/lcd_sync.v | 2,258 | module MODULE1 (
input rst,
input [23:0] VAR13,
input VAR18,
input VAR9,
input VAR17,
input VAR6,
output VAR3,
output [11:0] VAR11,
output [11:0] VAR1,
output [23:0] VAR8,
output VAR5
);
reg [11:0] VAR7;
reg [11:0] VAR10;
reg [23:0] VAR2;
reg VAR14;
reg VAR16;
reg VAR12;
assign VAR3 = VAR18;
assign VAR11 = VAR7;
assign... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/lsu_atomic.v | 14,521 | module MODULE1
(
clk, reset, VAR78, VAR14, VAR10, VAR43, VAR34, VAR95, VAR51,
VAR41, VAR45, VAR64, VAR6, VAR67, VAR68,
VAR80,
VAR88,
VAR1,
VAR44, VAR49, VAR77, VAR33, VAR97
);
parameter VAR5=32; parameter VAR50=4; parameter VAR75=32; parameter VAR94=32; parameter VAR25=2; parameter VAR47=32; parameter VAR8=0;
parameter... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.behavioral.pp.v | 7,224 | module MODULE1( VAR3, VAR11, VAR9, VAR2, VAR6, VAR5, VAR8, VAR7, VAR4 );
input VAR5, VAR8, VAR6, VAR2, VAR3, VAR9;
inout VAR7, VAR4;
output VAR11;
VAR1 VAR12(.VAR3(VAR3),.VAR11(VAR11),.VAR9(VAR9),.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5),.VAR8(VAR8),.VAR7(VAR7),.VAR4(VAR4));
VAR1 VAR10(.VAR3(VAR3),.VAR11(VAR11),.VAR9(VAR9),.... | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v | 15,079 | module MODULE1(
VAR13, VAR25, VAR43,
clk, rst, VAR19, VAR57, VAR73, addr, VAR78, VAR23
);
input VAR13;
input [VAR16 - 1:0] VAR43; output VAR25;
input clk; input rst; input VAR19; input [3:0] VAR57; input VAR73; input [10:0] addr; input [31:0] VAR78; output [31:0] VAR23;
assign VAR25 = VAR13;
VAR26 VAR11(
VAR7 VAR11(
VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah.functional.pp.v | 2,616 | module MODULE1 (
VAR10,
VAR13 ,
VAR17 ,
VAR24 ,
VAR1 ,
VAR20,
VAR15,
VAR6 ,
VAR3
);
output VAR10;
output VAR13 ;
input VAR17 ;
input VAR24 ;
input VAR1 ;
input VAR20;
input VAR15;
input VAR6 ;
input VAR3 ;
wire VAR16 ;
wire VAR4 ;
wire VAR5 ;
wire VAR18 ;
wire VAR21 ;
wire VAR9 ;
wire VAR7;
xor VAR23 (VAR16 , VAR17, VA... | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/PreProcessX.v | 4,081 | module MODULE1(
input [31:0] VAR42,
input [3:0] VAR4,
input [31:0] VAR1,
input [7:0] VAR18,
input VAR39,
output [31:0] VAR5,
output VAR47,
output [31:0] VAR25,
output [3:0] VAR46,
output [7:0] VAR19
);
reg [31:0] VAR9 = 32'h3f800000;
wire [31:0] VAR14;
assign VAR14 = VAR9;
wire VAR37,VAR30,VAR56,VAR16;
wire [3:0] VAR52... | apache-2.0 |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/9340d666125e38a0/mul17_16_stub.v | 1,309 | module MODULE1(VAR4, VAR1, VAR3, VAR2)
;
input VAR4;
input [16:0]VAR1;
input [15:0]VAR3;
output [8:0]VAR2;
endmodule | bsd-3-clause |
BoolLi/Pollard-s-p-1-algorithm | main.v | 2,901 | module MODULE1(input clk, input [31:0] VAR32, output [31:0] VAR39
);
wire VAR15;
wire VAR31;
wire VAR30;
wire VAR17;
reg VAR37;
reg VAR6;
wire [63:0] VAR7;
wire [7:0] VAR28;
wire[31:0] VAR34;
reg VAR13;
reg VAR5;
reg VAR10;
reg VAR40;
reg VAR11;
reg VAR38;
reg VAR29;
reg VAR8;
reg VAR22;
reg VAR25;
VAR9 VAR23 (.clk(clk... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p.functional.v | 1,365 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR4
);
output VAR3 ;
input VAR5 ;
input VAR4;
wire VAR6;
not VAR1 (VAR6, VAR4 );
and VAR2 (VAR3 , VAR5, VAR6 );
endmodule | apache-2.0 |
gralco/mojo-ide | Mojo IDE/base/mojo-v3/source/avr_interface.v | 2,262 | module MODULE1(
input clk,
input rst,
input VAR48,
output VAR11,
input VAR7,
input VAR4,
input VAR40,
output [3:0] VAR29,
output VAR22,
input VAR27,
input [3:0] VAR36,
output VAR24,
output [9:0] VAR30,
output [3:0] VAR15,
input [7:0] VAR26,
input VAR31,
output VAR5,
input VAR34,
output [7:0] VAR21,
output VAR45
);
wire... | gpl-3.0 |
gtaylormb/opl3_fpga | fpga/bd/opl3_cpu/ip/opl3_cpu_auto_pc_0/axi_data_fifo_v2_1_7/hdl/verilog/axi_data_fifo_v2_1_axi_data_fifo.v | 30,138 | module MODULE1 #
(
parameter VAR97 = "VAR192",
parameter integer VAR326 = 0,
parameter integer VAR74 = 4,
parameter integer VAR444 = 32,
parameter integer VAR288 = 32,
parameter integer VAR252 = 0,
parameter integer VAR62 = 1,
parameter integer VAR60 = 1,
parameter integer VAR32 = 1,
parameter integer VAR184 = 1,
param... | lgpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/halfband_interp.v | 4,408 | module MODULE1
(input VAR8, input reset, input enable,
input VAR31, input VAR42,
input [15:0] VAR32, input [15:0] VAR22,
output reg [15:0] VAR33, output reg [15:0] VAR13,
output wire [12:0] VAR12);
wire [15:0] VAR27;
wire [15:0] VAR36;
wire [15:0] VAR10;
wire [3:0] VAR1;
reg [3:0] VAR17;
reg [2:0] VAR18;
wire VAR15;
wi... | gpl-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/soc_system_onchip_memory2_0.v | 3,019 | module MODULE1 (
address,
VAR21,
VAR29,
clk,
VAR16,
reset,
VAR27,
write,
VAR31,
VAR2
)
;
parameter VAR20 = "MODULE1.VAR15";
output [ 63: 0] VAR2;
input [ 12: 0] address;
input [ 7: 0] VAR21;
input VAR29;
input clk;
input VAR16;
input reset;
input VAR27;
input write;
input [ 63: 0] VAR31;
wire VAR1;
wire [ 63: 0] VAR2;
... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9152/axi_ad9152_if.v | 4,487 | module MODULE1 (
VAR8,
VAR7,
VAR1,
VAR12,
VAR6,
VAR4,
VAR2,
VAR3,
VAR11,
VAR9,
VAR10,
VAR5);
input VAR8;
output [127:0] VAR7;
output VAR1;
input VAR12;
input [15:0] VAR6;
input [15:0] VAR4;
input [15:0] VAR2;
input [15:0] VAR3;
input [15:0] VAR11;
input [15:0] VAR9;
input [15:0] VAR10;
input [15:0] VAR5;
reg [127:0] VA... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/sdram.v | 14,170 | module MODULE1 (
input VAR17,
input VAR61,
input VAR40,
input VAR48,
input VAR5,
input [22:0] VAR41,
input [15:0] VAR49,
input [1:0] VAR71,
output [15:0] VAR50,
output reg VAR44,
input [15:0] VAR2, output [15:0] VAR26, output VAR7,
output reg [11:0] VAR76,
output reg [1:0] VAR21,
output VAR43,
output VAR18,
output reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21bo/sky130_fd_sc_hd__a21bo_2.v | 2,318 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR5 ,
VAR7,
VAR4,
VAR8,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR10 ;
input VAR5 ;
input VAR7;
input VAR4;
input VAR8;
input VAR1 ;
input VAR3 ;
VAR9 VAR6 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 ... | apache-2.0 |
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