repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
alonso193/proyecto1 | sintetizado/DATAblock.v | 88,509 | module \VAR62\MODULE6\VAR36=32 (VAR23, VAR46, VAR65, VAR77, VAR47, VAR40);
wire [8:0] 000;
wire [31:0] 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022;
wi... | gpl-3.0 |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_xbar_0/synth/triangle_intersect_xbar_0.v | 21,834 | module MODULE1 (
VAR113,
VAR6,
VAR46,
VAR51,
VAR108,
VAR11,
VAR42,
VAR70,
VAR131,
VAR96,
VAR31,
VAR109,
VAR2,
VAR87,
VAR20,
VAR78,
VAR56,
VAR47,
VAR105,
VAR93,
VAR125,
VAR119,
VAR121,
VAR60,
VAR37,
VAR9,
VAR126,
VAR18,
VAR17,
VAR127,
VAR64,
VAR50,
VAR104,
VAR30,
VAR29,
VAR129,
VAR22,
VAR59,
VAR4,
VAR53,
VAR114,
VAR102,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi.behavioral.v | 1,639 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR13 ,
VAR12
);
output VAR10 ;
input VAR8 ;
input VAR13 ;
input VAR12;
supply1 VAR4;
supply0 VAR3;
supply1 VAR9 ;
supply0 VAR1 ;
wire VAR7 ;
wire VAR5 ;
wire VAR15;
not VAR11 (VAR7 , VAR12 );
and VAR14 (VAR5 , VAR8, VAR13 );
nor VAR2 (VAR15, VAR7, VAR5 );
buf VAR6 (VAR10 , VAR15 );
endm... | apache-2.0 |
cmos3511/cmos_linux | python/pj/proj/rtl/LP/InstDecode.v | 4,258 | module MODULE1(VAR16,VAR9,VAR20,VAR7,
VAR17,VAR13,VAR11,VAR22,
VAR3,VAR14,reset);
input [31:0] VAR16; input VAR14; input reset;
output [3:0] VAR9, VAR20, VAR7; output [3:0] VAR17, VAR11; output VAR13, VAR22; output VAR3;
reg [31:0] VAR15; reg [3:0] VAR10; reg [3:0] VAR18; reg VAR5; reg VAR24; reg VAR6; reg VAR3;
parame... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o.pp.blackbox.v | 1,428 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR2 ,
VAR9 ,
VAR8 ,
VAR1 ,
VAR5,
VAR6,
VAR4 ,
VAR7
);
output VAR10 ;
input VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR8 ;
input VAR1 ;
input VAR5;
input VAR6;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/cart.v | 7,068 | module MODULE1
(
input wire clk,
input wire VAR3,
input wire VAR25,
input wire VAR29,
input wire [ 24-1:1] VAR10,
input wire [ 24-1:1] VAR31,
input wire VAR33,
input wire VAR28,
input wire VAR1,
input wire VAR16,
input wire [ 32-1:0] VAR22,
input wire [ 9-1:1] VAR18,
input wire [ 16-1:0] VAR7,
input wire VAR5,
input wi... | gpl-3.0 |
secworks/salsa20 | src/rtl/salsa20_qr.v | 3,559 | module MODULE1(
input wire [31 : 0] VAR1,
input wire [31 : 0] VAR13,
input wire [31 : 0] VAR11,
input wire [31 : 0] VAR9,
output wire [31 : 0] VAR16,
output wire [31 : 0] VAR8,
output wire [31 : 0] VAR10,
output wire [31 : 0] VAR14
);
reg [31 : 0] VAR15;
reg [31 : 0] VAR2;
reg [31 : 0] VAR12;
reg [31 : 0] VAR4;
assign ... | bsd-2-clause |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_buffer_manager.v | 8,756 | module MODULE1
parameter
VAR20 = 6
)
(
VAR21,
VAR14,
VAR10,
VAR4,
VAR18,
VAR22,
VAR11,
VAR12,
VAR8,
VAR5,
VAR3,
VAR2,
VAR16
);
localparam VAR13 = VAR9(VAR20);
input VAR21;
input VAR14;
output VAR10;
input VAR4;
input [VAR20-1:0] VAR18;
input VAR22;
output VAR11;
output [VAR20-1:0] VAR12;
input VAR8;
input [VAR20-1:0] V... | gpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/SPI_Controller/hdl/verilog/spi_shift.v | 9,419 | module MODULE1 (clk, rst, VAR10, VAR9, VAR6, VAR1, VAR19,
posedge, negedge, VAR23, VAR2,
VAR16, VAR21,
VAR13, VAR5, VAR14, VAR15, VAR3);
parameter VAR18 = 1;
input clk; input rst; input [3:0] VAR10; input [3:0] VAR9; input [VAR7-1:0] VAR6; input VAR1; input VAR19; input posedge; input negedge; input VAR23; input VAR2; ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a.symbol.v | 1,394 | module MODULE1 (
input VAR5,
input VAR4,
input VAR7 ,
input VAR9 ,
output VAR2
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
alan4186/ParCNN | DE2_115_CAMERA/v/CCD_Capture.v | 3,986 | module MODULE1( VAR19,
VAR23,
VAR24,
VAR22,
VAR7,
VAR18,
VAR12,
VAR4,
VAR6,
VAR16,
VAR21,
VAR5
);
input [11:0] VAR18;
input VAR12;
input VAR4;
input VAR6;
input VAR16;
input VAR21;
input VAR5;
output [11:0] VAR19;
output [15:0] VAR24;
output [15:0] VAR22;
output [31:0] VAR7;
output VAR23;
reg VAR3;
reg VAR1;
reg VAR20;... | mit |
Digilent/vivado-library | ip/Pmods/PmodOLED_v1_0/src/PmodOLED.v | 13,607 | module MODULE1
(VAR208,
VAR130,
VAR13,
VAR106,
VAR68,
VAR16,
VAR155,
VAR81,
VAR22,
VAR48,
VAR83,
VAR121,
VAR196,
VAR100,
VAR27,
VAR52,
VAR159,
VAR197,
VAR53,
VAR37,
VAR141,
VAR191,
VAR99,
VAR189,
VAR12,
VAR193,
VAR142,
VAR17,
VAR111,
VAR54,
VAR203,
VAR153,
VAR184,
VAR86,
VAR56,
VAR78,
VAR201,
VAR97,
VAR35,
VAR2,
VAR174... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fill/sky130_fd_sc_hd__fill.pp.blackbox.v | 1,173 | module MODULE1 (
VAR4,
VAR2,
VAR3 ,
VAR1
);
input VAR4;
input VAR2;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
martinmiranda14/Digitales | Lab_6/PS2_y_display.v | 3,705 | module MODULE1(
input VAR33,
input VAR11,
input VAR35,
input VAR2,
output [7:0] VAR24,
output VAR1,VAR50,VAR8,VAR23,VAR22,VAR39,VAR9,VAR34
);
wire reset;
wire VAR48;
wire VAR13;
wire [7:0] VAR27;
wire [2:0] VAR43;
wire [4:0] VAR21;
wire [31:0] VAR3;
wire [2:0] VAR28;
wire VAR18;
reg [3:0] VAR52,VAR57,VAR14,VAR45,VAR20,... | apache-2.0 |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/nios_design_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,243 | module MODULE1 (
clk,
VAR24,
VAR30,
VAR27,
VAR7,
VAR9,
VAR1,
VAR5,
VAR14,
VAR3,
VAR18,
VAR16,
VAR12,
VAR10,
VAR26,
VAR23
)
;
output [ 37: 0] VAR9;
output VAR1;
output VAR5;
output VAR14;
output VAR3;
output VAR18;
output VAR16;
output VAR12;
output VAR10;
output VAR26;
output VAR23;
input clk;
input [ 1: 0] VAR24;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4b/sky130_fd_sc_ms__or4b.behavioral.v | 1,498 | module MODULE1 (
VAR13 ,
VAR9 ,
VAR10 ,
VAR3 ,
VAR8
);
output VAR13 ;
input VAR9 ;
input VAR10 ;
input VAR3 ;
input VAR8;
supply1 VAR14;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR12 ;
wire VAR11 ;
wire VAR2;
not VAR7 (VAR11 , VAR8 );
or VAR6 (VAR2, VAR11, VAR3, VAR10, VAR9);
buf VAR5 (VAR13 , VAR2 );
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/spw_light_pll_0.v | 2,077 | module MODULE1(
input wire VAR10,
input wire rst,
output wire VAR64,
output wire VAR40
);
VAR63 #(
.VAR16("false"),
.VAR45("50.0 VAR22"),
.VAR5("VAR32"),
.VAR28(1),
.VAR20("200.000000 VAR22"),
.VAR31("0 VAR54"),
.VAR47(50),
.VAR48("0 VAR22"),
.VAR56("0 VAR54"),
.VAR34(50),
.VAR4("0 VAR22"),
.VAR41("0 VAR54"),
.VAR3(50)... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/pipestage.v | 1,186 | module MODULE1
(input clk,
input reset,
input VAR5,
input VAR3,
output reg valid,
input [VAR2-1:0] VAR1,
output reg [VAR2-1:0] VAR4);
always @(posedge clk)
if(reset)
begin
valid <= 0;
VAR4 <= 0;
end
else if(VAR5)
begin
valid <= 1;
VAR4 <= VAR1;
end
else if(VAR3)
begin
valid <= 0;
VAR4 <= 0;
end
endmodule | gpl-2.0 |
Jawanga/ece385final | finalproject/synthesis/submodules/finalproject_sdram.v | 24,562 | module MODULE1 (
clk,
rd,
VAR47,
wr,
VAR83,
VAR68,
VAR4,
VAR15,
VAR63,
VAR73
)
;
output VAR68;
output VAR4;
output VAR15;
output VAR63;
output [ 61: 0] VAR73;
input clk;
input rd;
input VAR47;
input wr;
input [ 61: 0] VAR83;
wire VAR68;
wire VAR4;
wire VAR15;
reg [ 1: 0] VAR12;
reg [ 61: 0] VAR21;
reg [ 61: 0] VAR42;
w... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_dtl_bscan.v | 4,982 | module MODULE1(VAR53 ,VAR26 ,VAR83 ,VAR36 ,
VAR86 ,VAR74 ,VAR38 ,VAR27 ,VAR1 ,VAR19 ,VAR10 ,
VAR16 ,VAR32 ,VAR25 ,VAR34 ,VAR80
,VAR62 ,VAR49 ,VAR30 ,VAR89 ,VAR50 ,
VAR87 ,VAR73 ,clk ,VAR28 ,VAR39 ,VAR24 ,VAR9 ,
VAR63 );
output VAR53 ;
output VAR36 ;
output VAR86 ;
output VAR16 ;
output VAR32 ;
output VAR30 ;
output VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapmet1/sky130_fd_sc_ms__tapmet1.functional.pp.v | 1,204 | module MODULE1 (
VAR2,
VAR1,
VAR4 ,
VAR3
);
input VAR2;
input VAR1;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
HarmonInstruments/verilog | sincos/cosrom_generic.v | 31,748 | module MODULE1 (
input VAR1, input [9:0] VAR2, VAR7, output reg [34:0] VAR4, VAR5);
reg [34:0] VAR6, VAR3;
reg [34:0] VAR8[0:1023];
always @ (posedge VAR1) begin
VAR6 <= VAR8[VAR2];
VAR3 <= VAR8[VAR7];
VAR4 <= VAR6;
VAR5 <= VAR3;
end | gpl-3.0 |
lfmunoz/vhdl | ip_blocks/sip_check_data/fifo_64_in_out/fifo_64in_out_stub.v | 1,526 | module MODULE1(rst, VAR6, VAR7, din, VAR5, VAR3, dout, VAR1, VAR4, valid, VAR2)
;
input rst;
input VAR6;
input VAR7;
input [63:0]din;
input VAR5;
input VAR3;
output [63:0]dout;
output VAR1;
output VAR4;
output valid;
output [11:0]VAR2;
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.functional.pp.v | 1,416 | module MODULE1( VAR15, VAR3, VAR5, VAR12, VAR14, VAR6, VAR1 );
input VAR5, VAR14, VAR3, VAR12;
inout VAR6, VAR1;
output VAR15;
wire VAR4;
not VAR10( VAR4, VAR5 );
wire VAR13;
not VAR7( VAR13, VAR14 );
wire VAR11;
not VAR9( VAR11, VAR3 );
wire VAR8;
not VAR2( VAR8, VAR12 );
or VAR16( VAR15, VAR4, VAR13, VAR11, VAR8 );
e... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/interconnect/wishbone_interconnect.v | 2,063 | module MODULE1 (
input clk,
input rst,
input VAR6,
input VAR2,
input VAR5,
input [3:0] VAR1,
input [31:0] VAR13,
input [31:0] VAR3,
output reg [31:0] VAR12,
output reg VAR10,
output VAR14,
{VAR8}
);
{VAR16}
parameter VAR18 = 8'hFF;
wire [7:0]VAR9;
wire [31:0] VAR17;
assign VAR9 = VAR13[31:24];
{VAR11}
{VAR15}
{VAR7}
as... | mit |
Openlights/hydra-fpga | hydra/hdl/strand_driver.v | 7,167 | module MODULE1 (
clk,
VAR27,
VAR21,
VAR7,
VAR13,
VAR26,
VAR17,
VAR24,
VAR19,
VAR3,
VAR25
);
parameter VAR20 = 24;
parameter VAR9 = 16;
input clk;
input VAR27;
input VAR21;
input [VAR9-1:0] VAR7;
output reg [VAR9-1:0] VAR13;
input [VAR20-1:0] VAR26;
input VAR17;
output reg VAR24;
output reg VAR19;
output reg VAR3;
outpu... | mit |
combinatorylogic/soc | backends/small1/hw/rtl/vga640x480.v | 7,245 | module MODULE1(input clk, input rst,
input VAR53,
input [7:0] VAR34,
output [12:0] VAR46,
output VAR2,
output VAR6,
output VAR48 );
reg [23:0] VAR41;
always @(posedge clk)
if (!rst)
VAR41 <= 0;
else
VAR41 <= VAR41 + 1;
reg VAR19;
reg VAR32;
reg [7:0] VAR11;
wire VAR13;
wire [7:0] VAR21;
wire VAR44;
VAR42 VAR8(.rst(rst)... | mit |
theapi/nand2tetris_fpga | hack/rtl/verilog/alu.v | 3,166 | module MODULE1 (
input [15:0] VAR13,
input [15:0] VAR10,
input VAR8, VAR7, VAR9, VAR6, VAR1, VAR16,
output [15:0] out,
output VAR5,
output VAR15
);
reg [15:0] VAR14;
reg [15:0] VAR4;
reg [15:0] VAR11;
reg [15:0] VAR3;
reg [15:0] VAR2 = 16'b0;
reg VAR12;
reg rng;
always @ (*) begin
if (VAR8 == 1) begin
VAR14 = 16'b0;
en... | mit |
bluespec/Flute | src_bsc_lib_RTL/SyncFIFO0.v | 10,499 | module MODULE1(
VAR15,
VAR19,
VAR28,
VAR32,
VAR26,
VAR25,
VAR20
) ;
parameter VAR10 = 2 ; parameter VAR6 = 1 ;
input VAR15 ;
input VAR19 ;
input VAR32 ;
output VAR26 ;
input VAR28 ;
input VAR25 ;
output VAR20 ;
wire [VAR6 : 0] VAR13 = ~({(VAR6 + 1){1'b1}} >> 1) ;
wire [VAR6 - 1 : 0] VAR22 = ~({(VAR6 + 0){1'b1}} >> 1) ;... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_fifo_v1_00_a/hdl/verilog/axi_fifo.v | 5,161 | module MODULE1 (
input VAR2,
input VAR8,
input VAR18,
output VAR21,
output [VAR29-1:0] VAR12,
input VAR9,
input VAR19,
output VAR3,
input VAR6,
input [VAR29-1:0] VAR24,
output VAR15
);
parameter VAR29 = 64;
parameter VAR14 = 1;
parameter VAR11 = 4;
generate if (VAR11 == 0) begin
reg [VAR29-1:0] VAR16;
reg VAR27 = 1'b0;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41ai/sky130_fd_sc_hd__o41ai.blackbox.v | 1,375 | module MODULE1 (
VAR3 ,
VAR10,
VAR9,
VAR6,
VAR5,
VAR2
);
output VAR3 ;
input VAR10;
input VAR9;
input VAR6;
input VAR5;
input VAR2;
supply1 VAR4;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Reset_Delay_block.v | 2,094 | module MODULE1
(
VAR1,
reset,
VAR4,
VAR6,
VAR7,
VAR11
);
input VAR1;
input reset;
input VAR4;
input VAR6;
input signed [31:0] VAR7; output signed [31:0] VAR11;
wire signed [31:0] VAR5; wire signed [31:0] VAR8; reg signed [31:0] VAR10; wire signed [31:0] VAR3; wire signed [31:0] VAR12;
assign VAR5 = 32'VAR9;
assign VAR8... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi.symbol.v | 1,371 | module MODULE1 (
input VAR2,
input VAR6,
input VAR9,
input VAR1,
output VAR5
);
supply1 VAR7;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1_bb.v | 1,886 | module MODULE1 #(
parameter VAR21 = 512,
parameter VAR19 = 8,
parameter VAR25 = 32,
parameter VAR5 = 5,
parameter VAR12 = 1,
parameter VAR9 = 1
) (
input wire clk, input wire VAR16, input wire [VAR21-1:0] VAR18, input wire VAR8, output wire [VAR5-1:0] VAR4, output wire [VAR21-1:0] VAR11, output wire [VAR25-1:0] VAR24, ... | mit |
juan199/Lab_Digitales | Proyecto/buffers.v | 1,354 | module MODULE1(
input wire VAR5,
input wire VAR3,
output reg [17:0] VAR2,
output reg VAR1
);
reg [17:0] VAR6;
integer VAR4;
begin
begin
begin
end
begin
begin
begin
end | lgpl-3.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v2_0_infrastructure.v | 24,252 | module MODULE1 #
(
parameter VAR2 = "VAR46", parameter VAR17 = 100, parameter VAR5 = 3000, parameter VAR11 = 2, parameter VAR12 = "VAR40",
parameter VAR54 = "VAR46",
parameter VAR53 = 4, parameter VAR52 = 1, parameter VAR43 = 45.0, parameter VAR18 = 16, parameter VAR51 = 4, parameter VAR45 = 64, parameter VAR8 = 16, pa... | bsd-2-clause |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/pikachu_jump_pixel/pikachu_jump_pixel_stub.v | 1,329 | module MODULE1(VAR3, VAR1, VAR2, VAR5, VAR4)
;
input VAR3;
input [0:0]VAR1;
input [12:0]VAR2;
input [11:0]VAR5;
output [11:0]VAR4;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2.behavioral.pp.v | 1,832 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR10 ,
VAR8,
VAR5,
VAR4 ,
VAR1
);
output VAR12 ;
input VAR7 ;
input VAR10 ;
input VAR8;
input VAR5;
input VAR4 ;
input VAR1 ;
wire VAR2 ;
wire VAR11;
xor VAR3 (VAR2 , VAR10, VAR7 );
VAR13 VAR6 (VAR11, VAR2, VAR8, VAR5);
buf VAR9 (VAR12 , VAR11 );
endmodule | apache-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_audio_out_serializer.v | 9,445 | module MODULE1 (
clk,
reset,
VAR30,
VAR14,
VAR36,
VAR31,
VAR32,
VAR20,
VAR28,
VAR15,
VAR2,
VAR23,
VAR11
);
parameter VAR1 = 15;
input clk;
input reset;
input VAR30;
input VAR14;
input VAR36;
input VAR31;
input [VAR1: 0] VAR32;
input VAR20;
input [VAR1: 0] VAR28;
input VAR15;
output reg [ 7: 0] VAR2;
output reg [ 7: 0] ... | mit |
unihd-cag/openhmc | rtl/hmc_controller/rx/rx_crc_compare.v | 19,907 | module MODULE1 #(
parameter VAR58 = 2,
parameter VAR32 = 4,
parameter VAR33 = 512
) (
input wire clk,
input wire VAR26,
input wire [VAR32-1:0] VAR2,
input wire [VAR32-1:0] VAR40,
input wire [VAR32-1:0] VAR43,
input wire [VAR33-1:0] VAR3,
input wire [(VAR32*4)-1:0] VAR18,
output wire [VAR33-1:0] VAR4,
output reg [VAR32-... | lgpl-3.0 |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/altera_reset_controller.v | 12,323 | module MODULE1
parameter VAR3 = 6,
parameter VAR76 = 0,
parameter VAR66 = 0,
parameter VAR39 = 0,
parameter VAR65 = 0,
parameter VAR58 = 0,
parameter VAR44 = 0,
parameter VAR37 = 0,
parameter VAR6 = 0,
parameter VAR4 = 0,
parameter VAR27 = 0,
parameter VAR50 = 0,
parameter VAR24 = 0,
parameter VAR61 = 0,
parameter VAR4... | mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/new/delta_sigma.v | 1,027 | module MODULE1(
input [15:0] din,
input VAR2,
output reg dout
);
reg [16:0] VAR1;
always @(posedge VAR2) begin
VAR1[16:0] = VAR1[15:0] + {~din[15], din[14:0]}; dout = VAR1[16];
end
endmodule | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/387128e4034068b3/zqynq_lab_1_design_processing_system7_0_0_stub.v | 5,351 | module MODULE1(VAR50, VAR15,
VAR55, VAR3, VAR32, VAR36,
VAR34, VAR35, VAR24, VAR6,
VAR1, VAR17, VAR57, VAR51, VAR68,
VAR27, VAR14, VAR67, VAR38,
VAR22, VAR9, VAR7, VAR16, VAR37,
VAR64, VAR33, VAR4, VAR59, VAR30,
VAR46, VAR47, VAR11, VAR8, VAR62,
VAR54, VAR44, VAR61, VAR48,
VAR56, VAR60, VAR41, VAR39, VAR42,
VAR40, VAR4... | mit |
jairov4/accel-oil | solution_kintex7/impl/ip/hdl/verilog/nfa_accept_samples_generic_hw.v | 73,209 | module MODULE1 (
VAR86,
VAR105,
VAR6,
VAR98,
VAR114,
VAR75,
VAR10,
VAR264,
VAR21,
VAR233,
VAR85,
VAR124,
VAR208,
VAR213,
VAR16,
VAR291,
VAR171,
VAR55,
VAR34,
VAR64,
VAR187,
VAR159,
VAR180,
VAR230,
VAR284,
VAR270,
VAR274,
VAR73,
VAR52,
VAR298,
VAR195,
VAR140,
VAR99,
VAR47,
VAR91,
VAR242,
VAR217,
VAR18,
VAR122,
VAR19,
VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi.pp.blackbox.v | 1,397 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR8 ,
VAR4 ,
VAR5 ,
VAR3,
VAR7,
VAR1 ,
VAR6
);
output VAR9 ;
input VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR5 ;
input VAR3;
input VAR7;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
azonenberg/antikernel-ipcores | noc/rpcv3/RPCv3Router.v | 11,987 | module MODULE1
parameter VAR8 = 32,
parameter VAR14 = 1'b0,
parameter VAR1 = 4,
parameter VAR9 = 32'h20202020,
parameter VAR4 = {4'b1111},
parameter VAR15 = 32'h20202020,
parameter VAR12 = 4'h0,
parameter VAR5 = 4'h0
)
(
input wire clk,
output wire[3:0] VAR19,
output wire[511:0] VAR21,
input wire[3:0] VAR2,
input wire[... | bsd-3-clause |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_intr_rd_mem.v | 2,272 | module MODULE1(
VAR5,
VAR15,
VAR18,
VAR3,
req,
VAR8,
VAR9,
VAR4,
VAR13,
VAR11,
VAR12
);
input VAR5, VAR15;
output VAR18, VAR3;
input VAR12, VAR11;
input [VAR16-1:0] VAR13, VAR4;
input req, VAR8;
input [VAR7-1:0] VAR9;
reg [VAR10-1:0] VAR20 = 0, VAR2 = 0;
reg [VAR19-1:0] VAR6 [0:VAR14-1]; wire VAR18, VAR3;
assign VAR3 =... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/adv7511/ac701/system_top.v | 6,232 | module MODULE1 (
VAR6,
VAR10,
VAR13,
VAR74,
VAR30,
VAR43,
VAR38,
VAR8,
VAR32,
VAR44,
VAR53,
VAR41,
VAR24,
VAR75,
VAR25,
VAR19,
VAR71,
VAR22,
VAR73,
VAR40,
VAR18,
VAR62,
VAR68,
VAR76,
VAR7,
VAR17,
VAR51,
VAR16,
VAR59,
VAR23,
VAR9,
VAR45,
VAR80,
VAR3,
VAR12,
VAR60,
VAR50,
VAR78,
VAR14,
VAR33,
VAR48);
input VAR6;
input VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2/sky130_fd_sc_hdll__and2.pp.symbol.v | 1,271 | module MODULE1 (
input VAR5 ,
input VAR6 ,
output VAR3 ,
input VAR4 ,
input VAR1,
input VAR7,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4/sky130_fd_sc_hdll__nand4.functional.v | 1,320 | module MODULE1 (
VAR5,
VAR3,
VAR7,
VAR8,
VAR6
);
output VAR5;
input VAR3;
input VAR7;
input VAR8;
input VAR6;
wire VAR2;
nand VAR4 (VAR2, VAR6, VAR8, VAR7, VAR3 );
buf VAR1 (VAR5 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ba/sky130_fd_sc_ms__o21ba_4.v | 2,316 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR1 ,
VAR8,
VAR4,
VAR7,
VAR3 ,
VAR5
);
output VAR9 ;
input VAR6 ;
input VAR1 ;
input VAR8;
input VAR4;
input VAR7;
input VAR3 ;
input VAR5 ;
VAR10 VAR2 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux2/sky130_fd_sc_hvl__mux2.pp.blackbox.v | 1,299 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR6 ,
VAR7 ,
VAR8,
VAR4,
VAR2 ,
VAR3
);
output VAR5 ;
input VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR8;
input VAR4;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.functional.v | 1,666 | module MODULE1( VAR3, VAR21, VAR20, VAR10, VAR9, VAR18 );
input VAR20, VAR21, VAR3, VAR18, VAR9;
output VAR10;
wire VAR1;
not VAR4( VAR1, VAR20 );
wire VAR7;
not VAR13( VAR7, VAR21 );
wire VAR8;
not VAR19( VAR8, VAR3 );
wire VAR5;
and VAR12( VAR5, VAR1, VAR7, VAR8 );
wire VAR17;
not VAR14( VAR17, VAR18 );
wire VAR15;
n... | apache-2.0 |
P3Stor/P3Stor | DDR3/phy/phy_top.v | 54,045 | module MODULE1 #
(
parameter VAR205 = 100,
parameter VAR280 = 2, parameter VAR199 = 3333, parameter VAR152 = 300.0, parameter VAR34 = "VAR228", parameter [7:0] VAR337 = 8'b00000001,
parameter [7:0] VAR326 = 8'b00000000,
parameter VAR36 = 2, parameter VAR67 = 1, parameter VAR71 = 10, parameter VAR102 = 1, parameter VAR1... | gpl-2.0 |
elegabriel/myzju | junior1/CA/pipeline3/code/alu.v | 2,062 | module MODULE1(VAR3,VAR2,VAR4,VAR1
);
input wire [31:0] VAR3,VAR2;
input wire [4:0] VAR4;
output reg [31:0] VAR1;
always @*
begin
case(VAR4)
5'd0: VAR1=VAR3+VAR2;
5'd1: VAR1=VAR3+VAR2;
5'd2: VAR1=VAR3-VAR2;
5'd3: VAR1=VAR3-VAR2;
5'd4: VAR1=VAR3&VAR2;
5'd5: VAR1=VAR3|VAR2;
5'd6: VAR1=VAR3^VAR2;
5'd7: VAR1=~(VAR3|VAR2);
... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.behavioral.v | 1,098 | module MODULE1( VAR2, VAR4 );
input VAR2;
output VAR4;
VAR5 VAR3(.VAR2(VAR2),.VAR4(VAR4));
VAR5 VAR1(.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
Triple-Z/COExperiment_Repo | Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu.v | 9,408 | module MODULE1(
input clk, input VAR74,
input [ 4:0] VAR49,
input [31:0] VAR2,
output [31:0] VAR61,
output [31:0] VAR93,
output [31:0] VAR46,
output [31:0] VAR32
);
reg [31:0] VAR70;
wire [31:0] VAR22;
wire [31:0] VAR62;
wire [31:0] VAR6;
wire VAR26;
assign VAR62[31:2] = VAR70[31:2] + 1'b1;
assign VAR62[1:0] = VAR70[1:... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/channel_128.v | 9,868 | module MODULE1 #(
parameter VAR63 = 9'd128,
parameter VAR85 = 2, parameter VAR75 = 1024,
parameter VAR70 = 512,
parameter VAR88 = 1024,
parameter VAR17 = VAR64((VAR63/32)+1)
)
(
input VAR7,
input VAR102,
input [2:0] VAR33, input [2:0] VAR1,
input [31:0] VAR62, input [VAR63-1:0] VAR3,
output VAR39, input VAR30, input VA... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/8d6f9c45e1ea3378/zynq_design_1_auto_pc_1_stub.v | 5,767 | module MODULE1(VAR57, VAR73, VAR78, VAR39,
VAR58, VAR50, VAR5, VAR26, VAR13, VAR29,
VAR77, VAR65, VAR69, VAR15, VAR1, VAR6, VAR45,
VAR4, VAR59, VAR46, VAR42, VAR22, VAR16, VAR43,
VAR28, VAR61, VAR2, VAR67, VAR37, VAR31,
VAR33, VAR12, VAR17, VAR47, VAR35, VAR71, VAR9,
VAR25, VAR40, VAR76, VAR63, VAR3, VAR41, VAR56,
VAR7... | mit |
dingzh/piplined-MIPS-CPU | src/LAB5/Top.v | 5,098 | module MODULE1(
input VAR6,
input wire VAR31,
input [2:0] VAR5,
output [7:0] VAR4,
input VAR29
);
wire VAR21;
reg [26:0] VAR27 = 0;
always@ (posedge VAR6) VAR27 = VAR27 + 1;
assign VAR21 = VAR29 ? VAR27[1] : VAR27[0];
assign VAR4[7] = VAR31;
assign VAR4[6] = VAR21;
wire [5:0] VAR15;
assign VAR4[5:0] = VAR15;
wire [31:0... | gpl-3.0 |
alexforencich/hdg2000 | fpga/lib/dsp/rtl/iq_join.v | 2,794 | module MODULE1 #
(
parameter VAR9 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR9-1:0] VAR14,
input wire VAR2,
output wire VAR11,
input wire [VAR9-1:0] VAR6,
input wire VAR13,
output wire VAR8,
output wire [VAR9-1:0] VAR10,
output wire [VAR9-1:0] VAR3,
output wire VAR7,
input wire VAR1
);
reg [VAR9-1:0] VAR5 ... | mit |
kammce/LPCXpresso-Nexys4-Servo-Commander | ServoCommander.srcs/sources_1/new/SerialServo.v | 5,031 | module MODULE1(
input wire VAR15,
input wire VAR14,
input wire rst,
input wire VAR16,
input wire VAR9,
input wire VAR7,
input wire [VAR2-1:0] VAR12,
output reg VAR13
);
parameter VAR18 = 11;
parameter VAR2 = 5;
parameter VAR10 = 16;
reg [VAR10-1:0] buffer;
reg [VAR2-1:0] VAR23;
reg [VAR18-1:0] VAR11;
reg [VAR2-1:0] VAR... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.functional.pp.v | 1,190 | module MODULE1( VAR13, VAR12, VAR6, VAR16, VAR14, VAR2 );
input VAR12, VAR6;
inout VAR14, VAR2;
output VAR13, VAR16;
and VAR8( VAR13, VAR12, VAR6 );
wire VAR10;
not VAR1( VAR10, VAR6 );
wire VAR11;
and VAR15( VAR11, VAR10, VAR12 );
wire VAR4;
not VAR7( VAR4, VAR12 );
wire VAR9;
and VAR5( VAR9, VAR4, VAR6 );
or VAR3( VA... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/buffers/RxFifo.v | 4,947 | module MODULE1(
VAR23,
VAR24,
VAR6,
VAR5,
VAR29,
VAR8,
VAR15,
VAR18,
VAR3,
VAR34,
VAR17,
VAR31,
VAR27 );
parameter VAR7 = 64;
parameter VAR22 = 6;
input VAR23;
input VAR24;
input VAR6;
input VAR5;
input VAR29;
output VAR8;
input [2:0] VAR15;
input VAR18;
input VAR3;
input VAR34;
input [7:0] VAR17;
output [7:0] VAR31;
i... | gpl-3.0 |
hwstar/Timestamper-FPGA | channel.v | 5,044 | module MODULE3(out, clk, VAR26, in);
output reg out;
input clk;
input VAR26;
input in;
reg [4:0] VAR29;
reg VAR32;
always @(posedge clk or negedge VAR26) begin
if(VAR26 == 0) begin
VAR29 <= 0;
out <= 0;
end else begin
VAR29[4] <= VAR29[3];
VAR29[3] <= VAR29[2];
VAR29[2] <= VAR29[1];
VAR29[1] <= VAR29[0];
VAR29[0] <= in... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp.functional.pp.v | 1,956 | module MODULE1 (
VAR6 ,
VAR12 ,
VAR17 ,
VAR4 ,
VAR2,
VAR14 ,
VAR10 ,
VAR11 ,
VAR13
);
output VAR6 ;
output VAR12 ;
input VAR17 ;
input VAR4 ;
input VAR2;
input VAR14 ;
input VAR10 ;
input VAR11 ;
input VAR13 ;
wire VAR3;
wire VAR8 ;
not VAR5 (VAR8 , VAR2 );
VAR16 VAR15 VAR9 (VAR3 , VAR4, VAR17, VAR8, , VAR14, VAR10);
b... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4.blackbox.v | 1,239 | module MODULE1 (
VAR5,
VAR2,
VAR6,
VAR4,
VAR1
);
output VAR5;
input VAR2;
input VAR6;
input VAR4;
input VAR1;
supply1 VAR3;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxtp/sky130_fd_sc_ls__edfxtp.functional.pp.v | 1,947 | module MODULE1 (
VAR6 ,
VAR11 ,
VAR10 ,
VAR4 ,
VAR14,
VAR2,
VAR16 ,
VAR13
);
output VAR6 ;
input VAR11 ;
input VAR10 ;
input VAR4 ;
input VAR14;
input VAR2;
input VAR16 ;
input VAR13 ;
wire VAR8 ;
wire VAR15;
VAR9 VAR12 (VAR15, VAR8, VAR10, VAR4 );
VAR3 VAR7 VAR5 (VAR8 , VAR15, VAR11, , VAR14, VAR2);
buf VAR1 (VAR6 , V... | apache-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v | 51,698 | module MODULE1 #
(
parameter VAR126 = 100, parameter VAR71 = 2, parameter VAR37 = 5, parameter VAR138 = "0",
parameter VAR143 = 5, parameter VAR27 = "VAR32", parameter VAR117 = 1, parameter VAR9 = 3, parameter VAR103 = 8, parameter VAR12 = 8, parameter VAR50 = "VAR67", parameter VAR146 = "VAR57", parameter VAR13 = 3, p... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2i/sky130_fd_sc_hd__mux2i_4.v | 2,214 | module MODULE2 (
VAR10 ,
VAR1 ,
VAR8 ,
VAR9 ,
VAR6,
VAR7,
VAR2 ,
VAR4
);
output VAR10 ;
input VAR1 ;
input VAR8 ;
input VAR9 ;
input VAR6;
input VAR7;
input VAR2 ;
input VAR4 ;
VAR5 VAR3 (
.VAR10(VAR10),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3b/sky130_fd_sc_hs__or3b.pp.symbol.v | 1,268 | module MODULE1 (
input VAR1 ,
input VAR5 ,
input VAR2 ,
output VAR4 ,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/SD/SD_Module_Interface.v | 2,067 | module MODULE1(
input VAR6,
input VAR16,
input VAR24,
output VAR7,
output VAR28,
output VAR5,
output [4:0] VAR26,
input VAR22,
input VAR8,
output VAR27,
input [29:0] VAR29,
input [4095:0] VAR12,
output[4095:0] VAR2
);
wire [7:0] VAR9, VAR20;
wire VAR25, VAR4, VAR23;
VAR13 VAR14(
.VAR5 (VAR5),
.VAR16 (VAR16),
.VAR17 (VA... | lgpl-3.0 |
ZiCog/xoro | rtl/Fifo.v | 2,037 | module MODULE1 (
input [7:0] VAR1,
output [7:0] VAR14,
input VAR17,
input VAR3,
output VAR10,
output VAR16,
input clk,
input reset);
wire [7:0] VAR6;
wire [7:0] VAR7;
wire VAR5;
reg [5:0] head;
reg [5:0] VAR4;
reg VAR8;
reg VAR13;
wire [5:0] VAR2;
wire [5:0] VAR11;
wire VAR15;
wire VAR18;
wire VAR12;
reg [7:0] VAR9 [0:... | mit |
Elphel/x353 | compressor/compressor333.v | 68,380 | module MODULE3( clk, VAR155, VAR216, VAR287, VAR228,
VAR309, VAR301, VAR16, VAR162, VAR166,
VAR242, VAR223, VAR152, VAR87, VAR113, VAR134, VAR307, VAR85, VAR114,
VAR112, VAR298, VAR316, VAR8, VAR147, VAR281, VAR86, VAR157, VAR333, VAR33, VAR212, VAR111, VAR260, VAR230, VAR72, VAR286, VAR353, VAR282,
VAR186,
VAR69, VAR3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi.functional.pp.v | 2,006 | module MODULE1 (
VAR15 ,
VAR8 ,
VAR7 ,
VAR4 ,
VAR16,
VAR2,
VAR5 ,
VAR12
);
output VAR15 ;
input VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR16;
input VAR2;
input VAR5 ;
input VAR12 ;
wire VAR13 ;
wire VAR14 ;
wire VAR10;
and VAR11 (VAR13 , VAR8, VAR7 );
nor VAR9 (VAR14 , VAR4, VAR13 );
VAR6 VAR1 (VAR10, VAR14, VAR16, VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_imd.v | 8,453 | module MODULE1(
VAR3, VAR20, VAR23, VAR29,
VAR35, VAR30, VAR13, VAR22,
VAR33, VAR59, VAR7,
VAR38, VAR60, VAR55, VAR9, VAR27,
VAR26, VAR47,
VAR54, VAR50, VAR39, VAR51, VAR32,
VAR1, VAR53,
VAR2, VAR49,
VAR63, VAR34,
VAR28, VAR17,
VAR56, VAR19
);
input VAR54,
VAR50,
VAR39;
input [31:0] VAR51;
input VAR32;
input VAR1, VAR5... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtp/sky130_fd_sc_ms__sdfrtp.symbol.v | 1,510 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR10,
input VAR6 ,
input VAR8 ,
input VAR3
);
supply1 VAR9;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
hakehuang/pycpld | ips/ip/spi_slave/spi_slave.v | 4,314 | module MODULE1(
clk,VAR20,VAR9,VAR16,VAR15,VAR7,VAR11
);
input clk;
input VAR7;
input VAR20,VAR9,VAR15;
output VAR16;
output VAR11;
reg VAR11;
reg[2:0] VAR1;
reg[2:0] VAR19;
reg[1:0] VAR3;
reg[2:0] VAR10;
reg[7:0] VAR6;
reg VAR18; reg [7:0] VAR8;
reg[7:0] VAR21;
reg [7:0] VAR12;
reg [7:0] VAR17;
wire VAR22;
wire VAR5;
... | mit |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/source/rtl/pipelined_multiplier.v | 1,087 | module MODULE1 #(parameter VAR8=32)(
input wire VAR6,
input wire [VAR8-1:0] VAR4,
input wire [VAR8-1:0] VAR12,
output reg [(VAR8-1) * 2:0] VAR9
);
reg [(VAR8-1):0] VAR13, VAR3;
wire [(VAR8-1) * 2:0] VAR1;
reg [(VAR8-1) * 2:0] VAR7, VAR10, VAR11, VAR2, VAR5;
assign VAR1 = VAR13 * VAR3;
always @(posedge VAR6) begin
VAR13... | gpl-3.0 |
VectorBlox/PYNQ | Pynq-Z1/vivado/ip/pmod_io_switch_1.0/hdl/pmod_io_switch_v1_0.v | 4,243 | module MODULE1 #
(
parameter integer VAR4 = 32,
parameter integer VAR40 = 4
)
(
output wire [7:0] VAR10,
input wire [7:0] VAR60,
input wire [7:0] VAR65,
input wire [7:0] VAR3,
output wire [7:0] VAR30,
output wire [7:0] VAR21,
output wire VAR29,
input wire VAR42,
input wire VAR66,
output wire VAR27,
input wire VAR9,
inp... | bsd-3-clause |
velizarefremov/MIPS | Part 4/Verilog Code/control_unit.v | 4,992 | module MODULE1(
output reg VAR5, output reg VAR12, output reg VAR13, output reg VAR9, output reg [1:0] VAR15, output reg VAR8, output reg VAR11, output reg VAR16, output reg VAR10, input [15:0] VAR7, input [15:0] VAR2 );
reg VAR4; wire [3:0] VAR3; wire [3:0] VAR6; wire VAR1; wire VAR14;
assign VAR3 = VAR7[11:8];
assign... | gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_sprs.v | 18,642 | module MODULE1(
clk, rst,
VAR10, VAR29, flag, VAR57, VAR84, VAR5,
VAR69, VAR50, VAR76, VAR74, VAR70,
VAR85, VAR77, VAR62, VAR58,
VAR18, VAR66, VAR11, VAR14, VAR15, VAR46, VAR86, VAR45,
VAR79, VAR44, VAR65, VAR37, VAR78,
VAR1, VAR87, VAR41,
VAR51, VAR3, VAR49,
VAR20, VAR33, VAR16, VAR81,
VAR30, VAR61, VAR72,
VAR28, VAR5... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_16.behavioral.pp.v | 1,187 | module MODULE1( VAR5, VAR1, VAR2, VAR4 );
input VAR5;
inout VAR2, VAR4;
output VAR1;
VAR6 VAR7(.VAR5(VAR5),.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR4));
VAR6 VAR3(.VAR5(VAR5),.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_dp.v | 4,511 | module MODULE1 (
VAR3, VAR14,
VAR7, VAR2, VAR1, VAR8, VAR16, VAR9, VAR12, VAR15, VAR18, VAR13 );
parameter VAR10 = 6; parameter VAR19 = 256;
output [15:0] VAR3; output [15:0] VAR14;
input [VAR10:0] VAR7; input VAR2; input VAR1; input [15:0] VAR8; input [1:0] VAR16; input [VAR10:0] VAR9; input VAR12; input VAR15; input ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a_2.v | 2,264 | module MODULE2 (
VAR5 ,
VAR9 ,
VAR4 ,
VAR6 ,
VAR8,
VAR3,
VAR2 ,
VAR10
);
output VAR5 ;
input VAR9 ;
input VAR4 ;
input VAR6 ;
input VAR8;
input VAR3;
input VAR2 ;
input VAR10 ;
VAR7 VAR1 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21o/sky130_fd_sc_ls__a21o.functional.pp.v | 1,994 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR13 ,
VAR10 ,
VAR12,
VAR7,
VAR11 ,
VAR9
);
output VAR6 ;
input VAR2 ;
input VAR13 ;
input VAR10 ;
input VAR12;
input VAR7;
input VAR11 ;
input VAR9 ;
wire VAR1 ;
wire VAR3 ;
wire VAR5;
and VAR15 (VAR1 , VAR2, VAR13 );
or VAR16 (VAR3 , VAR1, VAR10 );
VAR14 VAR4 (VAR5, VAR3, VAR12, VAR7);... | apache-2.0 |
FelixWinterstein/LEAP-HLS | filtering_algorithm/wrappers/verilog/bus_bridge.v | 4,670 | module MODULE1
parameter VAR30 = 32,
parameter VAR9 = 32
)
(
input clk,
input VAR21,
output VAR35,
output VAR34,
input VAR38,
input VAR43,
input VAR17,
input [VAR9-1:0] address,
input [31:0] VAR1,
input [VAR30-1:0] VAR22,
output reg [VAR30-1:0] VAR29,
output VAR27,
output [VAR30-1:0] VAR3,
output [VAR9-1:0] VAR7,
input... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b_m.v | 2,297 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR11,
VAR7,
VAR8 ,
VAR9
);
output VAR1 ;
input VAR4 ;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR11;
input VAR7;
input VAR8 ;
input VAR9 ;
VAR5 VAR10 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR... | apache-2.0 |
Sajid3/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/sd_wishbone.v | 5,611 | module MODULE1 (
input wire VAR18,
input wire VAR40,
input wire VAR12,
output reg VAR8,
input wire [31:0] VAR52,
input wire VAR41,
input wire VAR29,
output reg VAR10,
input wire [31:0] VAR6,
output wire VAR21,
output reg [6:0] VAR37,
output reg VAR47,
output reg [31:0] VAR45,
input wire [31:0] VAR1,
output wire VAR4,
o... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_xres4v2/sky130_fd_io__top_xres4v2.pp.blackbox.v | 2,470 | module MODULE1 (
VAR2 ,
VAR20 ,
VAR25 ,
VAR22 ,
VAR11,
VAR23 ,
VAR7 ,
VAR4 ,
VAR17 ,
VAR21 ,
VAR8 ,
VAR3 ,
VAR1 ,
VAR15 ,
VAR9 ,
VAR6 ,
VAR14 ,
VAR12 ,
VAR13 ,
VAR19 ,
VAR5 ,
VAR24 ,
VAR10 ,
VAR18 ,
VAR16
);
output VAR2 ;
inout VAR20 ;
inout VAR25 ;
inout VAR22 ;
input VAR11;
input VAR23 ;
input VAR7 ;
input VAR4 ;
inp... | apache-2.0 |
neale/CS-program | 474-VLSI/Lab_ADC/ADC_CTRL.v | 2,123 | module MODULE1 (
VAR11,
VAR15,
VAR7,
VAR9,
VAR8,
VAR18,
VAR6,
VAR12,
VAR4,
VAR14
);
input VAR11;
input VAR15;
input VAR7;
input VAR9;
input [2:0] VAR8;
output [7:0] VAR18;
output VAR6;
output VAR12;
output VAR4;
input VAR14;
reg VAR2;
reg VAR13;
wire [2:0] VAR16;
reg VAR3;
reg [3:0] VAR17;
reg [3:0] VAR1;
reg [11:0] VA... | unlicense |
LordRafa/Sobel-FPGA | Project_Without_Cache/ip/SIS/Sobel.v | 6,439 | module MODULE1 (
input clk,
input rst,
output [31:0] VAR26,
output VAR4,
input wire [8:0] VAR20,
output wire[31:0] VAR13,
input VAR23,
input VAR25,
output wire[3:0] VAR11,
output wire VAR6,
input wire[31:0] VAR37,
output wire[5:0] VAR22,
input VAR15,
output VAR39,
input [31:0] VAR34
);
parameter VAR17=32;
parameter VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai_4.v | 2,457 | module MODULE2 (
VAR12 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR11 ,
VAR1 ,
VAR9,
VAR6,
VAR8 ,
VAR10
);
output VAR12 ;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR11 ;
input VAR1 ;
input VAR9;
input VAR6;
input VAR8 ;
input VAR10 ;
VAR7 VAR2 (
.VAR12(VAR12),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR9... | apache-2.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_sh.v | 1,136 | module MODULE1 #(parameter VAR1=5, VAR4=32 )
(
input clk,
input [VAR1-1:0] din,
output [VAR1-1:0] VAR5
);
reg [VAR4-1:0] VAR3[VAR1-1:0];
genvar VAR6;
generate
for (VAR6=0; VAR6 < VAR1; VAR6=VAR6+1) begin: VAR2
always @(posedge clk)
VAR3[VAR6] <= {VAR3[VAR6][VAR4-2:0], din[VAR6]};
assign VAR5[VAR6] = VAR3[VAR6][VAR4-1];... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v | 3,665 | module MODULE1 (
input clk,
input VAR5,
input [31:0] VAR24,
input VAR18,
output reg VAR20,
input [23:0] VAR14,
input VAR15,
output reg VAR21,
input [31:0] VAR2,
input VAR17,
output reg VAR13,
input [31:0] VAR6,
input VAR12,
output reg VAR1,
input [31:0] VAR19,
input VAR25,
output reg VAR7,
output VAR16,
output reg [31:... | gpl-3.0 |
rurume/openrisc_vision_hardware | ISE/or1200_wb_biu.v | 14,161 | module MODULE1(
clk, rst, VAR40,
VAR26, VAR12, VAR5, VAR19, VAR32, VAR2,
VAR25, VAR39, VAR1, VAR28, VAR14, VAR10,
VAR38,
VAR11, VAR24,
VAR33, VAR43, VAR9, VAR37, VAR29, VAR21, VAR34,
VAR7, VAR17, VAR20
);
parameter VAR44 = VAR6;
parameter VAR8 = VAR6;
input clk; input rst; input [1:0] VAR40;
input VAR26; input VAR12; i... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/d_r_message_buffer_X.v | 4,924 | module MODULE1
parameter VAR19 = 2,
parameter VAR2 = 8,
parameter VAR5 = 16
)
(
VAR6,
VAR18,
VAR8,
VAR35,
VAR24,
VAR30,
VAR31,
VAR9,
VAR12,
VAR17,
VAR20,
VAR14,
VAR23
);
input VAR6;
input VAR18;
input [VAR19-1:0] VAR8;
input [VAR19-1:0] VAR35;
input [VAR2*VAR19-1:0] VAR24;
input [VAR5-1:0] VAR30;
input VAR31;
input [VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.symbol.v | 1,478 | module MODULE1 (
input VAR7 ,
output VAR4 ,
input VAR6 ,
input VAR1 ,
input VAR5,
input VAR2 ,
input VAR3
);
endmodule | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T17-tones/tones.v | 1,250 | module MODULE1(input wire clk, output wire VAR19, VAR6, VAR13, VAR2);
parameter VAR12 = VAR18;
parameter VAR3 = VAR14;
parameter VAR1 = VAR5;
parameter VAR9 = VAR8;
VAR16 #(VAR12)
VAR4 (
.VAR10(clk),
.VAR11(VAR19)
);
VAR16 #(VAR3)
VAR15 (
.VAR10(clk),
.VAR11(VAR6)
);
VAR16 #(VAR1)
VAR17 (
.VAR10(clk),
.VAR11(VAR13)
);
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2.blackbox.v | 1,323 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR6;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
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