repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_rf32x152b.v | 8,655 | module MODULE2(dout, VAR22, VAR25, VAR27, VAR2, VAR8, din, VAR28, VAR12,
VAR32, VAR42, VAR13, VAR3);
parameter VAR4 = 32;
input [4:0] VAR27;
input VAR25;
input VAR2;
input [4:0] VAR8;
input [151:0] din;
input VAR42;
input VAR3;
input VAR13;
input VAR32;
input VAR28;
input VAR12;
output [151:0] dout;
reg [151:0] dout;
o... | gpl-2.0 |
titorgalaxy/Titor | rtl/verilog/rc/RC.v | 2,844 | module MODULE1(
dout,
din,
address,
VAR4,
VAR9,
enable,
VAR2,
reset,
clk
);
output reg [VAR6-1:0] dout;
input wire [VAR6-1:0] din;
input wire [VAR6-1:0] address;
input wire [VAR11-1:0] VAR4;
input wire VAR9;
input wire enable;
output wire VAR2;
input reset;
input clk;
localparam VAR8 = 1*10**6;
reg [VAR6-1:0] VAR5;
reg... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_hr_to_fr.v | 1,298 | module MODULE1(
clk,
VAR9,
VAR5,
VAR12,
VAR4,
VAR2,
VAR8
);
input clk;
input VAR9;
input VAR5;
input VAR12;
input VAR4;
output VAR2;
output VAR8;
reg VAR7;
reg VAR6;
reg VAR10;
reg VAR1;
reg VAR11;
reg VAR3;
always @(posedge clk)
begin
VAR7 <= VAR9;
VAR10 <= VAR12;
VAR6 <= VAR5;
VAR1 <= VAR4;
end
always @(negedge clk)
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2b/sky130_fd_sc_lp__and2b_2.v | 2,136 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR6 ,
VAR8,
VAR5,
VAR3 ,
VAR9
);
output VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR8;
input VAR5;
input VAR3 ;
input VAR9 ;
VAR1 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR7 ,
VAR4,
VAR6
);
output VAR7 ... | apache-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/c_matrix_arbiter.v | 3,433 | module MODULE1
(clk, reset, VAR10, req, VAR8);
parameter VAR9 = 32;
parameter VAR17 = VAR2;
input clk;
input reset;
input VAR10;
input [0:VAR9-1] req;
output [0:VAR9-1] VAR8;
wire [0:VAR9-1] VAR8;
generate
if(VAR9 > 1)
begin
wire [0:VAR9*VAR9-1] VAR16;
genvar VAR3;
for(VAR3 = 0; VAR3 < VAR9; VAR3 = VAR3 + 1)
begin:VAR1... | mit |
nyaxt/dmix | dmix.v | 4,784 | module MODULE1 #(
parameter VAR60 = 1,
parameter VAR42 = 2,
parameter VAR63 = 1,
parameter VAR16 = 5,
parameter VAR29 = 32
)(
input wire VAR81,
input wire rst,
input wire [0:(VAR60-1)] VAR1,
output wire VAR62,
output wire VAR58,
output wire VAR75,
output wire VAR71,
input wire VAR86,
input wire VAR68,
output wire VAR14... | mit |
myriadrf/A2300 | hdl/wca/WcaDcOffset.v | 2,759 | module MODULE1 (
input VAR4,
input reset,
input VAR1,
input VAR3,
input signed [11:0] VAR5, output signed [11:0] VAR6, output signed [11:0] VAR8 );
reg signed [25:0] VAR2[1:0];
assign VAR6 = VAR2[VAR3][25:14];
assign VAR8 = VAR5 - VAR6;
wire signed [25:0] VAR7 = VAR2[VAR3] + {{(14){VAR8[11]}},VAR8};
always @(negedge VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o.pp.blackbox.v | 1,465 | module MODULE1 (
VAR5 ,
VAR3,
VAR4,
VAR6 ,
VAR1 ,
VAR7,
VAR2,
VAR9 ,
VAR8
);
output VAR5 ;
input VAR3;
input VAR4;
input VAR6 ;
input VAR1 ;
input VAR7;
input VAR2;
input VAR9 ;
input VAR8 ;
endmodule | apache-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/lsu/lsu_op_manager.v | 17,472 | module MODULE1
(
VAR59,
VAR1,
VAR58,
VAR104,
VAR121,
VAR89,
VAR18,
VAR26,
VAR113,
VAR21,
VAR32,
VAR36,
VAR75,
VAR99,
VAR77,
VAR81,
VAR125,
VAR42,
VAR19,
VAR5,
VAR14,
VAR56,
VAR107,
VAR52, VAR123, VAR72,
VAR54,
VAR78,
VAR86,
VAR9,
VAR112,
VAR31, VAR64,
VAR94, VAR110,
VAR76, VAR37,
VAR44,
VAR7,
VAR55,
VAR97,
VAR23,
VAR68... | bsd-3-clause |
walkthetalk/fsref | ip/fscpu/src/include/AM_img.v | 7,054 | module MODULE1 # (
parameter integer VAR18 = 12,
parameter integer VAR20 = 12,
parameter integer VAR7 = 32,
parameter integer VAR26 = 1
) (
input wire clk,
input wire VAR32,
input wire VAR6,
input wire VAR21,
input wire VAR43,
input wire [VAR20-1:0] VAR1,
input wire [VAR20-1:0] VAR39,
input wire VAR36,
input wire VAR15... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh.pp.blackbox.v | 1,452 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR6 ,
VAR4 ,
VAR3,
VAR5 ,
VAR7
);
output VAR2 ;
input VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR3;
input VAR5 ;
input VAR7 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/adc_model.v | 1,819 | module MODULE1
(input clk, input rst,
output [13:0] VAR2,
output VAR14,
input VAR12,
input VAR16,
output [13:0] VAR15,
output VAR10,
input VAR6,
input VAR3
);
VAR4 VAR13 ( ) ;
reg [13:0] VAR1 = 0;
reg [13:0] VAR8 = 0;
assign VAR2 = VAR16 ? VAR1 : 14'VAR11;
assign VAR14 = VAR16 ? 1'b0 : 1'VAR11;
assign VAR15 = VAR3 ? VA... | gpl-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/source/rtl/KOA.v | 7,899 | module MODULE1
(
input wire [VAR16-1:0] VAR25, input wire [VAR16-1:0] VAR20, output wire [2*VAR16-1:0] VAR30 );
wire [VAR16/2+1:0] VAR29;
wire [VAR16/2+1:0] VAR17;
wire [VAR16-1:0] VAR14;
wire [2*(VAR16/2+1)-1:0] VAR23;
wire [2*(VAR16/2+2)-1:0] VAR32;
wire [2*(VAR16/2+2)-1:0] VAR26;
wire [2*(VAR16/2+2)-1:0] VAR13;
wire... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv_1.v | 2,052 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR7,
VAR1,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR7;
input VAR1;
input VAR8 ;
input VAR6 ;
VAR4 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR7;
supply0 VAR1;... | apache-2.0 |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/sdram_control/Sdram_Control.v | 14,514 | module MODULE1(
VAR22,
VAR94,
VAR49,
VAR55,
VAR90,
VAR46,
VAR28,
VAR143,
VAR72,
VAR82,
VAR108,
VAR23,
VAR134,
VAR114,
VAR53,
VAR67,
VAR51,
VAR99,
VAR35,
VAR89,
VAR25,
VAR92,
VAR80,
VAR45,
VAR138,
VAR88,
VAR58,
VAR83,
VAR68,
VAR147,
VAR31,
VAR118,
VAR26,
VAR24,
VAR126,
VAR56,
VAR48,
VAR13,
VAR121,
VAR5,
VAR32,
VAR70,
VA... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_121.v | 1,522 | module MODULE1 (
VAR3,
VAR9
);
input [31:0] VAR3;
output [31:0]
VAR9;
wire [31:0]
VAR4,
VAR1,
VAR13,
VAR7,
VAR5,
VAR12,
VAR6,
VAR10,
VAR8;
assign VAR4 = VAR3;
assign VAR13 = VAR1 - VAR4;
assign VAR1 = VAR4 << 14;
assign VAR8 = VAR5 - VAR10;
assign VAR5 = VAR13 + VAR7;
assign VAR12 = VAR4 << 2;
assign VAR10 = VAR6 << 3;... | mit |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/altera_reset_controller.v | 12,023 | module MODULE1
parameter VAR12 = 6,
parameter VAR36 = 0,
parameter VAR37 = 0,
parameter VAR9 = 0,
parameter VAR70 = 0,
parameter VAR39 = 0,
parameter VAR3 = 0,
parameter VAR7 = 0,
parameter VAR8 = 0,
parameter VAR4 = 0,
parameter VAR76 = 0,
parameter VAR29 = 0,
parameter VAR50 = 0,
parameter VAR16 = 0,
parameter VAR33 ... | gpl-3.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v | 57,385 | module MODULE1 #
(
parameter VAR63 = 100,
parameter VAR222 = "135", parameter VAR220 = 64,
parameter VAR418 = "VAR376",
parameter VAR426 = "0", parameter VAR315 = 3, parameter VAR265 = 2, parameter VAR15 = "8", parameter VAR204 = "VAR243", parameter VAR102 = "VAR279", parameter VAR195 = 1, parameter VAR375 = 5,
paramet... | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_axi_mc_incr_cmd.v | 10,181 | module MODULE1 #
(
parameter integer VAR15 = 32,
parameter integer VAR2 = 30,
parameter integer VAR5 = 1,
parameter integer VAR12 = 32,
parameter integer VAR9 = 2,
parameter integer VAR8 = 0
)
(
input wire clk ,
input wire reset ,
input wire [VAR15-1:0] VAR21 ,
input wire [7:0] VAR13 ,
input wire [2:0] VAR1 ,
input wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3b/sky130_fd_sc_hd__and3b.symbol.v | 1,307 | module MODULE1 (
input VAR6,
input VAR4 ,
input VAR7 ,
output VAR1
);
supply1 VAR5;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
svofski/mahponk | src/deflector.v | 1,113 | module MODULE1(VAR1, VAR3, VAR4, VAR2);
input VAR1;
input [9:0] VAR3;
input [9:0] VAR4;
output reg[9:0] VAR2;
always @(posedge VAR1) begin
VAR2 = VAR3 - VAR4;
if (VAR2[9])
VAR2[8:0] = ~VAR2[8:0] + 1;
end
endmodule | bsd-2-clause |
samyk/proxmark3 | fpga/hi_flite.v | 11,727 | module MODULE1(
VAR28,
VAR2, VAR12, VAR1, VAR25, VAR4, VAR33,
VAR29, VAR8,
VAR18, VAR45, VAR41, VAR40,
VAR14,
VAR36
);
input VAR28;
output VAR2, VAR12, VAR1, VAR25, VAR4, VAR33;
input [7:0] VAR29;
output VAR8;
input VAR41;
output VAR18, VAR45, VAR40;
output VAR14;
input [3:0] VAR36;
assign VAR14 = 0;
wire VAR31 = VAR36... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a.blackbox.v | 1,303 | module MODULE1 (
VAR2 ,
VAR4,
VAR3,
VAR5,
VAR1
);
output VAR2 ;
input VAR4;
input VAR3;
input VAR5;
input VAR1;
supply1 VAR7;
supply0 VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai.symbol.v | 1,338 | module MODULE1 (
input VAR2,
input VAR1,
input VAR6,
input VAR7,
input VAR4,
output VAR3
);
supply1 VAR5;
supply0 VAR8;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_if.v | 6,825 | module MODULE1(
clk, rst,
VAR21, VAR12, VAR17, VAR9, VAR20,
VAR23, VAR11, VAR10, VAR16,
VAR18, VAR13, VAR7, VAR14,
VAR1, VAR2, VAR15
);
input clk;
input rst;
input [31:0] VAR21;
input VAR12;
input VAR17;
input [31:0] VAR9;
input [3:0] VAR20;
input VAR23;
output [31:0] VAR11;
output [31:0] VAR10;
input VAR16;
output VAR... | gpl-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/sequencer_scc_acv_phase_decode.v | 2,503 | module MODULE1
VAR5 = 32,
VAR4 = 8,
VAR6 = "false"
)
(
VAR1,
VAR3
);
input [VAR5 - 1:0] VAR1;
output [3:0] VAR3;
reg [3:0] VAR3;
generate
if (VAR6 == "true")
begin
always @ begin : VAR2
VAR3 = 4'b0110;
case (VAR1[2:0])
3'b000: begin
VAR3 = 4'b0010;
end
3'b001: begin
VAR3 = 4'b0011;
end
3'b010: begin
VAR3 = 4'b0100;
end... | gpl-3.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x8k_dp_synth.v | 4,399 | module MODULE1 (
VAR6,
VAR11,
VAR1,
VAR4,
VAR3,
VAR9,
VAR2,
VAR7,
VAR10,
VAR8,
VAR5,
VAR12
);
input VAR6;
input VAR11;
input [1 : 0] VAR1;
input [12 : 0] VAR4;
input [15 : 0] VAR3;
output [15 : 0] VAR9;
input VAR2;
input VAR7;
input [1 : 0] VAR10;
input [12 : 0] VAR8;
input [15 : 0] VAR5;
output [15 : 0] VAR12;
endmodu... | bsd-3-clause |
combinatorylogic/soc | backends/tiny1/hw/ice/initram.v | 4,483 | module MODULE2(input clk,
input [11:0] addr,
input [15:0] VAR9,
output [15:0] VAR5,
input VAR10,
input VAR12);
wire [15:0] VAR3;
wire [15:0] VAR17;
wire VAR7;
wire VAR15;
wire VAR4;
wire VAR1;
VAR13 MODULE2(.clk(clk),
.addr(addr[10:0]),
.VAR9(VAR9),
.VAR5(VAR3),
.VAR10(VAR7),
.VAR12(VAR15));
VAR11 MODULE1(.clk(clk),
.a... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp.pp.symbol.v | 1,587 | module MODULE1 (
input VAR12 ,
output VAR2 ,
output VAR11 ,
input VAR8,
input VAR10 ,
input VAR4 ,
input VAR9 ,
input VAR3 ,
input VAR7 ,
input VAR1 ,
input VAR6 ,
input VAR5
);
endmodule | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_jtag_uart.v | 16,904 | module MODULE2 (
clk,
VAR18,
VAR20,
VAR52,
VAR44,
VAR4,
VAR22
)
;
output VAR52;
output [ 7: 0] VAR44;
output VAR4;
output [ 5: 0] VAR22;
input clk;
input [ 7: 0] VAR18;
input VAR20;
wire VAR52;
wire [ 7: 0] VAR44;
wire VAR4;
wire [ 5: 0] VAR22;
always @(posedge clk)
begin
if (VAR20)
("%VAR41", VAR18);
end
assign VAR22 ... | gpl-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build1/alu_my.v | 331,118 | module MODULE1 (VAR7,VAR3,VAR5,VAR2,VAR8,VAR1,VAR4);
output [0:127] VAR1;
input [0:127] VAR7;
input [0:127] VAR3;
input [0:2] VAR5;
input [0:1] VAR2;
input [0:4] VAR8;
input [15:0] VAR4;
parameter VAR6 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR1;
always @(VAR7 or VAR3 or VAR5 or VAR2 or VAR8 or VAR4)
begi... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.behavioral.pp.v | 1,254 | module MODULE1( VAR1, VAR3, VAR6, VAR8, VAR7 );
input VAR6, VAR3;
inout VAR8, VAR7;
output VAR1;
VAR2 VAR4(.VAR1(VAR1),.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8),.VAR7(VAR7));
VAR2 VAR5(.VAR1(VAR1),.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o.symbol.v | 1,387 | module MODULE1 (
input VAR1,
input VAR6,
input VAR5,
input VAR8,
input VAR3,
output VAR4
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/alt_mem_ddrx_odt_gen.v | 14,233 | module MODULE1
VAR35 = 2,
VAR16 = 1,
VAR37 = 2, VAR33 = 2,
VAR8 = 1,
VAR31 = 4,
VAR7 = 4,
VAR38 = 3,
VAR12 = 3,
VAR41 = 4,
VAR4 = 4
)
(
VAR43,
VAR18,
VAR32,
VAR20,
VAR46,
VAR29,
VAR22,
VAR9,
VAR44,
VAR11,
VAR23,
VAR17,
VAR13,
VAR14,
VAR10
);
input VAR43;
input VAR18;
input [VAR12 -1:0] VAR32;
input [VAR7 -1:0] VAR20;
i... | gpl-2.0 |
hydai/Verilog-Practice | DigitalDesign/101062124_hw4/fifo_64x16.v | 2,702 | module MODULE1 (
input clk,
input VAR23,
input VAR22,
input VAR1,
input [15:0] VAR29,
output VAR27,
output VAR28,
output VAR13,
output VAR33,
output VAR37,
output reg [15:0] VAR14
);
wire [5:0] addr;
wire VAR18;
wire VAR6;
wire VAR17;
wire [15:0] VAR10;
wire [7:0] VAR26, VAR3, VAR12, VAR34;
reg [7:0] VAR31, VAR5, VAR35... | mit |
DSDL2016/project2 | source/project2_top.v | 6,283 | module MODULE1 (
input VAR94,
input VAR90,
input VAR36,
output VAR81,
input VAR11,
output VAR71,
input VAR101,
output VAR102,
inout VAR32, output VAR63,
inout VAR98, inout VAR57, input VAR3, output VAR49, inout VAR22, output VAR40,
output VAR55,
input VAR45,
output VAR59,
input VAR68,
output VAR12,
input VAR83,
output ... | mit |
hoglet67/CoPro6502 | src/wb/arm2/wb_tube.v | 4,346 | module MODULE1 #(
parameter VAR8 = 0 ) (
input clk,
input reset,
input VAR21,
input VAR12,
output reg VAR16,
input VAR15,
input [2:0] VAR13,
input [3:0] VAR3,
input [31:0] VAR19,
output reg [31:0] VAR18,
output reg [2:0] VAR4,
inout [7:0] VAR20,
output reg VAR23, output reg VAR9, output reg VAR22 );
wire VAR2 = VAR21 &... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221a/sky130_fd_sc_hs__o221a.pp.symbol.v | 1,368 | module MODULE1 (
input VAR4 ,
input VAR8 ,
input VAR6 ,
input VAR2 ,
input VAR1 ,
output VAR7 ,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
Jam-G/MIPS | ID_EX.v | 2,700 | module MODULE1(
input VAR18,
input VAR29,
input VAR10,
input [31:0]VAR47,
input [5:0]VAR16,
input [2:0]VAR13,
input VAR22,
input VAR42,
input VAR11,
input VAR8,
input VAR9,
input [1:0] VAR32,
input VAR33,
input VAR2,
input [3:0]VAR46,
input [1:0]VAR37,
input VAR41,
input [1:0]VAR28,
input [31:0]VAR25,
input [31:0]VAR39... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_sn/sky130_fd_sc_hs__udp_dff_pr_pp_sn.blackbox.v | 1,394 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR5
);
output VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR5;
endmodule | apache-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | src/dragster_spi_adapter.v | 4,341 | module MODULE1 #
(
VAR7 = 3,
VAR1 = 128,
VAR12 = 16
)
(
input wire clk,
input wire reset,
input wire VAR2,
output wire VAR4,
input wire VAR22,
input wire[1:0] VAR6,
output reg VAR14,
input wire VAR9,
output wire VAR11,
output reg[1:0] VAR20
);
reg[VAR12 - 1 : 0] VAR17[VAR1 - 1 : 0];
reg[1:0] VAR5[VAR1 - 1 : 0];
reg[3:0... | gpl-2.0 |
Kumikomi/openreroc_pwm | hardware/src/motor_ctl.v | 2,823 | module MODULE1(
input clk,
input VAR30,
input [31:0] VAR28,
input [0:0] VAR5,
input [0:0] VAR12,
output [31:0] VAR17,
output [0:0] VAR6,
output [0:0] VAR39,
output VAR3,
output VAR4,
output VAR9,
output VAR25
);
parameter VAR21 = 0,
VAR7 = 1,
VAR1 = 2,
VAR14 = 3,
VAR11 = 4,
VAR41 = 5;
wire [31:0] VAR13;
wire VAR2;
wire... | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPCG_Toggle_BNC_P_read_DT00h.v | 10,236 | module MODULE1
(
parameter VAR51 = 4
)
(
VAR11 ,
VAR21 ,
VAR50 ,
VAR52 ,
VAR23 ,
VAR16 ,
VAR27 ,
VAR39 ,
VAR20 ,
VAR25 ,
VAR44 ,
VAR33 ,
VAR22 ,
VAR30 ,
VAR24 ,
VAR6 ,
VAR4 ,
VAR40 ,
VAR26 ,
VAR28 ,
VAR32 ,
VAR17 ,
VAR34 ,
VAR13 ,
VAR36 ,
VAR1 ,
VAR41 ,
VAR35 ,
VAR31
);
input VAR11 ;
input VAR21 ;
input [5:0] VAR50 ;
i... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.v | 2,086 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR2,
VAR7,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR3 ;
input VAR2;
input VAR7;
input VAR6 ;
input VAR1 ;
VAR8 VAR4 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR2;
supply0 VAR7;... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/impl/verilog/FIFO_image_filter_img_1_data_stream_0_V.v | 3,017 | module MODULE2 (
clk,
VAR4,
VAR16,
VAR15,
VAR2);
parameter VAR10 = 32'd8;
parameter VAR14 = 32'd1;
parameter VAR3 = 32'd2;
input clk;
input [VAR10-1:0] VAR4;
input VAR16;
input [VAR14-1:0] VAR15;
output [VAR10-1:0] VAR2;
reg[VAR10-1:0] VAR26 [0:VAR3-1];
integer VAR24;
always @ (posedge clk)
begin
if (VAR16)
begin
for (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a.functional.pp.v | 2,188 | module MODULE1 (
VAR19 ,
VAR14 ,
VAR16 ,
VAR13 ,
VAR20 ,
VAR7 ,
VAR11,
VAR1,
VAR3 ,
VAR4
);
output VAR19 ;
input VAR14 ;
input VAR16 ;
input VAR13 ;
input VAR20 ;
input VAR7 ;
input VAR11;
input VAR1;
input VAR3 ;
input VAR4 ;
wire VAR12 ;
wire VAR10 ;
wire VAR6 ;
wire VAR15;
or VAR5 (VAR12 , VAR16, VAR14, VAR13 );
or ... | apache-2.0 |
dagrende/quad_stepper | qsfpga/qsfpga.v | 1,072 | module MODULE1(VAR8, VAR12, VAR20, VAR11, VAR15, VAR24, VAR9, VAR7);
parameter VAR14 = 32;
input VAR8, VAR12;
output VAR11;
input VAR20, VAR15, VAR24;
output VAR9, VAR7;
wire clk;
VAR4 #(
.VAR2("53.2")
) VAR16 (
.VAR17(1'b0),
.VAR10(clk)
);
reg [VAR14 - 1: 0] VAR22;
reg VAR9;
wire [VAR14 * 2 - 1: 0] VAR13;
wire [VAR14 ... | apache-2.0 |
jotego/jt51 | ver/common/sep32_cnt.v | 1,039 | module MODULE1(
input clk,
input VAR3,
input VAR2,
output reg [4:0] VAR4
);
reg VAR1;
always @(posedge clk) if(VAR3) begin : VAR5
VAR1 <= VAR2;
VAR4 <= (VAR2&&!VAR1) ? 5'd1 : VAR4 + 5'b1;
end
endmodule MODULE1 | gpl-3.0 |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_fmt.v | 9,780 | module MODULE1
(
input VAR7,
input [5:0] VAR5,
output reg [2:0] VAR26, output reg [4:0] VAR20, output VAR1
);
parameter VAR18 = 3'h0,
VAR22 = 3'h1,
VAR8 = 3'h2,
VAR15 = 3'h3,
VAR9 = 3'h4,
VAR11 = 3'h5,
VAR13 = 5'd0,
VAR19 = 5'd1,
VAR12 = 5'd2,
VAR28 = 5'd3,
VAR16 = 5'd4,
VAR25 = 5'd5,
VAR14 = 5'd6,
VAR2 = 5'd7,
VAR10 =... | gpl-3.0 |
xuwenyihust/MapReduce_NoC | RTL/mapper_router.v | 4,620 | module MODULE1(clk, rst, VAR5, VAR17, VAR40, VAR11, VAR4, VAR52, VAR59,
VAR39, VAR57, VAR27, VAR44, VAR34,
VAR19, VAR7, VAR55, VAR33,
VAR65, VAR18, VAR45, VAR28,
VAR42, VAR62, VAR2, VAR24,
VAR36, VAR8);
parameter VAR10=36;
parameter VAR64=8;
parameter VAR46=4;
parameter VAR61=5;
parameter VAR38=5;
input clk;
input rst;... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v | 6,167 | module MODULE1 #(
parameter VAR4 = 34,
parameter VAR20 = 0,
parameter VAR24 = 34,
parameter VAR25 = 0,
parameter VAR17 = 0,
parameter VAR14 = 0,
parameter VAR6 = 1,
parameter VAR22 = 1,
parameter VAR7 = 0,
parameter VAR18 = 34,
parameter VAR12 = 0,
parameter VAR2 = 1,
parameter VAR11 = 0,
parameter VAR16 = 1,
parameter... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1.pp.blackbox.v | 1,347 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR4 ,
VAR5,
VAR1,
VAR7 ,
VAR3
);
output VAR6 ;
input [7:0] VAR2 ;
input [7:0] VAR4 ;
input VAR5;
input VAR1;
input VAR7 ;
input VAR3 ;
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | example/C10LP/fpga/rtl/fpga.v | 5,557 | module MODULE1 (
input wire VAR8,
input wire VAR83,
input wire [3:0] VAR54,
input wire [2:0] VAR129,
output wire [3:0] VAR87,
input wire VAR15,
input wire [3:0] VAR74,
input wire VAR98,
output wire VAR48,
output wire [3:0] VAR56,
output wire VAR70,
output wire VAR7,
input wire VAR124
);
wire VAR103;
wire VAR67;
wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3b/sky130_fd_sc_hs__and3b_1.v | 2,091 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR7 ,
VAR8 ,
VAR4,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR4;
input VAR2;
VAR5 VAR6 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR1 ,
VAR3,
VAR7 ,
VAR8
);
output VAR1 ;
input VAR3;
input VAR7 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl.functional.v | 1,278 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
buf VAR1 (VAR2 , VAR3 );
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/syn/src/decoder.v | 21,721 | module MODULE3 (VAR17, VAR59, VAR33, VAR3, VAR70, VAR99);
output [3:0] VAR17;
output VAR59;
input [3:0] VAR33;
input [1:0] VAR3;
input [3:0] VAR70;
input [1:0] VAR99;
reg [3:0] VAR17;
reg VAR59;
reg [3:0] VAR141;
reg [3:0] VAR126;
reg [4:0] VAR52;
reg [4:0] VAR62;
parameter VAR84 = 4'd15;
always @ (VAR33 or VAR3)
begin... | mit |
saisrivathsa/Image-Watermarking | ipcore_dir/Cmul.v | 3,680 | module MODULE1 (
VAR19, VAR38
);
output [7 : 0] VAR19;
input [7 : 0] VAR38;
wire [7 : 2] VAR31;
wire [6 : 6] VAR3;
assign
VAR19[7] = VAR3[6],
VAR19[6] = VAR3[6],
VAR19[5] = VAR31[7],
VAR19[4] = VAR31[6],
VAR19[3] = VAR31[5],
VAR19[2] = VAR31[4],
VAR19[1] = VAR31[3],
VAR19[0] = VAR31[2],
VAR31[7] = VAR38[7],
VAR31[6] = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1.pp.blackbox.v | 1,291 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR2;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv.functional.pp.v | 1,748 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR1,
VAR12,
VAR2 ,
VAR11
);
output VAR7 ;
input VAR10 ;
input VAR1;
input VAR12;
input VAR2 ;
input VAR11 ;
wire VAR4 ;
wire VAR9;
not VAR6 (VAR4 , VAR10 );
VAR3 VAR8 (VAR9, VAR4, VAR1, VAR12);
buf VAR5 (VAR7 , VAR9 );
endmodule | apache-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/altera_up_audio_in_deserializer.v | 7,476 | module MODULE1 (
clk,
reset,
VAR11,
VAR33,
VAR37,
VAR30,
VAR13,
VAR23,
VAR29,
VAR9,
VAR26,
VAR3,
VAR15,
VAR1
);
parameter VAR4 = 15;
parameter VAR28 = 5'h0F;
input clk;
input reset;
input VAR11;
input VAR33;
input VAR37;
input VAR30;
input VAR13;
input VAR23;
input VAR29;
input VAR9;
output reg [ 7: 0] VAR26;
output re... | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/ipcore_dir/ddr_stream_fifo.v | 14,032 | module MODULE1(
VAR421,
VAR404,
VAR314,
VAR185,
VAR359,
VAR370,
VAR119,
VAR285,
VAR89,
VAR283,
VAR316
);
input VAR421;
input VAR404;
input VAR314;
input VAR185;
output VAR359;
input [63 : 0] VAR370;
output VAR119;
input VAR285;
output [63 : 0] VAR89;
output [9 : 0] VAR283;
output [9 : 0] VAR316;
VAR295 #(
.VAR140(0),
.... | mit |
rurume/openrisc_vision_hardware | ISE/or1200_ic_tag.v | 5,533 | module MODULE1(
clk, rst,
VAR5, VAR10, VAR17,
addr, en, VAR14, VAR1, VAR8, VAR16
);
parameter VAR2 = VAR6;
parameter VAR7 = VAR4;
input clk;
input rst;
input VAR5;
input [VAR3 - 1:0] VAR17;
output VAR10;
input [VAR7-1:0] addr;
input en;
input VAR14;
input [VAR2-1:0] VAR1;
output VAR8;
output [VAR2-2:0] VAR16;
assign VA... | gpl-2.0 |
sarchar/vga_de0_nano | framebuffer.v | 1,389 | module MODULE1
(input VAR2,
input VAR10,
input VAR4,
input VAR1,
input VAR7,
output reg [7:0] VAR8,
output reg [7:0] VAR9,
output reg [7:0] VAR3
);
reg VAR5;
reg [7:0] VAR6;
always @(posedge VAR10 or negedge VAR2 or posedge VAR7) begin
if(~VAR2 || VAR7) begin
VAR8 <= 8'b00000000;
VAR9 <= 8'b00000000;
VAR3 <= 8'b0000000... | mit |
chiggs/oc_mkjpeg | design/mdct/FinitePrecRndNrst.v | 2,984 | module MODULE1
parameter VAR17=37,
VAR13=16,
VAR3=15
)
( input wire VAR12,
input wire VAR7,
input wire signed [VAR17-1:0] VAR10,
input wire VAR8,
output wire signed [VAR13-1:0] VAR14,
output reg VAR4,
output reg VAR5
);
wire VAR2;
wire signed [VAR17-1:0] VAR16;
reg signed [VAR17-1:0] VAR15;
wire signed [VAR17-VAR3-1:0]... | lgpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/image_filter_top.v | 6,255 | module MODULE1 (
VAR78,
VAR17,
VAR50,
VAR28,
VAR60,
VAR25,
VAR67,
VAR4,
VAR21,
VAR59,
VAR31,
VAR27,
VAR85,
VAR64,
VAR84,
VAR15,
VAR35,
interrupt,
VAR71,
VAR57,
VAR13,
VAR1,
VAR32,
VAR40,
VAR14,
VAR20,
VAR26,
VAR33,
VAR36,
VAR5,
VAR83,
VAR12,
VAR19,
VAR11,
VAR52,
VAR22,
VAR47,
VAR70
);
parameter VAR24 = 5;
parameter VAR... | gpl-3.0 |
vvk/sysrek | processor/i_mem.v | 1,163 | module MODULE1
(
input [7:0]address,
output [31:0]VAR1
);
wire [31:0]program[255:0];
assign program[0]=32'h0036e000; assign program[1]=32'h0036e104; assign program[2]=32'h0010e001; assign program[3]=32'h00001200; assign program[4]=32'h0332e702; assign program[5]=32'h0036e301;
assign VAR1=program[address];
endmodule
---... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_ps_pp_pg/sky130_fd_sc_hs__udp_dff_ps_pp_pg.blackbox.v | 1,346 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR2 ,
VAR6 ,
VAR5,
VAR4
);
output VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR5;
input VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai.functional.pp.v | 1,960 | module MODULE1 (
VAR13,
VAR2,
VAR7 ,
VAR4 ,
VAR16 ,
VAR11 ,
VAR8 ,
VAR15
);
input VAR13;
input VAR2;
output VAR7 ;
input VAR4 ;
input VAR16 ;
input VAR11 ;
input VAR8 ;
input VAR15 ;
wire VAR8 VAR1 ;
wire VAR10 ;
wire VAR6;
or VAR3 (VAR1 , VAR8, VAR11, VAR16, VAR4 );
nand VAR14 (VAR10 , VAR15, VAR1 );
VAR9 VAR5 (VAR6, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3/sky130_fd_sc_hd__nor3.functional.pp.v | 1,844 | module MODULE1 (
VAR10 ,
VAR13 ,
VAR7 ,
VAR12 ,
VAR4,
VAR9,
VAR3 ,
VAR11
);
output VAR10 ;
input VAR13 ;
input VAR7 ;
input VAR12 ;
input VAR4;
input VAR9;
input VAR3 ;
input VAR11 ;
wire VAR6 ;
wire VAR5;
nor VAR2 (VAR6 , VAR12, VAR13, VAR7 );
VAR1 VAR14 (VAR5, VAR6, VAR4, VAR9);
buf VAR8 (VAR10 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1.functional.v | 1,344 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
wire VAR3;
not VAR1 (VAR3, VAR2 );
buf VAR4 (VAR5 , VAR3 );
endmodule | apache-2.0 |
AbhishekShah212/School_Projects | ELEN232/pset4/Problem4Part.v | 1,145 | module MODULE1(
input VAR5,
input VAR3,
input VAR6,
input VAR8,
input VAR2,
output reg VAR7,
output reg VAR4,
output reg VAR1
);
always @ (VAR5 or VAR3 or VAR6 or VAR8 or VAR2) begin
if ( VAR5 > VAR3 )
begin
VAR7 = 1;
VAR4 = 0;
VAR1 = 0;
end
else if ( VAR5 < VAR3 ) begin
VAR4 = 1;
VAR7 = 0;
VAR1 = 0;
end
else begin
VAR... | mit |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/Exponential/FSM_C_CORDIC.v | 16,997 | module MODULE1(
input wire VAR21, input wire VAR30, input wire VAR16, input wire VAR52, input wire VAR51, input wire VAR7, input wire VAR18, input wire [4:0] VAR14,
output reg VAR15, output reg VAR23, output reg [1:0] VAR50, output reg VAR2, output reg VAR8, output reg VAR28, output reg VAR45, output reg VAR46, output ... | gpl-3.0 |
alexforencich/verilog-ethernet | example/NetFPGA_SUME/fpga/rtl/si5324_i2c_init.v | 17,538 | module MODULE1 (
input wire clk,
input wire rst,
output wire [6:0] VAR16,
output wire VAR15,
output wire VAR6,
output wire VAR10,
output wire VAR2,
output wire VAR9,
output wire VAR4,
input wire VAR11,
output wire [7:0] VAR13,
output wire VAR1,
input wire VAR14,
output wire VAR3,
output wire VAR7,
input wire VAR5
);
lo... | mit |
ShepardSiegel/ocpi | scripts/altera/altplay2_htgs4/mkFTop_htgs4.v | 6,342 | module MODULE1(VAR43,
VAR28,
VAR53,
VAR29,
VAR10,
VAR50,
VAR40,
VAR42,
VAR13,
VAR14,
VAR20);
input VAR43;
input VAR28;
input VAR53;
input VAR29;
input [3 : 0] VAR10;
output [3 : 0] VAR50;
input [7 : 0] VAR40;
output [7 : 0] VAR42;
output VAR13;
output VAR14;
output VAR20;
wire [7 : 0] VAR42;
wire [3 : 0] VAR50;
wire VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv.pp.symbol.v | 1,242 | module MODULE1 (
input VAR5 ,
output VAR4 ,
input VAR3 ,
input VAR6,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_except.v | 22,447 | module MODULE1(
clk, rst,
VAR30, VAR15, VAR24, VAR36, VAR6, VAR21, VAR50,
VAR31, VAR8, VAR63, VAR28, VAR48, VAR61,
VAR18, VAR11, VAR29, VAR22, VAR16, VAR112,
VAR46, VAR72, VAR47, VAR76, VAR77, VAR65, VAR39,
VAR85, VAR92, VAR10,
VAR98, VAR32, VAR75, VAR83, VAR87, VAR23, VAR64, VAR52, VAR94, VAR54,
VAR56, VAR86, VAR59, V... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/tx_sync_gtp.v | 6,607 | module MODULE1
(
output VAR7,
output VAR14,
output VAR6,
input VAR11,
input VAR2
);
reg VAR13;
reg VAR8;
reg VAR3;
reg [14:0] VAR9;
reg [9:0] VAR4;
reg VAR12;
wire VAR10;
wire VAR15;
wire VAR1;
wire VAR16;
wire VAR5;
always @(posedge VAR11)
if(VAR2)
{VAR13,VAR12,VAR8,VAR3} <= VAR17 4'b1000;
else
begin
VAR13 <= VAR17 1'... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_qpll_reset.v | 13,343 | module MODULE1 #
(
parameter VAR32 = "VAR36", parameter VAR31 = "VAR17", parameter VAR26 = 1, parameter VAR23 = 1
)
(
input VAR8,
input VAR18,
input VAR19,
input [VAR26-1:0] VAR6,
input [(VAR26-1)>>2:0]VAR40,
input [(VAR26-1)>>2:0]VAR46,
input [ 1:0] VAR45,
input [VAR26-1:0] VAR41,
input [VAR26-1:0] VAR21,
output VAR30... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9643/axi_ad9643_if.v | 8,331 | module MODULE1 (
VAR24,
VAR41,
VAR3,
VAR55,
VAR44,
VAR2,
VAR43,
VAR39,
VAR15,
VAR36,
VAR45,
VAR10,
VAR35,
VAR53,
VAR16,
VAR34,
VAR25,
VAR51,
VAR38,
VAR42,
VAR32);
parameter VAR46 = 0;
parameter VAR18 = "VAR23";
input VAR24;
input VAR41;
input [13:0] VAR3;
input [13:0] VAR55;
input VAR44;
input VAR2;
output VAR43;
outpu... | gpl-3.0 |
alexforencich/verilog-axis | rtl/axis_mux.v | 9,630 | module MODULE1 #
(
parameter VAR65 = 4,
parameter VAR3 = 8,
parameter VAR13 = (VAR3>8),
parameter VAR56 = ((VAR3+7)/8),
parameter VAR31 = 0,
parameter VAR21 = 8,
parameter VAR25 = 0,
parameter VAR40 = 8,
parameter VAR44 = 1,
parameter VAR20 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR65*VAR3-1:0] VAR14,
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxbp/sky130_fd_sc_hs__edfxbp_1.v | 2,248 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR4 ,
VAR7 ,
VAR6 ,
VAR3,
VAR5
);
output VAR9 ;
output VAR1 ;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR3;
input VAR5;
VAR8 VAR2 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR9 ,
VAR1,
VAR4,
VAR7 ,
VAR6
... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/AXI4CommandDivider.v | 6,599 | module MODULE1
(
parameter VAR20 = 32 ,
parameter VAR10 = 32 ,
parameter VAR23 = 16 ,
parameter VAR26 = 16
)
(
VAR17 ,
VAR22 ,
VAR19 ,
VAR2 ,
VAR6 ,
VAR9 ,
VAR27,
VAR28 ,
VAR11 ,
VAR5 ,
VAR1 ,
VAR21
);
input VAR17 ;
input VAR22 ;
input [VAR20 - 1:0] VAR19 ;
input [VAR23 - 1:0] VAR2 ;
input VAR6 ;
output VAR9 ;
input VA... | gpl-3.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/altera_reset_controller.v | 12,017 | module MODULE1
parameter VAR52 = 6,
parameter VAR38 = 0,
parameter VAR54 = 0,
parameter VAR33 = 0,
parameter VAR16 = 0,
parameter VAR57 = 0,
parameter VAR11 = 0,
parameter VAR5 = 0,
parameter VAR69 = 0,
parameter VAR4 = 0,
parameter VAR3 = 0,
parameter VAR71 = 0,
parameter VAR39 = 0,
parameter VAR78 = 0,
parameter VAR3... | gpl-2.0 |
Murailab-arch/magukara | cores/rgmii2gmii/rtl/rgmii_io.v | 10,625 | module MODULE1
(
output [3:0] VAR101,
output VAR69,
input VAR82,
input VAR81,
input [3:0] VAR2,
input VAR136,
input VAR74,
input [7:0] VAR48, input VAR94,
input VAR13,
output [7:0] VAR84,
output VAR34,
output VAR86,
output VAR11,
output [1:0] VAR125,
output VAR127,
input reset
);
VAR73 VAR19 (
.VAR116(VAR119),
.VAR128 ... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_async/bsg_async_ptr_gray.v | 5,295 | module MODULE1 #(parameter VAR19(VAR4 )
,parameter VAR15=0
,parameter VAR21 = 0)
(
input VAR24
, input VAR17
, input VAR28 , input VAR7
, output [VAR4-1:0] VAR11 , output [VAR4-1:0] VAR20 , output [VAR4-1:0] VAR32 );
logic [VAR4-1:0] VAR30, VAR18;
logic [VAR4-1:0] VAR29, VAR25, VAR8;
logic [VAR4-1:0] VAR10, VAR22, VAR1... | bsd-3-clause |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_util_vector_logic_0_0/RAT_util_vector_logic_0_0_stub.v | 1,304 | module MODULE1(VAR3, VAR2, VAR1)
;
input [0:0]VAR3;
input [0:0]VAR2;
output [0:0]VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr.symbol.v | 1,311 | module MODULE1 (
input VAR6,
output VAR5
);
supply1 VAR1 ;
supply0 VAR3 ;
supply1 VAR7;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Elphel/x353 | memctrl353/descrproc353.v | 30,498 | module MODULE1 (clk, VAR14, VAR55, VAR37, VAR130, VAR52, VAR45, VAR2, VAR144, VAR27, VAR122, VAR83, VAR111, VAR11, VAR46, VAR19, VAR121, VAR40, VAR108, VAR58, VAR125, VAR54, VAR78, VAR9, VAR116, VAR95, VAR113, VAR131, VAR93 ); input clk; input [ 3:0] VAR14;
input [ 3:0] VAR55;
input [ 3:0] VAR37;
input VAR130;
input [1... | gpl-3.0 |
hoangt/NOCulator | hring/hw/buffered/src/c_port_filter.v | 6,427 | module MODULE1
(VAR17, VAR19, VAR22, VAR2);
parameter VAR10 = 2;
parameter VAR15 = 2;
parameter VAR24 = 5;
parameter VAR11 = 2;
parameter VAR26 = 4;
parameter VAR1 = 1;
parameter VAR14 = VAR21;
parameter VAR12 = VAR8;
parameter VAR3 = VAR20;
parameter VAR23 = 0;
parameter VAR25 = 0;
parameter VAR4 = 0;
input [0:VAR24-1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o.pp.blackbox.v | 1,421 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR2 ,
VAR9 ,
VAR3,
VAR7,
VAR10 ,
VAR8
);
output VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR9 ;
input VAR3;
input VAR7;
input VAR10 ;
input VAR8 ;
endmodule | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/TECH/altera/CLK_DIV2.v | 3,598 | module MODULE1 (
input VAR2,
input VAR3,
output reg VAR1
);
always @ (posedge VAR3 or posedge VAR2)
if (VAR2)
VAR1 <=0;
else
VAR1 <=!VAR1;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_2.behavioral.pp.v | 2,214 | module MODULE1( VAR12, VAR5, VAR3, VAR7, VAR9 );
input VAR12, VAR5;
inout VAR7, VAR9;
output VAR3;
reg VAR6;
VAR4 VAR1(.VAR12(VAR12),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7),.VAR9(VAR9),.VAR6(VAR6));
VAR4 VAR8(.VAR12(VAR12),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7),.VAR9(VAR9),.VAR6(VAR6));
not VAR13(VAR10,VAR5);
buf VAR2(VAR11,V... | apache-2.0 |
ShepardSiegel/ocpi | vhdl/biasWorker.v | 6,339 | module MODULE1 (
input clk,
input VAR33,
input [2:0] VAR26,
input [0:0] VAR1,
input [3:0] VAR19,
input [19:0] VAR25,
input [31:0] VAR31,
output reg [1:0] VAR4,
output reg [31:0] VAR30,
input [1:0] VAR23,
output reg [1:0] VAR15,
output reg VAR35,
input [2:0] VAR36,
input VAR29,
input VAR32,
input [11:0] VAR9,
input [31:... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111oi/sky130_fd_sc_hd__a2111oi.symbol.v | 1,401 | module MODULE1 (
input VAR9,
input VAR1,
input VAR8,
input VAR5,
input VAR10,
output VAR2
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ebufn/sky130_fd_sc_hs__ebufn.pp.symbol.v | 1,294 | module MODULE1 (
input VAR4 ,
output VAR1 ,
input VAR5,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
bgelb/digilite_zl | rtl/zl_reset_sync.v | 1,212 | module MODULE1
(
input clk,
input VAR3,
output VAR1
);
reg [1:0] VAR2;
always @(posedge clk or negedge VAR3) begin
if(!VAR3) begin
VAR2[1] <= 1'b0;
VAR2[0] <= 1'b0;
end
else begin
VAR2[1] <= 1'b1;
VAR2[0] <= VAR2[1];
end
end
assign VAR1 = VAR2[0];
endmodule | bsd-2-clause |
Elphel/x353 | extras/10364.v | 36,765 | module MODULE3 ( clk, VAR67, VAR50, VAR95, VAR116, do, VAR49, VAR78, VAR34, VAR107, VAR48, VAR69 );
parameter VAR23=24;
input clk; input VAR67; input VAR50; input VAR95; input [15:0] VAR116; output [31:0] do; input [1:0] VAR49; input [1:0] VAR78; input [1:0] VAR34; output [1:0] VAR107; output [1:0] VAR48; output [1:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_xres4v2/sky130_fd_io__top_xres4v2.functional.pp.v | 7,666 | module MODULE1 ( VAR33, VAR30, VAR35, VAR6,
VAR41, VAR2, VAR3, VAR22, VAR12, VAR38, VAR29, VAR17,
VAR32, VAR24, VAR27
,VAR13, VAR16, VAR28, VAR18,VAR44, VAR31, VAR37, VAR20, VAR36, VAR5
);
output VAR30;
inout VAR41;
inout VAR2;
inout VAR3;
input VAR32;
input VAR12;
input VAR38;
input VAR29;
input VAR17;
inout VAR24;
in... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr.functional.pp.v | 1,940 | module MODULE1 (
VAR13 ,
VAR7 ,
VAR8 ,
VAR10 ,
VAR11,
VAR4 ,
VAR6
);
output VAR13 ;
input VAR7 ;
input VAR8 ;
input VAR10 ;
input VAR11;
input VAR4 ;
input VAR6 ;
wire VAR12 ;
wire VAR2;
buf VAR5 (VAR12 , VAR7 );
VAR1 VAR9 (VAR2, VAR12, VAR11, VAR10);
buf VAR3 (VAR13 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3/sky130_fd_sc_hs__or3.behavioral.pp.v | 1,699 | module MODULE1 (
VAR8,
VAR6,
VAR10 ,
VAR11 ,
VAR2 ,
VAR4
);
input VAR8;
input VAR6;
output VAR10 ;
input VAR11 ;
input VAR2 ;
input VAR4 ;
wire VAR7 ;
wire VAR1;
or VAR5 (VAR7 , VAR2, VAR11, VAR4 );
VAR9 VAR3 (VAR1, VAR7, VAR8, VAR6);
buf VAR12 (VAR10 , VAR1 );
endmodule | apache-2.0 |
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