repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n.pp.blackbox.v | 1,393 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR7,
VAR5 ,
VAR1 ,
VAR4 ,
VAR3
);
output VAR2 ;
input VAR6 ;
input VAR7;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/new/GPIO_interface_AXI.v | 29,945 | module MODULE1 #
(
parameter VAR100 = 100000, parameter VAR13 = 32, parameter VAR5 = 32, parameter VAR4 = 8, parameter VAR85 = 1, parameter VAR81 = 16, parameter VAR98 = 16, parameter VAR74 = 10 )
(
input VAR117,
input VAR97,
input VAR11,
output VAR80,
input [32-1:0] VAR106,
input [3-1:0] VAR118,
input VAR99,
output VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.symbol.v | 1,438 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR6 ,
input VAR2,
input VAR5 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn.functional.v | 1,224 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR2 ;
input VAR1;
bufif0 VAR3 (VAR4 , VAR2, VAR1 );
endmodule | apache-2.0 |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/Multiplier/multiplier.v | 1,708 | module MODULE1
input wire [VAR1-1:0] VAR2,
input wire [VAR1-1:0] VAR5,
output wire [2*VAR1-1:0] VAR4
);
reg [2*VAR1-1:0] VAR3;
assign VAR4=VAR3;
always@(posedge clk)
begin
VAR3<= VAR2*VAR5;
end
endmodule | gpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_RVT_TT_210930.v | 242,184 | module MODULE1 (VAR8, VAR2, VAR3, VAR5, VAR7, VAR6);
output VAR8;
input VAR2, VAR3, VAR5, VAR7, VAR6;
wire VAR13, VAR1, VAR4;
wire VAR9, VAR12, VAR10;
wire VAR11;
not (VAR12, VAR6);
not (VAR9, VAR7);
not (VAR4, VAR5);
and (VAR10, VAR4, VAR9);
not (VAR1, VAR3);
not (VAR13, VAR2);
and (VAR11, VAR13, VAR1, VAR9);
or (VAR8... | bsd-3-clause |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_dff.v | 2,444 | module MODULE1
(clk, reset, VAR3, VAR2);
parameter VAR5 = 32;
parameter VAR1 = 0;
parameter VAR6 = VAR7;
parameter [VAR1:(VAR1+VAR5)-1] VAR4 = {VAR5{1'b0}};
input clk;
input reset;
input [VAR1:(VAR1+VAR5)-1] VAR3;
output [VAR1:(VAR1+VAR5)-1] VAR2;
reg [VAR1:(VAR1+VAR5)-1] VAR2;
generate
case(VAR6)
always @(posedge clk,... | mit |
alexforencich/hdg2000 | fpga/lib/dsp/rtl/i2s_tx.v | 3,137 | module MODULE1 #
(
parameter VAR5 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR5-1:0] VAR12,
input wire [VAR5-1:0] VAR7,
input wire VAR8,
output wire VAR2,
input wire VAR3,
input wire VAR9,
output wire VAR11
);
reg [VAR5-1:0] VAR17 = 0;
reg [VAR5-1:0] VAR4 = 0;
reg VAR18 = 0;
reg VAR10 = 0;
reg [VAR5-1:0] VA... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_1/hdl/verilog/feedforward_AXILiteS_s_axi.v | 9,418 | module MODULE1
VAR49 = 5,
VAR4 = 32
)(
input wire VAR25,
input wire VAR43,
input wire VAR53,
input wire [VAR49-1:0] VAR17,
input wire VAR51,
output wire VAR37,
input wire [VAR4-1:0] VAR33,
input wire [VAR4/8-1:0] VAR20,
input wire VAR22,
output wire VAR34,
output wire [1:0] VAR18,
output wire VAR46,
input wire VAR27,
i... | gpl-3.0 |
hcabrera-/lancetfish | RTL/processing_element/des_engine/rtl/des_datapath.v | 10,420 | module MODULE1
(
input wire clk,
input wire reset,
input wire enable,
input wire VAR6,
input wire [0:63] VAR8,
input wire [0:47] VAR7,
output wire [0:63] VAR2
);
wire [0:31] VAR11;
wire [0:31] VAR24;
wire [0:63] VAR23;
assign VAR23[0 +: 8] = {
VAR8[57],
VAR8[49],
VAR8[41],
VAR8[33],
VAR8[25],
VAR8[17],
VAR8[9],
VAR8[1]... | gpl-3.0 |
MeshSr/onetswitch20 | ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/ip/txfifo_512x72_to_36.v | 13,774 | module MODULE1(
rst,
VAR411,
VAR347,
din,
VAR231,
VAR137,
dout,
VAR153,
VAR408,
VAR332
);
input rst;
input VAR411;
input VAR347;
input [71 : 0] din;
input VAR231;
input VAR137;
output [35 : 0] dout;
output VAR153;
output VAR408;
output VAR332;
VAR174 #(
.VAR398(0),
.VAR11(0),
.VAR55(0),
.VAR100(0),
.VAR361(0),
.VAR108(... | lgpl-2.1 |
SLongofono/Senior_Design_Capstone | hdl/Ram2Ddr_RefComp/Source/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/ip_top/mig_7series_v1_9_memc_ui_top_std.v | 36,326 | module MODULE1 #
(
parameter VAR165 = 100,
parameter VAR152 = 64,
parameter VAR19 = "VAR154",
parameter VAR184 = "0", parameter VAR244 = 3, parameter VAR220 = 2, parameter VAR16 = "8", parameter VAR51 = "VAR191", parameter VAR126 = "VAR149", parameter VAR272 = 1, parameter VAR151 = 5,
parameter VAR137 = 12, parameter V... | mit |
hoglet67/CoPro6502 | src/zet/zet/zet_core.v | 6,545 | module MODULE1 (
input clk,
input rst,
input VAR36,
output VAR59,
input VAR16,
output VAR40,
output [19:0] VAR49,
input [15:0] VAR8,
input [15:0] VAR56,
output [15:0] VAR82,
output VAR24,
input VAR28,
output VAR37,
output VAR84,
output VAR25,
output [19:0] VAR5 );
wire [VAR26-1:0] VAR21;
wire [15:0] VAR72;
wire [15:0] ... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/BCHSharedKESforTiger4/src/d_parallel_FFM_gate_GF12.v | 6,621 | module MODULE1
(
input wire [11: 0] VAR3, input wire [11: 0] VAR4,
output wire [11: 0] VAR2 );
wire [11: 6] VAR14; wire [ 5: 0] VAR6;
wire [11: 6] VAR13; wire [ 5: 0] VAR7;
wire [16: 6] VAR9; wire [10: 0] VAR16; wire [22:12] VAR5; wire [16: 6] VAR8;
wire [22: 0] VAR12;
assign VAR14[11: 6] = VAR3[11: 6];
assign VAR6[ 5:... | gpl-3.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axis_register_slice_0_0/axis_infrastructure_v1_1/hdl/verilog/axis_infrastructure_v1_1_clock_synchronizer.v | 4,392 | module MODULE1 # (
parameter integer VAR7 = 4
)
(
input wire clk,
input wire VAR1 ,
output wire VAR4
);
localparam integer VAR6 = (VAR7 > 0) ? VAR7 : 1;
reg [VAR6-1:0] VAR2 = 'b0;
generate
if (VAR7 > 0) begin : VAR9
genvar VAR3;
always @(posedge clk) begin
VAR2[0] <= VAR1;
end
for (VAR3 = 1; VAR3 < VAR7 ; VAR3 = VAR3 +... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3_1.v | 2,072 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR8,
VAR6
);
output VAR2 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR8;
input VAR6;
VAR5 VAR4 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR2,
VAR7,
VAR1,
VAR3
);
output VAR2;
input VAR7;
input VAR1;
in... | apache-2.0 |
archlabo/Frix | common/ao486_rst_controller.v | 1,932 | module MODULE1
(
input wire VAR2,
input wire rst,
output reg VAR1,
input wire [1:0] address,
input wire write,
input wire [31:0] VAR3
);
always @(posedge VAR2) begin
if(rst) begin
VAR1 <= 1;
end else begin
if(write && VAR3[0] == 1'b0 && address == 4'b0000)
VAR1 <= 0;
end
else if(write && VAR3[0] == 1'b1 && address == 4... | bsd-2-clause |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/output_queue_reg_master.v | 74,600 | module MODULE1
(
input [31:0] VAR65 ,
input [31:0] VAR24 ,
input VAR32 ,
input VAR58 ,
output reg VAR50 ,
output reg[31:0] VAR11 ,
input clk,
input reset,
output reg[5:0]VAR52,
output reg[5:0]VAR44,
output reg[5:0]VAR4,
output reg[5:0]VAR51,
output reg[5:0]VAR67,
output reg[5:0]VAR9,
input [5:0]VAR40 ,
input [5:0]VAR21... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbn/sky130_fd_sc_lp__dfbbn.pp.blackbox.v | 1,481 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR8 ,
VAR1 ,
VAR7 ,
VAR9,
VAR2 ,
VAR5 ,
VAR3 ,
VAR10
);
output VAR4 ;
output VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR9;
input VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.behavioral.pp.v | 1,796 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR2,
VAR10,
VAR7 ,
VAR1
);
output VAR9 ;
input VAR4 ;
input VAR2;
input VAR10;
input VAR7 ;
input VAR1 ;
wire VAR5 ;
wire VAR12;
not VAR6 (VAR5 , VAR4 );
VAR11 VAR3 (VAR12, VAR5, VAR2, VAR10);
buf VAR8 (VAR9 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2b/sky130_fd_sc_ls__and2b.blackbox.v | 1,270 | module MODULE1 (
VAR4 ,
VAR5,
VAR3
);
output VAR4 ;
input VAR5;
input VAR3 ;
supply1 VAR7;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31oi/sky130_fd_sc_hd__a31oi.behavioral.v | 1,544 | module MODULE1 (
VAR8 ,
VAR7,
VAR12,
VAR4,
VAR3
);
output VAR8 ;
input VAR7;
input VAR12;
input VAR4;
input VAR3;
supply1 VAR10;
supply0 VAR2;
supply1 VAR13 ;
supply0 VAR6 ;
wire VAR5 ;
wire VAR1;
and VAR11 (VAR5 , VAR4, VAR7, VAR12 );
nor VAR9 (VAR1, VAR3, VAR5 );
buf VAR14 (VAR8 , VAR1 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_4.behavioral.pp.v | 1,164 | module MODULE1( VAR2, VAR7, VAR5, VAR6 );
input VAR2;
inout VAR5, VAR6;
output VAR7;
VAR3 VAR4(.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6));
VAR3 VAR1(.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_sctrdq.v | 6,494 | module MODULE1 (
VAR32, VAR11, VAR7, VAR21,
VAR2, VAR51, VAR28, VAR43, VAR23, VAR46, VAR4, VAR42, clk, VAR25,
VAR26, VAR14, VAR12, VAR34
);
input VAR2;
input [9:0] VAR51;
input [31:0] VAR28;
input VAR43;
output VAR32;
input VAR23;
input VAR46;
input VAR4;
input VAR42;
output [127:0] VAR11;
output [9:0] VAR7;
output VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a.functional.pp.v | 1,998 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR12 ,
VAR15 ,
VAR16,
VAR6,
VAR2 ,
VAR1
);
output VAR3 ;
input VAR8 ;
input VAR12 ;
input VAR15 ;
input VAR16;
input VAR6;
input VAR2 ;
input VAR1 ;
wire VAR4 ;
wire VAR11 ;
wire VAR13;
or VAR7 (VAR4 , VAR12, VAR8 );
and VAR9 (VAR11 , VAR4, VAR15 );
VAR10 VAR5 (VAR13, VAR11, VAR16, VAR6)... | apache-2.0 |
eecsninja/duinocube-core | altera/collision_table_256x16.v | 11,410 | module MODULE1 (
VAR20,
VAR8,
VAR60,
VAR30,
VAR7,
VAR23,
VAR40,
VAR22,
VAR39,
VAR59,
VAR47);
input [8:0] VAR20;
input [8:0] VAR8;
input [1:0] VAR60;
input [1:0] VAR30;
input VAR7;
input [15:0] VAR23;
input [15:0] VAR40;
input VAR22;
input VAR39;
output [15:0] VAR59;
output [15:0] VAR47;
tri1 [1:0] VAR60;
tri1 [1:0] VAR... | gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/BeMicro/src/fpgaminer_top.v | 5,034 | module MODULE1 (VAR25);
parameter VAR10 = VAR17;
parameter VAR10 = 0;
localparam [5:0] VAR7 = (6'd1 << VAR10);
localparam [31:0] VAR3 = (32'd1 << (7 - VAR10)) + 32'd1;
input VAR25;
reg [255:0] state = 0;
reg [511:0] VAR21 = 0;
reg [31:0] VAR8 = 32'h00000000;
wire VAR9;
VAR24 VAR41 (VAR25, VAR9);
assign VAR9 = VAR25;
wi... | gpl-3.0 |
sorgelig/ZX_Spectrum-128K_MIST | divmmc.v | 2,409 | module MODULE1
(
input VAR16,
input [1:0] VAR14,
input VAR4,
input VAR25,
input VAR13,
input VAR1,
input VAR8,
input [15:0] addr,
input [7:0] din,
output [7:0] dout,
input enable,
output VAR26,
output reg VAR23,
output VAR19,
input VAR7,
output VAR2
);
assign VAR26 = VAR22;
wire VAR3 = ~VAR1 & ~VAR4 & VAR8;
wire VAR12 ... | gpl-2.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_auto_pc_0/synth/design_SWandHW_standalone_auto_pc_0.v | 13,204 | module MODULE1 (
VAR80,
VAR34,
VAR42,
VAR59,
VAR39,
VAR12,
VAR21,
VAR13,
VAR105,
VAR48,
VAR97,
VAR5,
VAR64,
VAR46,
VAR30,
VAR44,
VAR20,
VAR49,
VAR95,
VAR1,
VAR17,
VAR92,
VAR26,
VAR31,
VAR101,
VAR75,
VAR82,
VAR35,
VAR99,
VAR71,
VAR61,
VAR4,
VAR108,
VAR51,
VAR2,
VAR98,
VAR102,
VAR45,
VAR11,
VAR96,
VAR89,
VAR78,
VAR27,
VA... | gpl-3.0 |
sirchuckalot/zet | cores/vga/rtl/vga_char_rom.v | 1,169 | module MODULE1 (
input clk,
input [11:0] addr,
output reg [ 7:0] VAR1
);
reg [7:0] VAR2[0:4095];
always @(posedge clk) VAR1 <= VAR2[addr]; | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_1.functional.pp.v | 1,081 | module MODULE1( VAR12, VAR9, VAR7, VAR6, VAR4, VAR13, VAR1 );
input VAR7, VAR9, VAR12, VAR4, VAR13, VAR1;
output VAR6;
or VAR3( VAR10, VAR9, VAR12 );
VAR11( VAR8, 1'b0, 1'b0, VAR7, VAR10, VAR1 );
wire VAR5;
not VAR14( VAR5, VAR8 );
or VAR2( VAR6, VAR7, VAR5 );
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/ssio_ddr_in.v | 3,617 | module MODULE1 #
(
parameter VAR31 = "VAR13",
parameter VAR25 = "VAR26",
parameter VAR24 = "VAR7",
parameter VAR16 = 1
)
(
input wire VAR28,
input wire [VAR16-1:0] VAR11,
output wire VAR21,
output wire [VAR16-1:0] VAR12,
output wire [VAR16-1:0] VAR2
);
wire VAR9;
wire VAR20;
generate
if (VAR31 == "VAR22") begin
if (VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn.pp.blackbox.v | 1,323 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR2,
VAR6 ,
VAR7 ,
VAR3 ,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR2;
input VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/J1_soc-master/hdl/j1soc.v | 3,578 | module MODULE1#(
parameter VAR18 = "../VAR16/VAR35/VAR15.VAR20" )(
VAR32, VAR9,
VAR19, VAR11, VAR28, VAR40, VAR5,VAR29, VAR1, VAR10, VAR34
);
input VAR19, VAR11,VAR40;
output VAR32, VAR5, VAR29, VAR28;
output VAR9;
input VAR1; output VAR10, VAR34;
wire VAR6; wire VAR4; wire [15:0] VAR27; reg [15:0] VAR8; wire [15:0] VA... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/ddr2/ddr2.v | 30,025 | module MODULE1 (
VAR59,
VAR34,
VAR70,
VAR77,
VAR33,
VAR37,
VAR21,
VAR35,
VAR47,
VAR52,
VAR73,
VAR27,
VAR30,
VAR6,
VAR5,
VAR86,
VAR25,
VAR8,
VAR87,
VAR9,
VAR76,
VAR107,
VAR101,
VAR91,
VAR49,
VAR11,
VAR31,
VAR84,
VAR32,
VAR61,
VAR105,
VAR50,
VAR43,
VAR44,
VAR53,
VAR80,
VAR92);
input [23:0] VAR59;
input VAR34;
input VAR70... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_rank_mach.v | 12,347 | module MODULE1 #
(
parameter VAR53 = "8",
parameter VAR52 = 4,
parameter VAR62 = "VAR4",
parameter VAR57 = 40,
parameter VAR46 = 4,
parameter VAR27 = 4,
parameter VAR61 = 2,
parameter VAR25 = 5,
parameter VAR18 = 5,
parameter VAR17 = 2,
parameter VAR58 = 30,
parameter VAR42 = 8,
parameter VAR14 = 4,
parameter VAR32 = 4... | mit |
eda-globetrotter/PicenoDecoders | final/src/alu.v | 176,826 | module MODULE1 (VAR22,VAR2,VAR33,VAR14,VAR27);
output [0:127] VAR27;
input [0:127] VAR22;
input [0:127] VAR2;
input [0:1] VAR33;
input [0:4] VAR14;
parameter VAR18 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR27;
reg [0:127] VAR28;
reg [0:15] VAR36;
reg [0:15] VAR12;
reg [0:15] VAR13;
reg [0:15] VAR15;
reg [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.v | 2,262 | module MODULE1 (
VAR2,
VAR8 ,
VAR10,
VAR7 ,
VAR3,
VAR4,
VAR1 ,
VAR5
);
output VAR2;
input VAR8 ;
input VAR10;
input VAR7 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR5 ;
VAR6 VAR9 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o.pp.symbol.v | 1,372 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR9 ,
input VAR3 ,
output VAR8 ,
input VAR5 ,
input VAR7,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22ai/sky130_fd_sc_hd__o22ai_1.v | 2,352 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR8 ,
VAR10 ,
VAR4 ,
VAR9,
VAR7,
VAR11 ,
VAR3
);
output VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR10 ;
input VAR4 ;
input VAR9;
input VAR7;
input VAR11 ;
input VAR3 ;
VAR1 VAR2 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR11(VAR11),
.... | apache-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/FIFO_pixelq_op_img_rows_V_channel3.v | 3,003 | module MODULE1 (
clk,
VAR17,
VAR4,
VAR3,
VAR22);
parameter VAR7 = 32'd12;
parameter VAR24 = 32'd2;
parameter VAR5 = 32'd3;
input clk;
input [VAR7-1:0] VAR17;
input VAR4;
input [VAR24-1:0] VAR3;
output [VAR7-1:0] VAR22;
reg[VAR7-1:0] VAR16 [0:VAR5-1];
integer VAR2;
always @ (posedge clk)
begin
if (VAR4)
begin
for (VAR2=... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/system.v | 41,898 | module MODULE1 (
input wire VAR58, input wire VAR238, output wire VAR240, output wire [14:0] VAR232, output wire [2:0] VAR48, output wire VAR200, output wire VAR129, output wire VAR222, output wire VAR127, output wire VAR51, output wire VAR37, output wire VAR89, output wire VAR143, inout wire [31:0] VAR38, inout wire [... | mit |
hoangt/NOCulator | hring/hw/buffered/src/c_padder.v | 2,673 | module MODULE1
(VAR9, VAR7);
parameter VAR2 = 32;
parameter VAR5 = 0;
parameter VAR8 = 0;
parameter VAR4 = 0;
parameter VAR1 = 0;
localparam VAR10 = VAR5 + VAR2 + VAR4;
input [0:VAR2-1] VAR9;
output [0:VAR10-1] VAR7;
wire [0:VAR10-1] VAR7;
genvar VAR3;
generate
for(VAR3 = 0; VAR3 < VAR10; VAR3 = VAR3 + 1)
begin:VAR6
if... | mit |
ptracton/wb_soc_template | rtl/LM32/rtl/jtag_cores.v | 2,432 | module MODULE1 (
input [7:0] VAR4,
input [2:0] VAR9,
output VAR2,
output [7:0] VAR10,
output [2:0] VAR8,
output VAR5,
output VAR14
);
wire VAR1;
wire VAR6;
wire VAR3;
wire VAR13;
wire VAR11;
wire reset;
VAR7 VAR7 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR13(VAR13),
.VAR11(VAR11),
.reset(reset)
);
reg [10:0] VAR15;
r... | mit |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/start_for_CvtColomb6.v | 3,003 | module MODULE2 (
clk,
VAR4,
VAR26,
VAR8,
VAR12);
parameter VAR20 = 32'd1;
parameter VAR18 = 32'd2;
parameter VAR14 = 32'd3;
input clk;
input [VAR20-1:0] VAR4;
input VAR26;
input [VAR18-1:0] VAR8;
output [VAR20-1:0] VAR12;
reg[VAR20-1:0] VAR7 [0:VAR14-1];
integer VAR13;
always @ (posedge clk)
begin
if (VAR26)
begin
for ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphetap/sky130_fd_sc_ls__decaphetap.pp.blackbox.v | 1,152 | module MODULE1 (
VAR1,
VAR2,
VAR3
);
input VAR1;
input VAR2;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2/sky130_fd_sc_ls__and2.behavioral.pp.v | 1,783 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR9 ,
VAR11,
VAR1,
VAR12 ,
VAR13
);
output VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR11;
input VAR1;
input VAR12 ;
input VAR13 ;
wire VAR6 ;
wire VAR8;
and VAR4 (VAR6 , VAR2, VAR9 );
VAR10 VAR7 (VAR8, VAR6, VAR11, VAR1);
buf VAR5 (VAR3 , VAR8 );
endmodule | apache-2.0 |
ptracton/pmodacl2 | soc/wb_uart/uart_transmitter.v | 13,057 | module MODULE1 (clk, VAR1, VAR10, VAR11, VAR19, enable, VAR37, VAR20, VAR4, VAR30, VAR40);
input clk;
input VAR1;
input [7:0] VAR10;
input VAR11;
input [7:0] VAR19;
input enable;
input VAR30;
input VAR40; output VAR37;
output [2:0] VAR20;
output [VAR36-1:0] VAR4;
reg [2:0] VAR20;
reg [4:0] counter;
reg [2:0] VAR14; reg... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/seven_seg_pio.v | 2,207 | module MODULE1 (
address,
VAR2,
clk,
VAR1,
VAR9,
VAR7,
VAR4,
VAR6
)
;
output [ 15: 0] VAR4;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR1;
input VAR9;
input [ 31: 0] VAR7;
wire VAR5;
reg [ 15: 0] VAR3;
wire [ 15: 0] VAR4;
wire [ 15: 0] VAR8;
wire [ 31: 0] VAR6;
assign VAR5 = 1;
assign V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor3/sky130_fd_sc_hs__xnor3.functional.pp.v | 1,725 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR1 ,
VAR8 ,
VAR5,
VAR4
);
output VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR5;
input VAR4;
wire VAR9 ;
wire VAR12;
xnor VAR2 (VAR9 , VAR7, VAR1, VAR8 );
VAR3 VAR11 (VAR12, VAR9, VAR5, VAR4);
buf VAR6 (VAR10 , VAR12 );
endmodule | apache-2.0 |
wallento/wb_interconnect | wb_interconnect_arb_rr.v | 6,436 | module MODULE1(
VAR4,
req, VAR7
);
parameter VAR5 = 2;
input [VAR5-1:0] req;
input [VAR5-1:0] VAR7;
output [VAR5-1:0] VAR4;
always @ begin : VAR6
integer VAR9,VAR2;
for (VAR9=0;VAR9<VAR5;VAR9=VAR9+1) begin
VAR3[VAR9] = {VAR5{1'b0}};
if(VAR9>0)
VAR3[VAR9][VAR9-1] = ~VAR7[VAR9-1];
end
else
VAR3[VAR9][VAR5-1] = ~VAR7[VAR5... | lgpl-3.0 |
dhesant/elec4320 | Lab2/main.v | 1,559 | module MODULE1( VAR4, VAR12, VAR1, VAR11 );
input [8:0] VAR4;
input VAR12;
output VAR1;
output [4:0] VAR11;
wire [4:0] VAR7;
wire [12:0] VAR17;
wire VAR9;
VAR5 encoder(
.VAR4(VAR4),
.VAR7(VAR7),
.clk(VAR12)
);
VAR15 VAR14 (
.VAR13(VAR7),
.VAR10(VAR17),
.VAR16(VAR12)
);
VAR2 VAR2(
.VAR12(VAR12),
.VAR9(VAR9)
);
VAR3 VAR1... | mit |
hydai/Verilog-Practice | DigitalDesign/hw4_FIFO/fifo_ctr.v | 5,301 | module MODULE1 (
input wire clk,
input wire VAR3,
input wire VAR7,
input wire VAR4,
output reg VAR21,
output reg VAR10,
output reg VAR24,
output reg VAR25,
output reg VAR5,
output reg VAR2,
output reg VAR6,
output reg VAR23,
output reg [4:0] addr
);
parameter VAR28 = 32;
parameter delay = 1.5;
parameter VAR22 = 2'b00;
... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.behavioral.pp.v | 2,914 | module MODULE1( VAR27, VAR12, VAR4, VAR26, VAR1, VAR19 );
input VAR4, VAR27, VAR12;
inout VAR1, VAR19;
output VAR26;
reg VAR11;
VAR25 VAR21(.VAR27(VAR27),.VAR12(VAR12),.VAR4(VAR4),.VAR26(VAR26),.VAR1(VAR1),.VAR19(VAR19),.VAR11(VAR11));
VAR25 VAR2(.VAR27(VAR27),.VAR12(VAR12),.VAR4(VAR4),.VAR26(VAR26),.VAR1(VAR1),.VAR19(... | apache-2.0 |
antmicro/yosys-symbiflow-plugins | ql-qlf-plugin/qlf_k6n10/brams_map.v | 3,836 | module \VAR4 (
output [31:0] VAR16,
input VAR28, VAR22,
input [8:0] VAR33,
input VAR15, VAR23,
input [8:0] VAR34,
input [31:0] VAR6,
input [31:0] VAR14
);
generate
VAR36 #()
VAR10 (
.dout(VAR16),
.VAR30 (VAR28 ),
.VAR9 (VAR15 ),
.VAR24 (VAR22 ),
.VAR8(VAR33),
.VAR7 (VAR23 ),
.VAR29(VAR34),
.VAR27 (VAR6 ),
.din (VAR14)
... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4.functional.pp.v | 1,983 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR15 ,
VAR3 ,
VAR17 ,
VAR9 ,
VAR2 ,
VAR10,
VAR1,
VAR12 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR15 ;
input VAR3 ;
input VAR17 ;
input VAR9 ;
input VAR2 ;
input VAR10;
input VAR1;
input VAR12 ;
input VAR4 ;
wire VAR13 ;
wire VAR16;
VAR8 VAR5 (VAR13 , VAR7, VAR15, VAR3, VAR17, VAR9, V... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_lfsr5.v | 2,433 | module MODULE1 (
out,
VAR4, clk, VAR1, VAR8, VAR3, reset
);
input VAR4;
input clk, VAR1, VAR8, VAR3, reset;
output [1:0] out;
reg [4:0] VAR2;
wire [4:0] VAR7;
always @ (VAR4 or VAR7 or reset)
begin
if (reset)
VAR2 = 5'b11111;
end
else if (VAR4)
begin
VAR2[1] = VAR7[0];
VAR2[2] = VAR7[1];
VAR2[3] = VAR7[2];
VAR2[4] = VA... | gpl-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_697_bits/rtl/pairing.v | 1,526 | module MODULE1(clk, reset, sel, addr, VAR6, VAR1, ready, VAR10, VAR2, VAR7);
input clk;
input reset; input sel;
input [5:0] addr;
input VAR6;
input VAR1; input ready; input VAR10;
output VAR2;
output VAR7;
reg [VAR8:0] VAR3, VAR5;
wire [VAR8:0] out;
assign VAR2 = VAR5[0];
VAR9
VAR4 (clk, reset, sel, addr, VAR6, VAR3, o... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/gtx_rx_valid_filter_v6.v | 11,837 | module MODULE1 #(
parameter VAR51 = 28,
parameter VAR22 = 1
)
(
output [1:0] VAR54,
output [15:0] VAR23,
output VAR52,
output VAR45,
output [ 2:0] VAR66,
output VAR37,
input [1:0] VAR1,
input [15:0] VAR64,
input VAR14,
input VAR20,
input [ 2:0] VAR35,
input VAR24,
input VAR40,
input VAR57,
input VAR6,
input VAR3
);
loc... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi.pp.symbol.v | 1,427 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR9 ,
input VAR1 ,
input VAR10 ,
input VAR11 ,
output VAR7 ,
input VAR5 ,
input VAR2,
input VAR4,
input VAR8
);
endmodule | apache-2.0 |
Willster419/ELEC3725_vivado_projects | assignment_3/assignment_3.srcs/sources_1/new/regfile.v | 1,616 | module MODULE1(
input [31:0] VAR3, input [31:0] VAR6, input [31:0] VAR4, input [31:0] VAR7, output [31:0] VAR9, output [31:0] VAR1, input clk
);
assign VAR9 = VAR3[0] ? 32'b0 : 32'VAR5; assign VAR1 = VAR6[0] ? 32'b0 : 32'VAR5;
MODULE2 VAR2[30:0]( .VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4[31:1]),
.VAR6(VAR6[31:1]),
.VAR3(VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv_16.v | 1,915 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR4,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR4;
input VAR2;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR6,
VAR5
);
output VAR6;
input VAR5;
supply1 VAR4;
supply0 VAR2;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/uart/uart_tx.v | 3,601 | module MODULE1 (
input wire clk,
input wire reset,
input wire VAR17,
input wire [VAR14] VAR15,
output wire VAR5,
output reg VAR7,
output reg VAR6
);
reg [VAR26] state;
reg [VAR21] VAR25;
reg [VAR10] VAR11;
reg [VAR14] VAR8;
assign VAR5 = (state == VAR13) ? VAR23 : VAR4;
always @(posedge clk or VAR3 reset) begin
if (res... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/dram_pt.v | 7,106 | module MODULE1(
VAR29, VAR11,
VAR18, VAR19, VAR20,
VAR35, VAR37,
clk, VAR38, VAR4,
VAR27, VAR23,
VAR12, VAR30,
VAR10, VAR46,
VAR36, VAR28, VAR3,
VAR1,
VAR24, VAR41,
VAR32
);
output VAR29;
output VAR11;
output [16:0] VAR18;
output [15:0] VAR19;
output VAR20;
output VAR35;
output [16:0] VAR37;
input clk;
input VAR38;
inp... | gpl-2.0 |
sh-chris110/chris | FPGA/uCos/system/synthesis/submodules/system_nios2_gen2_0_cpu_debug_slave_wrapper.v | 9,487 | module MODULE1 (
VAR16,
VAR5,
clk,
VAR26,
VAR24,
VAR41,
VAR18,
VAR47,
VAR37,
VAR17,
VAR42,
VAR48,
VAR45,
VAR21,
VAR14,
VAR12,
VAR38,
VAR35,
VAR52,
VAR46,
VAR43,
VAR55,
VAR29,
VAR50,
VAR53,
VAR56,
VAR49,
VAR11,
VAR15,
VAR10,
VAR9,
VAR1,
VAR2
)
;
output [ 37: 0] VAR43;
output VAR55;
output VAR29;
output VAR50;
output VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_1.v | 2,240 | module MODULE2 (
VAR8 ,
VAR1 ,
VAR2 ,
VAR9,
VAR6,
VAR3 ,
VAR7
);
output VAR8 ;
input [15:0] VAR1 ;
input [15:0] VAR2 ;
input VAR9;
input VAR6;
input VAR3 ;
input VAR7 ;
VAR4 VAR5 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR8,
VAR1,
VAR2
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3.behavioral.pp.v | 1,801 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR1 ,
VAR8 ,
VAR9,
VAR10,
VAR4 ,
VAR14
);
output VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR8 ;
input VAR9;
input VAR10;
input VAR4 ;
input VAR14 ;
wire VAR2 ;
wire VAR3;
or VAR7 (VAR2 , VAR1, VAR5, VAR8 );
VAR12 VAR11 (VAR3, VAR2, VAR9, VAR10);
buf VAR13 (VAR6 , VAR3 );
endmodule | apache-2.0 |
omicronns/studies-sys-rek | de1-soc/v/Reset_Delay.v | 2,663 | module MODULE1(VAR2,VAR6,VAR8,VAR1,VAR3,VAR5,VAR7);
input VAR2;
input VAR6;
output reg VAR8;
output reg VAR1;
output reg VAR3;
output reg VAR5;
output reg VAR7;
reg [31:0] VAR4;
always@(posedge VAR2 or negedge VAR6)
begin
if(!VAR6)
begin
VAR4 <= 0;
VAR8 <= 0;
VAR1 <= 0;
VAR3 <= 0;
VAR5 <= 0;
VAR7 <= 0;
end
else
begin
i... | mit |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipitc131_common_sync.v | 1,037 | module MODULE1
VAR3 = 0,
VAR1 = 1)
(
input wire rst,
input wire VAR2,
input wire [VAR1-1:0] VAR7,
output wire [VAR1-1:0] VAR5);
reg [VAR1-1:0] VAR6;
reg [VAR1-1:0] VAR4;
generate
if(VAR3)
assign VAR5 = VAR7;
else begin
always @ (posedge rst or posedge VAR2) begin
if(rst) begin
VAR6 <= {VAR1{1'b0}};
VAR4 <= {VAR1{1'b0}}... | mit |
monotone-RK/FACE | MCSoC-15/8-way_8-parallel/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_col_mach.v | 16,676 | module MODULE1 #
(
parameter VAR23 = 100,
parameter VAR6 = 3,
parameter VAR33 = "8",
parameter VAR58 = 12,
parameter VAR56 = 4,
parameter VAR9 = 8,
parameter VAR32 = 1,
parameter VAR17 = 0,
parameter VAR95 = 8,
parameter VAR88 = "VAR80",
parameter VAR20 = "VAR26",
parameter VAR41 = "VAR26",
parameter VAR105 = 31,
param... | mit |
olajep/oh | src/adi/hdl/library/common/ad_addsub.v | 3,534 | module MODULE1 #(
parameter VAR5 = 32,
parameter VAR9 = 32'h1,
parameter VAR10 = 0) (
input clk,
input [(VAR5-1):0] VAR1,
input [(VAR5-1):0] VAR11,
output reg [(VAR5-1):0] out,
input VAR8);
localparam VAR7 = 1;
localparam VAR14 = 0;
reg [VAR5:0] VAR3 = 'b0;
reg [VAR5:0] VAR13 = 'b0;
reg [(VAR5-1):0] VAR12 = 'b0;
reg [(... | mit |
m-labs/milkymist | cores/pfpu/rtl/pfpu_dma.v | 1,658 | module MODULE1(
input VAR6,
input VAR17,
input VAR14,
input [28:0] VAR3,
input [6:0] VAR5,
input [6:0] VAR11,
input [31:0] VAR1,
input [31:0] VAR2,
output ack,
output VAR4,
output [31:0] VAR16,
output [31:0] VAR15,
output VAR10,
output reg VAR9,
input VAR13
);
reg VAR8;
reg [28:0] VAR12;
reg [31:0] VAR7;
reg [31:0] VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai.functional.v | 1,566 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR1 ,
VAR6
);
output VAR2 ;
input VAR7 ;
input VAR1 ;
input VAR6;
wire VAR10 ;
wire VAR5 ;
wire VAR9;
not VAR8 (VAR10 , VAR6 );
or VAR4 (VAR5 , VAR1, VAR7 );
nand VAR3 (VAR9, VAR10, VAR5 );
buf VAR11 (VAR2 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1.behavioral.v | 1,440 | module MODULE1 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
supply1 VAR6;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR9 ;
wire VAR2;
not VAR8 (VAR2, VAR3 );
buf VAR1 (VAR4 , VAR2 );
endmodule | apache-2.0 |
egyp7/mor1kx | rtl/verilog/pfpu32/pfpu32_addsub.v | 13,306 | module MODULE1
(
input clk,
input rst,
input VAR67, input VAR37, input VAR48, input VAR29, input VAR27,
input [9:0] VAR8,
input [23:0] VAR44,
input VAR33,
input VAR34,
input [9:0] VAR2,
input [23:0] VAR61,
input VAR28,
input VAR51,
input VAR54,
input VAR1,
input VAR20,
input VAR15,
output reg VAR65, output reg VAR71, o... | mpl-2.0 |
richsoap/ThreeGrade | 数电实验/pre/exm7code/top_adder.v | 1,308 | module MODULE1(
input clk,
input VAR1,
output [1:0] VAR3,
output [3:0] VAR5
);
reg [3:0]VAR5;
reg [1:0]VAR3;
reg before;
wire VAR4;
wire [3:0]VAR6;
wire [3:0]VAR2;
wire [1:0]VAR7;
always@(posedge clk)
begin
if(~before&VAR1)
VAR3[1:0]<=VAR7[1:0];
end
else
VAR5[3:0]<=VAR2[3:0];
before<=VAR1;
end
assign VAR6[0]=~(VAR5[0]|... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/ETAII_N16_Q4_syn.v | 2,975 | module MODULE1 ( VAR43, VAR32, VAR21 );
input [15:0] VAR43;
input [15:0] VAR32;
output [16:0] VAR21;
wire VAR62, VAR72, VAR29, VAR51, VAR12, VAR26, VAR82, VAR56, VAR20, VAR9, VAR83, VAR28, VAR59, VAR73,
VAR70, VAR7, VAR47, VAR13, VAR2, VAR76, VAR1, VAR53, VAR37, VAR54, VAR19, VAR58, VAR27;
VAR24 VAR85 ( .VAR64(VAR32[7]... | gpl-3.0 |
shahid313/MSCourseWork | Adv ASIC Design and FPGA/8bitRISCProcessor/8bitRISCProcessor/RISC/TopModule.v | 1,072 | module MODULE1(input clk,rst,input [15:0] VAR13,input VAR17,
output VAR24, VAR7, VAR15, VAR19, VAR22, VAR21, VAR29, VAR3, VAR10, VAR18, VAR23, VAR9,VAR4
);
wire VAR14;
VAR27 VAR28(.VAR8(clk),.rst(rst),.VAR11(VAR14));
assign VAR4=VAR14;
wire [15:0]VAR5;
VAR2 VAR1(.clk(VAR14),.rst(rst),.VAR13(VAR13),.VAR17(VAR17),.VAR20(... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N8_R1_P6_syn.v | 2,070 | module MODULE1 ( VAR30, VAR10, VAR32 );
input [7:0] VAR30;
input [7:0] VAR10;
output [8:0] VAR32;
wire VAR55, VAR37, VAR33, VAR59, VAR26,
VAR1, VAR40, VAR46, VAR29, VAR13, VAR25, VAR11, VAR20, VAR63, VAR34;
VAR24 VAR57 ( .VAR4(VAR10[1]), .VAR48(VAR30[1]), .VAR21(VAR55), .VAR28(
VAR37), .VAR56(VAR32[1]) );
VAR24 VAR5 ( ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.pp.symbol.v | 1,394 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR4,
input VAR6 ,
input VAR5 ,
input VAR2 ,
input VAR7
);
endmodule | apache-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_DE0_Nano/hub_mem.v | 3,074 | module MODULE1
(
input VAR18,
input VAR20,
input VAR13,
input [3:0] VAR6,
input [13:0] VAR15,
input [31:0] VAR7,
output [31:0] VAR10
);
reg [7:0] VAR8 [8191:0];
reg [7:0] VAR17 [8191:0];
reg [7:0] VAR12 [8191:0];
reg [7:0] VAR19 [8191:0];
reg [7:0] VAR9;
reg [7:0] VAR3;
reg [7:0] VAR4;
reg [7:0] VAR2;
always @(posedge ... | gpl-3.0 |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | bcam_trs.v | 8,214 | module MODULE1
localparam VAR7 = VAR25(VAR15);
reg VAR5; wire [VAR16-1:0] VAR36;
VAR24 #( .VAR18 ( VAR15 ), .VAR34( VAR16 ), .VAR13( VAR12 ), .VAR8( "" )) VAR10 ( .clk ( clk ), .VAR37 ( !VAR5 ), .addr ( VAR11 ), .VAR17( VAR38 ), .VAR23( VAR36 ));
wire [VAR15-1:0] VAR26 ; reg VAR21 ; wire VAR32 = !VAR5 & (VAR38==VAR36);... | bsd-3-clause |
ahmed-agiza/LCSTA | Sample Files/synth.v | 1,911 | module MODULE1(VAR1, VAR6, clk, reset);
input clk;
input [16:0] VAR6;
output [16:0] VAR1;
input reset;
VAR4 00 (
.VAR3(clk),
.VAR2(VAR6[0]),
.VAR5(VAR1[0]),
.VAR8(reset),
.VAR7(1'b1)
);
VAR4 01 (
.VAR3(clk),
.VAR2(VAR6[1]),
.VAR5(VAR1[1]),
.VAR8(reset),
.VAR7(1'b1)
);
VAR4 02 (
.VAR3(clk),
.VAR2(VAR6[2]),
.VAR5(VAR1[2]... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_pcie_bram_top_7x.v | 8,601 | module MODULE1
parameter VAR32 = "VAR21", parameter VAR2 = 0, parameter [3:0] VAR12 = 4'h1, parameter [5:0] VAR34 = 6'h08,
parameter VAR24 = 31, parameter VAR18 = 24, parameter VAR33 = 1, parameter VAR1 = 2, parameter VAR27 = 1,
parameter VAR8 = 'h1FFF, parameter VAR10 = 1, parameter VAR23 = 2, parameter VAR29 = 1 )
(
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/fill/sky130_fd_sc_hdll__fill_1.v | 1,856 | module MODULE1 (
VAR3,
VAR1,
VAR5 ,
VAR6
);
input VAR3;
input VAR1;
input VAR5 ;
input VAR6 ;
VAR4 VAR2 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR6 ;
VAR4 VAR2 ();
endmodule | apache-2.0 |
Tsung-Wei/OpenTimer | example/map9v3/map9v3.v | 17,120 | module MODULE1(VAR35, reset, VAR26, VAR62, VAR14, VAR34, VAR5, VAR54, VAR11, VAR60, VAR23, VAR59, VAR56, VAR58, VAR3, VAR44, VAR48, VAR53, VAR7, VAR45, VAR46, VAR8, VAR2, VAR32, VAR12, VAR41, VAR22, VAR27, VAR65, VAR47, VAR57, VAR39, VAR51, VAR15, VAR66, VAR1, VAR50, VAR17);
wire 000;
wire 001;
wire 002;
wire 003;
wire... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3b/sky130_fd_sc_ms__and3b.symbol.v | 1,307 | module MODULE1 (
input VAR7,
input VAR8 ,
input VAR5 ,
output VAR6
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/top.v | 79,412 | module MODULE1 (
clk ,
VAR100 ,
VAR403 ,
VAR117 ,
VAR75 ,
VAR259 ,
VAR290 ,
VAR268 ,
VAR214 ,
VAR131 ,
VAR141 ,
VAR113 ,
VAR306 ,
VAR460 ,
VAR346 ,
VAR69 ,
VAR199 ,
VAR127 ,
VAR111 ,
VAR283 ,
VAR452 ,
VAR335 ,
VAR242 ,
VAR11 ,
VAR121 ,
VAR459 ,
VAR374 ,
VAR458 ,
VAR435 ,
VAR6 ,
VAR344 ,
VAR9 ,
VAR377 ,
VAR482 ,
VAR414 ... | gpl-3.0 |
ridecore/ridecore | src/fpga/alu.v | 1,163 | module MODULE1(
input wire [VAR1-1:0] VAR3,
input wire [VAR2-1:0] VAR6,
input wire [VAR2-1:0] VAR5,
output reg [VAR2-1:0] out
);
wire [VAR7-1:0] VAR4;
assign VAR4 = VAR5[VAR7-1:0];
always @(*) begin
case (VAR3)
default : out = 0;
endcase end
endmodule | bsd-3-clause |
lvd2/ngs | fpga/obsolete/fpgaF_dma2/dma/dma_zx.v | 5,995 | module MODULE1(
input clk,
input VAR9,
input VAR29, input VAR36,
input [7:0] VAR12, output reg [7:0] VAR11,
output reg VAR10,
output reg VAR34,
input [7:0] din, output reg [7:0] dout,
input VAR13, input VAR26,
input [1:0] VAR39,
output reg [20:0] VAR6,
output reg [7:0] VAR4,
input [7:0] VAR31,
output reg VAR28,
output ... | gpl-3.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/lsu_pipelined.v | 18,756 | module MODULE1
(
clk, reset, VAR8, VAR54, VAR78, VAR59, VAR32, VAR72, VAR45,
VAR25, VAR49, VAR64, VAR5, VAR36, VAR55,
VAR38,
VAR57,
VAR51
);
parameter VAR33=32; parameter VAR11=4; parameter VAR27=32; parameter VAR68=2; parameter VAR44=32; parameter VAR83=0;
parameter VAR23=6; parameter VAR21=1;
parameter VAR3=1;
parame... | mit |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T19-secnotas/secnotas.v | 1,768 | module MODULE1(input wire clk, output reg VAR13);
parameter VAR5 = VAR16;
parameter VAR1 = VAR14;
parameter VAR9 = VAR18;
parameter VAR17 = VAR7;
wire VAR15, VAR6, VAR10;
reg [1:0] sel = 0;
wire VAR2;
VAR19 #(VAR5)
VAR12 (
.VAR3(clk),
.VAR8(VAR15)
);
VAR19 #(VAR1)
VAR4 (
.VAR3(clk),
.VAR8(VAR6)
);
VAR19 #(VAR9)
VAR20 (... | gpl-2.0 |
colinww/spi-core-generator | source/negedge_sync.v | 1,118 | module MODULE1 (VAR3, VAR4, VAR1);
input VAR3;
input VAR4;
output VAR1;
reg VAR2;
reg VAR1; | gpl-3.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/SOC/synthesis/submodules/SoC_nios2_qsys_0_jtag_debug_module_wrapper.v | 10,146 | module MODULE1 (
VAR19,
VAR48,
clk,
VAR54,
VAR57,
VAR29,
VAR41,
VAR6,
VAR43,
VAR11,
VAR50,
VAR4,
VAR21,
VAR47,
VAR15,
VAR58,
VAR51,
VAR35,
VAR9,
VAR26,
VAR37,
VAR18,
VAR10,
VAR52,
VAR49,
VAR16,
VAR17,
VAR56,
VAR55,
VAR39,
VAR2,
VAR44,
VAR13,
VAR24,
VAR31,
VAR42
)
;
output [ 37: 0] VAR37;
output VAR18;
output VAR10;
out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd/sky130_fd_sc_hd__tapvgnd.blackbox.v | 1,249 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv.functional.v | 1,663 | module MODULE1 (
VAR4,
VAR10,
VAR6 ,
VAR3
);
input VAR4;
input VAR10;
output VAR6 ;
input VAR3 ;
wire VAR1 ;
wire VAR5;
not VAR7 (VAR1 , VAR3 );
VAR2 VAR9 (VAR5, VAR1, VAR4, VAR10);
buf VAR8 (VAR6 , VAR5 );
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/readpath.v | 2,906 | module MODULE1 (
VAR20,
VAR9,
);
parameter VAR22 = 16;
parameter VAR19 = 2;
input VAR20;
input VAR9;
input [VAR19-1:0] VAR3;
input [VAR22-1:0] VAR8;
input VAR10;
output VAR4;
output [VAR22*2-1:0] VAR26;
wire VAR15 = VAR3 [0];
wire VAR16 = VAR3 [1];
wire VAR31 = ~VAR3 [0];
wire VAR13 = ~VAR3 [1];
VAR21 VAR23 (
.VAR18 (V... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_4.behavioral.pp.v | 3,372 | module MODULE1( VAR4, VAR1, VAR7, VAR11, VAR6, VAR5, VAR10, VAR8 );
input VAR6, VAR5, VAR1, VAR7, VAR11;
inout VAR10, VAR8;
output VAR4;
VAR3 VAR2(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR11(VAR11),.VAR6(VAR6),.VAR5(VAR5),.VAR10(VAR10),.VAR8(VAR8));
VAR3 VAR9(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR11(VAR11),.VAR6(VAR6)... | apache-2.0 |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_mux_enc.v | 9,815 | module MODULE1 #
(
parameter VAR10 = "VAR6",
parameter integer VAR7 = 4,
parameter integer VAR35 = 2,
parameter integer VAR14 = 1
)
(
input wire [VAR35-1:0] VAR24,
input wire [VAR7*VAR14-1:0] VAR27,
output wire [VAR14-1:0] VAR2,
input wire VAR37
);
wire [VAR14-1:0] VAR38;
genvar VAR9;
function [VAR14-1:0] VAR36
(
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxbp/sky130_fd_sc_ms__dfxbp.functional.pp.v | 1,767 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR9,
VAR13,
VAR10 ,
VAR8
);
output VAR5 ;
output VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR9;
input VAR13;
input VAR10 ;
input VAR8 ;
wire VAR3;
VAR11 VAR2 VAR12 (VAR3 , VAR1, VAR7, , VAR9, VAR13);
buf VAR14 (VAR5 , VAR3 );
not VAR4 (VAR6 , VAR3 );
endmodule | apache-2.0 |
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