repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_nonsynth_mem_1r1w_sync_dma.v | 1,080 | module MODULE1
, parameter VAR21(VAR4)
, parameter VAR21(VAR1)
, parameter VAR13=(VAR15>>3)
, parameter VAR16=VAR13
, parameter VAR18=VAR10(VAR4)
, parameter VAR3=VAR10(VAR13)
, parameter VAR9=0
)
(
input VAR12
, input VAR20
, input VAR2
, input [VAR18-1:0] VAR5
, input VAR8
, input [VAR18-1:0] VAR17
, input [VAR15-1:0... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311oi/sky130_fd_sc_lp__a311oi_2.v | 2,450 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR11 ,
VAR8 ,
VAR3 ,
VAR4 ,
VAR1,
VAR5,
VAR10 ,
VAR12
);
output VAR2 ;
input VAR7 ;
input VAR11 ;
input VAR8 ;
input VAR3 ;
input VAR4 ;
input VAR1;
input VAR5;
input VAR10 ;
input VAR12 ;
VAR6 VAR9 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(V... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_controller/delay.v | 3,422 | module MODULE1
parameter VAR2 = 128
)
(
input VAR6,
input VAR3,
input VAR4,
output reg VAR5
);
reg [VAR2-1:0] VAR1;
always @(posedge VAR6)
begin
if(VAR3 == 0)
begin
VAR1 <= 0;
VAR5 <= 0;
end
else
begin
VAR1 <= {VAR1[VAR2-2:0], VAR4};
VAR5 <= VAR1[VAR2-1];
end
end
endmodule | gpl-3.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_sysclk.v | 7,061 | module MODULE1 (
clk,
VAR23,
VAR4,
VAR8,
VAR3,
VAR21,
VAR29,
VAR30,
VAR20,
VAR10,
VAR24,
VAR12,
VAR25,
VAR17,
VAR1,
VAR32,
VAR19,
VAR16,
VAR6
)
;
output [ 37: 0] VAR21;
output VAR29;
output VAR30;
output VAR20;
output VAR10;
output VAR24;
output VAR12;
output VAR25;
output VAR17;
output VAR1;
output VAR32;
output VAR19... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai_4.v | 2,361 | module MODULE2 (
VAR1 ,
VAR11 ,
VAR8 ,
VAR6 ,
VAR2 ,
VAR7,
VAR4,
VAR10 ,
VAR5
);
output VAR1 ;
input VAR11 ;
input VAR8 ;
input VAR6 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR10 ;
input VAR5 ;
VAR9 VAR3 (
.VAR1(VAR1),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.... | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/ResetInverter.v | 1,509 | module MODULE1(VAR2, VAR1);
input VAR2; output VAR1;
wire VAR1;
assign VAR1 = ! VAR2 ;
endmodule | lgpl-3.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/gtx_tx_sync_rate_v6.v | 14,057 | module MODULE1
parameter VAR58 = 1,
parameter VAR9 = 0 )
(
output reg VAR53 = 1'b0,
output reg VAR59 = 1'b0,
output reg VAR33 = 1'b0,
output reg VAR51 = 1'b0,
output reg VAR43 = 1'b0,
output reg VAR42 = 1'b0,
output reg VAR44 = 1'b0,
output reg VAR15 = 1'b0,
input VAR32,
input VAR34,
input VAR10,
input VAR55,
input VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50.pp.symbol.v | 1,356 | module MODULE1 (
input VAR6 ,
output VAR1 ,
input VAR5 ,
input VAR2,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
CatherineH/QubitekkCC | CC1/src/DE0Nano/verilog/coincidence_counter_bb.v | 3,864 | module MODULE1 (
VAR3,
VAR1,
VAR2,
VAR4);
input VAR3;
input VAR1;
input VAR2;
output [21:0] VAR4;
endmodule | mit |
The-OpenROAD-Project/asap7 | asap7sc7p5t_27/Verilog/asap7sc7p5t_OA_LVT_TT_201020.v | 197,600 | module MODULE1 (VAR6, VAR3, VAR7, VAR9, VAR11);
output VAR6;
input VAR3, VAR7, VAR9, VAR11;
wire VAR2, VAR1, VAR8;
wire VAR5, VAR10, VAR4;
not (VAR5, VAR11);
not (VAR8, VAR9);
and (VAR10, VAR8, VAR5);
not (VAR1, VAR7);
not (VAR2, VAR3);
and (VAR4, VAR2, VAR1, VAR5);
or (VAR6, VAR4, VAR10); | bsd-3-clause |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/DE2_115_makomk_serial/fpgaminer_top.v | 5,302 | module MODULE1 (VAR13, VAR18, VAR42, VAR20, VAR37);
parameter VAR35 = VAR43;
parameter VAR35 = 0;
localparam [5:0] VAR2 = (6'd1 << VAR35);
localparam [31:0] VAR29 = (32'd1 << (7 - VAR35)) + 32'd1;
input VAR13;
reg [255:0] state = 0;
reg [511:0] VAR10 = 0;
reg [31:0] VAR12 = 32'h00000000;
wire VAR27;
VAR11 VAR38 (VAR13,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dlatch_pr/sky130_fd_sc_hd__udp_dlatch_pr.blackbox.v | 1,291 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR3;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/sg_list_reader_64.v | 5,056 | module MODULE1 #(
parameter VAR18 = 9'd64
)
(
input VAR1,
input VAR6,
input [VAR18-1:0] VAR13, input VAR4, output VAR16,
output VAR5, output VAR12, input VAR3, output [63:0] VAR22, output [31:0] VAR19 );
reg [1:0] VAR21=VAR14, VAR21=VAR14;
reg [1:0] VAR15=VAR2, VAR15=VAR2;
reg [VAR18-1:0] VAR9={VAR18{1'd0}}, VAR9={VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.symbol.v | 1,294 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai.behavioral.v | 1,654 | module MODULE1 (
VAR7 ,
VAR12 ,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR12 ;
input VAR3 ;
input VAR6;
supply1 VAR5;
supply0 VAR13;
supply1 VAR11 ;
supply0 VAR10 ;
wire VAR4 ;
wire VAR1 ;
wire VAR9;
not VAR8 (VAR4 , VAR6 );
or VAR14 (VAR1 , VAR3, VAR12 );
nand VAR2 (VAR9, VAR4, VAR1 );
buf VAR15 (VAR7 , VAR9 );
endmodule | apache-2.0 |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/mkInputArbiter.v | 8,265 | module MODULE1(VAR22,
VAR25,
VAR27,
select,
VAR18);
input VAR22;
input VAR25;
input [4 : 0] VAR27;
output [4 : 0] select;
input VAR18;
wire [4 : 0] select;
reg [4 : 0] VAR32;
wire [4 : 0] VAR13;
wire VAR43;
wire [1 : 0] VAR12,
VAR24,
VAR29,
VAR5,
VAR35,
VAR31,
VAR21,
VAR51,
VAR17,
VAR49;
wire VAR6,
VAR28,
VAR26,
VAR16,... | gpl-2.0 |
jhennessy/parallella-hw-old | fpga/hdl/common/pulse2pulse.v | 1,615 | module MODULE1(
out,
VAR4, VAR7, in, reset
);
input VAR4;
input VAR7;
input in;
output out;
input reset;
wire VAR2;
wire VAR1;
VAR3 VAR3(
.out (VAR2),
.clk (VAR4),
.in (in),
.reset (reset));
VAR6 #(1) VAR6(
.out (VAR1),
.in (VAR2),
.clk (VAR7),
.reset (reset));
VAR5 VAR5(
.out (out),
.clk (VAR7),
.in (VAR1),
.reset (re... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_2.behavioral.pp.v | 1,383 | module MODULE1( VAR2, VAR3, VAR1, VAR4, VAR9, VAR8, VAR7 );
input VAR2, VAR3, VAR1, VAR4;
inout VAR8, VAR7;
output VAR9;
VAR10 VAR5(.VAR2(VAR2),.VAR3(VAR3),.VAR1(VAR1),.VAR4(VAR4),.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7));
VAR10 VAR6(.VAR2(VAR2),.VAR3(VAR3),.VAR1(VAR1),.VAR4(VAR4),.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_cos_s5.v | 1,180 | module MODULE1 (
enable,
VAR9,
VAR5,
VAR8);
input enable;
input VAR9;
input [31:0] VAR5;
output [31:0] VAR8;
wire [31:0] VAR4;
wire [31:0] VAR8 = VAR4[31:0];
VAR6 VAR2 (
.en (enable),
.VAR3(1'b0),
.clk(VAR9),
.VAR1(VAR5),
.VAR7(VAR4));
endmodule | mit |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_auto_pc_1/synth/image_processing_2d_design_auto_pc_1.v | 12,869 | module MODULE1 (
VAR70,
VAR10,
VAR17,
VAR89,
VAR28,
VAR76,
VAR80,
VAR36,
VAR61,
VAR41,
VAR7,
VAR110,
VAR111,
VAR21,
VAR107,
VAR50,
VAR34,
VAR65,
VAR113,
VAR23,
VAR39,
VAR106,
VAR54,
VAR73,
VAR109,
VAR47,
VAR46,
VAR12,
VAR81,
VAR9,
VAR59,
VAR93,
VAR25,
VAR53,
VAR55,
VAR18,
VAR88,
VAR102,
VAR68,
VAR62,
VAR92,
VAR31,
VAR7... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/reset_controller.v | 4,517 | module MODULE1
(
input VAR8,
input VAR6,
output VAR13,
output VAR22,
output VAR12,
input VAR21,
input VAR15,
input VAR7);
localparam VAR10 = VAR17(VAR1);
localparam VAR3 = 1 << VAR10;
reg [2:0] VAR19,VAR19;
wire [VAR10:0] VAR11;
assign VAR13 = VAR19[0];
assign VAR22 = VAR19[1] & VAR7;
assign VAR12 = VAR19[2];
counter
.... | gpl-3.0 |
osresearch/vst | fpga/dac.v | 1,302 | module MODULE1(
output VAR17,
output VAR7,
output VAR5, output VAR16, output VAR4 );
wire reset = 0;
wire VAR27, clk = VAR27;
VAR31 VAR30(1,1,VAR27);
reg [11:0] VAR23;
reg [11:0] VAR24;
reg VAR20;
wire VAR15;
wire VAR8;
wire [11:0] VAR6;
wire [11:0] VAR2;
reg VAR22;
wire VAR9;
VAR21 #(.VAR14(12)) VAR1(
.clk(clk),
.rese... | gpl-2.0 |
Digilent/vivado-library | ip/Pmods/PmodAD1_v1_0/hdl/PmodAD1_v1_0.v | 4,978 | module MODULE1 #
(
parameter VAR70 = 0,
parameter VAR38 = 20, parameter VAR66 = 60, parameter VAR20 = 500, parameter VAR68 = 400,
parameter integer VAR50 = 32,
parameter integer VAR62 = 4
)
(
input VAR53,
output VAR89,
output VAR56,
input VAR101,
output VAR102,
output VAR34,
input VAR76,
output VAR78,
output VAR10,
inp... | mit |
mistryalok/Zedboard | learning/training/MSD/s07v2/vivado/project_2/project_2.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v | 2,057 | module MODULE1
(VAR7,
VAR17,
VAR10,
VAR6,
VAR11,
VAR1,
VAR8,
VAR14,
VAR15,
VAR3,
VAR16,
VAR5,
VAR2,
VAR4,
VAR9);
input VAR7;
input VAR17;
input [7:0]VAR10;
output [31:0]VAR6;
output VAR11;
input VAR1;
output [3:0]VAR8;
output VAR14;
input [31:0]VAR15;
input VAR3;
output VAR16;
input [3:0]VAR5;
input VAR2;
input VAR4;
i... | gpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_SRAM_TT_210930.v | 231,432 | module MODULE1 (VAR9, VAR3, VAR1, VAR7, VAR4);
output VAR9;
input VAR3, VAR1, VAR7, VAR4;
wire VAR2, VAR5, VAR8;
wire VAR11, VAR10, VAR6;
not (VAR11, VAR4);
not (VAR8, VAR7);
not (VAR5, VAR1);
and (VAR10, VAR5, VAR8);
not (VAR2, VAR3);
and (VAR6, VAR2, VAR8);
or (VAR9, VAR6, VAR10, VAR11); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcin/sky130_fd_sc_ls__fahcin.pp.symbol.v | 1,325 | module MODULE1 (
input VAR2 ,
input VAR5 ,
input VAR4 ,
output VAR8,
output VAR7 ,
input VAR1 ,
input VAR9,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/altera_avalon_st_bytes_to_packets.v | 8,099 | module MODULE1
parameter VAR12 = 0 )
(
input clk,
input VAR4,
input VAR9,
output reg VAR7,
output reg [7: 0] VAR21,
output reg [VAR19-1: 0] VAR18,
output reg VAR20,
output reg VAR5,
output reg VAR16,
input VAR3,
input [7: 0] VAR6
);
reg VAR17, VAR2, VAR13;
wire VAR11, VAR8, VAR10, VAR14, VAR1;
wire [7:0] VAR15;
assign ... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_pipe_misc.v | 10,197 | module MODULE1 #
(
parameter VAR1 = 100,
parameter VAR31 = 0 ) (
input wire VAR5 , input wire VAR24 , input wire [1:0] VAR4 , input wire VAR11 , input wire [2:0] VAR9 , input wire VAR36 , input wire [5:0] VAR25 , input wire [5:0] VAR21 , output wire VAR23 , output wire VAR10 , output wire [1:0] VAR17 , output wire VAR3... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/alu_my.v | 331,119 | module MODULE1 (VAR7,VAR6,VAR3,VAR4,VAR2,VAR5,VAR8);
output [0:127] VAR5;
input [0:127] VAR7;
input [0:127] VAR6;
input [0:2] VAR3;
input [0:1] VAR4;
input [0:4] VAR2;
input [15:0] VAR8;
parameter VAR1 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR5;
always @(VAR7 or VAR6 or VAR3 or VAR4 or VAR2 or VAR8)
begi... | mit |
niketancm/tsea26 | lab2-3/rtl/mac_scale.v | 1,488 | module MODULE1
(input wire signed [39:0] VAR3,
input wire [2:0] VAR4,
output wire VAR2,
output reg [39:0] VAR6);
reg VAR5;
reg VAR1;
assign VAR2 = VAR1 | VAR5;
always@(*) begin
VAR5 = 0;
VAR1 = 0;
case (VAR4)
3'b000: begin
VAR6=VAR3; end
3'b001: begin
VAR6=VAR3 << 1; VAR5 = ~VAR3[39] & VAR3[38];
VAR1 = VAR3[39] & ~VAR3... | gpl-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_alex_v1_0/axis_alex.v | 2,028 | module MODULE1
(
input wire VAR7,
input wire VAR10,
output wire [3:0] VAR14,
output wire VAR9,
input wire [31:0] VAR16,
input wire VAR12
);
reg [15:0] VAR6, VAR3;
reg [11:0] VAR1, VAR11;
reg [1:0] VAR5, VAR4;
reg VAR15, VAR8;
reg VAR2, VAR13;
always @(posedge VAR7)
begin
if(~VAR10)
begin
VAR6 <= 16'd0;
VAR1 <= 12'd0;
V... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/verilog/ANN_ddiv_64ns_64ns_64_31.v | 1,903 | module MODULE1
VAR11 = 7,
VAR16 = 31,
VAR6 = 64,
VAR5 = 64,
VAR23 = 64
)(
input wire clk,
input wire reset,
input wire VAR2,
input wire [VAR6-1:0] VAR27,
input wire [VAR5-1:0] VAR21,
output wire [VAR23-1:0] dout
);
wire VAR12;
wire VAR17;
wire VAR7;
wire [63:0] VAR8;
wire VAR18;
wire [63:0] VAR24;
wire VAR10;
wire [63:... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.behavioral.pp.v | 1,561 | module MODULE1( VAR8, VAR2, VAR9, VAR7, VAR3, VAR4 );
input VAR7, VAR9, VAR8;
inout VAR3, VAR4;
output VAR2;
VAR5 VAR6(.VAR8(VAR8),.VAR2(VAR2),.VAR9(VAR9),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4));
VAR5 VAR1(.VAR8(VAR8),.VAR2(VAR2),.VAR9(VAR9),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_schmitt.v | 1,359 | module MODULE1(
out,
in,
VAR1 );
output out;
input in;
inout VAR1;
wire out = in;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221a/sky130_fd_sc_hdll__o221a.symbol.v | 1,402 | module MODULE1 (
input VAR6,
input VAR10,
input VAR2,
input VAR8,
input VAR1,
output VAR3
);
supply1 VAR4;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a.pp.symbol.v | 1,344 | module MODULE1 (
input VAR8 ,
input VAR5 ,
input VAR3 ,
output VAR4 ,
input VAR1 ,
input VAR7,
input VAR2,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi.behavioral.pp.v | 2,038 | module MODULE1 (
VAR17 ,
VAR4 ,
VAR13 ,
VAR10 ,
VAR8 ,
VAR11,
VAR15,
VAR1 ,
VAR5
);
output VAR17 ;
input VAR4 ;
input VAR13 ;
input VAR10 ;
input VAR8 ;
input VAR11;
input VAR15;
input VAR1 ;
input VAR5 ;
wire VAR12 ;
wire VAR16 ;
wire VAR2;
and VAR6 (VAR12 , VAR10, VAR4, VAR13 );
nor VAR7 (VAR16 , VAR8, VAR12 );
VAR3 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlrtp/sky130_fd_sc_lp__srdlrtp.functional.v | 1,861 | module MODULE1 (
VAR8 ,
VAR3,
VAR13 ,
VAR9 ,
VAR14
);
output VAR8 ;
input VAR3;
input VAR13 ;
input VAR9 ;
input VAR14;
wire VAR6;
wire VAR4;
wire VAR5;
wire VAR15 ;
wire VAR12 ;
not VAR7 (VAR4 , VAR3 );
VAR10 VAR1 VAR2 (VAR6 , VAR13, VAR9, VAR4, VAR14, VAR5, VAR15, VAR12);
bufif1 VAR11 (VAR8 , VAR6, VAR12 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_alt_ddrx_controller_wrapper.v | 17,925 | module MODULE1 (
VAR39,
VAR59,
VAR50,
VAR35,
VAR109,
VAR67,
VAR13,
VAR26,
VAR36,
VAR85,
VAR74,
VAR30,
VAR48,
VAR83,
VAR64,
VAR80,
VAR73,
VAR58,
VAR37,
VAR111,
VAR103,
VAR70,
VAR54,
VAR105,
VAR4,
VAR110,
VAR41,
VAR69,
VAR98,
VAR63,
VAR52,
VAR49,
VAR77,
VAR27,
VAR53,
VAR100,
VAR81,
VAR32,
VAR116,
VAR97,
VAR31,
VAR43,
VAR... | gpl-3.0 |
cospan/prometheus_fpga | rtl/slave_fifo/prometheus_fx3_stream_out.v | 3,559 | module MODULE1(
input VAR14,
input VAR4,
input VAR10,
input VAR9,
input VAR13,
input [31:0]VAR1,
output VAR11,
output VAR16
);
reg [2:0]VAR6;
reg [2:0]VAR2;
parameter [2:0] VAR5 = 3'd0;
parameter [2:0] VAR7 = 3'd1;
parameter [2:0] VAR15 = 3'd2;
parameter [2:0] VAR8 = 3'd3;
parameter [2:0] VAR18 = 3'd4;
parameter [2:0] ... | gpl-3.0 |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/new/tia.v | 16,461 | module MODULE2(VAR7, VAR126, VAR48, VAR100, VAR108, VAR84, VAR61, VAR62, VAR67, VAR116, VAR50, VAR101, VAR68, VAR46, VAR19, VAR70, VAR45, VAR3, VAR9, VAR17, VAR93); input [5:0] VAR7;
input [7:0] VAR126;
output [7:0] VAR48;
input [2:0] VAR100;
input VAR108;
input VAR84;
output VAR61;
input VAR62;
input VAR67;
input [1:0... | gpl-2.0 |
titorgalaxy/Titor | rtl/verilog/chardev/Character_Map.v | 30,790 | module MODULE1 (
VAR3,
VAR7,
VAR4,
VAR10,
reset,
clk
);
input [VAR12-1:0] VAR3;
input [VAR5-1:0] VAR7;
input [VAR5-1:0] VAR4;
output VAR10;
input reset;
input clk;
reg [VAR5-1:0] VAR11;
reg [VAR5-1:0] VAR6;
assign VAR10 = VAR11[VAR6];
wire VAR13 =
(VAR3 >= VAR2) && (VAR3 < VAR9) && (VAR7 >= 0) && (VAR7 < VAR1) && (VAR4... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/gpmc/fifo_to_gpmc.v | 5,988 | module MODULE1
(input clk, input reset, input VAR2, input VAR38,
input [17:0] VAR35, input VAR6, output VAR45,
output [15:0] VAR44, input [VAR33:1] VAR16, input VAR1, input VAR24,
output reg VAR28);
wire [17:0] VAR14;
reg VAR30;
reg [VAR33:1] addr;
reg [VAR32:0] VAR19, VAR11;
localparam VAR25 = 0;
localparam VAR29 = 1;... | gpl-2.0 |
aj-michael/Digital-Systems | HammingCodes/NewHammingDecoder.v | 1,423 | module MODULE1(VAR2, VAR1);
input [6:0] VAR2;
output [3:0] VAR1;
assign VAR1[3] = (VAR2[6]^VAR2[5]^VAR2[4]^VAR2[2])&(VAR2[6]^VAR2[5]^VAR2[3]^VAR2[1])&(VAR2[6]^VAR2[4]^VAR2[3]^VAR2[0]) ? ~VAR2[6] : VAR2[6];
assign VAR1[2] = (VAR2[6]^VAR2[5]^VAR2[4]^VAR2[2])&(VAR2[6]^VAR2[5]^VAR2[3]^VAR2[1])&!(VAR2[6]^VAR2[4]^VAR2[3]^VAR... | mit |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_ll_bridge.v | 2,439 | module MODULE1 #
(
parameter VAR11 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR11-1:0] VAR9,
input wire VAR8,
output wire VAR7,
input wire VAR5,
output wire [VAR11-1:0] VAR3,
output wire VAR6,
output wire VAR12,
output wire VAR1,
input wire VAR4
);
reg VAR2 = 1'b1;
always @(posedge clk) begin
if (rst) begin
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputisolatch/sky130_fd_sc_lp__inputisolatch.functional.v | 1,641 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR9
);
output VAR6 ;
input VAR10 ;
input VAR9;
wire VAR3 ;
wire VAR5;
wire VAR1 ;
VAR7 VAR2 VAR4 (VAR3 , VAR10, VAR9 );
buf VAR8 (VAR6 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi.functional.pp.v | 2,164 | module MODULE1 (
VAR12 ,
VAR15 ,
VAR1 ,
VAR9 ,
VAR2 ,
VAR8,
VAR5,
VAR7 ,
VAR19
);
output VAR12 ;
input VAR15 ;
input VAR1 ;
input VAR9 ;
input VAR2 ;
input VAR8;
input VAR5;
input VAR7 ;
input VAR19 ;
wire VAR18 ;
wire VAR4 ;
wire VAR17 ;
wire VAR10;
nand VAR14 (VAR18 , VAR1, VAR15 );
nand VAR11 (VAR4 , VAR2, VAR9 );
a... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2.pp.symbol.v | 1,269 | module MODULE1 (
input VAR6 ,
input VAR7 ,
output VAR1 ,
input VAR4 ,
input VAR3,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp.functional.pp.v | 2,774 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR20 ,
VAR8 ,
VAR26 ,
VAR12 ,
VAR15,
VAR22 ,
VAR7 ,
VAR1 ,
VAR11
);
output VAR4 ;
output VAR5 ;
input VAR20 ;
input VAR8 ;
input VAR26 ;
input VAR12 ;
input VAR15;
input VAR22 ;
input VAR7 ;
input VAR1 ;
input VAR11 ;
wire VAR21 ;
wire VAR24 ;
wire VAR17 ;
wire VAR18 ;
wire VAR9;
not VAR... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/acl_int_div64s.v | 4,801 | module MODULE1 (
enable,
VAR17,
VAR23,
VAR8,
VAR19,
VAR4);
input enable;
input VAR17;
input [63:0] VAR23;
input [63:0] VAR8;
output [63:0] VAR19;
output [63:0] VAR4;
wire [63:0] VAR18;
wire [63:0] VAR6;
wire [63:0] VAR4 = VAR18[63:0];
wire [63:0] VAR19 = VAR6[63:0];
VAR2 VAR1 (
.VAR17 (VAR17),
.VAR20 (enable),
.VAR23 (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s.pp.symbol.v | 1,325 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_cuvz.v | 8,197 | module MODULE1(
VAR26, VAR42,
VAR50, VAR3,
VAR36,
VAR25, VAR41,
VAR56, VAR8, VAR22, VAR60,
VAR51,
VAR58, VAR6, VAR18,
VAR31,
VAR49, VAR10, VAR57, VAR12, VAR40, VAR48,
VAR11, VAR47,
VAR59, VAR19, VAR53,
VAR32,
VAR20, VAR15,
VAR28, VAR37, VAR9, VAR43,
VAR30
);
parameter VAR1 = 16;
input VAR26;
input VAR42;
input VAR50;
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2_2.v | 2,102 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR9,
VAR3,
VAR7 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR9;
input VAR3;
input VAR7 ;
input VAR1 ;
VAR4 VAR8 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5,
VAR6,
VAR2
);
output VAR5;
... | apache-2.0 |
asicguy/gplgpu | hdl/de_temp/dex_top.v | 19,370 | module MODULE1
(
input VAR5, input VAR90, input VAR148, input [31:0] VAR13, input [31:0] VAR155, input [3:0] VAR87, input [3:0] VAR122, input [3:0] VAR124, input [3:0] VAR62, input VAR9, input VAR17, input VAR60, input VAR102, input [1:0] VAR98, input [1:0] VAR118, input VAR21, input VAR100, input VAR20, input VAR23, i... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/buffers/fifoRTL.v | 6,145 | module MODULE1(VAR27, VAR10, VAR20, VAR12, VAR17,
VAR6, VAR23, VAR9, VAR22, VAR24,
VAR11, VAR7, VAR13);
parameter VAR15 = 8;
parameter VAR5 = 64;
parameter VAR16 = 6;
input VAR27;
input VAR20;
input [VAR15-1:0] VAR17;
input VAR23;
input VAR11;
output VAR22;
input VAR10;
input VAR12;
output [VAR15-1:0] VAR6;
input VAR9;... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_1.functional.pp.v | 1,702 | module MODULE1( VAR15, VAR5, VAR9, VAR12, VAR4, VAR8, VAR3, VAR17 );
input VAR8, VAR4, VAR5, VAR15, VAR9;
inout VAR3, VAR17;
output VAR12;
wire VAR16;
not VAR6( VAR16, VAR8 );
wire VAR10;
not VAR11( VAR10, VAR4 );
wire VAR1;
and VAR22( VAR1, VAR16, VAR10 );
wire VAR18;
not VAR2( VAR18, VAR5 );
wire VAR19;
not VAR7( VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf.pp.symbol.v | 1,262 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR3 ,
input VAR1,
input VAR6,
input VAR4
);
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController/src/user_top.v | 35,041 | module MODULE1 # (
parameter VAR238 = 32,
parameter VAR364 = 32,
parameter VAR276 = 32'h80000000,
parameter VAR9 = 32'h80010000,
parameter VAR353 = 32,
parameter VAR68 = 64,
parameter VAR451 = 1,
parameter VAR455 = 1,
parameter VAR310 = 1,
parameter VAR199 = 1,
parameter VAR245 = 1,
parameter VAR389 = 1,
parameter VAR4... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch3/FPU_ADD_Substract_PIPELINED.v | 24,268 | module MODULE1
/*#(parameter VAR114 = 32, parameter VAR102 = 8, parameter VAR144 = 23,
parameter VAR59=26, parameter VAR189 = 5)
parameter VAR59 = 55, parameter VAR189 = 6) (
input wire clk,
input wire rst,
input wire VAR110,
input wire [VAR114-1:0] VAR141,
input wire [VAR114-1:0] VAR131,
input wire VAR150,
output wire... | gpl-3.0 |
plindstroem/oh | elink/hdl/elink.v | 11,108 | module MODULE1(
VAR43, VAR34, VAR78, VAR25,
VAR44, VAR1, VAR70, VAR12, VAR9,
VAR57, VAR40, VAR68, VAR31, VAR26,
VAR56, VAR39, VAR16, VAR18, VAR64,
VAR35, VAR46, VAR55, VAR89, VAR86,
timeout,
reset, VAR52, VAR29, VAR47, VAR32, VAR2,
VAR83, VAR8, VAR81, VAR42,
VAR72, VAR48, VAR10, VAR69, VAR65,
VAR82, VAR54, VAR17, VAR38... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_dac_if.v | 18,082 | module MODULE1 (
VAR99,
VAR79,
VAR141,
VAR85,
VAR3,
VAR57,
VAR67,
VAR187,
VAR25,
VAR133,
VAR117,
VAR4,
VAR62,
VAR44,
VAR81,
VAR158,
VAR52,
VAR131,
VAR122,
VAR55,
VAR142,
VAR61,
VAR128,
VAR169,
VAR23,
VAR127,
VAR6);
parameter VAR54 = 0;
parameter VAR153 = 0;
parameter VAR164 = 1;
parameter VAR163 = 1.667;
parameter VAR1... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/7cc4809675563003/ip_design_zed_audio_ctrl_0_0_stub.v | 2,366 | module MODULE1(VAR13, VAR23, VAR19, VAR3, VAR16,
VAR20, VAR12, VAR17, VAR18, VAR4, VAR9,
VAR5, VAR7, VAR21, VAR22, VAR2, VAR6,
VAR8, VAR1, VAR15, VAR11, VAR10, VAR14)
;
output VAR13;
output VAR23;
input VAR19;
output VAR3;
input VAR16;
input VAR20;
input [31:0]VAR12;
input VAR17;
input [31:0]VAR18;
input [3:0]VAR4;
inp... | mit |
asicguy/gplgpu | hdl/math/flt2int.v | 3,117 | module MODULE1
(
input clk,
input [31:0] VAR2,
output reg [15:0] VAR3
);
reg [14:0] VAR4;
always @* begin
end
if(VAR2[30:23] == 8'h7f) VAR4 = 16'h1; else begin
casex(VAR2[30:23])
8'VAR1: VAR4 = 15'h0; 8'b10000000: VAR4 = {14'h1, VAR2[22]}; 8'b10000001: VAR4 = {13'h1, VAR2[22:21]}; 8'b10000010: VAR4 = {12'h1, VAR2[22:20... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b.pp.symbol.v | 1,324 | module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR3 ,
input VAR6 ,
output VAR5 ,
input VAR4 ,
input VAR9,
input VAR1,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o.behavioral.v | 1,585 | module MODULE1 (
VAR7 ,
VAR4,
VAR12,
VAR11,
VAR9,
VAR6
);
output VAR7 ;
input VAR4;
input VAR12;
input VAR11;
input VAR9;
input VAR6;
supply1 VAR1;
supply0 VAR13;
supply1 VAR14 ;
supply0 VAR5 ;
wire VAR3 ;
wire VAR10;
and VAR2 (VAR3 , VAR4, VAR12 );
or VAR8 (VAR10, VAR9, VAR11, VAR3, VAR6);
buf VAR15 (VAR7 , VAR10 );
e... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_gsu/gsu_mult.v | 4,386 | module MODULE1 (
VAR13,
VAR17,
VAR15);
input [7:0] VAR13;
input [7:0] VAR17;
output [15:0] VAR15;
wire [15:0] VAR4;
wire [15:0] VAR15 = VAR4[15:0];
VAR8 VAR16 (
.VAR13 (VAR13),
.VAR17 (VAR17),
.VAR15 (VAR4),
.VAR2 (1'b0),
.VAR10 (1'b1),
.VAR5 (1'b0),
.VAR19 (1'b0),
.sum (1'b0));
VAR16.VAR18 = "VAR9=5",
VAR16.VAR11 = "... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp.behavioral.pp.v | 2,884 | module MODULE1 (
VAR31 ,
VAR16 ,
VAR10 ,
VAR2 ,
VAR19 ,
VAR24,
VAR27 ,
VAR23 ,
VAR9 ,
VAR17
);
output VAR31 ;
input VAR16 ;
input VAR10 ;
input VAR2 ;
input VAR19 ;
input VAR24;
input VAR27 ;
input VAR23 ;
input VAR9 ;
input VAR17 ;
wire VAR15 ;
wire VAR4 ;
wire VAR28 ;
reg VAR5 ;
wire VAR12 ;
wire VAR21 ;
wire VAR13 ;... | apache-2.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkGPR_RegFile.v | 6,954 | module MODULE1(VAR55,
VAR26,
VAR3,
VAR29,
VAR2,
VAR73,
VAR64,
VAR23,
VAR68,
VAR53,
VAR25,
VAR20,
VAR70,
VAR72,
VAR15);
input VAR55;
input VAR26;
input VAR3;
output VAR29;
input VAR2;
output VAR73;
input [4 : 0] VAR64;
output [63 : 0] VAR23;
input [4 : 0] VAR68;
output [63 : 0] VAR53;
input [4 : 0] VAR25;
output [63 : 0... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ui/ui_rd_data.v | 18,401 | module MODULE1 #
(
parameter VAR59 = 100,
parameter VAR96 = 256,
parameter VAR80 = "VAR6",
parameter VAR46 = "VAR75"
)
(
VAR18, VAR14, VAR61, VAR26,
VAR42, VAR81, VAR55, VAR1,
rst, clk, VAR90, VAR72, VAR25, VAR82,
VAR34, VAR95, VAR8
);
input rst;
input clk;
output wire VAR18;
output wire [3:0] VAR14;
reg [5:0] VAR19;
r... | lgpl-3.0 |
ffu/DSA-3.2.2 | usrp/fpga/sdr_lib/phase_acc.v | 1,628 | module MODULE1 (clk,reset,enable,VAR9,VAR5,VAR8,VAR1,VAR4);
parameter VAR11 = 0;
parameter VAR7 = 0;
parameter VAR6 = 32;
input clk, reset, enable, VAR9;
input [6:0] VAR5;
input [31:0] VAR8;
input VAR1;
output reg [VAR6-1:0] VAR4;
wire [VAR6-1:0] VAR3;
VAR12 #(VAR11) VAR2(.VAR10(clk),.reset(1'b0),.VAR9(VAR1),.addr(VAR5... | gpl-3.0 |
cr88192/bgbtech_bjx1core | srvcore/GpReg.v | 5,867 | parameter[5:0] VAR5 = 6'h00;
parameter[5:0] VAR23 = 6'h0F;
parameter[5:0] VAR27 = 6'h20;
parameter[5:0] VAR19 = 6'h2F;
parameter[5:0] VAR29 = 6'h30;
parameter[5:0] VAR42 = 6'h3F;
parameter[6:0] VAR35 = 7'h00;
parameter[6:0] VAR43 = 7'h0F;
parameter[6:0] VAR34 = 7'h20;
parameter[6:0] VAR21 = 7'h2F;
parameter[6:0] VAR47 ... | mit |
trnewman/VT-USRP-daughterboard-drivers_python | gr-sounder/src/fpga/lib/sounder_rx.v | 2,658 | module MODULE1(VAR22,VAR21,VAR23,VAR13,VAR27,
VAR14,VAR30,VAR8,VAR26,VAR16,VAR28);
input VAR22; input VAR21; input VAR23; input VAR13; input VAR27;
input [15:0] VAR14; input [4:0] VAR30;
input [15:0] VAR8; input [15:0] VAR26;
output [15:0] VAR16; output [15:0] VAR28;
reg [31:0] VAR6, VAR12;
reg [31:0] VAR19, VAR3;
wire... | gpl-3.0 |
mlab/pvs | hdl_harness/async_transmitter.v | 2,589 | module MODULE1(clk, VAR11, VAR5, VAR9, VAR2);
input clk, VAR11;
input [7:0] VAR5;
output VAR9, VAR2;
parameter VAR12 = 50000000; parameter VAR8 = 115200;
parameter VAR7 = 1;
parameter VAR15 = 16;
reg [VAR15:0] VAR6;
wire [VAR15:0] VAR14 = 17'h10000;
wire [VAR15:0] VAR14 = ((VAR8<<(VAR15-4))+(VAR12>>5))/(VAR12>>4);
wire... | gpl-3.0 |
htuNCSU/MmcCommunicationVerilog | MAX10_SLAVE/freedm_bus_slave/fb_slave_counters.v | 6,829 | module MODULE1 (VAR26, VAR12, VAR17, VAR19, VAR42, VAR31, VAR24,
VAR40, VAR7, VAR13, VAR3, VAR48, VAR11, VAR15,
VAR5, VAR45, VAR23, VAR46, VAR36,
VAR51, VAR27, VAR2, VAR39, VAR35, VAR8, VAR32
);
input VAR26; input VAR12;
input VAR17; input VAR19;
input VAR42;
input VAR31;
input VAR24;
input VAR40; input VAR7; input VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3_4.v | 2,184 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR4 ,
VAR2 ,
VAR6,
VAR10,
VAR5 ,
VAR3
);
output VAR9 ;
input VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR6;
input VAR10;
input VAR5 ;
input VAR3 ;
VAR8 VAR7 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/altera_up_av_config_auto_init_ob_de2_35.v | 7,573 | module MODULE1 (
VAR21,
VAR11
);
parameter VAR17 = 9'h01A;
parameter VAR2 = 9'h01A;
parameter VAR16 = 9'h07B;
parameter VAR13 = 9'h07B;
parameter VAR14 = 9'h0F8;
parameter VAR15 = 9'h006;
parameter VAR18 = 9'h000;
parameter VAR8 = 9'h001;
parameter VAR9 = 9'h002;
parameter VAR4 = 9'h001;
parameter VAR22 = 16'h0040;
par... | gpl-2.0 |
kernelpanics/Grad | Expanded-Hyperbolic-CORDIC/Verilog/Exponential/Coprocesador_CORDIC.v | 8,449 | module MODULE1#(parameter VAR101 = 32, parameter VAR55=8, parameter VAR43=5, parameter VAR15 = 8,
parameter VAR36 = 23, parameter VAR108 = 9) (
input wire [31:0] VAR92,
input wire VAR44, input wire VAR86, input wire VAR105, input wire VAR80, input wire VAR29, input wire VAR16, input wire VAR13, input wire VAR76, input ... | gpl-3.0 |
TUM-LIS/faultify | hardware/base_system/xpsLibraryPath/libFaultify/pcores/faultify_axi_wrapper_v1_00_a/hdl/verilog/cut_wrapper.v | 9,487 | module MODULE1 (
clk,
rst,
VAR200,
VAR110,
VAR3
);
input clk;
input rst;
input[31:0] VAR200;
output[53:0] VAR110;
input[215:0] VAR3;
VAR77 VAR109 (
.VAR46(clk),
.reset(rst),
.addr(VAR110 [19:0]),
.VAR213(VAR200 [31:0]),
.VAR174(VAR110 [51:20]),
.rd(VAR110[52]),
.wr(VAR110[53]),
.VAR223(VAR3[0]),
.VAR184(VAR3[1]),
.VAR1... | gpl-2.0 |
m-labs/milkymist | cores/tmu2/rtl/tmu2_vdivops.v | 2,509 | module MODULE1(
input VAR24,
input VAR17,
output VAR2,
input VAR9,
output VAR25,
input signed [17:0] VAR26,
input signed [17:0] VAR22,
input signed [17:0] VAR16,
input signed [17:0] VAR15,
input signed [17:0] VAR18,
input signed [17:0] VAR13,
input signed [17:0] VAR6,
input signed [17:0] VAR5,
input signed [11:0] VAR20... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver2/sky130_fd_sc_lp__busdriver2.functional.pp.v | 1,887 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR8,
VAR5,
VAR2,
VAR6 ,
VAR13
);
output VAR9 ;
input VAR7 ;
input VAR8;
input VAR5;
input VAR2;
input VAR6 ;
input VAR13 ;
wire VAR11 ;
wire VAR10;
VAR4 VAR3 (VAR11 , VAR7, VAR5, VAR2 );
VAR4 VAR1 (VAR10, VAR8, VAR5, VAR2 );
bufif0 VAR12 (VAR9 , VAR11, VAR10);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor3/sky130_fd_sc_ls__xor3.behavioral.v | 1,406 | module MODULE1 (
VAR2,
VAR4,
VAR8,
VAR7
);
output VAR2;
input VAR4;
input VAR8;
input VAR7;
supply1 VAR11;
supply0 VAR10;
supply1 VAR3 ;
supply0 VAR6 ;
wire VAR5;
xor VAR1 (VAR5, VAR4, VAR8, VAR7 );
buf VAR9 (VAR2 , VAR5 );
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/prcfg/bist/prcfg_dac.v | 6,537 | module MODULE1(
clk,
VAR15,
VAR4,
VAR16,
VAR17,
VAR8,
VAR12,
VAR5,
VAR1
);
localparam VAR2 = 8'hA1;
parameter VAR10 = 0;
input clk;
input [31:0] VAR15;
output [31:0] VAR4;
output VAR16;
input [15:0] VAR17;
output VAR8;
input VAR12;
output [15:0] VAR5;
input VAR1;
reg [15:0] VAR5 = 0;
reg VAR8 = 0;
reg VAR16 = 0;
reg [1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi.behavioral.v | 1,686 | module MODULE1 (
VAR13 ,
VAR14,
VAR6,
VAR4,
VAR2,
VAR15
);
output VAR13 ;
input VAR14;
input VAR6;
input VAR4;
input VAR2;
input VAR15;
supply1 VAR16;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR3 ;
wire VAR5 ;
wire VAR11 ;
wire VAR17;
and VAR8 (VAR5 , VAR4, VAR2 );
and VAR10 (VAR11 , VAR14, VAR6 );
nor VAR7 (VAR17, VAR5, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn.pp.blackbox.v | 1,287 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR2,
VAR1,
VAR4,
VAR5 ,
VAR3
);
output VAR6 ;
input VAR7 ;
input VAR2;
input VAR1;
input VAR4;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkTLB.v | 30,889 | module MODULE1(VAR37,
VAR122,
VAR147,
VAR90,
VAR49,
VAR80,
VAR154,
VAR85,
VAR101,
VAR21,
VAR189,
VAR27,
VAR44,
VAR173,
VAR200);
parameter [0 : 0] VAR140 = 1'b0;
input VAR37;
input VAR122;
input VAR147;
output VAR90;
input [15 : 0] VAR49;
input [26 : 0] VAR80;
output [130 : 0] VAR154;
output VAR85;
input [15 : 0] VAR101... | apache-2.0 |
jeffkub/n64-cart-reader | old/n64cartridge/src/sdram/autorefresh_counter.v | 5,634 | module MODULE1(
input VAR6,
input VAR2,
input VAR8,
output reg VAR4);
generate
if (VAR3 == 2000) begin
reg [10:0] VAR1;
wire VAR5,VAR7;
xnor(VAR5,VAR1[10],VAR1[8]);
assign VAR7 = (VAR1 == 11'h5D3);
always @(posedge VAR6,posedge VAR2) begin
if(VAR2) begin
VAR1 <= 0;
VAR4 <= 0;
end
else begin
if(VAR8)
VAR1 <= VAR7 ? 11'h... | mit |
Canaan-Creative/MM | verilog/superkdf9/soc/superkdf9.v | 3,653 | module MODULE1 (
input wire clk, rst
,output wire [3:0] VAR46
,input wire [31:0] VAR88
,output wire [10:0] VAR24
,output wire [31:0] VAR36
,output wire [31:0] VAR82
,input wire [31:0] VAR51
,input wire VAR14
,output wire VAR17
);
wire [31:0] VAR3, VAR71;
wire [31:0] VAR35, VAR86 ;
wire VAR56, VAR70;
wire VAR62, VAR79;
... | unlicense |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_cpu_jtag_debug_module_tck.v | 8,246 | module MODULE1 (
VAR26,
VAR39,
VAR36,
VAR29,
VAR18,
VAR13,
VAR1,
VAR19,
VAR14,
VAR8,
VAR28,
VAR10,
VAR30,
VAR40,
VAR21,
VAR31,
VAR35,
VAR11,
VAR20,
VAR37,
VAR2,
VAR5,
VAR7,
VAR24,
VAR17,
VAR23,
VAR12,
VAR15,
VAR22,
VAR38,
VAR9
)
;
output [ 1: 0] VAR12;
output VAR15;
output [ 37: 0] VAR22;
output VAR38;
output VAR9;
inp... | mit |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_rx/MAC_rx_add_chk.v | 6,743 | module MODULE1 (
VAR20 ,
VAR3 ,
VAR6 ,
VAR15 ,
VAR22 ,
VAR16 ,
VAR10 ,
VAR28 ,
VAR11 ,
VAR19
);
input VAR20 ;
input VAR3 ;
input VAR6 ;
input [7:0] VAR15 ;
input VAR22 ;
output VAR16 ;
input VAR10 ;
input [7:0] VAR28 ;
input [2:0] VAR11 ;
input VAR19 ;
reg [2:0] VAR14;
wire[2:0] VAR5;
wire[7:0] din;
wire[7:0] dout;
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ebufn/sky130_fd_sc_ms__ebufn.behavioral.pp.v | 1,870 | module MODULE1 (
VAR12 ,
VAR5 ,
VAR3,
VAR6,
VAR1,
VAR4 ,
VAR2
);
output VAR12 ;
input VAR5 ;
input VAR3;
input VAR6;
input VAR1;
input VAR4 ;
input VAR2 ;
wire VAR9 ;
wire VAR8;
VAR7 VAR10 (VAR9 , VAR5, VAR6, VAR1 );
VAR7 VAR11 (VAR8, VAR3, VAR6, VAR1 );
bufif0 VAR13 (VAR12 , VAR9, VAR8);
endmodule | apache-2.0 |
CeesWolfs/ceespu | src/gpu/primitives/dvi_encoder.v | 5,448 | module MODULE1 (
input VAR60,
input VAR25,
input VAR23,
input VAR19,
input rst,
input [7:0] VAR8,
input [7:0] VAR50,
input [7:0] VAR65,
input VAR31,
input VAR4,
input VAR51,
output reg [3:0] VAR30,
output reg [3:0] VAR71
);
reg VAR53, VAR2 = 1'h0;
wire [1-1:0] VAR27;
reg [5-1:0] VAR54;
VAR67 VAR42 (
.VAR9(VAR23),
.VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a.symbol.v | 1,383 | module MODULE1 (
input VAR10,
input VAR3,
input VAR6,
input VAR2,
input VAR1,
output VAR8
);
supply1 VAR7;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai.functional.v | 1,555 | module MODULE1 (
VAR13 ,
VAR10,
VAR5,
VAR8,
VAR7,
VAR9
);
output VAR13 ;
input VAR10;
input VAR5;
input VAR8;
input VAR7;
input VAR9;
wire VAR3 ;
wire VAR2 ;
wire VAR1;
nor VAR4 (VAR3 , VAR8, VAR10, VAR5 );
nor VAR12 (VAR2 , VAR7, VAR9 );
or VAR11 (VAR1, VAR2, VAR3);
buf VAR6 (VAR13 , VAR1 );
endmodule | apache-2.0 |
chipsalliance/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/brams_final_map.v | 15,800 | module MODULE2 (VAR122, VAR64, VAR93, VAR98, VAR103, VAR76, VAR42, VAR105, VAR29, VAR57, VAR90, VAR109, VAR18, VAR100, VAR65, VAR45, VAR75, VAR62, VAR127, VAR126, VAR95, VAR111, VAR86, VAR31, VAR5, VAR26, VAR102, VAR129);
parameter VAR17 = 11;
parameter VAR132 = 18;
parameter VAR78 = 4;
parameter VAR123 = 4;
parameter ... | apache-2.0 |
petrmikheev/miksys | verilog/STARTUP.v | 6,455 | module MODULE1 (
address,
VAR51,
VAR47);
input [8:0] address;
input VAR51;
output [31:0] VAR47;
tri1 VAR51;
wire [31:0] VAR27;
wire [31:0] VAR47 = VAR27[31:0];
VAR30 VAR18 (
.VAR21 (address),
.VAR46 (VAR51),
.VAR29 (VAR27),
.VAR6 (1'b0),
.VAR3 (1'b0),
.VAR28 (1'b1),
.VAR12 (1'b0),
.VAR24 (1'b0),
.VAR45 (1'b1),
.VAR5 (1... | gpl-3.0 |
ad510/ee201l_cpu | Cpu.v | 3,736 | module MODULE1
(clk, reset, VAR12, ack, VAR21, VAR26, VAR15,
VAR11, VAR3, VAR18, VAR14, VAR9, VAR16, VAR17);
localparam VAR25 = 32, VAR19 = 8, VAR2 = 8;
input clk, reset, VAR12, ack;
input [(VAR25 - 1) : 0] VAR21;
input [3:0] VAR26;
input [7:0] VAR15;
output [(VAR19 - 1) : 0] VAR11; output VAR3;
output reg [7:0] VAR18;... | mit |
shaform/ArkanoidOnVerilog | draw_block.v | 2,037 | module MODULE1(
input VAR4,
input [10:0] VAR10,
input [11:0] VAR16,
input [2:0] VAR14,
output [4:0] VAR11, VAR9,
output reg [3:0] out
);
parameter VAR8 = 160;
parameter VAR2 = 0;
parameter VAR7 = 320;
parameter VAR1 = 480;
wire VAR12;
assign VAR12 = VAR16 >= VAR8 && VAR16 < VAR8+VAR7 && VAR10 >= VAR2 && VAR10 < VAR2+VA... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_096bits.v | 1,917 | module MODULE2 (
clk,
VAR20, VAR31, VAR18, VAR12, VAR2, VAR24, VAR23, VAR13,
sum,
);
input clk;
input [VAR17+0-1:0] VAR20, VAR31, VAR18, VAR12, VAR2, VAR24, VAR23, VAR13;
output [VAR17 :0] sum;
reg [VAR17 :0] sum;
wire [VAR17+3-1:0] VAR19;
wire [VAR17+2-1:0] VAR10, VAR4;
wire [VAR17+1-1:0] VAR3, VAR7, VAR11, VAR29;
reg... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio/sky130_fd_io__top_sio.blackbox.v | 2,529 | module MODULE1 (
VAR1 ,
VAR15,
VAR14 ,
VAR24 ,
VAR27 ,
VAR8 ,
VAR9 ,
VAR16 ,
VAR5 ,
VAR22 ,
VAR23 ,
VAR2 ,
VAR3 ,
VAR13 ,
VAR10 ,
VAR7 ,
VAR6,
VAR25 ,
VAR18 ,
VAR4 ,
VAR28
);
output VAR1 ;
inout VAR15;
inout VAR14 ;
input [2:0] VAR24 ;
input VAR27 ;
input VAR8 ;
output VAR9 ;
input VAR16 ;
input VAR5 ;
input VAR22 ;
in... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/spartan6/hpdmc_ddrio.v | 2,288 | module MODULE1(
input VAR21,
input VAR6,
input VAR40,
input VAR44,
input VAR47,
input VAR29,
input [7:0] VAR46,
input [63:0] do,
output [63:0] VAR19,
output [3:0] VAR8,
inout [31:0] VAR28,
inout [3:0] VAR45,
input VAR25,
input VAR20,
input VAR39
);
wire [31:0] VAR33;
wire [31:0] VAR38;
wire [31:0] VAR41;
VAR42 VAR34(
.... | lgpl-3.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.