repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.v | 2,477 | module MODULE1 (
VAR4 ,
VAR3,
VAR1,
VAR11 ,
VAR10 ,
VAR5,
VAR2,
VAR8 ,
VAR9
);
output VAR4 ;
input VAR3;
input VAR1;
input VAR11 ;
input VAR10 ;
input VAR5;
input VAR2;
input VAR8 ;
input VAR9 ;
VAR6 VAR7 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fa/sky130_fd_sc_hd__fa_1.v | 2,278 | module MODULE2 (
VAR4,
VAR5 ,
VAR10 ,
VAR2 ,
VAR7 ,
VAR6,
VAR9,
VAR1 ,
VAR11
);
output VAR4;
output VAR5 ;
input VAR10 ;
input VAR2 ;
input VAR7 ;
input VAR6;
input VAR9;
input VAR1 ;
input VAR11 ;
VAR3 VAR8 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR... | apache-2.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | src/uart_rx.v | 1,990 | module MODULE1 (
input clk,
input VAR3,
output reg VAR4 = 1'b0,
output reg [7:0] VAR2 = 8'd0
);
reg [5:0] VAR1 = 6'b111111;
reg [3:0] counter = 4'd0;
reg [3:0] state = 4'd0;
reg [8:0] VAR5 = 9'd0;
wire VAR8 = VAR1[5] & VAR1[4] & VAR1[3] & ~VAR1[2];
wire VAR6 = VAR1[5] & VAR1[4] & VAR1[3];
wire VAR7 = ~VAR1[5] & ~VAR1[4... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2.pp.blackbox.v | 1,266 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR3,
VAR7,
VAR4 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR3;
input VAR7;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41a/sky130_fd_sc_ms__o41a.symbol.v | 1,366 | module MODULE1 (
input VAR7,
input VAR3,
input VAR2,
input VAR1,
input VAR9,
output VAR8
);
supply1 VAR6;
supply0 VAR10;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram_sc_1_rep2.v | 5,330 | module MODULE1(
VAR22, VAR17,
VAR27, VAR35,
VAR16, VAR25,
VAR20, VAR34,
VAR7, VAR24, VAR21,
VAR2, VAR13,
VAR23, VAR19,
VAR37, VAR11,
VAR5, VAR29,
VAR26, VAR31, VAR3,
VAR30, VAR9,
VAR33, VAR12, VAR38,
VAR8, VAR14, VAR6,
VAR1, VAR32, VAR28,
VAR18, VAR4,
VAR10, VAR36,
VAR15
);
input [127:0] VAR26;
input [27:0] VAR31;
outp... | gpl-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab4/Lab4-Project/BCD_Binary_Encoder.v | 5,233 | module MODULE1
parameter VAR15 = 8,
parameter VAR2 = 2
)
(
input VAR26,
output reg VAR25,
input [VAR15-1:0] VAR1,
output reg [VAR2*4-1:0] VAR7, output reg VAR4,
input VAR14,
input VAR13
);
reg [4:0] VAR16;
localparam [4:0]
VAR12 = 5'b00001,
VAR23 = 5'b00010,
VAR18 = 5'b00100,
VAR24 = 5'b01000,
VAR19 = 5'b10000;
localpa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfstp/sky130_fd_sc_lp__sdfstp.pp.blackbox.v | 1,434 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR3 ,
VAR2 ,
VAR9 ,
VAR5,
VAR4 ,
VAR8 ,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR10 ;
input VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR5;
input VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/sdram/cpu_cache.v | 10,386 | module MODULE1 (
input wire clk, input wire rst, input wire VAR40, input wire [ 6-1:0] VAR53, input wire [ 25-1:1] VAR79, input wire [ 2-1:0] VAR74, input wire [ 16-1:0] VAR30, output reg [ 16-1:0] VAR56, output reg VAR29, input wire [ 4-1:0] VAR50, input wire [ 25-1:0] VAR63, input wire VAR33, input wire VAR26, input ... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/RAMB16_S9_altera_bb.v | 6,155 | module MODULE1 (
address,
VAR4,
VAR2,
VAR3,
VAR1,
VAR5);
input [10:0] address;
input VAR4;
input [7:0] VAR2;
input VAR3;
input VAR1;
output [7:0] VAR5;
endmodule | mit |
gralco/mojo-ide | Mojo IDE/build/shared/base/mojo-v3/source/serial_rx.v | 1,689 | module MODULE1 #(
parameter VAR1 = 50,
parameter VAR22 = 6
)(
input clk,
input rst,
input VAR18,
output [7:0] VAR13,
output VAR20
);
localparam VAR16 = 2;
localparam VAR15 = 2'd0,
VAR7 = 2'd1,
VAR4 = 2'd2,
VAR17 = 2'd3;
reg [VAR22-1:0] VAR3, VAR8;
reg [2:0] VAR9, VAR19;
reg [7:0] VAR14, VAR21;
reg VAR2, VAR11;
reg [VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s.functional.v | 1,342 | module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
wire VAR4;
buf VAR2 (VAR4, VAR1 );
buf VAR5 (VAR3 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i_4.v | 2,214 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3 ,
VAR9 ,
VAR5,
VAR8,
VAR7 ,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR3 ;
input VAR9 ;
input VAR5;
input VAR8;
input VAR7 ;
input VAR2 ;
VAR6 VAR10 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE1 (... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_multiplier.v | 3,394 | module MODULE1 (
VAR5,
VAR10,
VAR4,
VAR8,
VAR14,
VAR2,
VAR15
);
input VAR5; input VAR10; input VAR4; input VAR8; input [VAR1] VAR14; input [VAR1] VAR2;
output [VAR1] VAR15; reg [VAR1] VAR15;
reg [VAR1] VAR7;
reg [VAR1] VAR13;
reg [VAR1] VAR9;
always @(posedge VAR5 VAR6)
begin
if (VAR10 == VAR12)
begin
VAR7 <= {VAR3{1'b... | lgpl-3.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/soc/i2s.v | 7,680 | module MODULE1
(
VAR8,
VAR9,
VAR12,
VAR6,
VAR3,
VAR13,
VAR18,
VAR11,
VAR16
);
parameter VAR15 = 6;
input VAR8 ;
input VAR9 ;
input[31:0] VAR12 ;
input VAR6 ;
output VAR3 ;
output VAR13 ;
output VAR18 ;
output VAR11 ;
output VAR16 ;
reg VAR7;
integer VAR1;
integer VAR5;
reg VAR2;
reg [15:0] VAR10;
reg [15:0] VAR17;
reg ... | mit |
DeadBugEngineering/myHDL_shenanigans | ssd1306_8x64bit_driver/ssd1306_8x64bit_driver.v | 40,942 | module MODULE1 (
clk,
reset,
VAR29,
VAR9,
VAR30,
VAR35,
VAR40,
VAR13,
VAR19,
VAR22,
VAR26,
VAR24,
VAR33,
VAR4,
VAR20,
VAR16,
VAR1
);
input clk;
input reset;
output VAR29;
reg VAR29;
input [63:0] VAR9;
input [63:0] VAR30;
input [63:0] VAR35;
input [63:0] VAR40;
input [63:0] VAR13;
input [63:0] VAR19;
input [63:0] VAR22;... | lgpl-2.1 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_cm16x40b.v | 12,308 | module MODULE1(
dout, VAR29, VAR19, VAR24,
VAR51, din, VAR5, VAR30, VAR16, VAR49, VAR8, VAR13,
VAR2, VAR47, VAR10, VAR25, VAR35
);
input [15:0] VAR51 ; input [39:0] din; input VAR5; input VAR30;
input [15:0] VAR16; input VAR49;
output [39:0] dout;
input VAR8; input [39:8] VAR13; output [15:0] VAR29 ;
output [15:0] VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/conb/sky130_fd_sc_hvl__conb.behavioral.v | 1,283 | module MODULE1 (
VAR7,
VAR6
);
output VAR7;
output VAR6;
supply1 VAR8;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
pullup VAR1 (VAR7 );
pulldown VAR5 (VAR6 );
endmodule | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/soc_system_master_secure_timing_adt.v | 1,780 | module MODULE1 (
input clk,
input VAR1,
input VAR2,
input [ 7: 0] VAR9,
output reg VAR7,
output reg [ 7: 0] VAR3,
input VAR8
);
reg [ 7: 0] VAR5;
reg [ 7: 0] VAR4;
reg [ 0: 0] ready;
reg VAR6;
always @(negedge VAR6) begin
end
always @* begin
VAR5 = {VAR9};
{VAR3} = VAR4;
end
always @* begin
ready[0] = VAR8;
VAR7 = VAR2... | mit |
osrf/wandrr | firmware/motor_controller/fpga/udp_rx_regs.v | 2,092 | module MODULE1
parameter VAR1=0,
parameter VAR15=0)
(input VAR7,
input [7:0] VAR6,
input VAR8,
input VAR11,
output VAR4, output [VAR34*32-1:0] VAR9);
wire [11:0] VAR31;
VAR28 #(12) VAR32(.VAR7(VAR7), .rst(~VAR8), .en(1'b1), .VAR26(VAR31 + 1'b1), .VAR30(VAR31));
wire [7:0] VAR2;
VAR28 #(8) VAR25(.VAR7(VAR7), .rst(~VAR8)... | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/amber23/a23_barrel_shift_fpga.v | 10,835 | module MODULE1 (
input [31:0] VAR5,
input VAR16,
input [7:0] VAR23, input VAR35, input [1:0] VAR27,
output [31:0] VAR3,
output VAR6
);
wire [31:0] VAR26;
wire [1:0] VAR39; wire [1:0] VAR38; wire [1:0] VAR25; wire [1:0] VAR36;
reg [32:0] VAR32; reg [32:0] VAR2; reg [15:0] VAR4;
reg [4:0] VAR8;
reg [2:0] VAR34; reg [2:0]... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_data_io.v | 16,279 | module MODULE1 #
(
parameter VAR35 = 100, parameter VAR18 = 2, parameter VAR44 = 3000, parameter VAR55 = 8, parameter VAR29 = 9, parameter VAR67 = 72, parameter VAR98 = 9, parameter VAR21 = "VAR3",
parameter VAR34 = 5, parameter VAR9 = "VAR86", parameter VAR33 = 300.0, parameter VAR88 = "VAR86", parameter VAR19 = "VAR6... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.functional.pp.v | 1,072 | module MODULE1( VAR3, VAR7, VAR2, VAR8, VAR5 );
input VAR3, VAR7;
inout VAR8, VAR5;
output VAR2;
wire VAR10;
not VAR4( VAR10, VAR3 );
wire VAR1;
not VAR6( VAR1, VAR7 );
or VAR9( VAR2, VAR10, VAR1 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.behavioral.v | 1,341 | module MODULE1( VAR8, VAR6, VAR4, VAR5, VAR3 );
input VAR3, VAR5, VAR4, VAR8;
output VAR6;
VAR7 VAR2(.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3));
VAR7 VAR1(.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/ui/ui_top.v | 13,574 | module MODULE1 #
(
parameter VAR67 = 100,
parameter VAR39 = 256,
parameter VAR45 = 32,
parameter VAR73 = 3,
parameter VAR21 = 12,
parameter VAR16 = 5,
parameter VAR3 = "VAR18",
parameter VAR69 = "VAR18",
parameter VAR33 = "VAR32",
parameter VAR43 = 2,
parameter VAR8 = 4,
parameter VAR46 = 2,
parameter VAR49 = 16,
param... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_irf.v | 88,325 | module MODULE2 (
VAR46, VAR209, VAR138,
VAR154, VAR152,
VAR199, VAR74, VAR171, VAR73, VAR143, VAR166, VAR67,
VAR53, VAR155, VAR70, VAR99,
VAR120, VAR62, VAR77, VAR181,
VAR102, VAR193, VAR167, VAR113,
VAR141, VAR137, VAR1,
VAR147, VAR128, VAR165,
VAR149, VAR7, VAR127,
VAR116, VAR153, VAR203,
VAR163, VAR96, VAR78
) ;
inp... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/coeff_rom.v | 1,153 | module MODULE1 (input VAR1, input [2:0] addr, output reg [15:0] VAR2);
always @(posedge VAR1)
case (addr)
3'd0 : VAR2 <= -16'd49;
3'd1 : VAR2 <= 16'd165;
3'd2 : VAR2 <= -16'd412;
3'd3 : VAR2 <= 16'd873;
3'd4 : VAR2 <= -16'd1681;
3'd5 : VAR2 <= 16'd3135;
3'd6 : VAR2 <= -16'd6282;
3'd7 : VAR2 <= 16'd20628;
endcase
endmod... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn_2.v | 2,148 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR1,
VAR8,
VAR6,
VAR3 ,
VAR9
);
output VAR5 ;
input VAR2 ;
input VAR1;
input VAR8;
input VAR6;
input VAR3 ;
input VAR9 ;
VAR4 VAR7 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR5 ,
VAR2 ,
VAR1
);
output VAR5 ;... | apache-2.0 |
solowandererY2K/FPGA-Quantum-Compiler | src/gate_rom.v | 6,739 | module MODULE1 (
address,
VAR29,
VAR46);
input [7:0] address;
input VAR29;
output [39:0] VAR46;
tri1 VAR29;
wire [39:0] VAR39;
wire [39:0] VAR46 = VAR39[39:0];
VAR48 VAR5 (
.VAR35 (address),
.VAR42 (VAR29),
.VAR16 (VAR39),
.VAR14 (1'b0),
.VAR9 (1'b0),
.VAR44 (1'b1),
.VAR47 (1'b0),
.VAR10 (1'b0),
.VAR30 (1'b1),
.VAR32 (... | mit |
martinmiranda14/Digitales | Lab_6/new/lab_6.v | 34,782 | module MODULE1(
input VAR168,
input VAR89,
input VAR114,
input VAR52,
input VAR18,
input VAR151,
output VAR110,
output VAR63,
output [3:0] VAR205,
output [3:0] VAR117,
output [3:0] VAR92,
output [5:0] VAR26,
output VAR81
);
localparam VAR104 = 212;
localparam VAR147 = 812;
localparam VAR207 = 184;
localparam VAR111 = 5... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/02CAD-JOYSTICK/Version_02/02 verilog/peripheral_adc.v | 1,139 | module MODULE1(input VAR7,
input VAR4,
input wr
input rd,
input din,
input rst,
input reg [3:0]addr,
output reg [7:0]dout,
output VAR10, output VAR6);
reg [3:0] VAR8;
wire VAR10; wire VAR6; wire dout;
VAR1 VAR3(.VAR2(din), .VAR7(VAR7), .reset(rst), .VAR5(dout), .VAR10(VAR10), .VAR6(VAR6), .rd(rd));
always @(*) begin
ca... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_2.v | 2,350 | module MODULE1 (
VAR9 ,
VAR8,
VAR5,
VAR7 ,
VAR4 ,
VAR3,
VAR1
);
output VAR9 ;
input VAR8;
input VAR5;
input VAR7 ;
input VAR4 ;
input VAR3;
input VAR1;
VAR6 VAR2 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR9 ,
VAR8,
VAR5,
VAR7 ,
VAR4
);
ou... | apache-2.0 |
GSejas/Karatsuba_FPU | ASIC_FLOW/global_sources/RecursiveKOA.v | 2,527 | module MODULE1
parameter VAR8=1) (
input wire clk,
input wire rst,
input wire VAR9,
input wire [VAR19-1:0] VAR7,
input wire [VAR19-1:0] VAR4,
output wire [2*VAR19-1:0] VAR6
);
wire [2*VAR19-1:0] VAR10;
generate
if (VAR8) begin : VAR5
VAR5 #(.VAR19(VAR19)) VAR2(
.VAR7(VAR7[VAR19-1:0]),
.VAR4(VAR4[VAR19-1:0]),
.VAR6(VAR1... | gpl-3.0 |
8l/soc | backends/small1/hw/soc/atlys/3rdparty/uart_rx.v | 4,083 | module MODULE1 #
(
parameter VAR6 = 8
)
(
input wire clk,
input wire rst,
output wire [VAR6-1:0] VAR18,
output wire VAR9,
input wire VAR11,
input wire VAR17,
output wire VAR13,
output wire VAR1,
output wire VAR10,
input wire [15:0] VAR4
);
reg [VAR6-1:0] VAR8 = 0;
reg VAR5 = 0;
reg VAR7 = 1;
reg VAR16 = 0;
reg VAR14 = ... | mit |
tugrulyatagan/RISC-processor | xilinx_processor/uart_tx.v | 3,133 | module MODULE1 #
(
parameter VAR3 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR3-1:0] VAR1,
input wire VAR6,
output wire VAR7,
output wire VAR5,
output wire VAR4,
input wire [15:0] VAR12
);
reg VAR2 = 0;
reg VAR10 = 1;
reg VAR8 = 0;
reg [VAR3:0] VAR11 = 0;
reg [18:0] VAR13 = 0;
reg [3:0] VAR9 = 0;
assign VAR7... | gpl-2.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/number_in.v | 1,725 | module MODULE1(
input [31:0] VAR4,
input [31:0] VAR10,
input [31:0] VAR2,
input [4:0] VAR1,
input VAR9,
output reg [32:0] VAR5
);
reg [31:0] new;
reg [6:0] VAR7;
reg [1:0] state;
reg VAR6;
parameter [1:0] VAR3 = 2'b00;
parameter [1:0] VAR12 = 2'b01;
parameter [1:0] VAR11 = 2'b10;
VAR8 state = 2'b00;
VAR8 VAR6 = 0;
alwa... | mit |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_fdest.v | 3,937 | module MODULE1 #(
parameter VAR1 = 26
) (
input VAR14,
input VAR22,
output [VAR1-1:0] VAR23,
output reg VAR24,
input VAR19,
input [63:0] VAR12,
input VAR4,
output VAR3,
input VAR10,
input VAR7,
output reg VAR20,
input [15:0] VAR13,
input [VAR1-1-1:0] VAR5,
output VAR17,
input VAR2,
output reg [15:0] VAR11,
output [VAR1... | lgpl-3.0 |
keith-epidev/VHDL-lib | top/lab_1/part_5/ip/clk_base/clk_base_stub.v | 1,174 | module MODULE1(VAR1, VAR3, VAR2)
;
input VAR1;
output VAR3;
output VAR2;
endmodule | gpl-2.0 |
LuckyChewie/SPI-Connection | ADCConnector.v | 3,963 | module MODULE1
(
VAR8, VAR3,
VAR9, VAR57, VAR51,
VAR17, VAR10, VAR43, VAR30, VAR23, VAR45, VAR1, VAR53,
VAR11, VAR52, VAR28, VAR35, VAR2, VAR5,
VAR47, VAR15, VAR26, VAR34, VAR46
);
input VAR8;
input VAR3;
input VAR9;
input VAR57;
input VAR51;
input VAR47;
input VAR15;
output VAR26;
output VAR34;
output VAR46;
input [15... | mit |
ptracton/wb_soc_template | rtl/MOR1KX/bench/verilog/mor1kx_traceport_monitor.v | 3,447 | module MODULE1(
VAR13,
clk, rst, VAR3, VAR8,
VAR2, VAR10, VAR6,
VAR26, VAR17
);
parameter VAR4 = 32;
parameter VAR7 = 5;
parameter VAR19 = "../out";
parameter VAR15 = 0;
parameter VAR20 = 1;
integer VAR21 = 0;
integer VAR24 = 0;
integer VAR25 = 0;
input clk;
input rst;
input VAR3;
input [31:0] VAR8;
input [VAR5-1:0] VA... | mit |
kyzhai/NUNY | src/hardware/reading.v | 6,374 | module MODULE1 (
address,
VAR42,
VAR5);
input [11:0] address;
input VAR42;
output [11:0] VAR5;
tri1 VAR42;
wire [11:0] VAR39;
wire [11:0] VAR5 = VAR39[11:0];
VAR17 VAR6 (
.VAR26 (address),
.VAR37 (VAR42),
.VAR46 (VAR39),
.VAR30 (1'b0),
.VAR31 (1'b0),
.VAR21 (1'b1),
.VAR18 (1'b0),
.VAR2 (1'b0),
.VAR38 (1'b1),
.VAR35 (1'... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9122_v6_00_a/hdl/verilog/axi_ad9122_dds.v | 10,665 | module MODULE1 (
VAR21,
VAR33,
VAR27,
VAR36,
VAR15,
VAR56,
VAR11,
VAR35,
VAR65,
VAR6,
VAR7,
VAR44,
VAR37,
VAR64,
VAR5,
VAR49,
VAR26);
input VAR21;
input VAR33;
output [15:0] VAR27;
output [15:0] VAR36;
output [15:0] VAR15;
output [15:0] VAR56;
input VAR11;
input VAR35;
input VAR65;
input [15:0] VAR6;
input [15:0] VAR7;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.v | 2,312 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR10 ,
VAR5,
VAR1 ,
VAR2 ,
VAR3 ,
VAR8
);
output VAR7 ;
output VAR9 ;
input VAR10 ;
input VAR5;
input VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR8 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MOD... | apache-2.0 |
combinatorylogic/soc | backends/tiny1/hw/rtl/core.v | 8,536 | module MODULE1(
input clk, input rst,
input irq, output reg VAR18,
output [15:0] VAR2,
output [15:0] VAR7,
input [15:0] VAR42,
input [15:0] VAR28,
output VAR40,
output VAR19);
parameter VAR35 = 0; parameter VAR47 = 1; parameter VAR37 = 2; parameter VAR46 = 3; parameter VAR44 = 4;
parameter VAR36 = 140;
parameter VAR29 ... | mit |
peteasa/parallella-fpga | AdiHDLLib/library/prcfg/default/prcfg_adc.v | 3,348 | module MODULE1 (
clk,
VAR4,
VAR10,
VAR3,
VAR2,
VAR5,
VAR1,
VAR9,
VAR8
);
localparam VAR6 = 8'hA0;
parameter VAR7 = 0;
input clk;
input [31:0] VAR4;
output [31:0] VAR10;
input VAR3;
input VAR2;
input [15:0] VAR5;
output VAR1;
output VAR9;
output [15:0] VAR8;
reg VAR1;
reg VAR9;
reg [15:0] VAR8;
assign VAR10 = {24'h0, VA... | lgpl-3.0 |
AngelTerrones/MUSB | Hardware/memory/memory.v | 4,030 | module MODULE1#(
parameter VAR1 = 8 )(
input clk,
input rst,
input [VAR1-1:0] VAR7, input [31:0] VAR6, input [3:0] VAR13, input VAR5, output reg [31:0] VAR8, output reg VAR15, input [VAR1-1:0] VAR11, input [31:0] VAR12, input [3:0] VAR4, input VAR16, output reg [31:0] VAR3, output reg VAR14 );
reg [31:0] VAR17;
reg [31... | mit |
JY-Kim/CA2016 | Sources/Processor.v | 8,269 | module MODULE1
(
input VAR19,
input VAR85,
output wire [31:0] VAR91,
output reg [7:0] VAR23
);
parameter VAR108 = 0,
VAR138 = 1;
wire [31:0] VAR12;
wire [31:0] VAR9;
wire [31:0] VAR92;
wire [31:0] VAR163;
wire [31:0] VAR166;
wire [31:0] VAR117;
wire [31:0] VAR41;
wire [31:0] VAR4, VAR100;
wire [31:0] VAR84;
wire [2:0] ... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_dp_array.v | 10,348 | module MODULE1(
VAR20, VAR30,
VAR22, VAR24, VAR17,
VAR4, VAR43,
VAR49, VAR21, VAR1,
VAR11, VAR2, VAR42,
VAR10, VAR14, VAR5, VAR16, VAR45,
VAR48, VAR33, VAR37,
VAR50, VAR6,
VAR13, VAR18,
VAR38, VAR25,
VAR31, VAR3,
VAR29, VAR39,
VAR51, VAR12,
VAR23, VAR19,
VAR15, VAR8,
VAR28, VAR44,
VAR47, VAR41,
VAR46, VAR36,
VAR27, VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3.behavioral.pp.v | 1,844 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR14 ,
VAR10 ,
VAR2,
VAR6,
VAR8 ,
VAR7
);
output VAR3 ;
input VAR5 ;
input VAR14 ;
input VAR10 ;
input VAR2;
input VAR6;
input VAR8 ;
input VAR7 ;
wire VAR12 ;
wire VAR13;
nor VAR11 (VAR12 , VAR10, VAR5, VAR14 );
VAR4 VAR9 (VAR13, VAR12, VAR2, VAR6);
buf VAR1 (VAR3 , VAR13 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a_4.v | 2,428 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR7 ,
VAR10 ,
VAR1 ,
VAR9 ,
VAR8,
VAR3,
VAR11 ,
VAR6
);
output VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR10 ;
input VAR1 ;
input VAR9 ;
input VAR8;
input VAR3;
input VAR11 ;
input VAR6 ;
VAR12 VAR5 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VA... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v | 23,247 | module MODULE2 #
(
parameter VAR9 = 2 )
(
input wire clk, input wire [VAR9-1:0] VAR19, input wire VAR28, input wire VAR18, output wire VAR21 );
localparam integer VAR13 = 2**VAR9;
reg [VAR13-1:0] VAR1 = {VAR13{1'b0}};
always @(posedge clk)
if (VAR28)
VAR1 <= {VAR1[VAR13-2:0], VAR18};
assign VAR21 = VAR1[VAR19];
endmodu... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.functional.pp.v | 1,462 | module MODULE1( VAR9, VAR16, VAR4, VAR1, VAR5, VAR15, VAR13 );
input VAR5, VAR1, VAR4, VAR9;
inout VAR15, VAR13;
output VAR16;
wire VAR14;
not VAR3( VAR14, VAR5 );
wire VAR8;
not VAR7( VAR8, VAR1 );
wire VAR18;
not VAR10( VAR18, VAR4 );
wire VAR6;
and VAR12( VAR6, VAR14, VAR8, VAR18 );
wire VAR17;
not VAR2( VAR17, VAR9... | apache-2.0 |
peteg944/music-fpga | Enlightened Main Project/Microphone.v | 2,866 | module MODULE1(
output VAR31, output VAR26, output reg VAR16, input VAR5, input clk,
input rst,
input VAR20, output reg VAR29, output reg [9:0] VAR17
);
reg VAR1;
reg [9:0] VAR10;
reg VAR12, VAR21;
reg VAR15;
reg [7:0] VAR6, VAR22;
wire [7:0] VAR8;
wire VAR9;
VAR18 #(6) VAR14(clk, rst, VAR5, VAR26, VAR31, VAR12, VAR6, ... | mit |
sirchuckalot/zet | cores/ps2/rtl/ps2_mouse_cmdout.v | 9,859 | module MODULE1 (
input clk,
input reset,
input [7:0] VAR13,
input VAR15,
input VAR10,
input VAR24,
input VAR30,
inout VAR6,
inout VAR32,
output reg VAR25,
output reg VAR27
);
parameter VAR31 = 1262; parameter VAR28 = 13; parameter VAR7 = 13'h0001; parameter VAR22 = 187500; parameter VAR19 = 20; parameter VAR16 = 20'h00... | gpl-3.0 |
vvk/sysrek | pipeline_summator/ipcore_dir/add.v | 13,407 | module MODULE2 (
VAR67, VAR146, VAR20
);
output [20 : 0] VAR67;
input [20 : 0] VAR146;
input [20 : 0] VAR20;
wire \VAR52/VAR110 ;
wire \VAR52/VAR137 ;
wire \VAR52/VAR89 ;
wire \VAR52/VAR108 ;
wire \VAR52/VAR4 ;
wire \VAR52/VAR96 ;
wire \VAR52/VAR63 ;
wire \VAR52/VAR65 ;
wire \VAR52/VAR104 ;
wire \VAR52/VAR72 ;
wire \VA... | gpl-2.0 |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/usb_system_sdram.v | 24,482 | module MODULE1 (
clk,
rd,
VAR33,
wr,
VAR55,
VAR15,
VAR77,
VAR9,
VAR81,
VAR49
)
;
output VAR15;
output VAR77;
output VAR9;
output VAR81;
output [ 61: 0] VAR49;
input clk;
input rd;
input VAR33;
input wr;
input [ 61: 0] VAR55;
wire VAR15;
wire VAR77;
wire VAR9;
reg [ 1: 0] VAR24;
reg [ 61: 0] VAR66;
reg [ 61: 0] VAR5;
wi... | apache-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi/solution1/impl/ip/hdl/verilog/compare.v | 64,801 | module MODULE1 (
VAR166,
VAR186,
VAR172,
VAR373,
VAR453,
VAR184,
VAR21,
VAR178,
VAR306,
VAR169,
VAR407,
VAR159,
VAR24,
VAR249,
VAR71,
VAR128,
VAR335,
VAR171,
VAR212,
VAR286,
VAR379
);
parameter VAR157 = 33'd1;
parameter VAR237 = 33'd2;
parameter VAR276 = 33'd4;
parameter VAR438 = 33'd8;
parameter VAR219 = 33'd16;
param... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_ADC_Peripheral_To_Phase_Current.v | 2,998 | module MODULE1
(
VAR9,
VAR15,
VAR2,
VAR18
);
input signed [17:0] VAR9; input signed [17:0] VAR15; output signed [17:0] VAR2; output signed [17:0] VAR18;
wire signed [17:0] VAR17 [0:1]; wire signed [17:0] VAR13; wire signed [19:0] VAR16; wire signed [19:0] VAR4; wire signed [19:0] VAR8; wire signed [19:0] VAR11 [0:1]; w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp.behavioral.pp.v | 3,432 | module MODULE1 (
VAR36 ,
VAR7 ,
VAR22 ,
VAR35 ,
VAR9 ,
VAR2,
VAR8,
VAR18 ,
VAR3 ,
VAR4 ,
VAR11 ,
VAR29
);
output VAR36 ;
input VAR7 ;
input VAR22 ;
input VAR35 ;
input VAR9 ;
input VAR2;
input VAR8;
input VAR18 ;
input VAR3 ;
input VAR4 ;
input VAR11 ;
input VAR29 ;
wire VAR30 ;
wire VAR10 ;
wire VAR21 ;
reg VAR16 ;
wi... | apache-2.0 |
aj-michael/Digital-Systems | Lab6-Part1/ipcore_dir/Clock65MHz.v | 5,608 | module MODULE1
( input VAR33,
output VAR16,
output VAR2
);
VAR8 VAR29
(.VAR24 (VAR13),
.VAR17 (VAR33));
wire VAR23;
wire VAR49;
wire [7:0] VAR37;
wire VAR10;
wire VAR25;
wire VAR20;
VAR26
.VAR15 (20),
.VAR35 (13),
.VAR34 ("VAR28"),
.VAR47 (10.0),
.VAR6 ("VAR12"),
.VAR38 ("1X"),
.VAR30 ("VAR27"),
.VAR42 (0),
.VAR5 ("VAR... | mit |
SI-RISCV/e200_opensource | rtl/e203/core/e203_clk_ctrl.v | 4,939 | module MODULE1 (
input clk, input VAR17, input VAR15,
input VAR31,
output VAR11,
input VAR32,
input VAR14,
input VAR10,
input VAR9,
input VAR22,
output VAR33,
input VAR3,
output VAR24,
output VAR27,
output VAR7,
output VAR13,
output VAR20,
output VAR36,
output VAR35,
input VAR39
);
wire VAR5 = VAR31 | (VAR32 & (~VAR39)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtn/sky130_fd_sc_hs__dlrtn.behavioral.pp.v | 2,350 | module MODULE1 (
VAR19 ,
VAR8 ,
VAR11 ,
VAR3,
VAR6 ,
VAR9
);
input VAR19 ;
input VAR8 ;
output VAR11 ;
input VAR3;
input VAR6 ;
input VAR9 ;
wire VAR14 ;
wire VAR15 ;
reg VAR13 ;
wire VAR21 ;
wire VAR10 ;
wire VAR1 ;
wire VAR7;
wire VAR16 ;
wire VAR22 ;
wire VAR17 ;
wire VAR5 ;
not VAR20 (VAR14 , VAR7 );
not VAR2 (VAR1... | apache-2.0 |
jameshegarty/rigel | platform/camera/vsrc/fifo_64w_32r_512d.v | 13,842 | module MODULE1(
rst,
VAR16,
VAR175,
din,
VAR221,
VAR248,
dout,
VAR239,
VAR21,
VAR427,
VAR11
);
input rst;
input VAR16;
input VAR175;
input [63 : 0] din;
input VAR221;
input VAR248;
output [31 : 0] dout;
output VAR239;
output VAR21;
output [9 : 0] VAR427;
output [8 : 0] VAR11;
VAR404 #(
.VAR261(0),
.VAR116(0),
.VAR2(0),... | mit |
DeadWitcher/amber-de0-nano | hw/vlog/amber25/a25_barrel_shift.v | 4,644 | module MODULE1 (
input VAR9,
input [31:0] VAR2,
input VAR10,
input [7:0] VAR11, input VAR4, input [1:0] VAR5,
output [31:0] VAR18,
output VAR1,
output VAR19
);
wire [31:0] VAR8;
wire VAR20;
wire [31:0] VAR6;
wire VAR14;
reg [31:0] VAR15 = 'd0;
reg VAR12 = 'd0;
reg VAR7 = 1'd1;
assign VAR19 = (|VAR11[7:2]) & VAR7;
assig... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4/sky130_fd_sc_hdll__and4.blackbox.v | 1,283 | module MODULE1 (
VAR2,
VAR7,
VAR4,
VAR6,
VAR1
);
output VAR2;
input VAR7;
input VAR4;
input VAR6;
input VAR1;
supply1 VAR8;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1p/sky130_fd_sc_lp__inputiso1p.pp.blackbox.v | 1,361 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR6,
VAR3 ,
VAR7 ,
VAR5 ,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR6;
input VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/custom/custom_engine_tx.v | 1,882 | module MODULE1
parameter VAR9 = 10,
parameter VAR1 = 0
)
(
input VAR15, input reset, input VAR13,
input VAR11, input [7:0] VAR14, input [31:0] VAR16,
output VAR2,
output VAR4,
input VAR5,
output VAR10,
output VAR12,
output [VAR9-1:0] VAR3,
input [VAR9-1:0] VAR7,
output [35:0] VAR8,
input [35:0] VAR6
);
assign VAR10 = V... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_out_dp.v | 6,151 | module MODULE1 (
VAR17,
VAR18,
VAR36,
VAR1,
VAR4,
VAR13,
VAR7,
VAR40,
VAR12,
VAR45,
VAR41,
VAR20,
VAR31,
VAR35,
VAR14,
VAR10,
VAR24,
VAR3,
VAR6,
VAR11,
VAR26,
VAR15,
VAR44,
VAR28,
VAR43,
VAR30,
VAR27,
VAR42,
VAR25,
VAR9
);
input [2:0] VAR17; input [1:0] VAR18; input [4:0] VAR36; input VAR1; input VAR4; input VAR13; inp... | gpl-2.0 |
dagrende/quad_stepper | qsfpga/gearbox.v | 2,042 | module MODULE1(clk, VAR3, VAR21, VAR10);
parameter VAR15 = 32;
parameter VAR16 = 53200000; parameter VAR20 = 19;
parameter VAR7 = 1 << VAR20; parameter VAR4 = 5;
parameter VAR13 = 1;
parameter VAR23 = 1;
parameter VAR24 = 200 * 32 * 6 / 1600; parameter VAR25 = VAR13 * VAR24;
input clk, VAR3, VAR21;
output VAR10;
reg [V... | apache-2.0 |
jotego/jt12 | hdl/alt/eg_step_ram.v | 1,917 | module MODULE1(
input [2:0] VAR1,
input [5:0] VAR11,
input [2:0] VAR8,
output reg VAR13
);
localparam VAR2=3'd0, VAR7=3'd1, VAR12=3'd2, VAR5=3'd7, VAR9=3'd3;
reg [7:0] VAR4;
reg [7:0] VAR3;
always @ begin : VAR6
if( VAR11[5:2]==4'hf && VAR1 == VAR2)
end
VAR4 = 8'b11111111; else
if( VAR11[5:2]==4'd0 && VAR1 != VAR2)
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a.blackbox.v | 1,373 | module MODULE1 (
VAR6 ,
VAR4,
VAR10,
VAR5,
VAR7,
VAR3
);
output VAR6 ;
input VAR4;
input VAR10;
input VAR5;
input VAR7;
input VAR3;
supply1 VAR8;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
plindstroem/oh | elink/hdl/ereset.v | 2,666 | module MODULE1 (
VAR7, VAR11, VAR12,VAR15,VAR8,
reset, VAR10, VAR1, VAR3,VAR9,VAR4
);
input reset;
input VAR10; input VAR1; input VAR3; input VAR9;
input VAR4;
output VAR7; output VAR11; output VAR12; output VAR15;
output VAR8;
reg VAR2;
reg VAR14;
reg VAR6;
reg VAR5;
reg VAR13;
always @ (posedge VAR3)
VAR14 <= reset;
... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/spi_engine/spi_engine_execution/spi_engine_execution.v | 7,260 | module MODULE1 (
input clk,
input VAR22,
output reg VAR56,
output VAR2,
input VAR26,
input [15:0] VAR32,
input VAR50,
output reg VAR35,
input [7:0] VAR8,
input VAR17,
output reg VAR9,
output [7:0] VAR66,
input VAR15,
output reg VAR62,
output [7:0] sync,
output reg VAR52,
output VAR21,
output reg VAR3,
input VAR18,
outp... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_32.v | 21,379 | module MODULE2 (
clk,
reset,
VAR105,
VAR52,
VAR62,
VAR140,
VAR84
);
parameter VAR14 = 18;
parameter VAR63 = 32;
parameter VAR37 = 16;
localparam VAR21 = 33;
input clk;
input reset;
input VAR105;
input VAR52;
input [VAR14-1:0] VAR62; output VAR140;
output [VAR14-1:0] VAR84;
localparam VAR124 = 18; localparam VAR10 = 36;... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/clocking/infrastructure.v | 12,892 | module MODULE1 #
(
parameter VAR9 = 100, parameter VAR18 = 3000, parameter VAR24 = 2, parameter VAR4 = "VAR26",
parameter VAR19 = 4, parameter VAR5 = 1, parameter VAR11 = 16, parameter VAR15 = 4, parameter VAR6 = 64, parameter VAR1 = 16, parameter VAR2 = 1
)
(
input VAR17, input VAR8, input VAR25,
output clk, output VA... | lgpl-3.0 |
hongyunnchen/miaow | src/verilog/rtl/exec/exec.v | 7,503 | module MODULE1(
VAR57,
VAR140,
VAR101,
VAR55,
VAR64,
VAR82,
VAR27,
VAR126,
VAR28,
VAR145,
VAR97,
VAR56,
VAR18,
VAR3,
VAR123,
VAR102,
VAR103,
VAR61,
VAR139,
VAR89,
VAR68,
VAR84,
VAR53,
VAR147,
VAR87,
VAR116,
VAR4,
VAR151,
VAR76,
VAR10,
VAR6,
VAR129,
VAR14,
VAR46,
VAR52,
VAR113,
VAR85,
VAR138,
VAR7,
VAR54,
VAR33,
VAR31,
... | bsd-3-clause |
hcabrera-/lancetfish | RTL/router/rtl/data_path.v | 8,057 | module MODULE1
(
input wire clk,
input wire reset,
input wire [VAR12-1:0] VAR61,
input wire [VAR12-1:0] VAR44,
input wire [VAR12-1:0] VAR39,
input wire [VAR12-1:0] VAR45,
input wire [VAR12-1:0] VAR13,
input wire [4:0] VAR35,
input wire [4:0] VAR31,
input wire [3:0] VAR4,
input wire [3:0] VAR55,
input wire [3:0] VAR33,
... | gpl-3.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/ip/Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v | 3,709 | module MODULE1 ( VAR7,
VAR36,
VAR33,
VAR22,
VAR11,
VAR69,
VAR34,
VAR40, VAR3,
VAR47,
VAR54,
VAR30,
VAR53,
VAR23,
VAR58,
VAR56,
VAR50 );
parameter VAR52 = 19'h4B000;
output [15:0] VAR36;
input [15:0] VAR7;
input [18:0] VAR33;
input VAR22,VAR11,VAR69;
input VAR40,VAR34;
reg [15:0] VAR36;
output [9:0] VAR3;
output [9:0] V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.behavioral.v | 3,634 | module MODULE1( VAR28, VAR8, VAR16, VAR12 );
input VAR28, VAR8, VAR16;
output VAR12;
reg VAR4;
VAR26 VAR10(.VAR28(VAR28),.VAR8(VAR8),.VAR16(VAR16),.VAR12(VAR12),.VAR4(VAR4));
VAR26 VAR21(.VAR28(VAR28),.VAR8(VAR8),.VAR16(VAR16),.VAR12(VAR12),.VAR4(VAR4));
not VAR14(VAR1,VAR8);
and VAR15(VAR27,VAR16,VAR1);
and VAR30(VAR6... | apache-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_iir_filter_v1_0/axis_iir_filter.v | 1,424 | module MODULE1
(
input wire VAR7,
input wire VAR5,
input wire [31:0] VAR3,
output wire [15:0] VAR9,
input wire [32:0] VAR4,
output wire [24:0] VAR18,
output wire [41:0] VAR12,
input wire [41:0] VAR11,
output wire [24:0] VAR1,
output wire [41:0] VAR13,
input wire [41:0] VAR15,
output wire VAR17,
input wire [15:0] VAR10,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4b/sky130_fd_sc_ls__or4b.behavioral.pp.v | 1,978 | module MODULE1 (
VAR13 ,
VAR11 ,
VAR3 ,
VAR5 ,
VAR10 ,
VAR8,
VAR14,
VAR7 ,
VAR6
);
output VAR13 ;
input VAR11 ;
input VAR3 ;
input VAR5 ;
input VAR10 ;
input VAR8;
input VAR14;
input VAR7 ;
input VAR6 ;
wire VAR4 ;
wire VAR2 ;
wire VAR1;
not VAR12 (VAR4 , VAR10 );
or VAR16 (VAR2 , VAR4, VAR5, VAR3, VAR11 );
VAR15 VAR9 ... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_axis_inf_rx.v | 5,963 | module MODULE1 #(
parameter VAR14 = 16) (
input clk,
input rst,
input valid,
input VAR17,
input [(VAR14-1):0] VAR27,
output reg VAR15,
output reg VAR12,
output reg [(VAR14-1):0] VAR7,
input VAR6);
reg [ 2:0] VAR13 = 'd0;
reg VAR9 = 'd0;
reg [(VAR14-1):0] VAR21 = 'd0;
reg VAR19 = 'd0;
reg [(VAR14-1):0] VAR1 = 'd0;
reg V... | mit |
Siliciumer/DOS-Mario-FPGA | sources/mario_font_rom.v | 17,723 | module MODULE1(
input wire [11:0] addr, output reg [7:0] VAR1 );
reg [7:0] VAR2;
always @(*)
VAR1 = VAR2;
always @*
case (addr)
12'h000: VAR2 = 8'b00000000; 12'h001: VAR2 = 8'b00000000; 12'h002: VAR2 = 8'b01111100; 12'h003: VAR2 = 8'b11000110; 12'h004: VAR2 = 8'b11000110; 12'h005: VAR2 = 8'b11001110; 12'h006: VAR2 = 8'... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2b/sky130_fd_sc_ls__and2b.behavioral.pp.v | 1,934 | module MODULE1 (
VAR13 ,
VAR5 ,
VAR6 ,
VAR4,
VAR8,
VAR10 ,
VAR15
);
output VAR13 ;
input VAR5 ;
input VAR6 ;
input VAR4;
input VAR8;
input VAR10 ;
input VAR15 ;
wire VAR7 ;
wire VAR12 ;
wire VAR2;
not VAR9 (VAR7 , VAR5 );
and VAR14 (VAR12 , VAR7, VAR6 );
VAR1 VAR3 (VAR2, VAR12, VAR4, VAR8);
buf VAR11 (VAR13 , VAR2 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32oi/sky130_fd_sc_ms__a32oi.pp.blackbox.v | 1,467 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR8 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR1,
VAR7,
VAR10 ,
VAR9
);
output VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR10 ;
input VAR9 ;
endmodule | apache-2.0 |
sabertazimi/hust-lab | verilog/labs/lab5/src/binary_multiplier_control_unit.v | 2,292 | module MODULE1
(
input VAR7,
input clk,
input VAR12,
input VAR9,
output VAR5,
output reg VAR4,
output reg VAR2,
output reg VAR11,
output reg VAR10
);
reg [2:0] state, VAR13;
parameter VAR8 = 0, VAR6 = 1, VAR3 = 2, VAR1 = 3;
assign VAR5 = VAR7; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv.behavioral.pp.v | 1,774 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR11,
VAR3,
VAR5 ,
VAR8
);
output VAR10 ;
input VAR2 ;
input VAR11;
input VAR3;
input VAR5 ;
input VAR8 ;
wire VAR12 ;
wire VAR1;
not VAR7 (VAR12 , VAR2 );
VAR9 VAR6 (VAR1, VAR12, VAR11, VAR3);
buf VAR4 (VAR10 , VAR1 );
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/pfpu32/pfpu32_top.v | 17,914 | module MODULE1
parameter VAR202 = 32
)
(
input clk,
input rst,
input VAR26,
input VAR143,
input VAR121,
input [VAR122-1:0] VAR56,
input [VAR67-1:0] VAR207,
input [VAR202-1:0] VAR176,
input [VAR202-1:0] VAR96,
output [VAR202-1:0] VAR40,
output VAR206,
output VAR148,
output VAR14,
output [VAR64-1:0] VAR90
);
wire VAR134 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcon/sky130_fd_sc_hd__fahcon.symbol.v | 1,358 | module MODULE1 (
input VAR8 ,
input VAR3 ,
input VAR2 ,
output VAR5,
output VAR4
);
supply1 VAR7;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/eth2dma_intercon/src/eth2dma_intercon.v | 7,603 | module MODULE1
(
input VAR63,
input VAR62,
input VAR8,
input VAR40,
input VAR61,
input VAR45,
output VAR28,
output VAR11,
output VAR37,
output VAR42,
input [31 : 0] VAR41,
input [31 : 0] VAR20,
input [31 : 0] VAR71,
input [31 : 0] VAR72,
input [3 : 0] VAR26,
input [3 : 0] VAR44,
input [3 : 0] VAR1,
input [3 : 0] VAR56,... | lgpl-2.1 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_pipeline.v | 35,580 | module MODULE1(
clk ,
VAR32 ,
VAR161 ,
VAR86 ,
VAR125 ,
VAR222 ,
VAR199 ,
VAR20 ,
VAR219 ,
VAR16 ,
VAR230 ,
VAR264 ,
VAR35 ,
VAR54 ,
VAR18 ,
VAR3 ,
VAR10 ,
VAR61
);
parameter VAR91 = 128 ;
input clk ;
input VAR32 ;
input VAR161 ;
input VAR86 ;
input [5:0] VAR125 ;
input [5:0] VAR222 ;
input VAR199 ;
input VAR20 ;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinvlp/sky130_fd_sc_lp__clkinvlp.behavioral.v | 1,369 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR3;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR7 ;
wire VAR5;
not VAR2 (VAR5, VAR4 );
buf VAR8 (VAR1 , VAR5 );
endmodule | apache-2.0 |
marshmellow42/proxmark3 | fpga/fpga_hf.v | 7,512 | module MODULE1(
input VAR65, output VAR46, input VAR23, input VAR55,
input VAR21, input VAR4, input VAR52,
output VAR70, output VAR12,
output VAR16, output VAR72, output VAR50, output VAR74,
input [7:0] VAR95, output VAR33, output VAR7,
output VAR62, output VAR24, input VAR89, output VAR47,
input VAR35, input VAR51,
ou... | gpl-2.0 |
toomij/DE2Labs | Lab4/lab4_part4.v | 2,248 | module MODULE3 (VAR22, VAR23, VAR9, VAR5, VAR24, VAR16, VAR18, VAR11, VAR19, VAR17, VAR10);
input VAR22;
input [3:0] VAR10;
output [15:0] VAR17;
output [0:6] VAR23, VAR9, VAR5, VAR24, VAR16, VAR18, VAR11, VAR19;
wire [25:0] VAR7;
wire [15:0] VAR13;
reg VAR8, VAR6;
VAR12 VAR14 (1, VAR22, VAR8, VAR7);
VAR2 VAR15 (1, VAR8... | gpl-2.0 |
fredyamalves/Collision-detection-for-a-CPU-FPGA-heterogeneous-System | Verilog design/inputs_mem.v | 14,339 | module MODULE1 #(VAR50 = 20, VAR30 = 14, VAR84 = 512)
(
input clk,
input VAR89,
output [VAR50-1:0] VAR79,
output [VAR30-1:0] VAR7,
output reg VAR60,
input VAR5,
input VAR48,
input [VAR30-1:0] VAR87,
input [VAR84-1:0] VAR27,
output [VAR84-1:0] VAR80,
input [31:0] VAR81,
output reg VAR34
);
reg VAR64;
reg VAR32;
reg [VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.behavioral.pp.v | 1,495 | module MODULE1( VAR1, VAR8, VAR4, VAR2, VAR5 );
input VAR8, VAR1;
inout VAR2, VAR5;
output VAR4;
VAR3 VAR6(.VAR1(VAR1),.VAR8(VAR8),.VAR4(VAR4),.VAR2(VAR2),.VAR5(VAR5));
VAR3 VAR7(.VAR1(VAR1),.VAR8(VAR8),.VAR4(VAR4),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
ptracton/wb_dsp | rtl/wb_daq_slave_registers.v | 10,199 | module MODULE1 (
VAR15, VAR10, VAR4, VAR22, VAR11,
VAR6, VAR18,
VAR29, VAR26,
VAR5, VAR12,
VAR23, VAR16, interrupt,
VAR3, VAR2, VAR20, VAR25, VAR28, VAR21, VAR9,
VAR1, VAR7, VAR17, VAR14,
VAR30, VAR8,
VAR24
) ;
parameter VAR19 = 32;
parameter VAR13 = 8;
parameter VAR27 = 0;
input VAR3;
input VAR2;
input [VAR13-1:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2/sky130_fd_sc_hs__and2_1.v | 1,959 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR5 ,
VAR6,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR6;
input VAR3;
VAR2 VAR7 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4,
VAR1,
VAR5
);
output VAR4;
input VAR1;
input VAR5;
supply1 VAR6;
supply0 VAR3;
VAR2 VAR7 (
.... | apache-2.0 |
kkiningh/cs231n-project | src/rtl/MatrixInputQueue/aFifo_256x8.v | 5,919 | module MODULE1
VAR21 = 8,
VAR34 = (1 << VAR21))
(output reg [VAR44-1:0] VAR11,
output reg VAR14,
input wire VAR50,
input wire VAR40,
input wire [VAR44-1:0] VAR35,
output reg VAR48,
input wire VAR27,
input wire VAR24,
input wire VAR13);
reg [VAR44-1:0] VAR45 [VAR34-1:0];
wire [VAR21-1:0] VAR28, VAR31;
wire VAR17;
wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_2.v | 2,240 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR3 ,
VAR4,
VAR2,
VAR5 ,
VAR6
);
output VAR8 ;
input [15:0] VAR7 ;
input [15:0] VAR3 ;
input VAR4;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR1 VAR9 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR8,
VAR7,
VAR3
);... | apache-2.0 |
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