repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
hanw/sonic-lite | hw/verilog/timestamp/xgmii_mux.v | 4,373 | module MODULE1 (
VAR20,
VAR5,
VAR2,
VAR6,
VAR22,
sel,
VAR13);
input VAR20;
input [65:0] VAR5;
input [65:0] VAR2;
input [65:0] VAR6;
input [65:0] VAR22;
input [1:0] sel;
output [65:0] VAR13;
wire [65:0] VAR4;
wire [65:0] VAR12 = VAR22[65:0];
wire [65:0] VAR17 = VAR6[65:0];
wire [65:0] VAR3 = VAR2[65:0];
wire [65:0] VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi.behavioral.pp.v | 2,194 | module MODULE1 (
VAR15 ,
VAR12 ,
VAR6 ,
VAR1,
VAR8,
VAR5,
VAR14 ,
VAR4
);
output VAR15 ;
input VAR12 ;
input VAR6 ;
input VAR1;
input VAR8;
input VAR5;
input VAR14 ;
input VAR4 ;
wire VAR11 ;
wire VAR3 ;
wire VAR10 ;
wire VAR7;
not VAR9 (VAR11 , VAR1 );
and VAR2 (VAR3 , VAR12, VAR6 );
nor VAR18 (VAR10 , VAR11, VAR3 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b.functional.v | 1,417 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR4 ,
VAR7
);
output VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR7;
wire VAR2 ;
wire VAR8;
nor VAR5 (VAR2 , VAR6, VAR4 );
and VAR3 (VAR8, VAR7, VAR2 );
buf VAR9 (VAR1 , VAR8 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.behavioral.pp.v | 2,375 | module MODULE1( VAR5, VAR9, VAR6, VAR10, VAR3, VAR7, VAR4 );
input VAR10, VAR3, VAR9, VAR5;
inout VAR7, VAR4;
output VAR6;
VAR2 VAR1(.VAR5(VAR5),.VAR9(VAR9),.VAR6(VAR6),.VAR10(VAR10),.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4));
VAR2 VAR8(.VAR5(VAR5),.VAR9(VAR9),.VAR6(VAR6),.VAR10(VAR10),.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4)); | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/riffa/sg_list_reader_128.v | 4,700 | module MODULE1 #(
parameter VAR13 = 9'd128
)
(
input VAR6,
input VAR3,
input [VAR13-1:0] VAR9, input VAR12, output VAR18,
output VAR4, output VAR10, input VAR17, output [63:0] VAR1, output [31:0] VAR5 );
reg VAR15=VAR2, VAR15=VAR2;
reg VAR21=VAR16, VAR21=VAR16;
reg [VAR13-1:0] VAR20={VAR13{1'd0}}, VAR20={VAR13{1'd0}};
... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_1.functional.v | 1,494 | module MODULE1( VAR15, VAR16, VAR12, VAR5, VAR14 );
input VAR5, VAR14, VAR16, VAR15;
output VAR12;
wire VAR8;
not VAR17( VAR8, VAR5 );
wire VAR13;
not VAR1( VAR13, VAR14 );
wire VAR18;
and VAR10( VAR18, VAR8, VAR13 );
wire VAR2;
not VAR3( VAR2, VAR16 );
wire VAR11;
not VAR9( VAR11, VAR15 );
wire VAR4;
and VAR6( VAR4, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai.symbol.v | 1,375 | module MODULE1 (
input VAR3,
input VAR5,
input VAR9,
input VAR8,
output VAR1
);
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/CY7C67200_IF.v | 2,109 | module MODULE1( VAR6,
VAR2,
VAR3, VAR8,
VAR11,
VAR18,
VAR13,
VAR16,
VAR1,
VAR15,
VAR10,
VAR5,
VAR9,
VAR12,
VAR7,
VAR14
);
input [31:0] VAR6; input [1:0] VAR3; input VAR8; input VAR11; input VAR18; input VAR13; input VAR16; output [31:0] VAR2; output VAR1;
inout [15:0] VAR15;
output [1:0] VAR10;
output VAR5;
output VAR9... | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build2/trash.v | 55,285 | module MODULE1 (VAR9,VAR5,VAR27,VAR17,VAR6);
output [0:127] VAR6;
input [0:127] VAR9;
input [0:127] VAR5;
input [0:1] VAR27;
input [0:4] VAR17;
integer VAR31;
reg [0:127] VAR6;
reg [0:127] VAR19;
reg [0:15] VAR29;
reg [0:15] VAR20;
reg [0:15] VAR10;
reg [0:15] VAR1;
reg [0:15] VAR18;
reg [0:15] VAR2;
reg [0:15] VAR21;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill.behavioral.v | 1,114 | module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
zhangly/azpr_cpu | rtl/bus/rtl/bus_master_mux.v | 2,683 | module MODULE1 (
input wire [VAR17] VAR23, input wire VAR13, input wire VAR4, input wire [VAR2] VAR20, input wire VAR9, input wire [VAR17] VAR22, input wire VAR30, input wire VAR31, input wire [VAR2] VAR27, input wire VAR6, input wire [VAR17] VAR15, input wire VAR21, input wire VAR7, input wire [VAR2] VAR11, input wire... | mit |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_hps_0.v | 29,816 | module MODULE1 #(
parameter VAR71 = 2,
parameter VAR190 = 3
) (
output wire VAR66, input wire VAR86, input wire [7:0] VAR9, input wire [31:0] VAR73, input wire [3:0] VAR25, input wire [2:0] VAR174, input wire [1:0] VAR26, input wire [1:0] VAR153, input wire [3:0] VAR189, input wire [2:0] VAR180, input wire VAR58, outpu... | gpl-2.0 |
m-labs/milkymist | cores/pfpu/rtl/pfpu_i2f.v | 1,559 | module MODULE1(
input VAR8,
input VAR11,
input [31:0] VAR20,
input VAR10,
output [31:0] VAR19,
output VAR14
);
reg VAR12;
reg VAR7;
reg [30:0] VAR5;
reg VAR18;
always @(posedge VAR8) begin
if(VAR11)
VAR12 <= 1'b0;
end
else
VAR12 <= VAR10;
VAR7 <= VAR20[31];
if(VAR20[31])
VAR5 <= 31'd0 - VAR20[30:0];
else
VAR5 <= VAR20[... | lgpl-3.0 |
superibk/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_sha256/rtl/verilog/sha256.v | 3,521 | module MODULE1 (
input clk,
input VAR13,
input [511:0] VAR21,
input [255:0] VAR32,
output [255:0] VAR44,
output reg VAR7
);
localparam VAR4 = 64;
reg [31:0] VAR5, VAR12, VAR40, VAR8, VAR1, VAR42, VAR26, VAR23;
reg [31:0] VAR6, VAR33, VAR2, VAR36, VAR16, VAR46, VAR28, VAR24;
reg [31:0] VAR34, VAR18;
reg [6:0] VAR45, VAR... | apache-2.0 |
yanhongwang/ColorImage | ToneReproduction/ToneReproduction.v | 2,481 | module MODULE2
(
input[ VAR2 - 1 : 0 ]VAR15,
input[ VAR2 - 1 : 0 ]VAR9,
input[ VAR2 - 1 : 0 ]VAR6,
input[ VAR2 - 1 : 0 ]VAR7,
output reg[ VAR2 - 1 : 0 ]VAR5,
output reg[ VAR2 - 1 : 0 ]VAR13,
output reg[ VAR2 - 1 : 0 ]VAR1
);
always@( VAR15 )
begin
if( VAR15 <= VAR11 )
begin
VAR5 = ( ( VAR9 * VAR12 ) + b1 );
VAR13 = ( (... | mit |
MarcoVogt/basil | firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v | 3,146 | module MODULE1 (
VAR27, VAR6, VAR16, VAR3, VAR26, VAR32, VAR29, VAR8, VAR17, VAR28
);
input wire VAR27;
input wire VAR6;
input wire [0 : 0] VAR16;
input wire [13 : 0] VAR3;
input wire [7 : 0] VAR26;
input wire [0 : 0] VAR32;
input wire [12 : 0] VAR29;
input wire [15 : 0] VAR8;
output wire [7 : 0] VAR17;
output wire [15... | bsd-3-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcjesdadc1/vc707/system_top.v | 10,957 | module MODULE1 (
VAR10,
VAR82,
VAR58,
VAR48,
VAR39,
VAR20,
VAR1,
VAR107,
VAR87,
VAR108,
VAR35,
VAR86,
VAR4,
VAR55,
VAR73,
VAR84,
VAR46,
VAR115,
VAR123,
VAR83,
VAR33,
VAR11,
VAR5,
VAR63,
VAR94,
VAR21,
VAR28,
VAR25,
VAR13,
VAR76,
VAR118,
VAR17,
VAR14,
VAR59,
VAR68,
VAR36,
VAR121,
VAR16,
VAR72,
VAR31,
VAR97,
VAR24,
VAR90,... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/yf32/pc_next.v | 3,927 | module MODULE1 (clk, reset, VAR10, VAR8, VAR6,
VAR2, VAR5, VAR1, VAR9);
input clk;
input reset;
input [31:2] VAR10;
input VAR8;
input VAR6;
input [25:0] VAR2;
input [ 1:0] VAR5;
output [31:0] VAR1;
output [31:0] VAR9;
reg[31:2] MODULE1;
reg[31:2] VAR7;
wire [31:2] VAR4 = VAR7 + 1;
wire [31:0] VAR1 = {VAR7, 2'b00} ;
wir... | mit |
BigEd/beeb816 | pcb/l1b_mk2.v | 10,871 | module MODULE1();
supply0 VAR143;
supply1 VAR204;
wire VAR251, VAR127, VAR207, VAR268, VAR4, VAR14, VAR218, VAR182;
wire VAR65, VAR6, VAR7, VAR146, VAR106, VAR277, VAR30, VAR221;
wire VAR33, VAR290, VAR122, VAR47, VAR175, VAR203, VAR269, VAR194;
wire VAR107, VAR11, VAR187, VAR85, VAR181, VAR24, VAR266, VAR144;
wire VAR... | lgpl-2.1 |
roberth188/EMU-Hearing-Assistance-Device | EMU_Basic_Project/DM_TLV5619_DAC_Interface_Module.v | 1,786 | module MODULE1(
VAR7,
VAR14,
VAR11,
VAR12,
VAR8,
VAR10,
VAR2,
VAR5,
VAR1,
VAR4,
VAR9
);
input VAR11, VAR12, VAR4;
input [9:0] VAR1;
input [11:0] VAR5;
input [8:0] VAR9;
output VAR14, VAR8, VAR10, VAR2;
output [11:0] VAR7;
reg [11:0] VAR7;
reg [14:0] VAR13;
wire VAR12, VAR14, VAR4;
wire [11:0] VAR5;
wire [8:0] VAR9;
reg... | mit |
osrf/wandrr | firmware/motor_controller/fpga/udp_inbound_chain.v | 10,230 | module MODULE1
(input VAR35, input [7:0] VAR106,
input VAR111,
input VAR45, input VAR33, input [7:0] VAR74,
input VAR83,
input VAR48,
output [1:0] VAR42,
output VAR104);
localparam VAR89 = 4, VAR24 = 3;
localparam VAR49 = 4'd0;
localparam VAR82 = 4'd1;
localparam VAR84 = 4'd2;
localparam VAR22 = 4'd3;
localparam VAR95 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2_1.v | 2,086 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR4,
VAR8,
VAR1 ,
VAR7
);
output VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR1 ;
input VAR7 ;
VAR3 VAR9 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR5,
VAR6,
VAR2
);
output VAR5;
... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_016bits.v | 1,917 | module MODULE1 (
clk,
VAR4, VAR9, VAR5, VAR29, VAR25, VAR15, VAR2, VAR6,
sum,
);
input clk;
input [VAR23+0-1:0] VAR4, VAR9, VAR5, VAR29, VAR25, VAR15, VAR2, VAR6;
output [VAR23 :0] sum;
reg [VAR23 :0] sum;
wire [VAR23+3-1:0] VAR7;
wire [VAR23+2-1:0] VAR32, VAR3;
wire [VAR23+1-1:0] VAR12, VAR20, VAR8, VAR28;
reg [VAR23+... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b.behavioral.v | 1,497 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR8 ;
input VAR2;
supply1 VAR7;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR10 ;
wire VAR4 ;
wire VAR12;
not VAR11 (VAR4 , VAR8 );
and VAR9 (VAR12, VAR4, VAR2 );
buf VAR6 (VAR3 , VAR12 );
endmodule | apache-2.0 |
bobnewgard/fcs | ver/uut_1_top.v | 2,825 | module MODULE1
(
output wire [31:0] VAR15,
output wire [31:0] VAR7,
output wire [31:0] VAR19,
output wire VAR18,
input wire [7:0] VAR3,
input wire VAR13,
input wire VAR8,
input wire VAR14,
input wire VAR17,
input wire VAR4
);
reg [31:0] VAR10;
reg VAR22;
reg [31:0] VAR16;
reg [31:0] VAR11;
reg [31:0] VAR9;
reg VAR1;
VA... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Prueba6/fifo.v | 3,257 | module MODULE1 # (parameter VAR6 = 5, VAR13 = 8)(
input reset, VAR19,
input rd, wr,
input [VAR13-1:0] din,
output [VAR13-1:0] dout,
output VAR16,
output VAR15
);
wire VAR4, VAR18;
reg VAR11, VAR2, VAR1, VAR12;
reg [VAR13-1:0] out;
always @ (posedge VAR19) VAR11 <= wr;
always @ (posedge VAR19) VAR2 <= VAR11;
assign VAR4... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/ip_pid_controller/hdl/ip_pid_controller_entity_declarations.v | 21,340 | module MODULE2 (din, clk, VAR55, VAR18, en, dout);
parameter VAR15= 16;
parameter VAR29= 4;
parameter VAR4= VAR61;
parameter VAR23= 8;
parameter VAR48= 2;
parameter VAR6= VAR61;
parameter VAR17 = 1;
parameter VAR8 = 0;
parameter VAR60 = VAR61;
parameter VAR45 = 0;
parameter VAR42 = 0;
parameter VAR16= VAR33;
parameter ... | gpl-3.0 |
scarlso/LED_controller | Design01.cydsn/Design01.cydsn/STC_Datapath16_v1_0/STC_Datapath16_v1_0.v | 8,534 | module MODULE1 (
output VAR44,
output VAR39,
output VAR50,
input VAR9,
input VAR11
);
parameter VAR18 = 0;
parameter VAR60 = 0;
parameter VAR6 = 0;
parameter VAR41 = 0;
parameter VAR10 = 0;
parameter VAR35 = 0;
parameter VAR2 = 0;
parameter VAR14 = 0;
localparam VAR24 = 3'h0;
localparam VAR43 = 3'h1;
localparam VAR33 =... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/minimac/rtl/minimac_graycounter.v | 1,187 | module MODULE1
(output reg [VAR7-1:0] VAR4,
input wire VAR1, input wire VAR5,
input wire VAR6);
reg [VAR7-1:0] VAR2;
always @ (posedge VAR6)
if (VAR5) begin
VAR2 <= {VAR7{1'VAR3 0}} + 1; VAR4 <= {VAR7{1'VAR3 0}}; end
else if (VAR1) begin
VAR2 <= VAR2 + 1;
VAR4 <= {VAR2[VAR7-1],
VAR2[VAR7-2:0] ^ VAR2[VAR7-1:1]};
end
end... | lgpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/V2NFC100DDR/src/NPCG_Toggle_SCC_N_poe.v | 4,312 | module MODULE1
(
parameter VAR22 = 4
)
(
VAR8 ,
VAR1 ,
VAR18 ,
VAR7 ,
VAR20 ,
VAR9 ,
VAR5 ,
VAR17 ,
VAR10 ,
VAR14 ,
VAR15 ,
VAR19 ,
VAR11 ,
VAR21
);
input VAR8 ;
input VAR1 ;
input [5:0] VAR18 ;
input [4:0] VAR7 ;
input [4:0] VAR20 ;
input VAR9 ;
output VAR5 ;
output VAR17 ;
output VAR10 ;
input [7:0] VAR14 ;
input [7:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n.blackbox.v | 1,367 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR3 ;
input VAR5;
supply1 VAR6;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
strigeus/fpganes | src/ppu.v | 32,343 | module MODULE1(input clk, input VAR11,
input VAR7,
input [2:0] VAR12, input [7:0] din, input read, input write, input VAR5, input [8:0] VAR2,
output [14:0] VAR6,
output [2:0] VAR1); reg VAR9; reg [14:0] VAR8;
reg [14:0] VAR3;
reg [2:0] VAR4;
reg VAR10; | gpl-3.0 |
lab1-ufba/Genius | pll_bb.v | 12,986 | module MODULE1 (
VAR2,
VAR4,
VAR1,
VAR3);
input VAR2;
output VAR4;
output VAR1;
output VAR3;
endmodule | gpl-3.0 |
hacktoberfest17/programming | computer_architecture/Day-4/rca.v | 2,237 | module MODULE2(VAR3,VAR28,VAR20,VAR8,VAR4,VAR1,VAR22,VAR24,b0,b1,VAR19,VAR9,VAR5,VAR25,VAR12,VAR27,VAR7,VAR2,VAR23,VAR18,VAR11,VAR21,VAR17,VAR6,VAR15,VAR10,VAR14,VAR16,VAR29,VAR26,VAR30,VAR13);
input VAR3,VAR28,VAR20,VAR8,VAR4,VAR1,VAR22,VAR24,b0,b1,VAR19,VAR9,VAR5,VAR25,VAR12,VAR27;
output VAR7,VAR2,VAR23,VAR18,VAR11,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba.behavioral.v | 1,958 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR10 ,
VAR11,
VAR7,
VAR3
);
output VAR9 ;
input VAR5 ;
input VAR10 ;
input VAR11;
input VAR7;
input VAR3;
wire VAR14 ;
wire VAR4 ;
wire VAR6;
nor VAR12 (VAR14 , VAR5, VAR10 );
nor VAR2 (VAR4 , VAR11, VAR14 );
VAR13 VAR1 (VAR6, VAR4, VAR7, VAR3);
buf VAR8 (VAR9 , VAR6 );
endmodule | apache-2.0 |
iamllama/EE2020 | ee2020.srcs/sources_1/imports/new/seg_disp.v | 2,689 | module MODULE3(
input clk,
input[7:0] VAR7,
input[7:0] VAR5,
input[7:0] VAR6,
input[7:0] VAR12,
input VAR10,
output reg[6:0] VAR3,
output reg[3:0] VAR20,
output VAR25
);
wire[6:0] VAR14;
wire[6:0] VAR19;
wire[6:0] VAR18;
wire[6:0] VAR22;
reg[2:0] state = 0;
assign VAR25 = 1;
MODULE1 MODULE3(VAR7, VAR14);
MODULE1 MODULE... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.blackbox.v | 1,311 | module MODULE1 (
VAR3,
VAR1 ,
VAR2 ,
VAR4
);
output VAR3;
input VAR1 ;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/altera/ad_lvds_clk.v | 2,911 | module MODULE1 (
VAR1,
VAR5,
clk);
parameter VAR2 = 0;
localparam VAR4 = 0;
localparam VAR3 = 1;
input VAR1;
input VAR5;
output clk;
assign clk = VAR1;
endmodule | gpl-3.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_clockgen.v | 5,582 | module MODULE1(VAR6, VAR1, VAR4, VAR2, VAR10, VAR7);
parameter VAR8=1;
input VAR6; input VAR1; input [7:0] VAR4;
output VAR7; output VAR2; output VAR10;
reg VAR7;
reg [7:0] VAR11;
wire VAR9;
wire [7:0] VAR3;
wire [7:0] VAR5;
assign VAR5[7:0] = (VAR4[7:0]<2)? 8'h02 : VAR4[7:0]; assign VAR3[7:0] = (VAR5[7:0]>>1) - 1'b1;
... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/bank_common.v | 17,377 | module MODULE1 #
(
parameter VAR110 = 100,
parameter VAR103 = 2,
parameter VAR115 = 1,
parameter VAR9 = 4,
parameter VAR98 = 2,
parameter VAR11 = 0,
parameter VAR113 = 44,
parameter VAR46 = 2,
parameter VAR101 = 4,
parameter VAR20 = 5, parameter VAR28 = 64
)
(
VAR55, VAR35, VAR43, VAR75,
VAR39, VAR17, VAR21, VAR42, VAR... | lgpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_37.v | 25,198 | module MODULE2 (
clk,
reset,
VAR144,
VAR45,
VAR67,
VAR168,
VAR50
);
parameter VAR173 = 18;
parameter VAR137 = 37;
parameter VAR95 = 19;
localparam VAR98 = 38;
input clk;
input reset;
input VAR144;
input VAR45;
input [VAR173-1:0] VAR67; output VAR168;
output [VAR173-1:0] VAR50;
localparam VAR107 = 18; localparam VAR62 =... | mit |
MIPSfpga/schoolMIPS | board/de4_230/de4_230.v | 1,576 | module MODULE1
(
input VAR24,
output VAR3,
input VAR30,
input VAR29,
input VAR8,
input VAR15,
input VAR7,
input VAR23,
input VAR11,
output [7:0] VAR10,
input [3:0] VAR9,
input VAR16, inout VAR5,
input [7:0] VAR1, input [3:0] VAR6, output [6:0] VAR18,
output VAR26,
output [6:0] VAR12,
output VAR4
);
wire clk;
wire VAR20... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/verilog/ANN_fcmp_32ns_32ns_1_1.v | 2,372 | module MODULE1
VAR40 = 5,
VAR5 = 1,
VAR37 = 32,
VAR15 = 32,
VAR41 = 1
)(
input wire [VAR37-1:0] VAR33,
input wire [VAR15-1:0] VAR38,
input wire [4:0] VAR31,
output wire [VAR41-1:0] dout
);
localparam [4:0]
VAR16 = 5'b00001,
VAR26 = 5'b00010,
VAR17 = 5'b00011,
VAR25 = 5'b00100,
VAR7 = 5'b00101,
VAR35 = 5'b00110,
VAR22 =... | gpl-3.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_microblaze_0_xlconcat_0/system_microblaze_0_xlconcat_0_stub.v | 1,461 | module MODULE1(VAR2, VAR7, VAR1, VAR4, VAR3, VAR5, VAR6, dout)
;
input [0:0]VAR2;
input [0:0]VAR7;
input [0:0]VAR1;
input [0:0]VAR4;
input [0:0]VAR3;
input [0:0]VAR5;
input [0:0]VAR6;
output [6:0]dout;
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/v6_emac_v2_2_block.v | 21,826 | module MODULE1 (
input VAR38,
output [27:0] VAR122,
output VAR58,
output VAR14,
output VAR76,
output [7:0] VAR44,
output VAR90,
output VAR21,
output VAR87,
input [7:0] VAR96,
output [31:0] VAR52,
output VAR128,
output VAR91,
output VAR18,
input [7:0] VAR26,
input VAR105,
input VAR9,
input VAR124,
output VAR72,
output V... | mit |
alexforencich/xfcp | lib/eth/rtl/eth_axis_rx.v | 15,360 | module MODULE1 #
(
parameter VAR21 = 8,
parameter VAR16 = (VAR21>8),
parameter VAR25 = (VAR21/8)
)
(
input wire clk,
input wire rst,
input wire [VAR21-1:0] VAR10,
input wire [VAR25-1:0] VAR13,
input wire VAR8,
output wire VAR26,
input wire VAR11,
input wire VAR9,
output wire VAR3,
input wire VAR22,
output wire [47:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbn/sky130_fd_sc_ls__dlrbn.functional.v | 1,942 | module MODULE1 (
VAR5 ,
VAR13 ,
VAR12,
VAR10 ,
VAR6
);
output VAR5 ;
output VAR13 ;
input VAR12;
input VAR10 ;
input VAR6 ;
wire VAR1 ;
wire VAR4;
wire VAR11 ;
not VAR15 (VAR1 , VAR12 );
not VAR3 (VAR4, VAR6 );
VAR2 VAR9 VAR8 (VAR11 , VAR10, VAR4, VAR1);
buf VAR7 (VAR5 , VAR11 );
not VAR14 (VAR13 , VAR11 );
endmodule | apache-2.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/ingress_buffer_manager.v | 18,400 | module MODULE1 #(
parameter VAR21 = 12, parameter VAR39 = 9
)(
input clk,
input rst,
input VAR52, input [1:0] VAR18, output reg VAR101, output reg [1:0] VAR59,
input VAR65, input VAR26, input VAR28, output reg VAR31, output [7:0] VAR85, output [9:0] VAR64, output [11:0] VAR48, output reg VAR46, output VAR17,
input VAR6... | mit |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_uart.v | 26,742 | module MODULE1 (
VAR30,
VAR15,
clk,
VAR92,
VAR88,
VAR97,
VAR83,
VAR101,
VAR19,
VAR40,
VAR80,
VAR2,
VAR44
)
;
output VAR40;
output VAR80;
output VAR2;
output VAR44;
input [ 9: 0] VAR30;
input VAR15;
input clk;
input VAR92;
input VAR88;
input VAR97;
input VAR83;
input [ 7: 0] VAR101;
input VAR19;
reg VAR20;
reg [ 9: 0] V... | gpl-3.0 |
cpulabs/mist1032isa | src/core/execute/execute_debugger.v | 2,567 | module MODULE1(
input wire VAR15,
input wire VAR9,
input wire VAR4,
input wire VAR6,
input wire VAR2,
input wire VAR17,
output wire VAR16,
output wire [31:0] VAR3,
output wire VAR11,
input wire [4:0] VAR7,
input wire VAR14
);
localparam VAR5 = 2'h0;
localparam VAR13 = 2'h1;
localparam VAR8 = 2'h2;
reg [1:0] VAR12;
reg ... | bsd-2-clause |
eda-globetrotter/PicenoDecoders | extra_credit/encoder.v | 1,237 | module MODULE1 (VAR2,VAR3);
output reg [14:0] VAR3;
input [10:0] VAR2;
reg [3:0] VAR1;
always @(*)
begin
VAR1[0]=VAR2[0]^VAR2[1]^VAR2[3]^VAR2[4]^VAR2[6]^VAR2[8]^VAR2[10];
VAR1[1]=((VAR2[0]^VAR2[2])^(VAR2[3]^VAR2[5]))^((VAR2[6]^VAR2[9])^VAR2[10]);
VAR1[2]=((VAR2[1]^VAR2[2])^(VAR2[3]^VAR2[7]))^((VAR2[8]^VAR2[9])^VAR2[10]... | mit |
antmicro/yosys | techlibs/ice40/arith_map.v | 2,172 | module MODULE1(
module 80ice40alu (VAR11, VAR23, VAR9, VAR31, VAR10, VAR1, VAR6);
parameter VAR19 = 0;
parameter VAR14 = 0;
parameter VAR12 = 1;
parameter VAR29 = 1;
parameter VAR2 = 1;
input [VAR12-1:0] VAR11;
input [VAR29-1:0] VAR23;
output [VAR2-1:0] VAR10, VAR1;
input VAR9, VAR31;
output [VAR2-1:0] VAR6;
wire VAR8 ... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai_1.v | 2,261 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR4 ,
VAR7 ,
VAR8,
VAR9,
VAR2 ,
VAR1
);
output VAR10 ;
input VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR8;
input VAR9;
input VAR2 ;
input VAR1 ;
VAR5 VAR3 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_7x_v1_8_pipe_clock.v | 21,021 | module MODULE1 #
(
parameter VAR8 = "VAR15", parameter VAR12 = "VAR15", parameter VAR95 = 1, parameter VAR90 = 3, parameter VAR25 = 0, parameter VAR87 = 2, parameter VAR143 = 2, parameter VAR114 = 1, parameter VAR46 = 0
)
(
input VAR121,
input VAR110,
input [VAR95-1:0] VAR122,
input VAR91,
input [VAR95-1:0] VAR39,
inpu... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_core/altera_tse_rgmii_in1.v | 5,071 | module MODULE1 (
VAR10,
VAR14,
VAR7,
VAR9,
VAR5);
input VAR10;
input VAR14;
input VAR7;
output VAR9;
output VAR5;
wire [0:0] VAR6;
wire [0:0] VAR8;
wire [0:0] VAR18 = VAR6[0:0];
wire VAR9 = VAR18;
wire [0:0] VAR13 = VAR8[0:0];
wire VAR5 = VAR13;
wire VAR21 = VAR14;
wire VAR12 = VAR21;
VAR22 VAR3 (
.VAR14 (VAR12),
.VAR7... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_PPS_OPENFLOW/DISPATHER/DISPATHER_OUTPUT_zyl.v | 6,483 | module MODULE1(
input clk,
input reset,
input VAR38,input [133:0] VAR9,input VAR40,input VAR46,output VAR18,
input VAR49,input [133:0] VAR23,input VAR12,input VAR6,output VAR20,
output reg VAR26,output reg [133:0] VAR3,output reg VAR19,output reg VAR30,input VAR39
);
wire VAR27;
wire VAR22;
reg VAR31;
wire [7:0] VAR37;... | apache-2.0 |
bargei/NoC264 | NoC264_3x3/mkRouterInputArbitersRoundRobin.v | 37,229 | module MODULE1(VAR215,
VAR2,
VAR157,
VAR91,
VAR4,
VAR57,
VAR78,
VAR19,
VAR118,
VAR115,
VAR40,
VAR3,
VAR205,
VAR13,
VAR117,
VAR64,
VAR81);
input VAR215;
input VAR2;
input [4 : 0] VAR157;
output [4 : 0] VAR91;
input VAR4;
input [4 : 0] VAR57;
output [4 : 0] VAR78;
input VAR19;
input [4 : 0] VAR118;
output [4 : 0] VAR115;... | mit |
alexforencich/verilog-axis | rtl/axis_demux.v | 10,715 | module MODULE1 #
(
parameter VAR11 = 4,
parameter VAR19 = 8,
parameter VAR13 = (VAR19>8),
parameter VAR15 = ((VAR19+7)/8),
parameter VAR21 = 0,
parameter VAR6 = 8,
parameter VAR25 = 0,
parameter VAR30 = 8,
parameter VAR31 = VAR30+VAR22(VAR11),
parameter VAR8 = 1,
parameter VAR10 = 1,
parameter VAR17 = 0
)
(
input wire ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_4.behavioral.v | 1,170 | module MODULE1( VAR3, VAR5, VAR4 );
input VAR3, VAR5;
output VAR4;
VAR1 VAR2(.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4));
VAR1 VAR6(.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_scaler_multiply_width.v | 6,273 | module MODULE1 (
clk,
reset,
VAR12,
VAR3,
VAR8,
VAR5,
VAR16,
VAR6,
VAR9,
VAR4,
VAR1,
VAR13,
VAR10,
VAR18
);
parameter VAR20 = 15; parameter VAR15 = 15;
parameter VAR7 = 0;
input clk;
input reset;
input [VAR20: 0] VAR12;
input [VAR15: 0] VAR3;
input VAR8;
input VAR5;
input VAR16;
input VAR6;
output VAR9;
output reg [VAR... | gpl-3.0 |
Nrpickle/ECE272 | Lab3_7SegDisplayDriver/section3_schematic_tf.v | 1,543 | module MODULE1();
reg VAR2;
reg VAR10;
reg VAR3;
reg VAR8;
wire VAR11;
wire VAR4;
wire VAR6;
wire VAR12;
wire VAR13;
wire VAR9;
wire VAR1;
VAR7 VAR5 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR13(VAR13),
.VAR9(VAR9),
.VAR1(VAR1)
); | mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v | 5,685 | module MODULE1 #
(
parameter integer VAR27 = 4
)
(
input wire clk,
input wire reset,
output wire [VAR27-1:0] VAR46,
output wire [1:0] VAR17,
output wire VAR23,
input wire VAR51,
input wire [1:0] VAR8,
input wire VAR11,
output wire VAR44,
input wire VAR47,
input wire [VAR27-1:0] VAR26,
input wire [7:0] VAR33,
input wire... | mit |
pradeep9676/pradeep_9676 | LZD_16bit.v | 1,549 | module MODULE1( in, out, valid
);
input [15:0]in;
output reg [3:0]out;
output reg valid;
wire VAR2,VAR3;
wire [2:0]VAR1, VAR4;
begin
begin
begin
end
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o_4.v | 2,342 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR9 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR10,
VAR2
);
output VAR6 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR10;
input VAR2;
VAR8 VAR3 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a.symbol.v | 1,357 | module MODULE1 (
input VAR1,
input VAR2,
input VAR4,
input VAR5,
input VAR6,
output VAR3
);
supply1 VAR7;
supply0 VAR8;
endmodule | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/altera_mult_add_opt2.v | 15,361 | module MODULE1
(
VAR209,
VAR120,
VAR210,
VAR237,
VAR91) ;
input VAR209;
input VAR120;
input [15:0] VAR210;
input [15:0] VAR237;
output [15:0] VAR91;
tri0 VAR209;
tri1 VAR120;
tri0 [15:0] VAR210;
tri0 [15:0] VAR237;
wire [15:0] VAR274;
VAR28 VAR284
(
.VAR209(VAR209),
.VAR107(),
.VAR120(VAR120),
.VAR210(VAR210),
.VAR237(... | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/ptp_ts_extract.v | 2,028 | module MODULE1 #
(
parameter VAR1 = 96,
parameter VAR9 = 1,
parameter VAR4 = VAR1+VAR9
)
(
input wire clk,
input wire rst,
input wire VAR3,
input wire VAR2,
input wire [VAR4-1:0] VAR8,
output wire [VAR1-1:0] VAR5,
output wire VAR6
);
reg VAR7 = 1'b0;
assign VAR5 = VAR8 >> VAR9;
assign VAR6 = VAR3 && !VAR7;
always @(pos... | mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_processing_system7_0_0/hdl/verilog/processing_system7_v5_3_trace_buffer.v | 8,668 | module MODULE1 #
(
parameter integer VAR28 = 128,
parameter integer VAR30 = 0,
parameter integer VAR1 = 12
)
(
input wire VAR29,
input wire VAR16,
input wire VAR13,
input wire [3:0] VAR6,
input wire [31:0] VAR24,
output wire VAR7,
output wire [3:0] VAR9,
output wire [31:0] VAR12
);
function integer VAR4 (input integer ... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/tlu/rtl/tlu_mmu_dp.v | 54,613 | module MODULE1 (
VAR12, VAR30, VAR189,
VAR102, VAR26,
VAR49, VAR191, VAR48,
VAR23, VAR14, VAR188,
VAR94, VAR43, VAR9, VAR61,
VAR157, VAR224, VAR74,
VAR34, VAR171, VAR164, VAR110,
VAR47, VAR190, VAR28,
VAR96, VAR98, VAR123,
VAR145, VAR59,
VAR92, VAR50,VAR244, VAR84,
VAR71,
VAR142, VAR218, VAR52,
VAR172, VAR87, VAR22,
VA... | gpl-2.0 |
freecores/zet86 | soc/vga/rtl/ram2k_b16.v | 3,246 | module MODULE1 (clk, rst, VAR11, VAR1, addr, VAR5, VAR13);
input clk;
input rst;
input VAR11;
input VAR1;
input [10:0] addr;
output [7:0] VAR5;
input [7:0] VAR13;
wire VAR4;
VAR7 VAR3 (.VAR8(VAR5),
.VAR2 (VAR4),
.VAR14 (addr),
.VAR6 (clk),
.VAR16 (VAR13),
.VAR10 (VAR4),
.VAR17 (VAR11),
.VAR9 (rst),
.VAR15 (VAR1));
end... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufinv/sky130_fd_sc_hs__bufinv.pp.blackbox.v | 1,206 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR2,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR2;
input VAR1;
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/utils/cdc_reset_sync.v | 1,127 | module MODULE1 (
input wire VAR10,
input wire VAR7,
input wire VAR3,
output wire VAR8
);
wire VAR9;
reg [1:0] VAR2;
always@(posedge VAR10) begin
VAR2[0] <= VAR7;
VAR2[1] <= VAR2[0];
end
reg VAR5;
VAR4 VAR5 = 0; always@(posedge VAR10) begin
if (VAR2[1])
VAR5 <= 1;
end
else if (VAR9)
VAR5 <= 0;
end
reg [2:0] VAR1;
always... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fsb/bsg_fsb_node_level_shift_fsb_domain.v | 3,332 | module MODULE1 #(parameter VAR27(VAR28 ))
(
input VAR10,
input VAR25,
input VAR13,
output VAR24,
output VAR16,
output VAR15,
output [VAR28-1:0] VAR4,
input VAR19,
input VAR1,
input [VAR28-1:0] VAR14,
output VAR9,
output VAR33,
output [VAR28-1:0] VAR29,
input VAR11,
input VAR12,
input [VAR28-1:0] VAR22,
output VAR20
);
... | bsd-3-clause |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/wb32_blockram.v | 4,912 | module MODULE1(
VAR23,
VAR24,
VAR15,
VAR21,
VAR40,
VAR6,
VAR10,
VAR18,
VAR26,
VAR13,
VAR2,
VAR27,
VAR39,
VAR5,
VAR20,
VAR30,
VAR4,
VAR37
);
input VAR23, VAR24;
input [10:0] VAR15, VAR2;
input [31:0] VAR21, VAR27;
input VAR6, VAR5, VAR10, VAR20, VAR26, VAR4;
input [3:0] VAR13, VAR37;
output [31:0] VAR40, VAR39;
output r... | gpl-2.0 |
parallella/oh | enoc/hdl/emesh_readback.v | 3,185 | module MODULE1 (
VAR17, VAR14, VAR5,
VAR2, clk, VAR18, VAR26, VAR21, VAR12
);
parameter VAR15 = 32; parameter VAR25 = 104;
input VAR2; input clk;
input VAR18; input [VAR25-1:0] VAR26; output VAR17;
input [63:0] VAR21;
output VAR14; output [VAR25-1:0] VAR5; input VAR12;
wire [12:0] VAR20; wire [VAR15-1:0] VAR24; wire [1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe_8.v | 1,899 | module MODULE2 (
VAR4,
VAR6,
VAR1 ,
VAR3
);
input VAR4;
input VAR6;
input VAR1 ;
input VAR3 ;
VAR2 VAR5 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR4;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR3 ;
VAR2 VAR5 ();
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | extra_credit/syn/netlist/spare/decoder.v | 1,923 | module MODULE1 (VAR5,VAR3);
output reg [10:0] VAR3;
input [14:0] VAR5;
reg [3:0] VAR2;
reg [3:0] VAR6;
reg [3:0] VAR4;
reg [14:0] VAR1;
always @(*)
begin
VAR2[0]=VAR5[2]^VAR5[4]^VAR5[6]^VAR5[8]^VAR5[10]^VAR5[12]^VAR5[14];
VAR2[1]=VAR5[2]^VAR5[5]^VAR5[6]^VAR5[9]^VAR5[10]^VAR5[13]^VAR5[14];
VAR2[2]=VAR5[4]^VAR5[5]^VAR5[6... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311oi/sky130_fd_sc_ls__a311oi.pp.blackbox.v | 1,429 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR9 ,
VAR4,
VAR1,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR9 ;
input VAR4;
input VAR1;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_1_0/mig_wrap_proc_sys_reset_1_0_stub.v | 1,811 | module MODULE1(VAR2, VAR4, VAR10,
VAR7, VAR3, VAR9, VAR8, VAR6,
VAR1, VAR5)
;
input VAR2;
input VAR4;
input VAR10;
input VAR7;
input VAR3;
output VAR9;
output [0:0]VAR8;
output [0:0]VAR6;
output [0:0]VAR1;
output [0:0]VAR5;
endmodule | mit |
rkrajnc/minimig-mist | rtl/minimig/userio.v | 18,836 | module MODULE1 (
input wire clk, input wire reset, input wire VAR111,
input wire VAR47,
input wire VAR66,
input wire VAR84,
input wire VAR115, input wire VAR101, input wire VAR109,
input wire [ 9-1:1] VAR36, input wire [ 16-1:0] VAR16, output reg [ 16-1:0] VAR32, inout wire VAR108, inout wire VAR85, output wire VAR87, ... | gpl-3.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/ram_controller_phy_alt_mem_phy_pll.v | 22,785 | module MODULE1 (
VAR118,
VAR127,
VAR38,
VAR82,
VAR90,
VAR137,
VAR98,
VAR42,
VAR85,
VAR110,
VAR64,
VAR71,
VAR35);
input VAR118;
input VAR127;
input [2:0] VAR38;
input VAR82;
input VAR90;
input VAR137;
output VAR98;
output VAR42;
output VAR85;
output VAR110;
output VAR64;
output VAR71;
output VAR35;
tri0 VAR118;
tri0 [2:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregsbp/sky130_fd_sc_lp__sregsbp.behavioral.pp.v | 2,875 | module MODULE1 (
VAR16 ,
VAR26 ,
VAR13 ,
VAR29 ,
VAR23 ,
VAR7 ,
VAR4,
VAR31 ,
VAR28 ,
VAR21 ,
VAR24
);
output VAR16 ;
output VAR26 ;
input VAR13 ;
input VAR29 ;
input VAR23 ;
input VAR7 ;
input VAR4;
input VAR31 ;
input VAR28 ;
input VAR21 ;
input VAR24 ;
wire VAR5 ;
wire VAR30 ;
wire VAR25 ;
reg VAR11 ;
wire VAR2 ;
wi... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/aemb/aeMB_xecu.v | 12,765 | module MODULE1 (
VAR78, VAR66, VAR76, VAR64, VAR58, VAR29,
VAR27, VAR52,
VAR21, VAR46, VAR25, VAR7, VAR38, VAR17, VAR47, VAR1, VAR60, VAR12,
VAR54, VAR10, VAR8, VAR74, VAR55, VAR37, VAR20, VAR24, VAR3, VAR11
);
parameter VAR30=32;
parameter VAR35=0;
parameter VAR5=0;
output [VAR30-1:2] VAR78;
output [3:0] VAR66;
output... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_operandmuxes.v | 6,581 | module MODULE1(
clk, rst,
VAR2, VAR5, VAR16, VAR18, VAR6, VAR11,
VAR17, VAR8, VAR15, VAR19, VAR3, VAR4
);
parameter VAR9 = VAR1;
input clk;
input rst;
input VAR2;
input VAR5;
input [VAR9-1:0] VAR16;
input [VAR9-1:0] VAR18;
input [VAR9-1:0] VAR6;
input [VAR9-1:0] VAR11;
input [VAR9-1:0] VAR17;
input [VAR12-1:0] VAR8;
in... | gpl-3.0 |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/system1_nios2_gen2_0.v | 5,783 | module MODULE1 (
input wire clk, input wire VAR24, input wire VAR6, output wire [20:0] VAR16, output wire [3:0] VAR3, output wire VAR18, input wire [31:0] VAR9, input wire VAR14, output wire VAR8, output wire [31:0] VAR21, output wire VAR12, output wire [20:0] VAR13, output wire VAR19, input wire [31:0] VAR5, input wir... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/halfband_ideal.v | 3,312 | module MODULE1 (
input VAR2,
input reset,
input enable,
input VAR6,
input wire signed [17:0] VAR9,
output reg VAR8,
output reg signed [17:0] VAR1
) ;
parameter VAR4 = 1 ;
parameter VAR5 = 2 ;
reg signed [40:0] VAR3 ;
reg signed [17:0] delay[30:0] ;
reg signed [17:0] VAR7[30:0] ;
reg [7:0] VAR11 ;
integer VAR10 ; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1.functional.pp.v | 1,867 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR1,
VAR3,
VAR2 ,
VAR4
);
output VAR9 ;
input VAR11 ;
input VAR1;
input VAR3;
input VAR2 ;
input VAR4 ;
wire VAR12 ;
wire VAR5;
not VAR6 (VAR12 , VAR11 );
VAR7 VAR10 (VAR5, VAR12, VAR1, VAR3);
buf VAR8 (VAR9 , VAR5 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_rdwr_data_tmg.v | 127,864 | module MODULE1
VAR124 = 2,
VAR61 = 8,
VAR16 = 1,
VAR121 = 1,
VAR104 = 6,
VAR89 = 1,
VAR188 = 10,
VAR187 = 0,
VAR131 = 0,
VAR138 = 2,
VAR2 = 1,
VAR67 = 1
)
(
VAR27,
VAR132,
VAR151,
VAR147,
VAR15,
VAR63,
VAR40,
VAR48, VAR184,
VAR102,
VAR133,
VAR19,
VAR100,
VAR56,
VAR144, VAR47,
VAR64,
VAR91,
VAR154,
VAR38,
VAR66,
VAR62,
... | lgpl-3.0 |
fallen/milkymist-mmu | cores/hpdmc_ddr32/rtl/hpdmc_ctlif.v | 3,300 | module MODULE1 #(
parameter VAR7 = 4'h0
) (
input VAR12,
input VAR15,
input [13:0] VAR10,
input VAR17,
input [31:0] VAR6,
output reg [31:0] VAR25,
output reg VAR8,
output reg VAR22,
output reg VAR11,
output reg VAR9,
output reg VAR13,
output reg VAR19,
output reg VAR5,
output reg [12:0] VAR1,
output reg [1:0] VAR2,
out... | lgpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.ip_user_files/ipstatic/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry.v | 4,336 | module MODULE1 #
(
parameter VAR8 = "VAR11"
)
(
input wire VAR4,
input wire VAR3,
input wire VAR2,
output wire VAR6
);
generate
if ( VAR8 == "VAR1" ) begin : VAR13
assign VAR6 = (VAR4 & VAR3) | (VAR2 & ~VAR3);
end else begin : VAR5
VAR10 VAR7
(
.VAR9 (VAR6),
.VAR12 (VAR4),
.VAR2 (VAR2),
.VAR3 (VAR3)
);
end
endgenerate
... | gpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v | 8,651 | module MODULE1 (VAR37, VAR7, VAR22, VAR30, VAR27, VAR36,
VAR5, VAR21, VAR3, VAR15, VAR9, VAR28,
VAR12, VAR29, VAR4, VAR38, VAR13, VAR6, VAR1, VAR31,
VAR11, VAR34, VAR10, VAR24, VAR17, VAR25,
VAR14, VAR19, VAR23, VAR32, VAR26, VAR16
);
input VAR38; input VAR13; input VAR37; input VAR7; input [1:0] VAR22; input VAR30; in... | gpl-2.0 |
chriz2600/DreamcastHDMI | Core/source/dc_video_reconfig.v | 2,423 | module MODULE1(
input VAR2,
input [7:0] VAR5,
output VAR8 VAR6,
output VAR1
);
reg [7:0] VAR7 = 0;
reg VAR4;
VAR8 VAR3; | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPM_Toggle_PIR.v | 6,309 | module MODULE1
(
VAR21 ,
VAR10 ,
VAR20 ,
VAR9 ,
VAR19 ,
VAR18 ,
VAR12
);
input VAR21 ;
input VAR10 ;
output VAR20 ;
output VAR9 ;
input VAR19 ;
output VAR18 ;
input VAR12 ;
parameter VAR16 = 6;
parameter VAR14 = 6'b000001;
parameter VAR8 = 6'b000010;
parameter VAR4 = 6'b000100; parameter VAR1 = 6'b001000; parameter VAR... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build1/regfile.v | 1,844 | module MODULE1(VAR3, VAR4, VAR7, VAR2, VAR5, clk);
parameter VAR6 = 8; parameter VAR1 = 8;
output [VAR1-1:0] VAR3;
input [VAR1-1:0] VAR4;
input clk;
input VAR5;
input [VAR6-1:0] VAR7, VAR2;
reg [VAR1-1:0] VAR3; reg [VAR6-1:0] MODULE1 [VAR1-1:0];
always @(posedge clk)
begin
if(VAR5)
begin
MODULE1[VAR7] <= VAR4;
end
else... | mit |
ychaim/FPGA-Litecoin-Miner | ICARUS-LX150/pbkdfengine.v | 20,275 | module MODULE1
(VAR31, VAR77, VAR58, VAR25, VAR23, VAR90, VAR108, VAR44, VAR7, VAR103, VAR24,
VAR40, VAR57, VAR35, VAR48, VAR45, VAR94, VAR88);
input VAR31; input VAR77;
input [255:0] VAR58;
input [255:0] VAR25;
input [127:0] VAR23;
input [31:0] VAR90;
input [3:0] VAR108;
output [31:0] VAR44;
output [31:0] VAR7;
output... | gpl-3.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/DE2_115_makomk_serial/sha256_transform.v | 7,740 | module MODULE3 #(
parameter VAR12 = 6'd4
) (
input clk,
input VAR29,
input [5:0] VAR74,
input [255:0] VAR18,
input [511:0] VAR67,
output reg [255:0] VAR4
);
localparam VAR62 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/bsg_source_sync_output.v | 12,731 | module MODULE1
parameter VAR8 = 5
, parameter VAR56 = 3 , parameter VAR68 = 8
, parameter VAR22 = {VAR68 { 2'b01 } }
)
(
input VAR6
, input VAR18
, input [VAR68-1:0] VAR47
, input VAR59
, output VAR5
, input VAR64
, input VAR50 , input VAR19
, input VAR13
, input [VAR68:0] VAR43
, output VAR63
, output logic VAR66 , ou... | bsd-3-clause |
firedom/combin-for-FPGA | src/decoders38.v | 2,278 | module MODULE1(in, out, en);
input [0:2]in;
input [0:2]en;
output [0:7]out;
wire VAR2;
and
VAR3(VAR2, en[0], ~en[1], ~en[2]);
nand
VAR1(out[0], ~in[2], ~in[1], ~in[0], VAR2),
VAR10(out[1], ~in[2], ~in[1], in[0], VAR2),
VAR6(out[2], ~in[2], in[1], ~in[0], VAR2),
VAR5(out[3], ~in[2], in[1], in[0], VAR2),
VAR8(out[4], in[... | gpl-3.0 |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/ip/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_0_data_prbs_gen.v | 4,725 | module MODULE1 #
(
parameter VAR4 = 100,
parameter VAR14 = "VAR9",
parameter VAR2 = 32, parameter VAR10 = 32
)
(
input VAR12,
input VAR1,
input VAR7,
input VAR6, input [VAR2 - 1:0] VAR3,
output [VAR2 - 1:0] VAR11 );
reg [VAR2 - 1 :0] VAR8;
reg [VAR2 :1] VAR13;
integer VAR5;
always @ (posedge VAR12)
begin
if (VAR6 && VA... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/controller/col_mach.v | 18,166 | module MODULE1 #
(
parameter VAR14 = 100,
parameter VAR38 = 3,
parameter VAR92 = "8",
parameter VAR12 = 12,
parameter VAR21 = 4,
parameter VAR43 = 8,
parameter VAR32 = 1,
parameter VAR13 = 0,
parameter VAR22 = 8,
parameter VAR89 = "VAR50",
parameter VAR49 = "VAR53",
parameter VAR59 = "VAR53",
parameter VAR106 = 31,
par... | lgpl-3.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.