repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
wsoltys/AtomFpga | mist/sd_card.v | 13,986 | module MODULE1 (
output [31:0] VAR31,
output reg VAR33,
output reg VAR29,
input VAR1,
output VAR4,
output VAR61,
input [7:0] VAR21,
input VAR56,
output [7:0] VAR26,
input VAR38,
input VAR48,
input VAR12,
input VAR17,
input VAR6,
output reg VAR54
);
reg VAR30 = 1'b0; always @(posedge VAR30 or posedge VAR1) begin
if(VAR1... | apache-2.0 |
LSaldyt/qnp | output/vs/opt_var14_multi.v | 18,150 | module MODULE1(VAR14, VAR13, VAR2, VAR9, VAR11, VAR1, VAR3, VAR10, VAR7, VAR12, VAR15, VAR6, VAR4, VAR5, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 02... | mit |
zhangry868/MultiCycleCPU | Multiple_Cycles_CPU/ALU.v | 2,399 | module MODULE5(VAR7,VAR17);
input [3:0] VAR7;
output [2:0] VAR17;
assign VAR17[2] = ((!VAR7[3])&(!VAR7[1]))|(!VAR7[3]& VAR7[2]& VAR7[0])|(VAR7[3]&VAR7[1]);
assign VAR17[1] = (!VAR7[3]&!VAR7[2]&!VAR7[1])|(VAR7[3]&!VAR7[2]&!VAR7[0])|(VAR7[2]&VAR7[1]&!VAR7[0])|(VAR7[3]&VAR7[1]);
assign VAR17[0] = (!VAR7[2]&!VAR7[1])|(!VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbp/sky130_fd_sc_ms__dfbbp.blackbox.v | 1,435 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR9 ,
VAR6 ,
VAR5 ,
VAR8
);
output VAR1 ;
output VAR2 ;
input VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR8;
supply1 VAR10;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/GC_fifo.v | 13,416 | module MODULE1(
clk,
rst,
din,
VAR163,
VAR128,
dout,
VAR107,
VAR120,
VAR289
);
input clk;
input rst;
input [31 : 0] din;
input VAR163;
input VAR128;
output [31 : 0] dout;
output VAR107;
output VAR120;
output [12 : 0] VAR289;
VAR226 #(
.VAR18(0),
.VAR237(0),
.VAR360(0),
.VAR270(0),
.VAR138(0),
.VAR274(0),
.VAR264(0),
.V... | gpl-2.0 |
aj-michael/Digital-Systems | MultiplicationUnit/Controller.v | 2,355 | module MODULE1(VAR6, VAR15, VAR13, VAR2, VAR16, VAR18);
input VAR6, VAR15, VAR13;
output reg [2:0] VAR16;
output reg [2:0] VAR2;
output reg VAR18;
parameter VAR7 = 4'b0000;
parameter VAR20 = 4'b0001;
parameter VAR11 = 4'b0010;
parameter VAR12 = 4'b0011;
parameter VAR14 = 4'b0100;
parameter VAR8 = 4'b0101;
parameter VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai.blackbox.v | 1,364 | module MODULE1 (
VAR4 ,
VAR3,
VAR8,
VAR9,
VAR7
);
output VAR4 ;
input VAR3;
input VAR8;
input VAR9;
input VAR7;
supply1 VAR6;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_28.v | 19,500 | module MODULE3 (
clk,
reset,
VAR134,
VAR27,
VAR166,
VAR78,
VAR158
);
parameter VAR61 = 18;
parameter VAR4 = 28;
parameter VAR56 = 14;
localparam VAR112 = 29;
input clk;
input reset;
input VAR134;
input VAR27;
input [VAR61-1:0] VAR166; output VAR78;
output [VAR61-1:0] VAR158;
localparam VAR1 = 18; localparam VAR142 = 36... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31oi/sky130_fd_sc_hd__a31oi.functional.pp.v | 2,038 | module MODULE1 (
VAR16 ,
VAR4 ,
VAR8 ,
VAR7 ,
VAR11 ,
VAR5,
VAR3,
VAR15 ,
VAR13
);
output VAR16 ;
input VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR11 ;
input VAR5;
input VAR3;
input VAR15 ;
input VAR13 ;
wire VAR6 ;
wire VAR12 ;
wire VAR9;
and VAR2 (VAR6 , VAR7, VAR4, VAR8 );
nor VAR14 (VAR12 , VAR11, VAR6 );
VAR17 VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o31ai/sky130_fd_sc_hdll__o31ai.blackbox.v | 1,355 | module MODULE1 (
VAR9 ,
VAR7,
VAR4,
VAR6,
VAR2
);
output VAR9 ;
input VAR7;
input VAR4;
input VAR6;
input VAR2;
supply1 VAR3;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/src_axi_mm.v | 6,489 | module MODULE1 #(
parameter VAR29 = 3,
parameter VAR52 = 64,
parameter VAR32 = 32,
parameter VAR5 = 3,
parameter VAR35 = 4,
parameter VAR36 = 8)(
input VAR2,
input VAR23,
input VAR45,
output VAR3,
input [VAR32-1:VAR5] VAR60,
input [VAR35-1:0] VAR7,
input enable,
output reg VAR28 = 1'b0,
output VAR54,
input VAR44,
outpu... | mit |
set-soft/collection-kefir_i | blocks/Varios/Comunicación/Templates/ft245_sync_if_m.v | 1,055 | module MODULE1
parameter VAR15=0, parameter VAR9=0, parameter VAR7=0, parameter VAR14=0) (
inout [7:0] VAR5,
input VAR8,
input VAR2,
output VAR18,
output VAR1,
input VAR11,
output VAR13,
output VAR19,
input VAR3,
input [7:0] VAR10,
input VAR6,
output VAR17,
output [7:0] VAR4,
output VAR12,
input VAR16);
endmodule | gpl-2.0 |
mbuesch/pyprofibus | phy_fpga/uart_mod.v | 17,446 | module MODULE1 (
input clk,
input VAR7,
input [23:0] VAR6,
output reg VAR8,
output reg VAR4,
output reg VAR5,
);
localparam VAR1 = 4;
reg [23:0] VAR9;
wire [23:0] VAR3;
wire [23:0] VAR2;
assign VAR3 = (VAR6 >= VAR1) ? VAR6 : VAR1;
assign VAR2 = VAR3 >> 1; | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/yf32/pc_next.v | 4,064 | module MODULE1 (clk, reset, VAR6, VAR2, VAR10,
VAR9, VAR3, VAR7, VAR5);
input clk;
input reset;
input [31:2] VAR6;
input VAR2;
input VAR10;
input [25:0] VAR9;
input [ 1:0] VAR3;
output [31:0] VAR7;
output [31:0] VAR5;
reg[31:2] MODULE1;
reg[31:2] VAR4;
wire [31:2] VAR1 = VAR4 + 1;
wire [31:0] VAR7 = {VAR4, 2'b00} ;
wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o_4.v | 2,448 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR2 ,
VAR12 ,
VAR3 ,
VAR5 ,
VAR8,
VAR11,
VAR10 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR12 ;
input VAR3 ;
input VAR5 ;
input VAR8;
input VAR11;
input VAR10 ;
input VAR4 ;
VAR1 VAR9 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(V... | apache-2.0 |
asicguy/gplgpu | hdl/ramdac_sp/crcx.v | 4,342 | module MODULE1
(
input VAR2,
input VAR6,
input VAR7,
input VAR8,
input [7:0] VAR3,
input [7:0] VAR11,
input [7:0] VAR10,
output [7:0] VAR9,
output [7:0] VAR12,
output [7:0] VAR1
);
reg[23:0] VAR4;
wire[23:0] VAR5 ;
assign VAR5[23:16] = VAR3[7:0] ;
assign VAR5[15: 8] = VAR11[7:0] ;
assign VAR5[ 7: 0] = VAR10[7:0] ;
alwa... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_ResetCatchAndSync.v | 2,261 | module MODULE1(
input VAR5,
input reset,
input VAR14,
output VAR17
);
wire VAR15;
wire VAR10;
wire [2:0] VAR4;
wire [2:0] VAR12;
wire VAR16;
wire [1:0] VAR13;
wire [2:0] VAR8;
wire VAR2;
wire VAR3;
VAR1 VAR7 (
.VAR5(VAR15),
.reset(VAR10),
.VAR9(VAR4),
.VAR6(VAR12),
.VAR11(VAR16)
);
assign VAR17 = VAR14 ? reset : VAR3;
... | apache-2.0 |
phase4ground/DVB-receiver | modem/hdl/library/lookup_table_behavioural/lookup_table_behavioural.v | 3,464 | module MODULE1 #
(
parameter integer VAR21 = 32,
parameter integer VAR7 = 8
)
(
input wire VAR4,
input wire VAR8,
output wire VAR16,
input wire [VAR7-1:0] VAR23,
input wire VAR19,
input wire VAR11,
output wire VAR22,
output wire VAR17,
input wire VAR10,
output reg [VAR21-1:0] VAR18,
output reg VAR5,
output reg VAR13,
i... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/wb_zbt/wb_zbt.v | 4,340 | module MODULE1(
input clk,
input rst,
input [31:0] VAR37,
input [31:0] VAR14,
output [31:0] VAR20,
input [ 3:0] VAR10,
input VAR6,
input VAR30,
output VAR21,
input VAR9,
input [31:0] VAR5,
input [31:0] VAR28,
output [31:0] VAR33,
input [ 3:0] VAR29,
input VAR7,
input VAR41,
output VAR27,
input VAR24,
output VAR4,
outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a_4.v | 2,248 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR10 ,
VAR8 ,
VAR1,
VAR7,
VAR5 ,
VAR9
);
output VAR4 ;
input VAR6 ;
input VAR10 ;
input VAR8 ;
input VAR1;
input VAR7;
input VAR5 ;
input VAR9 ;
VAR3 VAR2 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd.blackbox.v | 1,219 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_2.behavioral.v | 1,098 | module MODULE1( VAR1, VAR3 );
input VAR1;
output VAR3;
VAR2 VAR5(.VAR1(VAR1),.VAR3(VAR3));
VAR2 VAR4(.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/vcr_comb_alloc_mac.v | 7,251 | module MODULE1
(clk, reset, VAR1, VAR27, VAR10, VAR9,
VAR30, VAR22, VAR7, VAR17,
VAR13, VAR28, VAR11, VAR14);
parameter VAR19 = 2;
parameter VAR15 = 2;
localparam VAR25 = VAR19 * VAR15;
parameter VAR29 = 1;
localparam VAR5 = VAR25 * VAR29;
parameter VAR16 = 5;
localparam VAR3 = VAR23(VAR16);
parameter VAR24 = VAR21;
lo... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb.behavioral.pp.v | 1,998 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR5 ,
VAR14 ,
VAR4 ,
VAR6,
VAR1,
VAR12 ,
VAR8
);
output VAR11 ;
input VAR2 ;
input VAR5 ;
input VAR14 ;
input VAR4 ;
input VAR6;
input VAR1;
input VAR12 ;
input VAR8 ;
wire VAR15 ;
wire VAR17 ;
wire VAR9;
nor VAR10 (VAR15 , VAR2, VAR5 );
and VAR7 (VAR17 , VAR15, VAR14, VAR4 );
VAR13 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b_4.v | 2,254 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR3,
VAR5,
VAR10 ,
VAR6
);
output VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR3;
input VAR5;
input VAR10 ;
input VAR6 ;
VAR2 VAR8 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
qiuzou/nysa_saya | rtl/link/sata_link_layer.v | 11,199 | module MODULE1 (
input rst, input clk,
output VAR20,
input VAR16,
output VAR70,
input VAR18,
input VAR38,
output VAR56,
input VAR88,
output [31:0] VAR44,
output VAR83,
input [31:0] VAR69,
input [3:0] VAR86,
input VAR43,
output VAR78,
input [31:0] VAR63,
input [31:0] VAR52,
input VAR22,
output VAR35,
input VAR9,
output ... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/phy_init.v | 136,321 | module MODULE1 #
(
parameter VAR290 = 100,
parameter VAR102 = 4, parameter VAR103 = 3000, parameter VAR243 = 64, parameter VAR37 = 2,
parameter VAR42 = 10,
parameter VAR56 = 1, parameter VAR170 = 64,
parameter VAR43 = 8,
parameter VAR55 = 3, parameter VAR100 = 14,
parameter VAR247 = 1,
parameter VAR146 = 1, parameter V... | lgpl-3.0 |
GSejas/Aproximate-Arithmetic-Operators | src_lib/multlib/KOA_2c_approx.v | 6,257 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR44,
input wire [VAR39-1:0] VAR40,
input wire [VAR39-1:0] VAR11,
output wire [2*VAR39-1:0] VAR26
);
wire [1:0] VAR28;
wire [3:0] VAR7;
assign VAR28 = 2'b00;
assign VAR7 = 4'b0000;
wire [VAR39/2-1:0] VAR18;
wire [VAR39/2:0] VAR33;
wire [VAR39/2-3:0] VAR32;
wi... | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_prc_core.v | 11,116 | module MODULE1
(
VAR23,
reset,
VAR34,
VAR39,
read,
VAR5,
VAR8,
VAR36,
VAR25,
VAR32,
VAR10,
VAR4,
VAR14,
VAR2,
VAR11,
enable,
VAR15,
VAR6,
VAR31,
VAR12,
VAR26,
VAR21,
VAR20
);
parameter VAR13 = 8;
parameter VAR42 = 3;
parameter VAR43 = 7;
parameter VAR18 = 32;
localparam VAR29 = 32; localparam VAR30 = 3;
input VAR23;
in... | mit |
walkthetalk/fsref | ip/fsa/src/include/fsa_detect_edge.v | 12,488 | module MODULE1 #(
parameter integer VAR103 = 8,
parameter integer VAR100 = 12,
parameter integer VAR46 = 12,
parameter integer VAR67 = 4,
parameter integer VAR68 = 12 )(
input clk,
input VAR93,
input wire VAR79 ,
input wire VAR56 ,
input wire VAR57 ,
input wire VAR66 ,
input wire VAR99 ,
input wire VAR62 ,
input wire V... | gpl-3.0 |
mda-ut/AquaTux | fpga/fpga_hw/top_level/RS232/Altera_UP_RS232_In_Deserializer.v | 4,788 | module MODULE1 (
clk,
reset,
VAR9,
VAR31,
VAR16,
VAR4
);
parameter VAR17 = 9;
parameter VAR22 = 9'd1;
parameter VAR18 = 9'd433;
parameter VAR15 = 9'd216;
parameter VAR14 = 11;
parameter VAR12 = 9;
input clk;
input reset;
input VAR9;
input VAR31;
output reg [7:0] VAR16;
output [(VAR12 - 1):0] VAR4;
wire VAR1;
wire VAR8;... | gpl-2.0 |
kyflores/ice-mc | rtl/spi_comm_top.v | 1,174 | module MODULE1(VAR12, reset, VAR21, VAR29, VAR30, VAR26, VAR7,
VAR4, VAR2, VAR11, VAR8, VAR16, VAR25, VAR5, VAR20);
input VAR12;
input reset;
output VAR21;
output VAR4, VAR2, VAR11, VAR8, VAR16, VAR25, VAR5, VAR20;
input VAR29;
output VAR30;
output VAR26;
output VAR7;
wire VAR24, VAR28, VAR15;
wire[7:0] VAR18, VAR1;
VA... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v | 2,859 | module MODULE1
, parameter VAR12(VAR14)
, parameter VAR16=0
, parameter VAR36=VAR28(VAR14)
)
(input VAR3
, input VAR33
, input [VAR5(VAR15, 1):0] VAR26
, input [VAR36-1:0] VAR25
, input VAR21
, input [VAR5(VAR15, 1):0] VAR11
, input VAR8
, output logic [VAR5(VAR15, 1):0] VAR29
);
wire VAR2 = VAR33;
if (VAR15 == 0)
begi... | bsd-3-clause |
parallella/oh | common/dv/dut_clockdiv.v | 1,182 | module MODULE1(
VAR13, VAR4, VAR1, VAR6, VAR17,
VAR10, VAR11, VAR7, VAR9, VAR3, VAR14, VAR8, VAR12
);
parameter VAR2 = 1;
parameter VAR16 = 104;
input VAR10;
input VAR11;
input VAR7;
input [VAR2*VAR2-1:0] VAR9;
input VAR3;
output VAR13;
output VAR4;
input [VAR2-1:0] VAR14;
input [VAR2*VAR16-1:0] VAR8;
output [VAR2-1:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtp/sky130_fd_sc_ls__sdfrtp.pp.blackbox.v | 1,474 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR6,
VAR3 ,
VAR9 ,
VAR2 ,
VAR5
);
output VAR8 ;
input VAR10 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR6;
input VAR3 ;
input VAR9 ;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.functional.v | 1,557 | module MODULE1( VAR1, VAR15, VAR16, VAR17 );
input VAR15, VAR1, VAR16;
output VAR17;
wire VAR3;
and VAR11( VAR3, VAR15, VAR1, VAR16 );
wire VAR12;
not VAR14( VAR12, VAR1 );
wire VAR7;
not VAR10( VAR7, VAR16 );
wire VAR13;
and VAR9( VAR13, VAR12, VAR7, VAR15 );
wire VAR19;
not VAR18( VAR19, VAR15 );
wire VAR6;
and VAR5(... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/v7_ethernet_top.v | 4,668 | module MODULE1
(
input VAR7,
input VAR58,
output VAR48,
input VAR52, input VAR50, output VAR55, output VAR1, input VAR37, input VAR24,
output VAR44,
output VAR35,
input VAR62,
output VAR61,
output VAR18,
output VAR40,
input VAR14, input VAR10, input [31:0] VAR32, input [31:0] VAR57, input [31:0] VAR28, input [31:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4b/sky130_fd_sc_hd__nor4b.symbol.v | 1,323 | module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR7 ,
input VAR6,
output VAR4
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o_4.v | 2,448 | module MODULE2 (
VAR11 ,
VAR9 ,
VAR8 ,
VAR4 ,
VAR12 ,
VAR5 ,
VAR1,
VAR7,
VAR10 ,
VAR2
);
output VAR11 ;
input VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR12 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR10 ;
input VAR2 ;
VAR3 VAR6 (
.VAR11(VAR11),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtn/sky130_fd_sc_lp__dlxtn.functional.v | 1,697 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR3 ;
input VAR2;
wire VAR10 ;
wire VAR12 ;
wire VAR8;
wire VAR9 ;
VAR5 VAR1 VAR11 (VAR12 , VAR3, VAR10 );
not VAR6 (VAR10 , VAR2 );
buf VAR4 (VAR7 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn_1.v | 2,150 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR1,
VAR3,
VAR9,
VAR7 ,
VAR4
);
output VAR2 ;
input VAR8 ;
input VAR1;
input VAR3;
input VAR9;
input VAR7 ;
input VAR4 ;
VAR5 VAR6 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR2 ,
VAR8 ,
VAR1
);
output VAR2 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbn/sky130_fd_sc_hd__dlrbn_1.v | 2,480 | module MODULE2 (
VAR11 ,
VAR3 ,
VAR9,
VAR10 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR7 ,
VAR8
);
output VAR11 ;
output VAR3 ;
input VAR9;
input VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR8 ;
VAR5 VAR1 (
.VAR11(VAR11),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7)... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/vgafb/rtl/vgafb.v | 4,963 | module MODULE1 #(
parameter VAR68 = 4'h0,
parameter VAR10 = 26
) (
input VAR19,
input VAR12,
input [13:0] VAR5,
input VAR13,
input [31:0] VAR7,
output [31:0] VAR15,
output [VAR10-1:0] VAR20,
output VAR33,
input VAR66,
input [63:0] VAR14,
output VAR23,
output [VAR10-1:0] VAR8,
input [63:0] VAR41,
input VAR26,
input VAR6... | lgpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_memc_ui_top_std.v | 36,324 | module MODULE1 #
(
parameter VAR245 = 100,
parameter VAR130 = 64,
parameter VAR186 = "VAR227",
parameter VAR260 = "0", parameter VAR6 = 3, parameter VAR149 = 2, parameter VAR135 = "8", parameter VAR99 = "VAR156", parameter VAR175 = "VAR185", parameter VAR268 = 1, parameter VAR67 = 5,
parameter VAR205 = 12, parameter VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25.pp.blackbox.v | 1,343 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR5,
VAR4,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR5;
input VAR4;
input VAR6 ;
input VAR2 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/yacc/ram_module_altera.v | 5,353 | module MODULE1(VAR24,VAR58,VAR1,VAR46,VAR38,VAR47,VAR53,VAR21,VAR12,VAR28,
VAR9,VAR13);
input VAR24,VAR58;
input VAR53;
input [31:0] VAR21;
input VAR28;
input [7:0] VAR9;
input VAR13;VAR5 VAR30
input [14:0] VAR38,VAR47; reg [14:0] VAR61;
input [13:0] VAR38,VAR47; reg [13:0] VAR61;
input [11:0] VAR38,VAR47; reg [11:0] V... | mit |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/clk_108MHz/clk_108MHz_stub.v | 1,182 | module MODULE1(VAR1, MODULE1, VAR2)
;
input VAR1;
output MODULE1;
output VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o.functional.v | 1,443 | module MODULE1 (
VAR7 ,
VAR6,
VAR1,
VAR10,
VAR4
);
output VAR7 ;
input VAR6;
input VAR1;
input VAR10;
input VAR4;
wire VAR3 ;
wire VAR2;
and VAR8 (VAR3 , VAR6, VAR1 );
or VAR5 (VAR2, VAR3, VAR4, VAR10);
buf VAR9 (VAR7 , VAR2 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_12.behavioral.pp.v | 1,187 | module MODULE1( VAR4, VAR3, VAR7, VAR6 );
input VAR4;
inout VAR7, VAR6;
output VAR3;
VAR1 VAR5(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR6(VAR6));
VAR1 VAR2(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR6(VAR6)); | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/MULT_sumXsq/MULT_sumXsq.v | 4,400 | module MODULE1 (
VAR4,
VAR14,
VAR1);
input [25:0] VAR4;
input [23:0] VAR14;
output [49:0] VAR1;
wire [49:0] VAR11;
wire [49:0] VAR1 = VAR11[49:0];
VAR8 VAR15 (
.VAR4 (VAR4),
.VAR14 (VAR14),
.VAR1 (VAR11),
.VAR10 (1'b0),
.VAR16 (1'b1),
.VAR12 (1'b0),
.sum (1'b0));
VAR15.VAR7 = "VAR19=VAR9,VAR13=9",
VAR15.VAR17 = "VAR18... | gpl-2.0 |
GREO/GNU-Radio | usrp/fpga/models/fifo_1c_2k.v | 1,551 | module MODULE1 ( VAR12, VAR18, VAR19, VAR10, VAR14, VAR4, VAR3,
VAR2, VAR1, VAR7, VAR17, VAR15, VAR6);
parameter VAR16 = 32;
parameter VAR5 = 2048;
input [31:0] VAR12;
input VAR18;
input VAR19;
input VAR10;
input VAR14;
input VAR4;
output [31:0] VAR3;
output VAR2;
output VAR1;
output [10:0] VAR7;
output VAR17;
output V... | gpl-3.0 |
valptek/v586 | core_rtl/realign.v | 6,659 | module MODULE1 (
clk,
VAR24,
VAR21,VAR10,
VAR25,VAR15,
VAR26,VAR1,
VAR18,VAR7,
VAR20,
VAR2,
VAR19,
VAR4,
VAR23,
VAR22,
VAR3,
VAR28
);
input [31:0] VAR23 ,VAR19 ,VAR20;
output [31:0] VAR22,VAR4,VAR2;
input VAR24,clk;
input VAR21,VAR10,VAR26,VAR1;
input [1:0] VAR3;
output [3:0] VAR28;
output VAR15,VAR25,VAR18,VAR7;
reg V... | apache-2.0 |
bbrown1867/ObjectTracking | hw/common/video_input/yuv422_to_yuv444.v | 1,055 | module MODULE1
(
input wire VAR2,
input wire VAR10,
input wire [15:0] VAR6,
input wire VAR12,
output wire [7:0] VAR3,
output wire [7:0] VAR4,
output wire [7:0] VAR9,
output wire VAR7
);
reg VAR1;
reg [7:0] VAR11;
reg [7:0] VAR5;
reg [7:0] VAR13;
reg VAR8;
assign VAR3 = VAR11;
assign VAR4 = VAR5;
assign VAR9 = VAR13;
as... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.behavioral.v | 1,542 | module MODULE1 (
VAR2 ,
VAR3,
VAR7,
VAR9,
VAR6
);
output VAR2 ;
input VAR3;
input VAR7;
input VAR9;
input VAR6;
supply1 VAR12;
supply0 VAR1;
supply1 VAR14 ;
supply0 VAR10 ;
wire VAR8 ;
wire VAR13;
or VAR5 (VAR8 , VAR7, VAR3 );
and VAR11 (VAR13, VAR8, VAR9, VAR6);
buf VAR4 (VAR2 , VAR13 );
endmodule | apache-2.0 |
manu3193/GatoTDD | Gato_Top.v | 3,452 | module MODULE1(
input clk , VAR88, input VAR90, input VAR94, input VAR92,
input VAR56,
input VAR24,
input VAR8,
output VAR20,VAR22, output [2:0] VAR19, output [3:0] VAR34
);
wire VAR41;
wire [3:0] VAR34;
wire [1:0] VAR26;
wire [1:0] VAR78;
wire [1:0] VAR37;
wire [2:0] state;
wire VAR79;
wire VAR53;
wire VAR97;
wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.v | 2,128 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR9 ,
VAR5,
VAR1,
VAR4 ,
VAR3
);
output VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR5;
input VAR1;
input VAR4 ;
input VAR3 ;
VAR7 VAR8 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6 ,
VAR2,
VAR9
);
output VAR6 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_1.v | 2,345 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR10 ,
VAR11 ,
VAR8 ,
VAR5,
VAR9,
VAR3 ,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR10 ;
input VAR11 ;
input VAR8 ;
input VAR5;
input VAR9;
input VAR3 ;
input VAR2 ;
VAR7 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.... | apache-2.0 |
google/bbcpu | cpu.v | 8,687 | module MODULE1(
input clk,
output VAR16);
localparam VAR1 = 4;
localparam VAR73 = 8;
localparam VAR40 = VAR73 - VAR1;
localparam VAR55 = 4'b0000; localparam VAR39 = 4'b0001; localparam VAR79 = 4'b0010; localparam VAR30 = 4'b0011; localparam VAR52 = 4'b0100; localparam VAR50 = 4'b0101; localparam VAR42 = 4'b0110; localp... | apache-2.0 |
davidkoltak/tawas-core | ip/debug_ip/rtl/spdr_fifo.v | 2,245 | module MODULE1
(
input VAR2,
input VAR10,
input VAR3,
input [7:0] din,
input VAR14,
output VAR5,
output [7:0] dout,
input VAR8,
output VAR7
);
reg [1:0] VAR15;
reg [3:0] VAR4;
reg [3:0] VAR1;
reg [3:0] VAR9;
reg [1:0] VAR18;
reg [3:0] VAR6;
reg [3:0] VAR17;
reg [3:0] VAR19;
always @ (posedge VAR10)
VAR15 <= VAR18;
alwa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15.behavioral.pp.v | 1,866 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR1,
VAR11,
VAR7 ,
VAR6
);
output VAR8 ;
input VAR2 ;
input VAR1;
input VAR11;
input VAR7 ;
input VAR6 ;
wire VAR5 ;
wire VAR10;
buf VAR3 (VAR5 , VAR2 );
VAR12 VAR4 (VAR10, VAR5, VAR1, VAR11);
buf VAR9 (VAR8 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3b/sky130_fd_sc_ms__nand3b.pp.symbol.v | 1,313 | module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR7 ,
output VAR4 ,
input VAR8 ,
input VAR3,
input VAR5,
input VAR6
);
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_lfsr36.v | 2,025 | module MODULE1(
clk,
VAR1,
VAR2,
word
);
input clk;
input VAR1;
input VAR2;
output reg [35:0] word;
always @(posedge clk or negedge VAR1) begin
if(~VAR1) begin
word <= 36'hF0F0AA55;
end
else if(VAR2) begin
word[35] <= word[0];
word[34] <= word[35];
word[33] <= word[34];
word[32] <= word[33];
word[31] <= word[32];
word[... | gpl-3.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0_stub.v | 1,296 | module MODULE1(VAR2, VAR1, VAR3, VAR5, VAR4)
;
output VAR2;
output VAR1;
output VAR3;
input VAR5;
input VAR4;
endmodule | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_084.v | 1,519 | module MODULE2 (
VAR5,
VAR12
);
input [31:0] VAR5;
output [31:0]
VAR12;
wire [31:0]
VAR11,
VAR7,
VAR13,
VAR8,
VAR4,
VAR2,
VAR10,
VAR6,
VAR1;
assign VAR11 = VAR5;
assign VAR8 = VAR11 << 4;
assign VAR10 = VAR2 - VAR4;
assign VAR2 = VAR13 << 8;
assign VAR1 = VAR10 + VAR6;
assign VAR4 = VAR13 - VAR8;
assign VAR6 = VAR4 << ... | mit |
jmahler/mips-cpu | im.v | 1,164 | module MODULE1(
input wire clk,
input wire [31:0] addr,
output wire [31:0] VAR1);
parameter VAR4 = 128; parameter VAR6 = "VAR2.VAR5";
reg [31:0] VAR3 [0:127]; | gpl-3.0 |
chiragsakhuja/gpu | fb_block.v | 7,041 | module MODULE1 (
address,
VAR44,
VAR31,
VAR37,
VAR15);
input [7:0] address;
input VAR44;
input [7:0] VAR31;
input VAR37;
output [7:0] VAR15;
tri1 VAR44;
wire [7:0] VAR25;
wire [7:0] VAR15 = VAR25[7:0];
VAR7 VAR20 (
.VAR18 (address),
.VAR24 (VAR44),
.VAR6 (VAR31),
.VAR12 (VAR37),
.VAR52 (VAR25),
.VAR29 (1'b0),
.VAR5 (1'... | gpl-2.0 |
efabless/openlane | designs/aes_cipher/src/aes_cipher.v | 10,245 | module MODULE1(clk, rst, VAR111, VAR3, VAR77, VAR86, VAR27, VAR41, VAR94, VAR99 );
input clk, rst;
input VAR111, VAR41, VAR94;
output VAR3, VAR99;
input [127:0] VAR77;
input [127:0] VAR86;
output [127:0] VAR27;
wire [31:0] VAR51, VAR85, VAR5, VAR89;
reg [127:0] VAR127;
reg [127:0] VAR27;
reg [7:0] VAR73, VAR39, VAR82, ... | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/keyboard.v | 17,139 | module MODULE1(
input wire VAR16, input wire VAR28, input wire VAR4,
input wire rst,
output reg VAR7,
output reg VAR26,
output reg VAR44,
output reg VAR25,
output reg VAR35,
output reg VAR10,
output reg VAR31,
output reg VAR23,
output reg VAR12,
output reg VAR34,
output reg VAR33
);
localparam reg [7:0] VAR40 = 8'h11;
... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/KOA_1c.v | 5,688 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR6,
input wire [VAR3-1:0] VAR19,
input wire [VAR3-1:0] VAR11,
output wire [2*VAR3-1:0] VAR25
);
wire [1:0] VAR30;
wire [3:0] VAR7;
assign VAR30 = 2'b00;
assign VAR7 = 4'b0000;
wire [VAR3/2-1:0] VAR28;
wire [VAR3/2:0] VAR34;
wire [VAR3/2-3:0] VAR31;
wire [VAR... | gpl-3.0 |
hakehuang/pycpld | ips/ip/spi_slave_cpha0/spi_slave_cpha0.v | 2,925 | module MODULE1(
clk,VAR2,VAR9,VAR12,VAR11,VAR8
);
input clk;
input VAR8;
input VAR2,VAR9,VAR11;
output VAR12;
reg VAR10;
reg[2:0] VAR17;
reg[2:0] VAR16;
reg[1:0] VAR4;
reg[2:0] VAR1;
reg[7:0] VAR3;
reg VAR15; reg [7:0] VAR14;
wire VAR7;
wire VAR6;
wire VAR13;
wire VAR5;
always @(posedge clk or negedge VAR8)begin
if(!VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2.blackbox.v | 1,241 | module MODULE1 (
VAR2,
VAR4,
VAR6
);
output VAR2;
input VAR4;
input VAR6;
supply1 VAR5;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Transform_dq_to_ABC.v | 3,451 | module MODULE1
(
VAR8,
VAR19,
VAR23,
VAR6,
VAR1,
VAR3,
VAR12
);
input signed [17:0] VAR8; input signed [17:0] VAR19; input signed [17:0] VAR23; input signed [17:0] VAR6; output signed [17:0] VAR1; output signed [17:0] VAR3; output signed [17:0] VAR12;
wire signed [17:0] VAR7; wire signed [17:0] VAR4; wire signed [17:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probec_p/sky130_fd_sc_hd__probec_p.symbol.v | 1,282 | module MODULE1 (
input VAR1,
output VAR3
);
supply0 VAR4;
supply0 VAR2 ;
supply1 VAR6 ;
supply1 VAR5;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4_2.v | 2,275 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR6 ,
VAR4,
VAR3,
VAR2 ,
VAR8
);
output VAR1 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR8 ;
VAR10 VAR11 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(V... | apache-2.0 |
1995parham/AlteraDE2-RS232 | src/async-trasmitter.v | 1,820 | module MODULE1(
input clk,
input VAR2,
input [7:0] VAR13,
output VAR17,
output VAR16
);
parameter VAR15 = 50000000; parameter VAR6 = 9600;
generate
if(VAR15<VAR6*8 && (VAR15 % VAR6!=0)) VAR1 VAR4("VAR10 VAR9 with VAR19 VAR6 VAR8");
endgenerate
wire VAR18 = 1'b1;
wire VAR18;
VAR3 #(VAR15, VAR6) VAR11(.clk(clk), .enable(... | gpl-2.0 |
LordRafa/Sobel-FPGA | SISSources/V/SIS.v | 6,964 | module MODULE1 (
input clk,
input rst,
output wire[VAR52-1:0] VAR71,
input VAR39,
output wire[VAR59-1:0] VAR9,
output wire VAR10,
output wire[VAR18-1:0] VAR51,
output wire[VAR54-1:0] VAR83,
output wire[VAR52-1:0] VAR74,
input VAR88,
input VAR61,
output wire[VAR59-1:0] VAR87,
output wire VAR55,
input wire[VAR18-1:0] VAR... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp1/toplevel/mrfm/mrfm.v | 6,841 | module MODULE1
(output VAR40,
input VAR132,
input VAR65,
input VAR8,
inout VAR104,
input VAR1,
input VAR125,
output VAR98,
output VAR28,
input wire [11:0] VAR6,
input wire [11:0] VAR64,
input wire [11:0] VAR24,
input wire [11:0] VAR15,
output wire [13:0] VAR29,
output wire [13:0] VAR53,
output wire VAR113,
output wire ... | gpl-2.0 |
chriz2600/DreamcastHDMI | Core/source/char_rom/char_rom.v | 24,748 | module MODULE1 (
input [11:0] address,
input VAR2,
output [7:0] VAR3
);
reg[7:0] VAR4;
reg[7:0] VAR1;
assign VAR3 = VAR1;
always @(posedge VAR2) begin
case (address)
endcase
VAR1 <= VAR4;
end
endmodule | mit |
gtaylormb/fpga_nes | hw/zybo_vivado/zybo_vivado.runs/synth_1/nes_top_X99.v | 3,823 | module MODULE1(VAR1,VAR2);
input[5:0] VAR1;
output reg[7:0] VAR2;
always @(VAR1)
begin
case(VAR1)
6'b000000: VAR2 = 8'b01101101;
6'b000001: VAR2 = 8'b00100010;
6'b000010: VAR2 = 8'b00000010;
6'b000011: VAR2 = 8'b01000010;
6'b000100: VAR2 = 8'b10000001;
6'b000101: VAR2 = 8'b10100000;
6'b000110: VAR2 = 8'b10100000;
6'b00... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o.pp.blackbox.v | 1,397 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR1 ,
VAR6 ,
VAR5 ,
VAR8,
VAR2,
VAR4 ,
VAR9
);
output VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR8;
input VAR2;
input VAR4 ;
input VAR9 ;
endmodule | apache-2.0 |
subailong/miaow | src/verilog/rtl/lsu/PS_flops_issue_lsu.v | 2,589 | module MODULE1 (
VAR7,
VAR37,
VAR36,
VAR5,
VAR23,
VAR21,
VAR11,
VAR38,
VAR33,
VAR26,
VAR17,
VAR4,
VAR31,
VAR32,
VAR18,
VAR19,
VAR10,
VAR34,
VAR40,
VAR1,
VAR24,
VAR35,
VAR15,
VAR9,
clk,
rst
);
input VAR7;
input [5:0] VAR37;
input [15:0] VAR36;
input [11:0] VAR5;
input [11:0] VAR23;
input [11:0] VAR21;
input [11:0] VAR11... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/common/rtl/bw_clk_cl_ctu_2xcmp.v | 1,937 | module MODULE1(VAR2 ,VAR1 );
output VAR2 ;
input VAR1 ;
assign VAR2 = VAR1;
endmodule | gpl-2.0 |
adbrant/zuma-fpga | verilog/platforms/altera/init_config.v | 6,505 | module MODULE1 (
address,
VAR27,
VAR38);
input [12:0] address;
input VAR27;
output [31:0] VAR38;
tri1 VAR27;
wire [31:0] VAR16;
wire [31:0] VAR38 = VAR16[31:0];
VAR3 VAR32 (
.VAR43 (address),
.VAR37 (VAR27),
.VAR13 (VAR16),
.VAR39 (1'b0),
.VAR41 (1'b0),
.VAR53 (1'b1),
.VAR7 (1'b0),
.VAR24 (1'b0),
.VAR34 (1'b1),
.VAR9 (... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21boi/sky130_fd_sc_ls__a21boi.pp.symbol.v | 1,394 | module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR8,
output VAR1 ,
input VAR6 ,
input VAR5,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
chriz2600/DreamcastHDMI | Core/source/configuration.v | 1,041 | module MODULE1(
input VAR6,
input VAR10 VAR5,
inout 480pactiven,
input VAR9,
input VAR8,
output reg VAR4,
output reg [3:0] VAR12,
output reg VAR3
);
reg VAR1 = 1'b0;
reg VAR13 = 1'b0;
reg 480pactivenreg = 1'VAR7;
assign 480pactiven = 480pactivenreg;
always @(posedge VAR6) begin
if (VAR1 != VAR13) begin
VAR3 <= 1'b1;
en... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf_1.v | 1,993 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR4,
VAR6,
VAR5 ,
VAR3
);
output VAR7 ;
input VAR2 ;
input VAR4;
input VAR6;
input VAR5 ;
input VAR3 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR7,
VAR2
);
output VAR7;
input VAR2;
supply1 VAR4;
supply0 VAR6;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2/sky130_fd_sc_ms__mux2.behavioral.v | 1,604 | module MODULE1 (
VAR11 ,
VAR12,
VAR9,
VAR6
);
output VAR11 ;
input VAR12;
input VAR9;
input VAR6 ;
supply1 VAR10;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR7 ;
wire VAR4;
VAR8 VAR1 (VAR4, VAR12, VAR9, VAR6 );
buf VAR3 (VAR11 , VAR4);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/conb/sky130_fd_sc_ls__conb_1.v | 2,042 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR4,
VAR8,
VAR7 ,
VAR6
);
output VAR3 ;
output VAR5 ;
input VAR4;
input VAR8;
input VAR7 ;
input VAR6 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR3,
VAR5
);
output VAR3;
output VAR5;
supply1 VAR4;
supply0 VAR... | apache-2.0 |
secworks/sha512 | src/rtl/sha512_core.v | 17,408 | module MODULE1(
input wire clk,
input wire VAR28,
input wire VAR93,
input wire VAR99,
input wire [1 : 0] VAR48,
input wire VAR19,
input wire [31 : 0] VAR109,
input wire [1023 : 0] VAR12,
output wire ready,
output wire [511 : 0] VAR23,
output wire VAR1
);
localparam VAR62 = 79;
localparam VAR41 = 2'h0;
localparam VAR105... | bsd-2-clause |
SiLab-Bonn/basil | basil/firmware/modules/utils/bus_to_ip.v | 1,114 | module MODULE1
parameter VAR8 = 0,
parameter VAR6 = 0,
parameter VAR5 = 16,
parameter VAR11 = 8
)
(
input wire VAR10,
input wire VAR1,
input wire [VAR5-1:0] VAR14,
inout wire [VAR11-1:0] VAR9,
output wire VAR15,
output wire VAR2,
output wire [VAR5-1:0] VAR3,
output wire [VAR11-1:0] VAR12,
input wire [VAR11-1:0] VAR4
);... | bsd-3-clause |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T24-uart-tx/scicad2.v | 4,723 | module MODULE1 (input wire clk, output wire VAR19 );
parameter VAR5 = VAR10;
parameter VAR15 = VAR14;
reg VAR8 = 0;
wire ready;
reg [7:0] VAR1;
reg [7:0] VAR12;
reg VAR26;
wire VAR13;
reg VAR11; reg VAR18;
always @(posedge clk)
VAR8 <= 1;
VAR4 #(.VAR5(VAR5))
VAR6 (
.clk(clk),
.VAR8(VAR8),
.VAR1(VAR12),
.VAR18(VAR18),
.... | gpl-2.0 |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/vlan_adder.v | 7,255 | module MODULE1
parameter VAR1 = VAR9/8
)
( input [VAR9-1:0] VAR31,
input [VAR1-1:0] VAR16,
input VAR37,
output VAR14,
output reg [VAR9-1:0] VAR24,
output reg [VAR1-1:0] VAR21,
output reg VAR12,
input VAR30,
input reset,
input clk
);
localparam VAR44 = 5;
localparam VAR13 = 0,
VAR4 = 1,
VAR18 = 2,
VAR29 = 3,
VAR40 = 4;
... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.v | 2,814 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR12 ,
VAR4 ,
VAR3 ,
VAR6,
VAR1,
VAR8 ,
VAR10 ,
VAR2 ,
VAR13 ,
VAR14
);
output VAR9 ;
input VAR7 ;
input VAR12 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR1;
input VAR8 ;
input VAR10 ;
input VAR2 ;
input VAR13 ;
input VAR14 ;
VAR5 VAR11 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR12(VAR12),
.VA... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_hcmd_table_prp.v | 3,777 | module MODULE1 # (
parameter VAR26 = 45,
parameter VAR24 = 8
)
(
input clk,
input VAR14,
input [VAR24-1:0] VAR33,
input [VAR26-1:0] VAR12,
input [VAR24-1:0] VAR34,
output [VAR26-1:0] VAR17
);
localparam VAR32 = "7SERIES";
localparam VAR1 = "36Kb";
localparam VAR6 = 0;
localparam VAR21 = VAR26;
localparam VAR23 = VAR26;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbp/sky130_fd_sc_hd__dlrbp.functional.pp.v | 2,072 | module MODULE1 (
VAR2 ,
VAR14 ,
VAR10,
VAR6 ,
VAR8 ,
VAR7 ,
VAR9 ,
VAR12 ,
VAR11
);
output VAR2 ;
output VAR14 ;
input VAR10;
input VAR6 ;
input VAR8 ;
input VAR7 ;
input VAR9 ;
input VAR12 ;
input VAR11 ;
wire VAR17;
wire VAR5;
not VAR1 (VAR17 , VAR10 );
VAR15 VAR16 VAR3 (VAR5 , VAR6, VAR8, VAR17, , VAR7, VAR9);
buf V... | apache-2.0 |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/core/axis_control_if.v | 3,729 | module MODULE1
parameter VAR34 = 32,
parameter VAR9 = 32,
parameter VAR15 = 32,
parameter VAR32 = 32,
parameter VAR37 = 32,
parameter VAR7 = 32,
parameter VAR27 = 1
)
(
input VAR16,
input VAR43,
input VAR1,
input [11:0] VAR40,
input VAR26,
input VAR25,
input VAR29,
output VAR44,
input [VAR32-1 : 0] VAR22,
input [(VAR32... | lgpl-2.1 |
alan4186/16bit-Processor | alu16.v | 1,233 | module MODULE1(
input clk,rst,
input [2:0] VAR2, input [15:0] VAR5,VAR1,
output reg [15:0] out, VAR3
);
always@(*) begin
if(rst == 1'b0) begin
out <= VAR4'd0;
end else begin
case(VAR2)
default: out <= VAR4'd0;
endcase
end
end
always@(posedge clk or negedge rst) begin
if(rst == 1'b0) begin
VAR3 = VAR4'd0;
end else begin... | mit |
zeruniverse/pipelined_CPU | ISE project/control_unit.v | 3,657 | module MODULE1(VAR13,VAR29,VAR25,VAR7,VAR3,VAR11,VAR33,VAR1,VAR21,VAR10,VAR42,VAR45,VAR32,VAR35,VAR17,VAR40,VAR39,VAR15,VAR5,VAR37,VAR38,VAR34,VAR19,VAR36);
input wire [5:0] VAR25,VAR7;
input wire [4:0] VAR3,VAR11,VAR33,VAR10;
input wire VAR1,VAR21,VAR42,VAR45,VAR37;
output wire VAR29,VAR32,VAR35,VAR17,VAR40,VAR15,VAR5... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10-old/HAL.v | 5,184 | module MODULE1(
input VAR5,
input VAR17,
input VAR7,
inout VAR42,
inout VAR9,
inout VAR52,
inout VAR3,
inout VAR40,
inout VAR47,
output VAR20,
output VAR48,
output [23:0] VAR46,
output VAR2,
input VAR37,
output VAR83,
output [14: 0] VAR8,
output [ 2: 0] VAR1,
output VAR77,
output VAR50,
output VAR22,
output VAR57,
outp... | gpl-3.0 |
tommythorn/yari | shared/rtl/yari-core/stage_I.v | 14,757 | module MODULE1(input wire VAR27
,input wire VAR33 ,input wire VAR61 ,input wire [31:0] VAR47
,input wire VAR91
,input wire [31:0] VAR59
,input VAR71
,output reg [29:0] VAR80
,output reg VAR5 = 0
,input [31:0] VAR79
,input VAR8
,output reg VAR39 = 0 ,output wire [31:0] VAR102
,output reg VAR60 = 0
,output wire [31:0] VA... | gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.