repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2.symbol.v | 1,357 | module MODULE1 (
input VAR2,
output VAR6
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/acl_valid_fifo_counter.v | 3,709 | module MODULE1
parameter integer VAR2 = 32, parameter integer VAR17 = 0, parameter integer VAR16 = 0 )
(
input logic VAR4,
input logic VAR1,
input logic VAR5,
output logic VAR9,
input logic VAR3,
output logic VAR12,
output logic VAR6,
output logic VAR8
);
localparam VAR10 = (VAR17 == 0) ?
((VAR2 > 1 ? VAR11(VAR2-1) : 0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.v | 2,411 | module MODULE2 (
VAR1 ,
VAR2,
VAR4,
VAR10 ,
VAR7 ,
VAR9,
VAR11,
VAR3 ,
VAR8
);
output VAR1 ;
input VAR2;
input VAR4;
input VAR10 ;
input VAR7 ;
input VAR9;
input VAR11;
input VAR3 ;
input VAR8 ;
VAR6 VAR5 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR8... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp.blackbox.v | 1,345 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR1;
supply1 VAR7;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v | 10,553 | module MODULE1(
VAR50, VAR38, VAR18,
clk, rst, VAR5, VAR21, VAR46, addr, VAR32, VAR11
);
parameter VAR28 = 11;
parameter VAR29 = 8;
input VAR50;
input [VAR47 - 1:0] VAR18;
output VAR38;
input clk; input rst; input VAR5; input VAR21; input VAR46; input [VAR28-1:0] addr; input [VAR29-1:0] VAR32; output [VAR29-1:0] VAR11;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1p/sky130_fd_sc_lp__inputiso1p.pp.symbol.v | 1,357 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR2,
input VAR4 ,
input VAR6 ,
input VAR1 ,
input VAR7
);
endmodule | apache-2.0 |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/ip/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_0_memc_flow_vcontrol.v | 15,757 | module MODULE1 #
(
parameter VAR39 = 100,
parameter VAR55 = 4,
parameter VAR37 = 32,
parameter VAR25 = 6,
parameter VAR60 = 4,
parameter VAR41 = "VAR62",
parameter VAR72 = "VAR74"
)
(
input VAR69,
input [9:0] VAR8,
input [3:0] VAR40,
input [5:0] VAR57,
input VAR65,
output reg VAR44,
input VAR54,
input [2:0] VAR64,
inpu... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad6676/axi_ad6676_channel.v | 5,392 | module MODULE1 (
VAR19,
VAR28,
VAR22,
VAR29,
VAR26,
VAR53,
VAR14,
VAR15,
VAR48,
VAR25,
VAR56,
VAR24,
VAR32,
VAR43,
VAR47,
VAR38,
VAR2,
VAR10,
VAR7);
parameter VAR55 = 0;
parameter VAR4 = 0;
input VAR19;
input VAR28;
input [31:0] VAR22;
input VAR29;
output [31:0] VAR26;
output VAR53;
output VAR14;
output VAR15;
output V... | gpl-3.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/soc_system/synthesis/submodules/soc_system_hps_0.v | 9,603 | module MODULE1 #(
parameter VAR31 = 0,
parameter VAR10 = 0
) (
output wire VAR2, input wire [28:0] VAR35, input wire [7:0] VAR27, output wire VAR33, output wire [63:0] VAR11, output wire VAR36, input wire VAR1, input wire VAR34, input wire [28:0] VAR25, input wire [7:0] VAR38, output wire VAR28, output wire [63:0] VAR1... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/src_axi_mm.v | 6,120 | module MODULE1 (
input VAR55,
input VAR17,
input VAR20,
output VAR30,
input [31:VAR43] VAR32,
input [3:0] VAR15,
input [2:0] VAR45,
input enable,
output VAR71,
input VAR63,
input VAR40,
output VAR66,
output VAR50,
input VAR2,
output [1:0] VAR16,
input [VAR31-1:0] VAR54,
output [VAR31-1:0] VAR35,
output [VAR31-1:0] VAR3... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_snoop_out_queue.v | 2,450 | module MODULE1 (
valid,
VAR4, VAR3, clk, VAR6
);
input VAR4;
output valid;
input VAR3;
input clk;
input VAR6;
wire [15:0] VAR1;
wire [15:0] counter;
VAR5 #(VAR9) VAR8 (.din(VAR1), .en(VAR2), .VAR7(counter), .VAR6(VAR6), .clk(clk));
assign VAR2 = VAR4 ^ VAR3;
assign VAR1 = (VAR4)? counter + 1'b1:
counter - 1'b1;
assign ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n.pp.symbol.v | 1,379 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR4,
input VAR7 ,
input VAR5 ,
input VAR1 ,
input VAR2
);
endmodule | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/uart_transmitter.v | 12,445 | module MODULE1 (clk, VAR21, VAR38, VAR9, VAR39, enable, VAR5, VAR43, VAR19, VAR34, VAR2);
input clk;
input VAR21;
input [7:0] VAR38;
input VAR9;
input [7:0] VAR39;
input enable;
input VAR34;
input VAR2; output VAR5;
output [2:0] VAR43;
output [VAR12-1:0] VAR19;
reg [2:0] VAR43;
reg [4:0] counter;
reg [2:0] VAR17; reg [... | gpl-2.0 |
gajjanag/6111_Project | src/acc.v | 6,830 | module MODULE2 #(parameter VAR35=8)
(input clk , input[VAR35-1:0] VAR21,
input VAR39, output VAR25);
reg[VAR35-1:0] VAR26 = 0;
always @(posedge clk) begin
if (VAR39) begin
VAR26 <= {VAR21[VAR35-2:0], 1'b0};
end
else begin
VAR26 <= {VAR26[VAR35-2:0], 1'b0};
end
end
assign VAR25 = VAR39 ? VAR21[VAR35-1] : VAR26[VAR35-1];... | gpl-3.0 |
google/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram | cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/gf180mcu_fd_ip_sram__sram64x8m8wm1.v | 15,914 | module MODULE1 (
VAR45,
VAR37,
VAR43,
VAR15,
VAR48,
VAR35,
VAR13,
VAR46,
VAR24
);
input VAR45;
input VAR37; input VAR43; input [7:0] VAR15; input [5:0] VAR48;
input [7:0] VAR35;
output [7:0] VAR13;
inout VAR46;
inout VAR24;
reg [7:0] VAR14[63:0];
reg [7:0] VAR38;
wire VAR34;
wire VAR31;
wire VAR22;
reg VAR19; reg VAR9;... | apache-2.0 |
SymbiFlow/nextpnr | generic/synth/prims.v | 1,091 | module MODULE2 #(
parameter VAR4 = 4,
parameter [2**VAR4-1:0] VAR8 = 0
) (
input [VAR4-1:0] VAR2,
output VAR17
);
wire [VAR4-1:0] VAR21;
genvar VAR9;
generate
for (VAR9 = 0; VAR9 < VAR4; VAR9 = VAR9 + 1'b1)
assign VAR21[VAR9] = (VAR2[VAR9] === 1'VAR19) ? 1'b0 : VAR2[VAR9];
endgenerate
assign VAR17 = VAR8[VAR21];
endmod... | isc |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Position/Integrador_Theta.v | 3,881 | module MODULE1(
input [15:0] VAR3,
input [15:0] VAR20,
input enable,
input rst,
input clk,
output [31:0] VAR8,
output reg VAR5
);
wire VAR16;
reg en;
reg [63:0] VAR12;
reg [63:0] VAR1;
wire [31:0] VAR2;
reg VAR14;
assign VAR8 = VAR12[63:32];
VAR21 VAR24(
.clk(clk),
.rst(VAR14),
.en(en),
.VAR19(VAR20),
.VAR22(VAR3),
.VA... | mit |
eecsninja/duinocube-core | common/main_avr.v | 5,295 | module MODULE1(clk, reset,
VAR42, VAR5, VAR13, VAR30, VAR29,
VAR43, VAR34, VAR15, VAR22, VAR25, VAR12,
VAR20, VAR6, VAR9);
input clk;
input reset;
input VAR42; input VAR5; input VAR13; input [VAR17-1:0] VAR30; inout [VAR2-1:0] VAR29;
output VAR43; output VAR34; output VAR15; output [1:0] VAR22; output [VAR14-1:0] VAR25... | gpl-3.0 |
mbus/mbus | mbus/verilog/no_pwr_gating_yesheng/mbus_general_layer_wrapper.v | 4,459 | module MODULE1(
input VAR21,
input VAR17,
input VAR39,
input [19:0] VAR31,
input [VAR22-1:0] VAR42,
output [VAR22-1:0] VAR34,
input VAR4,
output VAR62,
output VAR15,
input VAR25,
output VAR65,
input VAR58,
input VAR64,
output VAR6,
input [VAR47-1:0] VAR8,
input [VAR14-1:0] VAR30,
input VAR37,
input VAR45,
input VAR61,
... | apache-2.0 |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RegAligned.v | 2,270 | module MODULE1(VAR7, VAR8, VAR1, VAR3, VAR4);
parameter VAR6 = 1;
parameter VAR9 = { VAR6 {1'b0}} ;
input VAR7;
input VAR8;
input VAR4;
input [VAR6 - 1 : 0] VAR3;
output [VAR6 - 1 : 0] VAR1;
reg [VAR6 - 1 : 0] VAR1;
always@(posedge VAR7 or VAR5 VAR8) begin
if (VAR8 == VAR2)
VAR1 <= VAR10 VAR9;
end
else
begin
if (VAR4)
... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.cache/ip/2018.2/3bcfc1a1fd008685/design_1_rst_ps7_0_50M_0_stub.v | 1,873 | module MODULE1(VAR9, VAR8, VAR6,
VAR3, VAR4, VAR1, VAR7, VAR10,
VAR2, VAR5)
;
input VAR9;
input VAR8;
input VAR6;
input VAR3;
input VAR4;
output VAR1;
output [0:0]VAR7;
output [0:0]VAR10;
output [0:0]VAR2;
output [0:0]VAR5;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai.behavioral.pp.v | 2,048 | module MODULE1 (
VAR12 ,
VAR8 ,
VAR10 ,
VAR1 ,
VAR6 ,
VAR5,
VAR3,
VAR13 ,
VAR2
);
output VAR12 ;
input VAR8 ;
input VAR10 ;
input VAR1 ;
input VAR6 ;
input VAR5;
input VAR3;
input VAR13 ;
input VAR2 ;
wire VAR4 ;
wire VAR16 ;
wire VAR17;
or VAR14 (VAR4 , VAR10, VAR8 );
nand VAR15 (VAR16 , VAR6, VAR4, VAR1 );
VAR7 VAR11... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai.functional.pp.v | 2,027 | module MODULE1 (
VAR11 ,
VAR17 ,
VAR14 ,
VAR16 ,
VAR5 ,
VAR10,
VAR8,
VAR9 ,
VAR6
);
output VAR11 ;
input VAR17 ;
input VAR14 ;
input VAR16 ;
input VAR5 ;
input VAR10;
input VAR8;
input VAR9 ;
input VAR6 ;
wire VAR12 ;
wire VAR7 ;
wire VAR4;
or VAR2 (VAR12 , VAR14, VAR17, VAR16 );
nand VAR15 (VAR7 , VAR5, VAR12 );
VAR13... | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/verilog/feedforward_fdiv_32ns_32ns_32_16.v | 1,927 | module MODULE1
VAR4 = 2,
VAR27 = 16,
VAR23 = 32,
VAR1 = 32,
VAR20 = 32
)(
input wire clk,
input wire reset,
input wire VAR16,
input wire [VAR23-1:0] VAR21,
input wire [VAR1-1:0] VAR17,
output wire [VAR20-1:0] dout
);
wire VAR25;
wire VAR11;
wire VAR8;
wire [31:0] VAR2;
wire VAR14;
wire [31:0] VAR7;
wire VAR22;
wire [31... | gpl-3.0 |
AmeerAbdelhadi/Switched-Multiported-RAM | lvt_1ht.v | 9,108 | module MODULE1
localparam VAR3 = VAR15(VAR36); localparam VAR4 = VAR14 - 1 ;
reg [VAR3*VAR14-1:0] VAR11; reg [ VAR14-1:0] VAR13 ; always @(posedge clk) begin
VAR11 <= VAR25;
VAR13 <= VAR7 ;
end
reg [VAR3 -1:0] VAR33 [VAR14-1:0] ; reg [VAR3 -1:0] VAR9 [VAR14-1:0] ; wire [VAR4*VAR8 -1:0] VAR42 [VAR14-1:0] ; reg [VAR4 -1:... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s.behavioral.pp.v | 1,766 | module MODULE1 (
VAR3,
VAR5,
VAR4 ,
VAR7
);
input VAR3;
input VAR5;
output VAR4 ;
input VAR7 ;
wire VAR2 ;
wire VAR9;
buf VAR8 (VAR2 , VAR7 );
VAR10 VAR1 (VAR9, VAR2, VAR3, VAR5);
buf VAR6 (VAR4 , VAR9 );
endmodule | apache-2.0 |
Jside/nova1 | nova_io_dummy.v | 2,199 | module MODULE1(VAR3, VAR10, VAR11, VAR4, VAR7, VAR9, VAR5);
input VAR3;
input VAR10;
input VAR11;
input VAR4;
input [0:7] VAR7;
input [0:15] VAR9;
output reg [0:15] VAR5;
parameter VAR8 = 6'o00;
reg VAR1;
reg VAR2;
always @(posedge VAR3) begin
if(VAR10) begin
VAR5 <= 16'VAR6;
VAR1 <= 1'b1;
VAR2 <= 1'b0;
end
else begin
... | gpl-3.0 |
cr88192/bgbtech_bjx1core | bjx1c32b1/DecOp3_1.v | 36,711 | module MODULE1(
clk,
VAR52,
VAR7,
VAR113,
VAR176,
VAR133,
VAR230,
VAR3,
VAR143,
VAR328
);
parameter VAR117 = 0; parameter VAR293 = 0; parameter VAR56 = 1;
input clk; input[47:0] VAR52; input[15:0] VAR7;
output[6:0] VAR113;
output[6:0] VAR176;
output[6:0] VAR133;
output[31:0] VAR230;
output[3:0] VAR3;
output[3:0] VAR143... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap.behavioral.v | 1,112 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | Sincronizador.v | 1,188 | module MODULE1(VAR13,VAR9,VAR5,VAR4,VAR12,VAR8,VAR1,VAR3,VAR17,VAR6,clk);
input wire VAR13,VAR9,VAR5,VAR4,VAR12,clk;
output wire VAR8,VAR1,VAR17,VAR6,VAR3;
VAR18 VAR16 (
.VAR14(VAR13),
.clk(clk),
.VAR7(VAR8)
);
VAR18 VAR10 (
.VAR14(VAR9),
.clk(clk),
.VAR7(VAR1)
);
VAR18 VAR2 (
.VAR14(VAR5),
.clk(clk),
.VAR7(VAR3)
);
VA... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/acl_atomics_nostall.v | 39,283 | module MODULE2
(
VAR75, VAR46,
VAR127,
VAR157,
VAR118,
VAR102,
VAR122,
VAR112,
VAR87,
VAR19,
VAR43,
VAR11,
VAR109,
VAR97,
VAR54,
VAR57,
VAR35,
VAR82,
VAR70,
VAR145,
VAR60,
VAR61
);
parameter VAR51=3;
parameter VAR63=4;
parameter VAR105=8'b11111111; parameter VAR136=27; parameter VAR1=96; parameter VAR25=6; parameter VA... | mit |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_sram_0.v | 7,223 | module MODULE1 (
clk,
reset,
address,
VAR13,
read,
write,
VAR14,
VAR15,
VAR10,
VAR12,
VAR11,
VAR6,
VAR1,
VAR4,
VAR2,
VAR3
);
input clk;
input reset;
input [17: 0] address;
input [ 1: 0] VAR13;
input read;
input write;
input [15: 0] VAR14;
inout [15: 0] VAR15;
output reg [15: 0] VAR10;
output reg VAR12;
output reg [17: ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222o/sky130_fd_sc_ms__a222o.pp.blackbox.v | 1,456 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR5 ,
VAR7 ,
VAR11 ,
VAR3 ,
VAR4 ,
VAR6,
VAR8,
VAR2 ,
VAR9
);
output VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR7 ;
input VAR11 ;
input VAR3 ;
input VAR4 ;
input VAR6;
input VAR8;
input VAR2 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1.pp.blackbox.v | 1,291 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR2;
input VAR4;
endmodule | apache-2.0 |
mithro/HDMI2USB-litex-firmware | gateware/encoder/vhdl/HeaderRAM.v | 2,196 | module MODULE1(VAR1, VAR5, VAR7, VAR3, clk, VAR4);
output [7:0] VAR4;
input [7:0] VAR1;
input[9:0] VAR7;
input[9:0] VAR5;
input clk, VAR3;
reg [9:0] VAR2;
reg[7:0] VAR6 [1023:0] ; | bsd-2-clause |
swallat/yosys | techlibs/achronix/speedster22i/cells_arith.v | 2,594 | module MODULE1(
module 80alteramax10alu (VAR19, VAR22, VAR3, VAR13, VAR7, VAR12, VAR29);
parameter VAR24 = 0;
parameter VAR25 = 0;
parameter VAR36 = 1;
parameter VAR17 = 1;
parameter VAR16 = 1;
input [VAR36-1:0] VAR19;
input [VAR17-1:0] VAR22;
output [VAR16-1:0] VAR7, VAR12;
input VAR3, VAR13;
output VAR29;
wire VAR6 =... | isc |
8l/kestrel | 2/nexys2/computer/T_kestrel2.v | 1,837 | module MODULE1;
reg VAR9;
reg VAR20;
reg VAR5;
reg VAR4;
wire VAR15;
wire VAR21;
wire VAR22;
wire VAR17;
wire VAR18;
wire VAR2;
wire VAR14;
wire VAR11;
wire VAR16;
wire VAR10;
wire VAR23;
wire VAR3;
wire VAR8;
wire VAR12;
wire [2:0] VAR1;
wire [2:0] VAR19;
wire [2:1] VAR6;
VAR7 VAR13 (
.VAR15(VAR15),
.VAR21(VAR21),
.VA... | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_select_mofn.v | 2,401 | module MODULE1
(select, VAR2, VAR7);
parameter VAR5 = 4;
parameter VAR4 = 32;
input [0:VAR5-1] select;
input [0:VAR5*VAR4-1] VAR2;
output [0:VAR4-1] VAR7;
wire [0:VAR4-1] VAR7;
generate
genvar VAR8;
for(VAR8 = 0; VAR8 < VAR4; VAR8 = VAR8 + 1)
begin:VAR6
wire [0:VAR5-1] VAR1;
genvar VAR9;
for(VAR9 = 0; VAR9 < VAR5; VAR9... | mit |
alexforencich/verilog-ethernet | rtl/ssio_sdr_out_diff.v | 2,990 | module MODULE1 #
(
parameter VAR27 = "VAR7",
parameter VAR2 = "VAR8",
parameter VAR18 = 1
)
(
input wire clk,
input wire [VAR18-1:0] VAR10,
output wire VAR29,
output wire VAR9,
output wire [VAR18-1:0] VAR24,
output wire [VAR18-1:0] VAR3
);
wire VAR12;
wire [VAR18-1:0] VAR14;
VAR16 #(
.VAR27(VAR27),
.VAR2(VAR2),
.VAR18(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill_diode/sky130_fd_sc_ls__fill_diode.blackbox.v | 1,197 | module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_example_top_29.v | 7,066 | module MODULE1 (
VAR67,
VAR17,
VAR12,
VAR18,
VAR68,
VAR6,
VAR31,
VAR71,
VAR60,
VAR2,
VAR16,
VAR33,
VAR43,
VAR3,
VAR53,
VAR49,
VAR35,
VAR47,
VAR25,
VAR46,
VAR19
)
;
output [ 12: 0] VAR12;
output [ 2: 0] VAR18;
output VAR68;
output [ 0: 0] VAR6;
inout [ 0: 0] VAR31;
inout [ 0: 0] VAR71;
output [ 0: 0] VAR60;
output [ 3: ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtn/sky130_fd_sc_lp__dlxtn.symbol.v | 1,341 | module MODULE1 (
input VAR3 ,
output VAR1 ,
input VAR6
);
supply1 VAR4;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/HLS_accel_v1_0/dbdcd11c/hdl/verilog/HLS_accel_fcmp_32ns_32ns_1_1.v | 2,474 | module MODULE1
VAR40 = 9,
VAR26 = 1,
VAR17 = 32,
VAR8 = 32,
VAR20 = 1
)(
input wire [VAR17-1:0] VAR33,
input wire [VAR8-1:0] VAR19,
input wire [4:0] VAR29,
output wire [VAR20-1:0] dout
);
localparam [4:0]
VAR22 = 5'b00001,
VAR10 = 5'b00010,
VAR30 = 5'b00011,
VAR21 = 5'b00100,
VAR25 = 5'b00101,
VAR38 = 5'b00110,
VAR12 =... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/6d4b02c9ba6a5d75/zqynq_lab_1_design_axi_gpio_1_0_stub.v | 2,345 | module MODULE1(VAR4, VAR3, VAR15,
VAR7, VAR14, VAR18, VAR12, VAR13, VAR16,
VAR20, VAR5, VAR8, VAR11, VAR9, VAR10,
VAR2, VAR6, VAR17, VAR19, VAR1)
;
input VAR4;
input VAR3;
input [8:0]VAR15;
input VAR7;
output VAR14;
input [31:0]VAR18;
input [3:0]VAR12;
input VAR13;
output VAR16;
output [1:0]VAR20;
output VAR5;
input VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.behavioral.pp.v | 1,174 | module MODULE1( VAR7, VAR4, VAR6, VAR1 );
input VAR7;
inout VAR6, VAR1;
output VAR4;
VAR5 VAR2(.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1));
VAR5 VAR3(.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
hakehuang/pycpld | ips/ip/pwm_out/pwm_out.v | 1,174 | module MODULE1(VAR5, clk, enable, VAR7, VAR6, VAR3, VAR1);
input VAR5;
input clk;
input enable;
input[31:0] VAR3;
input[31:0] VAR1;
output VAR7;
output VAR6;
reg VAR4;
reg [31:0] VAR2;
always @(posedge clk or negedge VAR5) begin
if (!VAR5) begin
VAR2 <= 0;
end
else if (enable)
begin
if (VAR2 < VAR3) begin
VAR2 <= VAR2 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_mux_4to2/sky130_fd_sc_hs__udp_mux_4to2.symbol.v | 1,327 | module MODULE1 (
input VAR7,
input VAR1,
input VAR5,
input VAR2,
output VAR4 ,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_4.v | 2,599 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR1 ,
VAR11 ,
VAR7 ,
VAR4,
VAR9 ,
VAR5 ,
VAR12 ,
VAR8
);
output VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR11 ;
input VAR7 ;
input VAR4;
input VAR9 ;
input VAR5 ;
input VAR12 ;
input VAR8 ;
VAR3 VAR2 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR4(VAR4),
.VA... | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/daisho-usb3/usb3_crc.v | 27,360 | module MODULE4(
input wire [10:0] VAR1,
output wire [4:0] VAR5
);
wire [10:0] VAR7 = { VAR1[0], VAR1[1], VAR1[2], VAR1[3], VAR1[4],
VAR1[5], VAR1[6], VAR1[7], VAR1[8], VAR1[9],
VAR1[10] };
wire [4:0] VAR6 = 5'h1F;
wire [4:0] VAR4 = { ^VAR7[10:9] ^ ^VAR7[6:5] ^ VAR7[3] ^ VAR7[0] ^ VAR6[0] ^ ^VAR6[4:3],
VAR7[10] ^ ^VAR7[... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tap/sky130_fd_sc_ms__tap.pp.blackbox.v | 1,215 | module MODULE1 (
VAR4,
VAR3,
VAR1 ,
VAR2
);
input VAR4;
input VAR3;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.behavioral.pp.v | 1,476 | module MODULE1( VAR3, VAR4, VAR8, VAR2, VAR6 );
input VAR4, VAR3;
inout VAR2, VAR6;
output VAR8;
VAR5 VAR1(.VAR3(VAR3),.VAR4(VAR4),.VAR8(VAR8),.VAR2(VAR2),.VAR6(VAR6));
VAR5 VAR7(.VAR3(VAR3),.VAR4(VAR4),.VAR8(VAR8),.VAR2(VAR2),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_bleeder/sky130_fd_sc_hd__lpflow_bleeder_1.v | 2,087 | module MODULE2 (
VAR6,
VAR1 ,
VAR3 ,
VAR7 ,
VAR5
);
input VAR6;
inout VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR5 ;
VAR4 VAR2 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR6
);
input VAR6;
wire VAR1;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR5 ;
VAR4 VAR2 (
.VAR6(VAR6)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4bb/sky130_fd_sc_hdll__and4bb.behavioral.pp.v | 2,018 | module MODULE1 (
VAR15 ,
VAR13 ,
VAR3 ,
VAR8 ,
VAR5 ,
VAR7,
VAR12,
VAR14 ,
VAR16
);
output VAR15 ;
input VAR13 ;
input VAR3 ;
input VAR8 ;
input VAR5 ;
input VAR7;
input VAR12;
input VAR14 ;
input VAR16 ;
wire VAR6 ;
wire VAR4 ;
wire VAR2;
nor VAR10 (VAR6 , VAR13, VAR3 );
and VAR9 (VAR4 , VAR6, VAR8, VAR5 );
VAR17 VAR1... | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T25-uart-rx/echo.v | 1,999 | module MODULE1(input wire clk, input wire VAR2, output wire VAR4 );
localparam VAR10 = VAR11;
wire VAR9;
wire [7:0] VAR5;
reg VAR8 = 0;
wire ready;
always @(posedge clk)
VAR8 <= 1;
VAR3 #(VAR10)
VAR6 (.clk(clk), .VAR8(VAR8), .VAR2(VAR2), .VAR9(VAR9), .VAR5(VAR5) );
VAR1 #(VAR10)
VAR7 ( .clk(clk), .VAR8(VAR8), .VAR12(VA... | gpl-2.0 |
jhol/butterflylogic | rtl/stage.v | 6,550 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR17,
input wire [31:0] VAR18, input wire VAR37, input wire [7:0] din, input wire VAR38, input wire [31:0] VAR35, input wire VAR15,
input wire VAR20,
input wire [1:0] VAR11,
output reg VAR19,
output reg VAR13
);
localparam VAR12 = 1'b1;
localparam VAR32 = 1'b0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrckapwr/sky130_fd_sc_hd__lpflow_isobufsrckapwr.functional.pp.v | 2,390 | module MODULE1 (
VAR10 ,
VAR17,
VAR13 ,
VAR3,
VAR8 ,
VAR4 ,
VAR16 ,
VAR19
);
output VAR10 ;
input VAR17;
input VAR13 ;
input VAR3;
input VAR8 ;
input VAR4 ;
input VAR16 ;
input VAR19 ;
wire VAR15 ;
wire VAR2 ;
wire VAR14 ;
wire VAR9;
not VAR11 (VAR15 , VAR17 );
and VAR5 (VAR2 , VAR15, VAR13 );
VAR6 VAR18 (VAR14 , VAR2,... | apache-2.0 |
aquaxis/FPGAMAG18 | modules/fmrv32im_v1/src/fmrv32im_alu.v | 3,371 | module MODULE1
(
input VAR1,
input VAR46,
input VAR44,
input VAR35,
input VAR41,
input VAR38,
input VAR43,
input VAR3,
input VAR7,
input VAR17,
input VAR40,
input VAR8,
input VAR10,
input VAR11,
input VAR32,
input VAR36,
input VAR45,
input VAR13,
input VAR20,
input VAR4,
input VAR30,
input VAR5,
input VAR15,
input VAR4... | mit |
mbus/mbus | releases/mbus_example-v1.2/verilog/mbus_int_ctrl.v | 2,889 | module MODULE1
(
input VAR16,
input VAR18,
input VAR8, input VAR7,
input VAR12,
input VAR1,
input VAR4, input VAR15, output reg VAR17,
output reg VAR13,
input VAR5
);
reg VAR19;
reg VAR2;
always @ * begin
if (VAR8 ==VAR6)
VAR19 = 0;
end
else
VAR19 = VAR12;
end
wire VAR10 = ((~VAR19) & (~VAR7));
always @ (negedge VAR16 ... | apache-2.0 |
arthurafarias/UFCG-EE-LASD-2014.1-Experiments | preparacao-3.alpha/Output_LiquidCrystalDisplay_Controller.v | 1,503 | module MODULE1 ( VAR10,VAR7,
VAR14,VAR15,
VAR3,VAR6,
VAR8,
VAR12,
VAR2,
VAR1 );
parameter VAR13 = 16;
input [7:0] VAR10;
input VAR7,VAR14;
input VAR3,VAR6;
output reg VAR15;
output [7:0] VAR8;
output reg VAR2;
output VAR12;
output VAR1;
reg [4:0] VAR11;
reg [1:0] VAR4;
reg VAR5,VAR9;
assign VAR8 = VAR10;
assign VAR12 =... | gpl-2.0 |
tommythorn/yari | shared/rtl/altera/CycloneIII/dpram.v | 4,435 | module MODULE1 (VAR38,
VAR27, VAR26, VAR62, VAR29, VAR76,
VAR15, VAR3, VAR16, VAR51, VAR43);
parameter VAR37 = 32;
parameter VAR50 = 7;
parameter VAR42 = "VAR73";
input [VAR50-1:0] VAR27;
input [VAR50-1:0] VAR15;
input [VAR37/8-1:0] VAR26;
input [VAR37/8-1:0] VAR3;
input VAR38;
input [VAR37-1:0] VAR62;
input [VAR37-1:0... | gpl-2.0 |
chenm001/connectal | verilog/LinkInverter.v | 1,981 | module MODULE1(VAR11,
VAR9,
VAR3,
VAR10,
VAR6,
VAR2,
VAR7,
VAR4,
VAR8,
VAR5
);
parameter VAR1 = 1;
input VAR11;
input VAR9;
output [VAR1-1 : 0] VAR2;
input [VAR1-1 : 0] VAR3;
input VAR7;
input VAR10;
output VAR4;
output VAR6;
output VAR8;
output VAR5;
assign VAR2 = VAR3;
assign VAR4 = 1;
assign VAR6 = 1;
assign VAR8 = ... | mit |
Jafet95/proy_3_grupo_2_sem_1_2016 | timing_generator_VGA.v | 3,960 | module MODULE1
(
input wire clk,reset,
output wire VAR20,VAR6,VAR21,VAR24,
output wire [9:0] VAR8, VAR17
);
localparam VAR5 = 640;localparam VAR15 = 48;localparam VAR27 = 16;localparam VAR2 = 96;localparam VAR4 = 480;localparam VAR26 = 10;localparam VAR22 = 33;localparam VAR23 = 2;
reg VAR11, VAR12;
reg[9:0] VAR10, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o_m.v | 2,345 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR9 ,
VAR10 ,
VAR6 ,
VAR7,
VAR5,
VAR3 ,
VAR8
);
output VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR10 ;
input VAR6 ;
input VAR7;
input VAR5;
input VAR3 ;
input VAR8 ;
VAR11 VAR2 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxtp/sky130_fd_sc_ls__sedfxtp_4.v | 2,466 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR3 ,
VAR12 ,
VAR1 ,
VAR4 ,
VAR8,
VAR2,
VAR9 ,
VAR6
);
output VAR7 ;
input VAR11 ;
input VAR3 ;
input VAR12 ;
input VAR1 ;
input VAR4 ;
input VAR8;
input VAR2;
input VAR9 ;
input VAR6 ;
VAR10 VAR5 (
.VAR7(VAR7),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/Design-of-various-multiplier-Array-Booth-Wallace--master/Hybrid multiplier/Hybrid multiplier.v | 6,312 | module MODULE4(VAR102,VAR59,VAR74);
input [7:0] VAR102,VAR59;
output [15:0] VAR74;
wire [7:0] VAR25,VAR39,VAR47,VAR4,VAR65,VAR16,VAR49,VAR45;
wire [9:0] VAR75,VAR52,VAR76,VAR110;
wire [3:0] VAR23,VAR71,VAR107;
wire [6:0] VAR21,VAR111;
wire [12:0] VAR108,VAR14;
wire [6:0] VAR48;
wire [11:0] VAR63;
wire [3:0] VAR51,VAR55... | gpl-3.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/system/synthesis/system.v | 40,631 | module MODULE1 (
input wire VAR147, input wire VAR201, output wire VAR217, output wire [14:0] VAR86, output wire [2:0] VAR200, output wire VAR195, output wire VAR105, output wire VAR41, output wire VAR211, output wire VAR186, output wire VAR143, output wire VAR42, output wire VAR233, inout wire [31:0] VAR157, inout wir... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/ppu/ppu.v | 12,813 | module MODULE1
(
input VAR138, input VAR87, input [ 2:0] VAR64, input VAR134, input VAR100, input [ 7:0] VAR143, input [ 7:0] VAR115, output [ 7:0] VAR57,
output [9:0] VAR121, output [9:0] VAR116, output VAR119, output VAR109, output [ 2:0] VAR131, output [ 2:0] VAR17, output [ 1:0] VAR161,
output VAR37, output [13:0] ... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad7091r_v1_00_a/hdl/verilog/axi_ad7091r.v | 10,381 | module MODULE1 (
VAR24,
VAR120,
VAR131,
VAR91,
VAR21,
VAR125,
VAR123,
VAR49,
VAR50,
VAR153,
VAR81,
VAR109,
VAR42,
VAR23,
VAR133,
VAR64,
VAR147,
VAR122,
VAR85,
VAR119,
VAR32,
VAR94,
VAR116,
VAR148,
VAR137,
VAR130,
VAR38,
VAR52,
VAR139,
VAR140,
VAR13,
VAR19,
VAR102,
VAR141,
VAR104,
VAR61,
VAR135,
VAR73);
parameter VAR126... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.behavioral.v | 5,359 | module MODULE1( VAR1, VAR2, VAR7, VAR4, VAR10, VAR6, VAR3 );
input VAR10, VAR6, VAR3, VAR7, VAR2, VAR1;
output VAR4;
VAR9 VAR8(.VAR1(VAR1),.VAR2(VAR2),.VAR7(VAR7),.VAR4(VAR4),.VAR10(VAR10),.VAR6(VAR6),.VAR3(VAR3));
VAR9 VAR5(.VAR1(VAR1),.VAR2(VAR2),.VAR7(VAR7),.VAR4(VAR4),.VAR10(VAR10),.VAR6(VAR6),.VAR3(VAR3)); | apache-2.0 |
redfern314/RFIDuino | verilog/fsk_iface_mchester.v | 3,390 | module MODULE1(
input VAR7,
input VAR13,
input VAR11,
output reg VAR12,
output reg VAR2,
output reg VAR6
);
integer VAR1, VAR8, VAR9, VAR3;
reg [2:0] VAR10;
reg VAR5;
reg [1:0] VAR4; | gpl-3.0 |
Feuerwerk/fpgaNES | pixel_pll/pixel_pll_0002.v | 2,075 | module MODULE1(
input wire VAR30,
input wire rst,
output wire VAR21,
output wire VAR51
);
VAR4 #(
.VAR64("false"),
.VAR63("50.0 VAR52"),
.VAR14("VAR45"),
.VAR54(1),
.VAR3("25.000000 VAR52"),
.VAR49("0 VAR22"),
.VAR6(50),
.VAR67("0 VAR52"),
.VAR41("0 VAR22"),
.VAR33(50),
.VAR13("0 VAR52"),
.VAR28("0 VAR22"),
.VAR71(50),... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/common/ad_rst.v | 2,834 | module MODULE1 (
input VAR2,
input clk,
output VAR4,
output reg rst);
reg VAR6 = 1'd1;
reg VAR3 = 1'd1;
reg VAR1 = 1'd1;
reg VAR5 = 1'd1;
always @(posedge clk or posedge VAR2) begin
if (VAR2) begin
VAR6 <= 1'b1;
VAR3 <= 1'b1;
VAR1 <= 1'b1;
end else begin
VAR6 <= 1'b0;
VAR3 <= VAR6;
VAR1 <= VAR3;
end
end
always @(posedg... | mit |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/riffa/scsdpram.v | 2,937 | module MODULE1
parameter VAR11 = 32,
parameter VAR4 = 1024
)
(
input VAR5,
input VAR3,
input [VAR7(VAR4)-1:0] VAR8,
output [VAR11-1:0] VAR12,
input VAR1,
input [VAR7(VAR4)-1:0] VAR9,
input [VAR11-1:0] VAR2
);
reg [VAR11-1:0] VAR10 [VAR4-1:0];
reg [VAR11-1:0] VAR6;
assign VAR12 = VAR6;
always @(posedge VAR5) begin
if (V... | mit |
monotone-RK/FACE | IEICE-Trans/data_compression/4-way_2-tree/src/riffa/rxc_engine_classic.v | 20,954 | module MODULE1
parameter VAR16 = 128,
parameter VAR67 = 10)
( input VAR142,
input VAR76, input VAR42, output VAR49,
input [VAR16-1:0] VAR3,
input VAR113,
input VAR91,
input [VAR51-1:0] VAR66,
input VAR88,
input [VAR51-1:0] VAR102,
input [VAR107-1:0] VAR6,
output [VAR16-1:0] VAR71,
output VAR104,
output [(VAR16/32)-1:0]... | mit |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/misc/shift_reg.v | 2,077 | module MODULE1
input clk,
input VAR1,
input [VAR10:0] VAR2,
input VAR11,
output VAR9
);
reg [VAR8:0] VAR3 = VAR7;
wire [VAR5:0] VAR4;
assign VAR9 = VAR3[VAR2];
assign VAR4 = {VAR3, VAR11};
always @(posedge clk)
if (VAR1)
VAR3 <= #VAR6 VAR4[VAR8:0];
endmodule | lgpl-3.0 |
martinmiranda14/Digitales | Lab_6/Prueba_codigos_teclado.v | 1,822 | module MODULE1(
input VAR34,
input VAR36,
input VAR16,
input VAR39,
output [7:0] VAR7,
output [7:0] VAR14,
output VAR31,VAR33,VAR38,VAR20,VAR26,VAR22,VAR19,VAR12
);
wire reset;
wire VAR37;
wire [7:0] VAR25;
wire [4:0] VAR40;
wire [2:0] VAR13;
assign reset=~VAR36;
VAR11 VAR27(
.VAR10(VAR25),
.VAR40(VAR40),
.VAR13(VAR13)... | apache-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/soc_system_jtag_uart.v | 16,785 | module MODULE1 (
clk,
VAR34,
VAR55,
VAR17,
VAR11,
VAR13,
VAR9
)
;
output VAR17;
output [ 7: 0] VAR11;
output VAR13;
output [ 5: 0] VAR9;
input clk;
input [ 7: 0] VAR34;
input VAR55;
wire VAR17;
wire [ 7: 0] VAR11;
wire VAR13;
wire [ 5: 0] VAR9;
always @(posedge clk)
begin
if (VAR55)
("%VAR8", VAR34);
end
assign VAR9 = ... | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.v | 2,370 | module MODULE2 (
VAR9 ,
VAR5,
VAR1 ,
VAR4 ,
VAR7 ,
VAR10 ,
VAR6 ,
VAR2
);
output VAR9 ;
input VAR5;
input VAR1 ;
input VAR4 ;
input VAR7 ;
input VAR10 ;
input VAR6 ;
input VAR2 ;
VAR3 VAR8 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODU... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_CKINVDC_LVT_TT_210930.v | 11,786 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
not (VAR2, VAR1); | bsd-3-clause |
kactus2/ipxactexamplelib | tut.fi/communication.template/spi_slave/1.0/spi_slave.v | 3,053 | module MODULE1 #(
parameter VAR5 = 0
) (
input VAR1,
input VAR10,
input VAR4,
output reg VAR13,
input VAR2 );
localparam VAR16 = 8; localparam VAR14 = VAR9(VAR16);
reg [VAR16-1:0] VAR8;
reg [VAR16-1:0] VAR11;
reg [VAR14-1:0] VAR12;
reg [VAR14-1:0] VAR6;
reg VAR7;
reg VAR3;
always @(posedge VAR1 or posedge VAR2) begin
i... | mit |
CospanDesign/sdio-device | rtl/cia/sdio_cccr.v | 8,928 | module MODULE1 (
input clk,
input rst,
input VAR24,
input VAR10,
input [7:0] VAR97,
input VAR78,
input [7:0] VAR91,
output [7:0] VAR27,
output reg [7:0] VAR63,
input [7:0] VAR26,
output reg [7:0] VAR93,
input [7:0] VAR16,
output reg VAR65,
output reg [2:0] VAR76,
output reg VAR52,
output reg VAR41,
input VAR48,
output ... | mit |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_pipe_eq.v | 35,582 | module MODULE1 #
(
parameter VAR101 = "VAR131",
parameter VAR109 = "VAR74",
parameter VAR121 = 1
)
(
input VAR126,
input VAR112,
input VAR44,
input [ 1:0] VAR30,
input [ 3:0] VAR7,
input [ 3:0] VAR129,
input [ 5:0] VAR89,
input [ 1:0] VAR69,
input [ 2:0] VAR29,
input [ 5:0] VAR118,
input [ 3:0] VAR127,
input VAR77,
inp... | mit |
ahmed-agiza/LCSTA | Sample Files/mac.v | 12,513 | module MODULE5 (sum, VAR100, VAR37, VAR111, VAR247, VAR53);
output sum;
output VAR100;
output VAR37;
input VAR111;
input VAR247;
input VAR53;
assign sum = VAR111 ^ VAR247 ^ VAR53;
assign VAR100 = VAR111 & VAR247;
assign VAR37 = VAR111 | VAR247;
endmodule
module MODULE9 (VAR242, VAR76, clk, reset);
output [16:0] VAR242;... | gpl-2.0 |
YoelRP/PROYECTO | bin/enpoint/DATA/CRC16_D1024.v | 76,279 | module MODULE1(
VAR4,
VAR2,
VAR6
);
output reg [15:0] VAR4;
input wire [1023:0] VAR2;
input wire [15:0] VAR6;
reg [1023:0] VAR5;
reg [15:0] VAR3;
reg [15:0] VAR1;
always @ (*)
begin
VAR5 = VAR2;
VAR3 = VAR6;
VAR1[0] = VAR5[1023] ^ VAR5[1021] ^ VAR5[1020] ^ VAR5[1017] ^ VAR5[1016] ^ VAR5[1014] ^ VAR5[1012] ^ VAR5[1011] ... | gpl-3.0 |
SteffenReith/J1Sc | src/main/verilog/arch/IceBreaker/Board_IceBreaker.v | 2,247 | module MODULE1 (VAR6,
VAR11,
VAR3,
VAR15,
VAR22,
VAR9,
VAR20,
VAR12,
VAR26,
VAR19);
input VAR6;
input VAR11;
input [0:0] VAR3;
input [1:0] VAR9;
input VAR12;
output [3:0] VAR15;
output [0:0] VAR22;
output VAR26;
output VAR19;
inout [7:0] VAR20;
wire VAR14;
wire VAR2;
wire [7:0] VAR27;
wire [7:0] VAR17;
wire [7:0] VAR1;... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_nsr_pp_pg_n.symbol.v | 1,663 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR1 ,
input VAR6 ,
input VAR3 ,
input VAR5,
input VAR8 ,
input VAR7
);
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_force_adapt.v | 12,790 | module MODULE1 (
input VAR45,
input VAR18,
input VAR55,
input [5:0] VAR33,
input [2:0] VAR22,
input [1:0] VAR26,
input VAR17,
input VAR12,
input [1:0] VAR16,
input [31:0] VAR56,
input [31:0] VAR4,
input [31:0] VAR38,
input [31:0] VAR31,
input [31:0] VAR40,
input [31:0] VAR49,
input [31:0] VAR60,
input [31:0] VAR50,
inp... | gpl-3.0 |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/mpuc541.v | 5,290 | module MODULE1 ( VAR11,VAR4 ,VAR5, VAR20,VAR19,VAR12 ,VAR17 ,VAR2 );
input VAR11 ;
wire VAR11 ;
input VAR4 ;
wire VAR4 ;
input VAR5; input VAR20 ; wire VAR20 ;
input [VAR3-1:0] VAR19 ;
wire signed [VAR3-1:0] VAR19 ;
input [VAR3-1:0] VAR12 ;
wire signed [VAR3-1:0] VAR12 ;
output [VAR3-1:0] VAR17 ;
reg [VAR3-1:0] VAR17 ;... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Clamp_block1.v | 1,590 | module MODULE1
(
VAR2,
VAR7,
VAR8,
VAR5
);
input signed [35:0] VAR2; input VAR7;
input signed [35:0] VAR8; output VAR5;
wire VAR9;
wire VAR3;
wire VAR6;
wire VAR4;
assign VAR9 = (VAR8 <= 36'VAR1 ? 1'b1 :
1'b0);
assign VAR3 = (VAR2 <= 36'VAR1 ? 1'b1 :
1'b0);
assign VAR6 = ~ (VAR9 ^ VAR3);
assign VAR4 = VAR6 & VAR7;
assi... | gpl-3.0 |
MeshSr/onetswitch45 | ons45-app52-ref_ofshw/vivado/onets_7045_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/fallthrough_small_fifo_v2.v | 4,494 | module MODULE1
parameter VAR8 = 3,
parameter VAR15 = 2**VAR8 - 1)
(
input [VAR11-1:0] din, input VAR12,
input VAR4,
output [VAR11-1:0] dout, output VAR6,
output VAR10,
output VAR1,
output reg VAR2,
input reset,
input clk
);
reg VAR13, VAR9;
VAR14
.VAR8 (VAR8),
.VAR15 (VAR15))
VAR3
(.din (din),
.VAR12 (VAR12),
.VAR4 (VA... | lgpl-2.1 |
Franderg/Ascensor | manejo_entradas.v | 1,397 | module MODULE1(
input clk,
input VAR3,
input VAR1,
input VAR10,
input VAR5,
input VAR8,
input VAR9,
input VAR4,
input VAR11,
input VAR6,
input VAR2,
output reg [3:0] VAR7
); | gpl-3.0 |
gajjanag/6111_Project | src/slow_clk.v | 1,661 | module MODULE1(input clk, output MODULE1);
parameter VAR1 = 27'd49999999;
reg [31:0] VAR3 = 0;
reg VAR2 = 0;
always @(posedge clk) begin
if (VAR3 == VAR1) begin
VAR2 <= ~VAR2;
VAR3 <= 0;
end
else begin
VAR3 <= VAR3 + 1;
end
end
assign MODULE1 = VAR2;
endmodule | gpl-3.0 |
racerxdl/SuperINT | Slave Codes/FPGA/LedPWM.v | 1,179 | module MODULE1(
input clk,
input [7:0] VAR3,
output out
);
reg [7:0] VAR2;
reg VAR1;
always @(posedge clk)
begin
if(VAR2 <= VAR3 & VAR3 != 0)
VAR1 <= 1;
end
else
VAR1 <= 0;
VAR2 <= VAR2+1;
end
assign out = VAR1;
endmodule | gpl-2.0 |
egyp7/mor1kx | rtl/verilog/mor1kx_ticktimer.v | 2,547 | module MODULE1
(
input clk,
input rst,
output [31:0] VAR16,
output [31:0] VAR19,
input VAR7,
input VAR15,
input [15:0] VAR14,
input [31:0] VAR9,
output VAR8,
output [31:0] VAR12
);
reg [31:0] VAR4;
reg [31:0] VAR17;
wire VAR13;
wire VAR18;
wire VAR6;
wire VAR1;
wire VAR5;
assign VAR16 = VAR4;
assign VAR19 = VAR17;
assi... | mpl-2.0 |
csturton/wirepatch | system/hardware/cores/uart16550/bench/verilog/uart_device.v | 22,816 | module MODULE1
(
VAR35,
VAR34,
VAR29,
VAR20,
VAR32,
VAR12,
VAR52,
VAR43
);
input VAR35;
output VAR34;
input VAR29;
output VAR20;
input VAR32;
output VAR12;
output VAR52;
output VAR43;
reg VAR9; reg VAR30; reg VAR75; reg VAR37 = 1'b1;
reg VAR24 = 1'b1;
reg VAR48 = 1'b1;
real VAR42 = 20;
real VAR23 = 0;
integer VAR67 = 5... | mit |
jotego/jt12 | hdl/mixer/jt12_mixer.v | 2,727 | module MODULE1 #(parameter VAR12=16,VAR27=16,VAR4=16,VAR16=16,VAR21=20)
(
input clk,
input VAR26,
input signed [VAR12-1:0] VAR1,
input signed [VAR27-1:0] VAR19,
input signed [VAR4-1:0] VAR3,
input signed [VAR16-1:0] VAR13,
input [7:0] VAR29,
input [7:0] VAR14,
input [7:0] VAR28,
input [7:0] VAR6,
output reg signed [VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn.functional.v | 1,216 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR4
);
output VAR2 ;
input VAR3 ;
input VAR4;
bufif0 VAR1 (VAR2 , VAR3, VAR4 );
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/m26_rx/m26_rx_core.v | 5,081 | module MODULE1
parameter VAR49 = 16,
parameter VAR50 = 0,
parameter VAR23 = 0
)(
input wire VAR4,
input wire VAR64,
input wire [1:0] VAR40,
input wire VAR2,
output wire VAR85,
output wire [31:0] VAR7,
input wire VAR22,
input wire [VAR49-1:0] VAR24,
input wire [7:0] VAR15,
output reg [7:0] VAR3,
input wire VAR32,
input ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor3/sky130_fd_sc_ms__xor3.behavioral.v | 1,406 | module MODULE1 (
VAR8,
VAR10,
VAR6,
VAR9
);
output VAR8;
input VAR10;
input VAR6;
input VAR9;
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR11 ;
wire VAR3;
xor VAR7 (VAR3, VAR10, VAR6, VAR9 );
buf VAR2 (VAR8 , VAR3 );
endmodule | apache-2.0 |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter_006.v | 6,161 | module MODULE1 #(
parameter VAR19 = 18,
parameter VAR10 = 0,
parameter VAR22 = 18,
parameter VAR23 = 0,
parameter VAR21 = 0,
parameter VAR20 = 0,
parameter VAR6 = 1,
parameter VAR18 = 1,
parameter VAR17 = 0,
parameter VAR24 = 18,
parameter VAR3 = 0,
parameter VAR2 = 1,
parameter VAR16 = 0,
parameter VAR14 = 1,
paramete... | gpl-2.0 |
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