repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp.functional.pp.v | 1,966 | module MODULE1 (
VAR2 ,
VAR18 ,
VAR14 ,
VAR15 ,
VAR8 ,
VAR10 ,
VAR12,
VAR1
);
output VAR2 ;
input VAR18 ;
input VAR14 ;
input VAR15 ;
input VAR8 ;
input VAR10 ;
input VAR12;
input VAR1;
wire VAR9 ;
wire VAR11;
wire VAR17 ;
VAR16 VAR4 (VAR11, VAR17, VAR8, VAR10 );
VAR16 VAR5 (VAR17 , VAR9, VAR14, VAR15 );
VAR3 VAR7 VAR6... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_iss_probe.v | 1,733 | module MODULE1 (
VAR17
);
parameter VAR26 = 1;
parameter VAR4 = "VAR27";
input [VAR26-1:0] VAR17;
VAR32 VAR6 (
.VAR15 (VAR17),
.VAR10 ()
,
.VAR31 (),
.VAR24 (),
.VAR16 (),
.VAR5 (),
.VAR29 (),
.VAR25 (),
.VAR13 (),
.VAR12 (),
.VAR19 (),
.VAR18 (),
.VAR3 (),
.VAR8 (),
.VAR14 (),
.VAR22 (),
.VAR33 (),
.VAR2 (),
.VAR34 ()... | lgpl-3.0 |
SiLab-Bonn/monopix_daq | firmware/src/monopix_core.v | 12,402 | module MODULE1 (
input wire VAR97,
inout wire [7:0] VAR96,
input wire [15:0] VAR43,
input wire VAR124,
input wire VAR128,
input wire VAR15,
input wire VAR67,
input wire VAR179,
input wire VAR140,
input wire VAR142,
input wire VAR138,
input wire VAR44,
output wire VAR99,
output wire [31:0] VAR21,
input wire VAR145,
inpu... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/registers.v | 26,627 | module MODULE1
parameter VAR187 = 12,
parameter VAR31 = 512, parameter VAR12 = "VAR8",
parameter VAR142 = 2,
parameter VAR185 = 32,
parameter VAR39 = "VAR73",
parameter VAR84= 1,
parameter VAR82= 1)
(
input VAR184,
input VAR93,
input [VAR83-1:0] VAR192,
input VAR90,
input VAR148,
input [VAR40(VAR83/32)-1:0] VAR80,
inpu... | gpl-3.0 |
olajep/oh | src/common/hdl/oh_oddr.v | 1,198 | module MODULE1 #(parameter VAR1 = 1) (
input clk, input [VAR1-1:0] VAR2, input [VAR1-1:0] VAR3, output [VAR1-1:0] out );
reg [VAR1-1:0] VAR4;
reg [VAR1-1:0] VAR6;
reg [VAR1-1:0] VAR5;
always @ (posedge clk)
begin
VAR4[VAR1-1:0] <= VAR2[VAR1-1:0];
VAR6[VAR1-1:0] <= VAR3[VAR1-1:0];
end
always @ (negedge clk)
VAR5[VAR1-1:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tap/sky130_fd_sc_ms__tap.blackbox.v | 1,208 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp.pp.blackbox.v | 1,406 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR4 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR6,
VAR8,
VAR10 ,
VAR5
);
output VAR1 ;
output VAR9 ;
input VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR6;
input VAR8;
input VAR10 ;
input VAR5 ;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | DynamicFocus_bb.v | 5,130 | module MODULE1 (
address,
VAR2,
VAR1);
input [14:0] address;
input VAR2;
output [7:0] VAR1;
endmodule | mit |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/hdl/fmrv32im_artya7_wrapper.v | 1,118 | module MODULE1
(VAR3,
VAR9,
VAR2,
VAR8,
VAR6,
VAR10);
input VAR3;
output [31:0]VAR9;
input VAR2;
output VAR8;
input [31:0]VAR6;
output [31:0]VAR10;
wire VAR3;
wire [31:0]VAR9;
wire VAR2;
wire VAR8;
wire [31:0]VAR6;
wire [31:0]VAR10;
VAR5 VAR7
(.VAR3(VAR3),
.VAR1(VAR6),
.VAR4(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8... | mit |
asicguy/gplgpu | hdl/vga/memif_toplevel.v | 21,170 | module MODULE1
(
input VAR115,
input VAR27,
input VAR34,
input VAR90,
input VAR80,
input VAR118,
input VAR59,
input VAR113,
input VAR117,
input VAR39,
input VAR56,
input VAR180,
input VAR57,
input VAR173,
input [4:0] VAR128,
input VAR50,
input VAR87,
input VAR150,
input VAR99,
input VAR78,
input VAR106,
input VAR185,
i... | gpl-3.0 |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_bridge.v | 2,251 | module MODULE1
(
input rst,
input clk,
input [68:0] VAR29,
output [68:0] VAR4,
input [68:0] VAR18,
output [68:0] VAR21
);
parameter VAR17 = 0;
parameter VAR20 = 1;
parameter VAR11 = 0;
parameter VAR27 = 1;
reg [68:0] VAR25;
reg [68:0] VAR3;
reg [68:0] VAR19;
reg [68:0] VAR10;
assign VAR4 = VAR3;
assign VAR21 = VAR10;
w... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_convert_from_int.v | 7,824 | module MODULE1(VAR17, VAR55, VAR54, VAR46, enable, VAR6, VAR20, VAR44, VAR16);
parameter VAR15 = 0;
parameter VAR23 = 1;
parameter VAR39 = 0;
input VAR17, VAR55;
input [31:0] VAR54;
output [31:0] VAR46;
input enable, VAR6, VAR44;
output VAR20, VAR16;
reg VAR42;
wire VAR36;
wire VAR47;
reg VAR50;
wire VAR4;
wire VAR18;
... | mit |
nyaxt/dmix | spdif_tx.v | 4,385 | module MODULE1(
input wire clk, input wire rst,
input wire [1:0] VAR3,
input [47:0] VAR6,
output wire [1:0] VAR17,
input wire [191:0] VAR22,
input wire [191:0] VAR34,
output wire VAR18
);
reg VAR23;
always @(posedge clk) begin
if (rst)
VAR23 <= 1'b0;
end
else
VAR23 <= ~VAR23;
end
wire VAR10 = VAR23;
reg [47:0] VAR39;
a... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2_m.v | 2,083 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR6 ,
VAR1,
VAR7,
VAR9 ,
VAR8
);
output VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR1;
input VAR7;
input VAR9 ;
input VAR8 ;
VAR3 VAR4 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR2,
VAR5,
VAR6
);
output VAR2;
... | apache-2.0 |
Elphel/x393_sata | x393/wrap/pll_base.v | 6,234 | module MODULE1#(
parameter VAR38 = 0.000, parameter VAR3 = "VAR36", parameter VAR37 = 1, parameter VAR24 = 0.000, parameter VAR11 = 0.000, parameter VAR15 = 0.000, parameter VAR39 = 0.000,
parameter VAR7 = 0.000,
parameter VAR1 = 0.000,
parameter VAR41 = 0.000,
parameter VAR2= 0.5, parameter VAR17= 0.5,
parameter VAR48... | gpl-3.0 |
ptracton/Picoblaze | projects/display/rtl/display_top.v | 3,549 | module MODULE1 (
VAR31, VAR11, VAR30,
VAR27, VAR7, VAR16
) ;
input VAR27;
input VAR7;
input VAR16;
output VAR31;
output [3:0] VAR11;
output [7:0] VAR30;
wire VAR24; wire VAR29;
wire VAR31;
wire [7:0] VAR19;
wire [7:0] VAR32;
wire [7:0] VAR8;
wire [7:0] VAR4;
wire [7:0] VAR17;
wire [3:0] VAR11;
wire [7:0] VAR30;
VAR1 VA... | mit |
aquaxis/FPGAMAG18 | modules/gpio_v1/src/fmrv32im_axi_gpio.v | 8,341 | module MODULE1
(
input VAR22,
input VAR10,
input [15:0] VAR16,
input [3:0] VAR24,
input [2:0] VAR6,
input VAR7,
output VAR54,
input [31:0] VAR3,
input [3:0] VAR53,
input VAR34,
output VAR47,
output VAR57,
input VAR17,
output [1:0] VAR12,
input [15:0] VAR31,
input [3:0] VAR20,
input [2:0] VAR13,
input VAR30,
output VAR3... | mit |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_FlagReg_0_1/RAT_FlagReg_0_1_stub.v | 1,328 | module MODULE1(VAR1, VAR4, VAR3, VAR2, VAR5, VAR6)
;
input VAR1;
input VAR4;
input VAR3;
input VAR2;
input VAR5;
output VAR6;
endmodule | mit |
UA3MQJ/fpga-synth | modules/note_pitch2dds_2st_gen.v | 7,020 | module MODULE1(VAR3, VAR4, VAR5, VAR1);
input wire VAR3;
input wire [6:0] VAR4;
input wire [13:0] VAR5;
output reg [31:0] VAR1;
reg [32:0] VAR9;
reg [31:0] VAR6;
reg [7:0] VAR8;
reg [3:0] state;
reg [6:0] VAR7;
reg [13:0] VAR2; | gpl-3.0 |
zhangly/azpr_cpu | rtl/cpu/rtl/mem_stage.v | 6,983 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR34, input wire VAR32, output wire VAR22,
output wire [VAR17] VAR21,
input wire [VAR17] VAR26, output wire [VAR9] VAR19, output wire VAR23, output wire VAR12, output wire [VAR17] VAR25,
input wire [VAR17] VAR8, input wire VAR44, input wire VAR45, output wi... | mit |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_interleaver.v | 2,382 | module MODULE1
(VAR8, VAR9);
parameter VAR7 = 8;
parameter VAR6 = 2;
localparam VAR4 = VAR7 / VAR6;
input [0:VAR7-1] VAR8;
output [0:VAR7-1] VAR9;
wire [0:VAR7-1] VAR9;
generate
genvar VAR3;
for(VAR3 = 0; VAR3 < VAR4; VAR3 = VAR3 + 1)
begin:VAR1
genvar VAR5;
for(VAR5 = 0; VAR5 < VAR6; VAR5 = VAR5 + 1)
begin:VAR2
assign... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.blackbox.v | 1,360 | module MODULE1 (
VAR9 ,
VAR5,
VAR1,
VAR3,
VAR2
);
output VAR9 ;
input VAR5;
input VAR1;
input VAR3;
input VAR2;
supply1 VAR6;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_tx/MAC_tx_Ctrl.v | 22,985 | module MODULE1 (
VAR2 ,
VAR15 ,
VAR16 ,
VAR73 ,
VAR21 ,
VAR4 ,
VAR13 ,
VAR23 ,
VAR39 ,
VAR52 ,
VAR18 ,
VAR30 ,
VAR69 ,
VAR8 ,
VAR75 ,
VAR64 ,
VAR48 ,
VAR51 ,
VAR66 ,
VAR62 ,
VAR35 ,
VAR46 ,
VAR59 ,
VAR26 ,
VAR60 ,
VAR76 ,
VAR12 ,
VAR32 ,
VAR29 ,
VAR9 ,
VAR34 ,
VAR27 ,
VAR71 ,
VAR65 ,
VAR28 ,
VAR22,
VAR43 ,
VAR41 ,
VAR7... | apache-2.0 |
PyLCARS/PythonUberHDL | myHDL_ComputerFundamentals/Memorys/memory_array.v | 1,170 | module MODULE1 (
VAR11,
VAR9,
VAR4,
VAR6,
VAR3,
clk,
VAR7
);
input [7:0] VAR11;
input VAR9;
input [4:0] VAR4;
input [4:0] VAR6;
output [7:0] VAR3;
wire [7:0] VAR3;
input clk;
input VAR7;
reg [7:0] VAR1 [0:16-1];
VAR2 begin: VAR12
integer VAR10;
for(VAR10=0; VAR10<16; VAR10=VAR10+1) begin
VAR1[VAR10] = 0;
end
end
always... | bsd-3-clause |
jhol/butterflylogic | rtl/meta.v | 3,686 | module MODULE1 (
input wire VAR3,
input wire VAR1,
input wire VAR2,
input wire VAR6,
output reg VAR9,
output wire [7:0] VAR7
);
reg [5:0] VAR5, VAR10;
reg [5:0] VAR4;
reg [7:0] VAR8[63:0];
assign VAR7 = VAR8[VAR5];
begin
begin
begin | gpl-2.0 |
chenm001/x266 | lib/RAM_Nx1.v | 2,397 | module MODULE1(VAR12, VAR3, VAR9, VAR11, VAR15, VAR14, VAR8, VAR4);
parameter VAR2 = 72;
parameter VAR5 = 512;
parameter VAR10 = 9;
parameter VAR7 = 18;
parameter VAR1 = 2048;
parameter VAR6 = 11;
input VAR12;
input VAR3;
input VAR9;
input VAR11;
input [VAR10-1:0] VAR15;
input [VAR6-1:0] VAR14;
input [VAR2-1:0] VAR8;
o... | bsd-2-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpu/integracion_fisica/front_end/source/DECO_CORDIC_OP2.v | 2,159 | module MODULE1 (
input wire VAR4,
input wire VAR2,
input wire [1:0] VAR1,
output reg VAR5,
output reg VAR3
);
always @(*) begin
if(VAR2 == 1'b0)
begin case (VAR1)
2'b00 : begin
VAR5 = 1'b0;
VAR3 = VAR4;
end
2'b01 : begin
VAR5 = 1'b1;
VAR3 = ~VAR4;
end
2'b10 : begin
VAR5 = 1'b1;
VAR3 = VAR4;
end
2'b11 : begin
VAR5 = 1'b... | gpl-3.0 |
golfit/QcmMasterController | lut_n.v | 6,588 | module MODULE1(clk,VAR4, state);
input clk;
input [13:0] VAR4;
output reg [6:0] state;
parameter VAR1=4'b0100;
parameter VAR3=1;
always @(posedge clk) begin
end
if(VAR4>VAR2[0]) state=7'b1010000; else if(VAR4>VAR2[1]) state=7'b1001111;
else if(VAR4>VAR2[2]) state=7'b1001110;
else if(VAR4>VAR2[3]) state=7'b1001101;
else... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd.pp.symbol.v | 1,236 | module MODULE1 (
input VAR3 ,
input VAR2,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/chip.v | 15,757 | module MODULE1 (
input wire clk ,
input wire VAR85 ,
input wire reset
,input wire VAR25
,output wire VAR53
,input wire [VAR28-1:0] VAR22
,output wire [VAR112-1:0] VAR37
,inout wire [VAR47-1:0] VAR21
);
wire [VAR31] VAR110;
wire VAR106;
wire VAR8;
wire [VAR102] VAR97;
wire VAR60;
wire VAR75;
wire [VAR31] VAR56;
wire VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1.behavioral.pp.v | 4,893 | module MODULE1 (
VAR47 ,
VAR10 ,
VAR18 ,
VAR28,
VAR41,
VAR16 ,
VAR37
);
output VAR47 ;
input [7:0] VAR10 ;
input [7:0] VAR18 ;
input VAR28;
input VAR41;
input VAR16 ;
input VAR37 ;
wire VAR43 ;
wire VAR6 ;
wire VAR45 ;
wire VAR31 ;
wire VAR8 ;
wire VAR32 ;
wire VAR11 ;
wire VAR29 ;
wire VAR39 ;
wire VAR30 ;
wire VAR22;... | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_srl_fifo.v | 3,795 | module MODULE1 #
(
parameter VAR25 = 8,
parameter VAR13 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR25-1:0] VAR15,
input wire VAR18,
output wire VAR19,
input wire VAR12,
input wire VAR4,
output wire [VAR25-1:0] VAR17,
output wire VAR26,
input wire VAR22,
output wire VAR6,
output wire VAR7,
output wire [VAR8... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor3/sky130_fd_sc_hvl__nor3_1.v | 2,206 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR5,
VAR4,
VAR7 ,
VAR10
);
output VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR5;
input VAR4;
input VAR7 ;
input VAR10 ;
VAR9 VAR1 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
rkrajnc/minimig-mist | lib/altera/maxii_atoms.v | 53,691 | module MODULE1(
primitive VAR2 (VAR20, VAR14, VAR23, VAR6, VAR9, VAR18, VAR19);
input VAR23;
input VAR9;
input VAR18;
input VAR6;
input VAR14;
input VAR19;
output VAR20; reg VAR20;
VAR15 VAR20 = 1'b0;
VAR1
(??) ? ? 1 1 ? : ? : -; VAR17 ? ? 1 1 ? : ? : -; 1 1 (01) 1 1 ? : ? : 1; 1 1 (01) 1 VAR17 ? : ? : 1;
1 1 ? 1 VAR17... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2.pp.blackbox.v | 1,291 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR4,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR4;
input VAR2;
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/basys3/abacus/Seg_Scroll_REM.v | 1,097 | module MODULE1(
input clk,
input VAR1,
input [19:0] VAR3,
output [15:0] VAR4
);
reg [26:0] VAR2;
reg [23:0] VAR6;
always @(posedge VAR5 or posedge VAR1)
begin
if(VAR1==1)
begin
VAR6 [19:0] <= VAR3[19:0];
VAR6 [23:20] <= 'hC;
end
else
begin
VAR6 [19:0] <= VAR6[23:4];
VAR6 [23:20] <= VAR6[3:0];
end
end
assign VAR4[15:0] ... | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/i2c_master_byte_ctrl.v | 10,288 | module MODULE1 (
clk, rst, VAR17, VAR30, VAR16, VAR10, read, write, VAR6, din,
VAR21, VAR12, dout, VAR37, VAR31, VAR18, VAR20, VAR15, VAR24, VAR5, VAR36 );
input clk; input rst; input VAR17;
input [15:0] VAR30;
input VAR16;
input VAR10;
input read;
input write;
input VAR6;
input [7:0] din;
output VAR21;
reg VAR21;
outp... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_12.behavioral.pp.v | 1,187 | module MODULE1( VAR7, VAR5, VAR1, VAR3 );
input VAR7;
inout VAR1, VAR3;
output VAR5;
VAR4 VAR2(.VAR7(VAR7),.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3));
VAR4 VAR6(.VAR7(VAR7),.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3_1.v | 2,164 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR3,
VAR6,
VAR2 ,
VAR4
);
output VAR5 ;
input VAR8 ;
input VAR3;
input VAR6;
input VAR2 ;
input VAR4 ;
VAR1 VAR7 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR5,
VAR8
);
output VAR5;
input VAR8;
supply1 VAR3;
supply0 VAR6;... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_axi_basic_tx_pipeline.v | 22,925 | module MODULE1 #(
parameter VAR16 = 128, parameter VAR7 = "VAR49", parameter VAR53 = 1,
parameter VAR27 = (VAR16 == 128) ? 2 : 1, parameter VAR8 = VAR16 / 8 ) (
input [VAR16-1:0] VAR11, input VAR36, output VAR26, input [VAR8-1:0] VAR22, input VAR60, input [3:0] VAR18,
output [VAR16-1:0] VAR32, output VAR19, output VAR2... | lgpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361_rx_channel.v | 8,609 | module MODULE1 (
VAR29,
VAR23,
VAR31,
VAR26,
VAR60,
VAR49,
VAR53,
VAR92,
VAR14,
VAR54,
VAR79,
VAR16,
VAR33,
VAR63,
VAR95,
VAR39,
VAR72,
VAR10,
VAR37,
VAR66,
VAR19,
VAR101,
VAR51,
VAR74,
VAR70,
VAR48,
VAR77,
VAR99);
parameter VAR20 = 0;
parameter VAR21 = 0;
parameter VAR57 = 0;
input VAR29;
input VAR23;
input VAR31;
inp... | mit |
SymbiFlow/yosys | techlibs/common/gate2lut.v | 1,447 | module MODULE1(
module 90lutnot (VAR4, VAR7);
input VAR4;
output VAR7;
wire [VAR2-1:0] VAR8;
assign VAR8 = {VAR4};
\lut #(
.VAR5(VAR2),
.VAR9(4'b01)
) lut (
.VAR4(VAR8),
.VAR7(VAR7)
);
endmodule
module 90lutor (VAR4, VAR1, VAR7);
input VAR4, VAR1;
output VAR7;
wire [VAR2-1:0] VAR8;
assign VAR8 = {VAR1, VAR4};
\lut #(
.... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbp/sky130_fd_sc_hs__sdfbbp.pp.blackbox.v | 1,497 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR1 ,
VAR8 ,
VAR2 ,
VAR9 ,
VAR4 ,
VAR3,
VAR10 ,
VAR6
);
output VAR5 ;
output VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR3;
input VAR10 ;
input VAR6 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.behavioral.pp.v | 3,497 | module MODULE1( VAR7, VAR10, VAR5, VAR4, VAR9, VAR3, VAR6, VAR1 );
input VAR5, VAR10, VAR7, VAR9, VAR3;
inout VAR6, VAR1;
output VAR4;
VAR8 VAR2(.VAR7(VAR7),.VAR10(VAR10),.VAR5(VAR5),.VAR4(VAR4),.VAR9(VAR9),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1));
VAR8 VAR11(.VAR7(VAR7),.VAR10(VAR10),.VAR5(VAR5),.VAR4(VAR4),.VAR9(VAR9),.V... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/general/sirv_gnrl_bufs.v | 15,360 | module MODULE6 # (
parameter VAR80 = 0,
parameter VAR93 = 1,
parameter VAR66 = 32
) (
input VAR88,
output VAR44,
input [VAR66-1:0] VAR40,
output VAR87,
input VAR67,
output [VAR66-1:0] VAR45,
input clk,
input VAR94
);
genvar VAR82;
generate
if(VAR93 == 0) begin: VAR11
assign VAR87 = VAR88;
assign VAR44 = VAR67;
assign V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a.behavioral.pp.v | 2,074 | module MODULE1 (
VAR2 ,
VAR12 ,
VAR8 ,
VAR11 ,
VAR7 ,
VAR6 ,
VAR5,
VAR10,
VAR18 ,
VAR4
);
output VAR2 ;
input VAR12 ;
input VAR8 ;
input VAR11 ;
input VAR7 ;
input VAR6 ;
input VAR5;
input VAR10;
input VAR18 ;
input VAR4 ;
wire VAR15 ;
wire VAR17 ;
wire VAR9;
or VAR16 (VAR15 , VAR8, VAR12 );
and VAR14 (VAR17 , VAR11, V... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_hstl_pad.v | 4,774 | module MODULE1(VAR44 ,VAR56 ,VAR15 ,VAR31 ,VAR49 ,clk ,VAR2
,VAR9 ,VAR12 ,VAR45 ,VAR59 ,VAR61 ,VAR38 ,
VAR14 ,VAR50 ,VAR60 ,VAR7 ,VAR10 ,VAR34 ,VAR29 ,VAR27 ,VAR18 ,
VAR57 ,VAR66, VAR43 );
input [5:4] VAR56 ;
output VAR44 ;
output VAR61 ;
output VAR29 ;
input VAR15 ;
input VAR31 ;
input VAR49 ;
input clk ;
input VAR2 ;... | gpl-2.0 |
Raamakrishnan/MyProc | MyProc2/EXE.v | 3,759 | module MODULE1 (
input wire clk,
input wire [VAR13 - 1:0] VAR10,
input wire [VAR13 - 3:0] VAR1,
input wire [VAR13 - 1:0] VAR22,
input wire [VAR13 - 1:0] VAR7,
output wire [VAR13 - 1:0] VAR17,
output wire [VAR13 - 3:0] VAR25,
output reg [VAR13 - 1:0] VAR33,
output reg [VAR13 - 1:0] VAR19,
input wire VAR26,
output wire V... | mit |
nliu96/openHMC_Altera | src/openhmc_16x_rf.v | 19,009 | module MODULE1 (
input wire clk,
input wire VAR27,
input wire[6:3] address,
output reg VAR65,
output reg VAR77,
input wire VAR6,
output reg[63:0] VAR46,
input wire VAR39,
input wire[63:0] VAR19,
input wire VAR2,
input wire VAR16,
input wire VAR51,
input wire VAR71,
input wire VAR68,
input wire[9:0] VAR34,
input wire[9:... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai.symbol.v | 1,371 | module MODULE1 (
input VAR1,
input VAR8,
input VAR7,
input VAR9,
output VAR2
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o.symbol.v | 1,358 | module MODULE1 (
input VAR8,
input VAR3,
input VAR6,
input VAR4,
input VAR5,
output VAR2
);
supply1 VAR7;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4b/sky130_fd_sc_hd__or4b_2.v | 2,291 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR4 ,
VAR9 ,
VAR1 ,
VAR6,
VAR10,
VAR2 ,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR9 ;
input VAR1 ;
input VAR6;
input VAR10;
input VAR2 ;
input VAR5 ;
VAR11 VAR3 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR... | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_phy_alt_mem_phy_pll_bb.v | 17,726 | module MODULE1 (
VAR13,
VAR9,
VAR7,
VAR4,
VAR5,
VAR11,
VAR12,
VAR2,
VAR6,
VAR8,
VAR1,
VAR14,
VAR3,
VAR10);
input VAR13;
input VAR9;
input [3:0] VAR7;
input VAR4;
input VAR5;
input VAR11;
output VAR12;
output VAR2;
output VAR6;
output VAR8;
output VAR1;
output VAR14;
output VAR3;
output VAR10;
tri0 VAR13;
tri0 [3:0] VAR... | gpl-3.0 |
ucb-bar/chipyard | generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v | 1,332 | module MODULE1
(
input VAR8,
input reset,
output VAR2,
input VAR9,
input [VAR12-1:0] VAR11,
input [VAR12-1:0] VAR3,
input VAR1,
output VAR14,
output reg [VAR12-1:0] VAR4,
output VAR13
);
localparam VAR6 = 2'b00, VAR10 = 2'b01, VAR7 = 2'b10;
reg [1:0] state;
reg [VAR12-1:0] VAR5;
assign VAR2 = state == VAR6;
assign VAR1... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/pat_gen/axi_pipe.v | 6,183 | module MODULE1 (
input VAR36,
input VAR38,
input [7:0] VAR13,
input VAR11,
input VAR21,
output VAR25,
output [7:0] VAR2,
output VAR7,
output VAR6,
input VAR34
);
reg [5:0] VAR30;
reg [5:0] VAR17;
reg VAR1;
reg VAR27;
reg VAR10;
wire [1:0] VAR5;
wire [1:0] VAR33;
assign VAR25 = VAR27;
assign VAR7 = VAR10;
always @(VAR11... | lgpl-3.0 |
cpulabs/mist1032isa | src/core/execute/execute_exception.v | 4,913 | module MODULE1(
input wire VAR28,
input wire VAR4,
input wire VAR1,
input wire VAR3,
input wire VAR36,
input wire VAR32,
input wire VAR14,
input wire VAR6,
input wire VAR25,
input wire VAR19,
input wire VAR2,
input wire VAR31,
input wire [31:0] VAR23,
input wire VAR22,
input wire [6:0] VAR11,
input wire VAR18,
input wi... | bsd-2-clause |
hakehuang/pycpld | ips/ip/spi_slave_b2b_reduced/spi_slave_b2b_act_l_reduced.v | 2,971 | module MODULE1(
clk,VAR13,VAR3,VAR2,VAR11,VAR15,VAR7
);
input clk;
input VAR15;
input VAR13,VAR3,VAR11;
output VAR2;
output VAR7;
reg VAR7;
reg VAR9;
reg [7:0] VAR4;
reg [7:0] VAR16;
reg [7:0] VAR6;
wire VAR8;
wire VAR10;
wire VAR12;
wire VAR5;
wire VAR17;
reg VAR1, VAR14;
always@(posedge clk)
begin
if(!VAR15) begin
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxtp/sky130_fd_sc_ls__sdfxtp.symbol.v | 1,410 | module MODULE1 (
input VAR1 ,
output VAR9 ,
input VAR2,
input VAR6,
input VAR8
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_083.v | 1,550 | module MODULE2 (
VAR9,
VAR13
);
input [31:0] VAR9;
output [31:0]
VAR13;
wire [31:0]
VAR1,
VAR2,
VAR3,
VAR6,
VAR8,
VAR12,
VAR4,
VAR7,
VAR11,
VAR10;
assign VAR1 = VAR9;
assign VAR7 = VAR4 << 4;
assign VAR10 = VAR11 << 2;
assign VAR12 = VAR1 << 5;
assign VAR3 = VAR2 - VAR1;
assign VAR2 = VAR1 << 6;
assign VAR11 = VAR8 - V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn.behavioral.v | 2,407 | module MODULE1 (
VAR21 ,
VAR9,
VAR2 ,
VAR10
);
output VAR21 ;
input VAR9;
input VAR2 ;
input VAR10 ;
supply1 VAR12;
supply0 VAR5;
supply1 VAR22 ;
supply0 VAR7 ;
wire VAR1 ;
wire VAR13 ;
reg VAR11 ;
wire VAR8 ;
wire VAR14 ;
wire VAR24 ;
wire VAR3;
wire VAR16 ;
wire VAR19 ;
wire VAR6 ;
wire VAR15 ;
not VAR18 (VAR1 , VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi.pp.blackbox.v | 1,397 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR8 ,
VAR7 ,
VAR5 ,
VAR2,
VAR3,
VAR6 ,
VAR9
);
output VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR7 ;
input VAR5 ;
input VAR2;
input VAR3;
input VAR6 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp.functional.v | 1,891 | module MODULE1 (
VAR3 ,
VAR6,
VAR2,
VAR12 ,
VAR15,
VAR4
);
output VAR3 ;
output VAR6;
input VAR2;
input VAR12 ;
input VAR15;
input VAR4;
wire VAR1 ;
wire VAR10;
VAR5 VAR14 (VAR10, VAR12, VAR15, VAR4 );
VAR9 VAR11 VAR13 (VAR1 , VAR10, VAR2 );
buf VAR8 (VAR3 , VAR1 );
not VAR7 (VAR6 , VAR1 );
endmodule | apache-2.0 |
YosysHQ/yosys | techlibs/xilinx/brams_xc6v_map.v | 7,211 | module MODULE1 (...);
parameter VAR1 = 0;
parameter VAR90 = "VAR64";
parameter VAR38 = 0;
parameter VAR68 = 1;
parameter VAR43 = 1;
parameter VAR63 = 1;
parameter VAR73 = 1;
parameter VAR26 = 1;
parameter VAR100 = "VAR103";
parameter VAR49 = 0;
parameter VAR54 = 1;
parameter VAR74 = 1;
parameter VAR77 = 1;
parameter VA... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31o/sky130_fd_sc_hd__a31o_1.v | 2,337 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR5 ,
VAR6 ,
VAR7 ,
VAR9,
VAR1,
VAR11 ,
VAR2
);
output VAR8 ;
input VAR4 ;
input VAR5 ;
input VAR6 ;
input VAR7 ;
input VAR9;
input VAR1;
input VAR11 ;
input VAR2 ;
VAR3 VAR10 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufinv/sky130_fd_sc_hd__bufinv_8.v | 2,044 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR1,
VAR6,
VAR5 ,
VAR3
);
output VAR2 ;
input VAR8 ;
input VAR1;
input VAR6;
input VAR5 ;
input VAR3 ;
VAR7 VAR4 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR2,
VAR8
);
output VAR2;
input VAR8;
supply1 VAR1;
supply0 VAR6;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_2.behavioral.v | 3,726 | module MODULE1( VAR12, VAR6, VAR7, VAR23 );
input VAR12, VAR6, VAR7;
output VAR23;
reg VAR11;
VAR15 VAR26(.VAR12(VAR12),.VAR6(VAR6),.VAR7(VAR7),.VAR23(VAR23),.VAR11(VAR11));
VAR15 VAR25(.VAR12(VAR12),.VAR6(VAR6),.VAR7(VAR7),.VAR23(VAR23),.VAR11(VAR11));
not VAR30(VAR20,VAR6);
and VAR9(VAR4,VAR7,VAR20);
and VAR21(VAR27,... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/acl_arb2.v | 11,889 | module MODULE3
parameter string VAR20 = "VAR29", parameter integer VAR19 = 1, parameter integer VAR21 = 0,
parameter integer VAR11 = 32, parameter integer VAR10 = 4, parameter integer VAR22 = 32, parameter integer VAR30 = VAR11 / 8, parameter integer VAR38 = 1 )
(
input logic VAR8,
input logic VAR34,
VAR1 VAR31,
VAR1 V... | mit |
Digilent/vivado-library | ip/Pmods/PmodESP32_v1_0/src/PmodESP32.v | 19,701 | module MODULE1
(VAR64,
VAR120,
VAR195,
VAR58,
VAR169,
VAR185,
VAR25,
VAR101,
VAR159,
VAR15,
VAR177,
VAR51,
VAR148,
VAR14,
VAR10,
VAR190,
VAR139,
VAR123,
VAR196,
VAR144,
VAR75,
VAR45,
VAR166,
VAR28,
VAR60,
VAR43,
VAR152,
VAR55,
VAR99,
VAR47,
VAR40,
VAR44,
VAR178,
VAR78,
VAR132,
VAR194,
VAR186,
VAR114,
VAR161,
VAR172,
VA... | mit |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_select_1ofn.v | 2,430 | module MODULE1
(select, VAR4, VAR2);
parameter VAR6 = 4;
parameter VAR9 = 32;
input [0:VAR6-1] select;
input [0:VAR6*VAR9-1] VAR4;
output [0:VAR9-1] VAR2;
wire [0:VAR9-1] VAR2;
generate
genvar VAR8;
for(VAR8 = 0; VAR8 < VAR9; VAR8 = VAR8 + 1)
begin:VAR3
wire [0:VAR6-1] VAR5;
genvar VAR1;
for(VAR1 = 0; VAR1 < VAR6; VAR1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.behavioral.pp.v | 1,259 | module MODULE1( VAR1, VAR6, VAR4, VAR8, VAR3 );
input VAR1, VAR6;
inout VAR8, VAR3;
output VAR4;
VAR2 VAR7(.VAR1(VAR1),.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8),.VAR3(VAR3));
VAR2 VAR5(.VAR1(VAR1),.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8),.VAR3(VAR3)); | apache-2.0 |
perillamint/humbleverilogcalc | calculator.v | 1,595 | module MODULE1 (VAR26, VAR16, VAR7, VAR13, VAR10);
input[5:0] VAR26;
input[5:0] VAR16;
input[3:0] VAR7;
output[5:0] VAR13;
output VAR10;
wire[5:0] sum;
wire[5:0] VAR18;
wire[5:0] VAR1;
wire[5:0] VAR5;
wire[5:0] VAR2;
wire[5:0] VAR33;
wire[5:0] VAR17;
wire[5:0] VAR21;
wire[5:0] VAR27;
wire[5:0] VAR32;
wire[5:0] VAR25;
w... | gpl-3.0 |
bit0fun/Fusion-Core | Fusion-Core-Base/shift_left_32.v | 1,623 | module MODULE1(
input[31:0] VAR1, output[31:0] out );
assign out[0] = VAR1[31];
assign out[1] = VAR1[0];
assign out[2] = VAR1[1];
assign out[3] = VAR1[2];
assign out[4] = VAR1[3];
assign out[5] = VAR1[4];
assign out[6] = VAR1[5];
assign out[7] = VAR1[6];
assign out[8] = VAR1[7];
assign out[9] = VAR1[8];
assign out[10] ... | gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_4/synth/design_1_auto_pc_4.v | 13,308 | module MODULE1 (
VAR73,
VAR49,
VAR78,
VAR71,
VAR61,
VAR70,
VAR109,
VAR66,
VAR111,
VAR4,
VAR10,
VAR27,
VAR90,
VAR82,
VAR80,
VAR24,
VAR53,
VAR67,
VAR79,
VAR104,
VAR91,
VAR36,
VAR54,
VAR101,
VAR88,
VAR69,
VAR112,
VAR95,
VAR102,
VAR19,
VAR74,
VAR20,
VAR52,
VAR94,
VAR96,
VAR22,
VAR105,
VAR55,
VAR114,
VAR110,
VAR7,
VAR45,
VA... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_sine.v | 6,656 | module MODULE1 (
clk,
VAR37,
VAR25,
VAR23,
VAR27);
parameter VAR12 = 16;
localparam VAR18 = VAR12 - 1;
input clk;
input [15:0] VAR37;
output [15:0] VAR25;
input [VAR18:0] VAR23;
output [VAR18:0] VAR27;
reg [VAR18:0] VAR22 = 'd0;
reg VAR32 = 'd0;
reg [15:0] VAR29 = 'd0;
reg [15:0] VAR19 = 'd0;
reg [VAR18:0] VAR14 = 'd0;... | mit |
freecores/eco32 | fpga/src/dsp/pixel.v | 1,591 | module MODULE1(clk, VAR4, VAR12,
MODULE1, VAR9, VAR20, VAR16, VAR21,
VAR8, VAR19, VAR11, VAR6, VAR7);
input clk;
input VAR4;
input [7:0] VAR12;
input MODULE1;
input VAR9;
input VAR20;
input VAR16;
input VAR21;
output reg VAR8;
output reg VAR19;
output reg [2:0] VAR11;
output reg [2:0] VAR6;
output reg [2:0] VAR7;
wire ... | bsd-2-clause |
iAklis/teoca | EXPR5/MAIN.v | 4,758 | module MODULE1(
input clk,
input VAR26,
input VAR37,
input VAR32,
input VAR9, input [15:0] VAR34, input [2:0] VAR10,
input wire [4:0] VAR13,
input wire [4:0] VAR30,
input wire [4:0] VAR6, output wire [31:0] VAR11,
output wire [31:0] VAR3, output wire [31:0] VAR29, output VAR27, VAR23
);
wire [31:0] VAR7;
register VAR19... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcon/sky130_fd_sc_ls__fahcon.functional.pp.v | 2,730 | module MODULE1 (
VAR22,
VAR17 ,
VAR13 ,
VAR25 ,
VAR5 ,
VAR9 ,
VAR24 ,
VAR6 ,
VAR2
);
output VAR22;
output VAR17 ;
input VAR13 ;
input VAR25 ;
input VAR5 ;
input VAR9 ;
input VAR24 ;
input VAR6 ;
input VAR2 ;
wire VAR18 ;
wire VAR4 ;
wire VAR16 ;
wire VAR15 ;
wire VAR3 ;
wire VAR11 ;
wire VAR21;
xor VAR23 (VAR18 , VAR13... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapmet1/sky130_fd_sc_hs__tapmet1.functional.pp.v | 1,153 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
schelleg/PYNQ | boards/ip/audio_direct_1.1/hdl/audio_direct_v1_1.v | 3,187 | module MODULE1 #
(
parameter integer VAR22 = 32,
parameter integer VAR23 = 5
)
(
input wire VAR34,
input wire VAR64,
output wire VAR54,
output wire VAR1,
output wire VAR24,
input wire VAR38,
input wire VAR32,
input wire [VAR23-1 : 0] VAR17,
input wire [2 : 0] VAR42,
input wire VAR9,
output wire VAR37,
input wire [VAR22... | bsd-3-clause |
sh-chris110/chris | FPGA/uCos/system/synthesis/submodules/system_nios2_gen2_0_cpu_debug_slave_tck.v | 8,218 | module MODULE1 (
VAR20,
VAR39,
VAR1,
VAR6,
VAR35,
VAR3,
VAR21,
VAR37,
VAR19,
VAR8,
VAR4,
VAR33,
VAR13,
VAR7,
VAR12,
VAR17,
VAR40,
VAR18,
VAR14,
VAR24,
VAR11,
VAR5,
VAR36,
VAR9,
VAR16,
VAR26,
VAR23,
VAR31,
VAR10,
VAR29,
VAR32
)
;
output [ 1: 0] VAR23;
output VAR31;
output [ 37: 0] VAR10;
output VAR29;
output VAR32;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4b/sky130_fd_sc_hd__or4b.pp.blackbox.v | 1,335 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR4 ,
VAR2,
VAR1,
VAR6 ,
VAR8
);
output VAR3 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR2;
input VAR1;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/AU250/fpga_10g/rtl/fpga.v | 26,707 | module MODULE1 (
input wire reset,
input wire [3:0] VAR190,
output wire [2:0] VAR362,
inout wire VAR189,
inout wire VAR22,
output wire VAR16,
output wire VAR206,
input wire VAR255,
input wire VAR315,
output wire VAR275,
output wire VAR171,
input wire VAR47,
input wire VAR305,
output wire VAR390,
output wire VAR439,
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4.pp.symbol.v | 1,264 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR6 ,
input VAR7 ,
output VAR3 ,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/riffa/reorder_queue.v | 12,607 | module MODULE1
parameter VAR68 = 9'd128,
parameter VAR86 = 4'd12,
parameter VAR54 = 512, parameter VAR58 = 5, parameter VAR70 = VAR68/32,
parameter VAR45 = VAR83(VAR70+1),
parameter VAR60 = 2**VAR58,
parameter VAR80 = VAR54/4,
parameter VAR84 = VAR32(VAR80+1),
parameter VAR91 = VAR32(VAR80/VAR70), parameter VAR13 = VAR... | mit |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo_2clock_cascade.v | 2,621 | module MODULE1
(input VAR31, input [VAR8-1:0] VAR23, input VAR18, output VAR24,
output [15:0] VAR27, output [15:0] VAR26,
input VAR6, output [VAR8-1:0] VAR19, output VAR10, input VAR3,
output [15:0] VAR9, output [15:0] VAR32,
input VAR13);
wire [VAR8-1:0] VAR15, VAR20;
wire VAR14, VAR28, VAR1, VAR22;
wire [VAR4-1:0] VA... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.functional.pp.v | 1,290 | module MODULE1( VAR12, VAR8, VAR7, VAR14, VAR1, VAR4 );
input VAR7, VAR8, VAR14;
inout VAR1, VAR4;
output VAR12;
wire VAR10;
not VAR13( VAR10, VAR7 );
wire VAR2;
not VAR6( VAR2, VAR8 );
wire VAR9;
and VAR15( VAR9, VAR10, VAR2 );
wire VAR5;
not VAR11( VAR5, VAR14 );
or VAR3( VAR12, VAR9, VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2a/sky130_fd_sc_hd__o2bb2a.behavioral.v | 1,658 | module MODULE1 (
VAR5 ,
VAR8,
VAR15,
VAR12 ,
VAR6
);
output VAR5 ;
input VAR8;
input VAR15;
input VAR12 ;
input VAR6 ;
supply1 VAR3;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR4 ;
wire VAR16 ;
wire VAR11 ;
wire VAR10;
nand VAR13 (VAR16 , VAR15, VAR8 );
or VAR14 (VAR11 , VAR6, VAR12 );
and VAR1 (VAR10, VAR16, VAR11);
buf V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111oi/sky130_fd_sc_ls__a2111oi.symbol.v | 1,401 | module MODULE1 (
input VAR5,
input VAR2,
input VAR4,
input VAR3,
input VAR10,
output VAR1
);
supply1 VAR9;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfsbp/sky130_fd_sc_hs__sdfsbp.behavioral.v | 2,843 | module MODULE1 (
VAR22 ,
VAR8 ,
VAR17 ,
VAR6 ,
VAR20 ,
VAR23 ,
VAR4,
VAR3 ,
VAR18
);
input VAR22 ;
input VAR8 ;
output VAR17 ;
output VAR6 ;
input VAR20 ;
input VAR23 ;
input VAR4;
input VAR3 ;
input VAR18 ;
wire VAR5 ;
wire VAR9 ;
wire VAR13 ;
reg VAR15 ;
wire VAR2 ;
wire VAR11 ;
wire VAR21 ;
wire VAR28;
wire VAR1 ;
w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfsbp/sky130_fd_sc_hvl__dfsbp.blackbox.v | 1,360 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR9 ,
VAR8 ,
VAR6
);
output VAR4 ;
output VAR1 ;
input VAR9 ;
input VAR8 ;
input VAR6;
supply1 VAR2;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/lsu/rtl/lsu_pcx_qmon.v | 4,989 | module MODULE1 (
VAR18, VAR22, VAR15,
VAR14, VAR13, VAR21, VAR5, VAR1, VAR23, VAR24
) ;
input VAR14 ;
input VAR13;
input VAR21;
input VAR5;
input VAR1;
output VAR18;
input VAR23 ; input VAR24 ;
output VAR22 ; output VAR15 ;
wire clk;
wire reset ,VAR25 ;
wire VAR19, VAR4 ;
wire VAR10, VAR7 ;
wire VAR16, VAR17 ;
wire VAR... | gpl-2.0 |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | bcam.v | 11,070 | module MODULE1
localparam VAR3 = VAR50(VAR14);
reg VAR37;
reg [VAR3-1:0] VAR44;
reg [VAR45 -1:0] VAR1,VAR41;
always @(posedge clk, posedge rst)
if (rst) {VAR37,VAR44,VAR1,VAR41} <= {(1 +VAR3+VAR45 +VAR45 ){1'b0}};
else {VAR37,VAR44,VAR1,VAR41} <= { VAR48,VAR18,VAR26,VAR40 };
reg VAR25;
reg [VAR3-1:0] VAR38;
reg [VAR45 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.v | 2,375 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR11 ,
VAR1 ,
VAR2 ,
VAR6,
VAR9,
VAR4 ,
VAR3
);
output VAR8 ;
output VAR5 ;
input VAR11 ;
input VAR1 ;
input VAR2 ;
input VAR6;
input VAR9;
input VAR4 ;
input VAR3 ;
VAR7 VAR10 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4),
.VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_1.behavioral.pp.v | 1,316 | module MODULE1( VAR7, VAR4, VAR9, VAR5, VAR8, VAR6 );
input VAR7, VAR4, VAR9;
inout VAR8, VAR6;
output VAR5;
VAR1 VAR3(.VAR7(VAR7),.VAR4(VAR4),.VAR9(VAR9),.VAR5(VAR5),.VAR8(VAR8),.VAR6(VAR6));
VAR1 VAR2(.VAR7(VAR7),.VAR4(VAR4),.VAR9(VAR9),.VAR5(VAR5),.VAR8(VAR8),.VAR6(VAR6)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/altera_reset_controller.v | 3,485 | module MODULE1
parameter VAR27 = 6,
parameter VAR17 = "VAR12",
parameter VAR5 = 2
)
(
input VAR24,
input VAR18,
input VAR13,
input VAR15,
input VAR26,
input VAR2,
input VAR6,
input VAR11,
input VAR3,
input VAR9,
input VAR21,
input VAR19,
input VAR23,
input VAR4,
input VAR8,
input VAR10,
input clk,
output VAR25
);
local... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4.functional.v | 1,329 | module MODULE1 (
VAR1,
VAR3,
VAR5,
VAR6,
VAR2
);
output VAR1;
input VAR3;
input VAR5;
input VAR6;
input VAR2;
wire VAR7;
nor VAR4 (VAR7, VAR3, VAR5, VAR6, VAR2 );
buf VAR8 (VAR1 , VAR7 );
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/basys3/abacus/Seg_Scroll_QU.v | 1,091 | module MODULE1(
input clk,
input VAR5,
input [19:0] VAR3,
output [15:0] VAR6
);
reg [26:0] VAR1;
reg [23:0] VAR4;
always @(posedge VAR2 or posedge VAR5)
begin
if(VAR5==1)
begin
VAR4 [19:0] <= VAR3[19:0];
VAR4 [23:20] <= 'hC;
end
else
begin
VAR4 [19:0] <= VAR4[23:4];
VAR4 [23:20] <= VAR4[3:0];
end
end
assign VAR6[15:0] ... | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/timer_0.v | 6,823 | module MODULE1 (
address,
VAR12,
clk,
VAR30,
VAR25,
VAR23,
irq,
VAR33
)
;
output irq;
output [ 15: 0] VAR33;
input [ 2: 0] address;
input VAR12;
input clk;
input VAR30;
input VAR25;
input [ 15: 0] VAR23;
wire VAR29;
wire VAR5;
wire VAR2;
reg [ 3: 0] VAR18;
wire VAR14;
reg VAR20;
wire VAR3;
wire [ 31: 0] VAR6;
reg [ 31:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp_4.v | 2,289 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR8 ,
VAR6,
VAR9 ,
VAR5 ,
VAR4 ,
VAR2
);
output VAR10 ;
input VAR3 ;
input VAR8 ;
input VAR6;
input VAR9 ;
input VAR5 ;
input VAR4 ;
input VAR2 ;
VAR1 VAR7 (
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dlatch_pr/sky130_fd_sc_ms__udp_dlatch_pr.symbol.v | 1,360 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
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