repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50.behavioral.v | 1,439 | module MODULE1 (
VAR9,
VAR5
);
output VAR9;
input VAR5;
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
wire VAR8;
buf VAR6 (VAR8, VAR5 );
buf VAR7 (VAR9 , VAR8 );
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/spartan3/iobs.v | 7,304 | module MODULE1 (
VAR34,
VAR26, VAR21,
VAR39,
VAR74,
VAR2,
VAR16,
VAR70,
VAR59,
VAR8,
VAR67,
VAR36,
VAR24,
VAR20,
VAR7,
VAR43,
VAR13,
VAR14,
VAR31,
VAR29,
VAR64,
VAR46,
VAR49,
VAR35,
VAR15,
VAR37,
VAR57
);
parameter VAR1 = 16;
parameter VAR71 = 13;
parameter VAR58 = 2;
parameter VAR25 = VAR1 / VAR58 - 1;
input VAR34;
in... | lgpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/axi_dwidth_converter_v2_1/0a9a1aa5/hdl/verilog/axi_dwidth_converter_v2_1_b_downsizer.v | 10,780 | module MODULE1 #
(
parameter VAR16 = "none",
parameter integer VAR2 = 1
)
(
input wire VAR5,
input wire VAR9,
input wire VAR30,
input wire VAR3,
input wire [8-1:0] VAR20,
output wire VAR14,
input wire [VAR2-1:0] VAR34,
output wire [VAR2-1:0] VAR24,
output wire [2-1:0] VAR19,
output wire VAR17,
input wire VAR27,
input w... | gpl-3.0 |
asicguy/gplgpu | hdl/ramdac_sp/blnk.v | 5,723 | module MODULE1
(
input VAR22,
input reset,
input VAR27,
input VAR5,
input VAR4,
input VAR17,
input VAR29,
input VAR9,
output reg VAR25,
output VAR7,
output reg VAR31,
output reg VAR3,
output VAR24,
output reg VAR20,
output reg VAR30,
output reg VAR26,
output reg VAR18,
output reg VAR8,
output reg VAR19
);
reg VAR6,
VAR... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/spu/rtl/spu_wen.v | 10,433 | module MODULE1 (
VAR71,
VAR18,
VAR4,
VAR68,
VAR29,
VAR7,
VAR41,
VAR47,
VAR11,
VAR27,
VAR33,
VAR43,
VAR24,
VAR50,
VAR67,
VAR72,
VAR35,
VAR38,
VAR54,
VAR20,
VAR57,
VAR70,
VAR64,
VAR23,
VAR73,
VAR32,
VAR21,
reset,
VAR19);
input reset;
input VAR19;
input VAR21;
input [1:0] VAR23;
input VAR33;
input VAR43;
input [3:0] VAR24... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31o/sky130_fd_sc_hdll__a31o.blackbox.v | 1,362 | module MODULE1 (
VAR3 ,
VAR5,
VAR8,
VAR9,
VAR7
);
output VAR3 ;
input VAR5;
input VAR8;
input VAR9;
input VAR7;
supply1 VAR4;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_pma_lvds_tx.v | 8,490 | module MODULE1 (
VAR41,
VAR13,
VAR52,
VAR37);
input VAR41;
input [9:0] VAR13;
input VAR52;
output [0:0] VAR37;
wire [0:0] VAR24;
wire [0:0] VAR37 = VAR24[0:0];
VAR35 VAR18 (
.VAR41 (VAR41),
.VAR13 (VAR13),
.VAR52 (VAR52),
.VAR37 (VAR24),
.VAR2 (1'b0),
.VAR6 (),
.VAR14 (1'b0),
.VAR43 (1'b1),
.VAR25 (),
.VAR39 (),
.VAR10... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4b/sky130_fd_sc_hd__nor4b.behavioral.pp.v | 1,988 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR4 ,
VAR2,
VAR8,
VAR11 ,
VAR10
);
output VAR12 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR4 ;
input VAR2;
input VAR8;
input VAR11 ;
input VAR10 ;
wire VAR14 ;
wire VAR9 ;
wire VAR5;
not VAR15 (VAR14 , VAR4 );
nor VAR17 (VAR9 , VAR7, VAR6, VAR3, VAR14 );
VAR13 VAR16... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/small_fifo_bb.v | 5,912 | module MODULE1 (
VAR4,
VAR5,
VAR1,
VAR7,
VAR2,
VAR9,
VAR3,
VAR8,
VAR6);
input VAR4;
input [71:0] VAR5;
input VAR1;
input VAR7;
input VAR2;
output VAR9;
output VAR3;
output [71:0] VAR8;
output [2:0] VAR6;
endmodule | mit |
amrmorsey/Digital-Design-Project | sbox6.v | 3,538 | module MODULE1(
VAR1,
VAR2
);
input [6:1] VAR1;
output reg [4:1] VAR2;
wire [6:1] VAR3;
assign VAR3 = {VAR1[6], VAR1[1], VAR1[5 : 2]};
always @(VAR3)
begin
case (VAR3)
6'b000000: VAR2 <= 4'd12;
6'b000001: VAR2 <= 4'd1;
6'b000010: VAR2 <= 4'd10;
6'b000011: VAR2 <= 4'd15;
6'b000100: VAR2 <= 4'd9;
6'b000101: VAR2 <= 4'd2;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2/sky130_fd_sc_hd__and2_0.v | 2,086 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR4 ,
VAR9,
VAR3,
VAR8 ,
VAR1
);
output VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR9;
input VAR3;
input VAR8 ;
input VAR1 ;
VAR2 VAR6 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7,
VAR5,
VAR4
);
output VAR7;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai.symbol.v | 1,394 | module MODULE1 (
input VAR8,
input VAR3,
input VAR7 ,
input VAR5 ,
output VAR6
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
jeichenhofer/chuck-light | SoC/ip/altsource_probe/hps_reset_bb.v | 3,070 | module MODULE1 (
VAR3,
VAR2,
VAR1);
input VAR3;
input VAR2;
output [2:0] VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp_8.v | 2,002 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR2 ,
VAR1,
VAR3
);
input VAR6 ;
input VAR4 ;
output VAR2 ;
input VAR1;
input VAR3;
VAR7 VAR5 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6 ,
VAR4,
VAR2
);
input VAR6 ;
input VAR4;
output VAR2 ;
supply1 VAR1;
supply0 VAR3;
VAR7 VAR5 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb.symbol.v | 1,339 | module MODULE1 (
input VAR8,
input VAR6,
input VAR4 ,
input VAR5 ,
output VAR3
);
supply1 VAR2;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
SymbiFlow/yosys | techlibs/xilinx/cells_map.v | 16,262 | module \VAR51 (input VAR87, input VAR109, input VAR6, output VAR45);
parameter VAR25 = 0;
parameter [VAR25-1:0] VAR68 = 0;
parameter VAR42 = 1;
parameter VAR39 = 2;
\VAR86 #(.VAR25(VAR25), .VAR68(VAR68), .VAR42(VAR42), .VAR39(VAR39)) VAR110 (.VAR87(VAR87), .VAR109(VAR109), .VAR44(VAR25-1), .VAR6(VAR6), .VAR45(VAR45));
... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fah/sky130_fd_sc_ls__fah.pp.blackbox.v | 1,308 | module MODULE1 (
VAR6,
VAR1 ,
VAR4 ,
VAR2 ,
VAR3 ,
VAR9,
VAR5,
VAR7 ,
VAR8
);
output VAR6;
output VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR9;
input VAR5;
input VAR7 ;
input VAR8 ;
endmodule | apache-2.0 |
ammelto/FPGAdventure | Adventure/HallwayLeft.v | 1,091 | module MODULE1(VAR5, VAR4, VAR3, VAR6, VAR1);
input VAR5;
input [9:0]VAR4;
input [8:0]VAR3;
input [7:0]VAR1;
output [7:0]VAR6;
reg [7:0]VAR2;
always @(posedge VAR5) begin
if(((VAR3 < 40) && (VAR4 < 260)) || ((VAR3 < 40) && ~(VAR4 < 380))) begin
VAR2[7:0] <= VAR1;
end
else if(VAR4 < 40)
VAR2[7:0] <= VAR1;
end
else if(~(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a_2.v | 2,339 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR4 ,
VAR3 ,
VAR1 ,
VAR7,
VAR11,
VAR10 ,
VAR2
);
output VAR5 ;
input VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR7;
input VAR11;
input VAR10 ;
input VAR2 ;
VAR9 VAR6 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR10(VAR10),
.... | apache-2.0 |
vvk/sysrek | martix_multiplier/multiplier.v | 1,748 | module MODULE1(
input clk,
input [12:0] VAR10,
input [12:0] VAR9,
output [26:0] VAR16,
output [26:0] VAR12
);
reg [12:0] VAR13 = 13'b1111111111110; reg [12:0] VAR11 = 13'b0000000100101; reg [12:0] VAR6 = 13'b0000000110010; reg [12:0] VAR2 = 13'b1111101001100;
wire [25:0] VAR14;
wire [25:0] VAR1;
wire[25:0] VAR17;
wire ... | gpl-2.0 |
DougFirErickson/parallella-hw | fpga/old/emaxi/hdl/syncfifo.v | 3,431 | module MODULE1
parameter VAR20 = 5,
parameter VAR7 = 16
)
(
input clk,
input reset,
input [VAR7-1:0] VAR26,
input VAR17,
input VAR29,
output wire [VAR7-1:0] VAR5,
output reg VAR16,
output reg VAR23
);
reg [VAR20-1:0] VAR15;
reg [VAR20-1:0] VAR10;
reg [VAR20-1:0] VAR27;
always @ ( posedge clk ) begin
if( reset ) begin
V... | gpl-3.0 |
jameshegarty/rigel | misc/lte_float32_float32_bool.v | 19,509 | module MODULE1 (
VAR56, VAR92, VAR177, out
);
parameter VAR250="VAR190";
input wire VAR56;
input wire VAR92;
input [63 : 0] VAR177;
output [0:0] out;
wire clk;
assign clk=VAR56;
wire [31:0] VAR146;
wire [31:0] VAR123;
wire [0:0] VAR153;
assign VAR146 = VAR177[31:0];
assign VAR123 = VAR177[63:32];
assign out = VAR153;
w... | mit |
jotego/jt12 | hdl/adpcm/jt10_adpcmb_interpol.v | 2,652 | module MODULE1(
input VAR18,
input clk,
input VAR28, input VAR17, input VAR9,
input signed [15:0] VAR4,
output signed [15:0] VAR27
);
localparam VAR25=6;
reg signed [15:0] VAR13, VAR15;
reg signed [16:0] VAR6;
reg VAR5=1'b0;
reg [3:0] VAR14, VAR26;
reg [VAR25-1:0] VAR24;
reg signed [15:0] VAR2;
wire [15:0] VAR21;
reg [... | gpl-3.0 |
ncos/Xilinx-Verilog | Donov-I/digital-display.v | 1,699 | module MODULE1(
input [15:0] VAR7,
input VAR6, output reg [7:0] VAR8,
output reg [3:0] select,
input clk
);
reg [31:0] VAR5;
wire [31:0] VAR9;
wire [31:0] VAR10;
always @(posedge clk)
begin
if (VAR6 == 1'b0) VAR5 <= VAR10;
if (VAR6 == 1'b1) VAR5 <= VAR9;
end
always @(posedge clk)
begin
select <= select << 1;
if (select... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o.behavioral.pp.v | 1,994 | module MODULE1 (
VAR6 ,
VAR13 ,
VAR15 ,
VAR5 ,
VAR10,
VAR14,
VAR4 ,
VAR1
);
output VAR6 ;
input VAR13 ;
input VAR15 ;
input VAR5 ;
input VAR10;
input VAR14;
input VAR4 ;
input VAR1 ;
wire VAR16 ;
wire VAR12 ;
wire VAR2;
and VAR7 (VAR16 , VAR13, VAR15 );
or VAR11 (VAR12 , VAR16, VAR5 );
VAR9 VAR3 (VAR2, VAR12, VAR10, VA... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_088.v | 1,528 | module MODULE1 (
VAR10,
VAR7
);
input [31:0] VAR10;
output [31:0]
VAR7;
wire [31:0]
VAR6,
VAR12,
VAR8,
VAR11,
VAR3,
VAR5,
VAR9,
VAR14,
VAR2;
assign VAR6 = VAR10;
assign VAR8 = VAR12 - VAR6;
assign VAR12 = VAR6 << 7;
assign VAR2 = VAR14 - VAR9;
assign VAR14 = VAR9 << 3;
assign VAR5 = VAR6 << 1;
assign VAR11 = VAR8 << 4;... | mit |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/mega/in_buf.v | 4,276 | module MODULE2
(
VAR8,
VAR13) ;
input [0:0] VAR8;
output [0:0] VAR13;
wire [0:0] VAR11;
VAR3 VAR9
(
.VAR5(VAR8),
.VAR14(VAR11[0:0])
,
.VAR1(1'b0),
.VAR6(1'b0)
);
VAR9.VAR10 = "false",
VAR9.VAR7 = "false",
VAR9.VAR12 = "VAR3";
assign
VAR13 = VAR11;
endmodule
module MODULE1 (
VAR8,
VAR13);
input [0:0] VAR8;
output [0:0]... | bsd-3-clause |
iDoka/GOST-28147-89 | rtl/gost28147.v | 3,536 | module MODULE1 (
input clk, input rst, input VAR4, input [255:0] VAR16, input [63:0] VAR9, input VAR14, output reg VAR27, output reg [63:0] VAR23, output reg VAR7, input VAR21 );
reg [1:0] state;
reg [1:0] VAR10;
localparam VAR24 = 2'b00,
VAR17 = 2'b01,
VAR18 = 2'b10;
always @(posedge clk) begin: VAR13
if (rst)
state <... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_CKINVDC_LVT_FF_210930.v | 11,786 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
not (VAR2, VAR1); | bsd-3-clause |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_hdmi_tx_int_n.v | 3,424 | module MODULE1 (
address,
VAR2,
clk,
VAR11,
VAR12,
VAR6,
VAR5,
irq,
VAR9
)
;
output irq;
output [ 31: 0] VAR9;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR11;
input VAR12;
input VAR6;
input [ 31: 0] VAR5;
wire VAR7;
reg VAR13;
reg VAR3;
wire VAR8;
reg VAR4;
wire VAR1;
wire VAR14;
wire irq;
reg VAR15;
wire VA... | gpl-3.0 |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/imports/NMOS/ALU.v | 2,250 | module MODULE1( clk, VAR11, VAR9, VAR19, VAR14, VAR15, VAR21, VAR12, VAR8, VAR5, VAR7, VAR20, VAR6, VAR23 );
input clk;
input VAR9;
input [3:0] VAR11; input [7:0] VAR19;
input [7:0] VAR14;
input VAR15;
input VAR12; output [7:0] VAR8;
output VAR21;
output VAR5;
output VAR7;
output VAR20;
output VAR6;
input VAR23;
reg [7... | gpl-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_in_ctl.v | 22,283 | module MODULE1 (
VAR137,
VAR124,
VAR87,
VAR13,
VAR27,
VAR121,
VAR5,
VAR4,
VAR72,
VAR120,
VAR123,
VAR89,
VAR16,
VAR92,
VAR103,
VAR83,
VAR19,
VAR18,
VAR142,
VAR52,
VAR111,
VAR21,
VAR25,
VAR38,
VAR146,
VAR53,
VAR35,
VAR10,
VAR11,
VAR15,
VAR76,
VAR66
);
input VAR137; input [123:118] VAR124; input [3:2] VAR87; input VAR13; ... | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/phy_pd.v | 23,431 | module MODULE1 #
(
parameter VAR23 = 100,
parameter VAR11 = "VAR48", parameter VAR64 = 16 )
(
output [99:0] VAR47, input [4:0] VAR78,
output [4:0] VAR44,
output reg VAR25, output reg VAR63, output VAR19, input VAR8, input VAR62,
input VAR51, input [1:0] VAR33, input VAR32,
input VAR58,
input VAR77, input VAR70, input V... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_039.v | 1,561 | module MODULE2 (
VAR12,
VAR9
);
input [31:0] VAR12;
output [31:0]
VAR9;
wire [31:0]
VAR13,
VAR2,
VAR3,
VAR7,
VAR1,
VAR8,
VAR5,
VAR4,
VAR15,
VAR14;
assign VAR13 = VAR12;
assign VAR4 = VAR3 << 4;
assign VAR15 = VAR5 - VAR4;
assign VAR5 = VAR1 - VAR8;
assign VAR1 = VAR7 - VAR3;
assign VAR7 = VAR3 << 11;
assign VAR14 = VAR... | mit |
alexforencich/xfcp | lib/eth/rtl/ssio_ddr_out_diff.v | 3,186 | module MODULE1 #
(
parameter VAR5 = "VAR3",
parameter VAR20 = "VAR25",
parameter VAR18 = "VAR9",
parameter VAR21 = 1
)
(
input wire clk,
input wire VAR28,
input wire [VAR21-1:0] VAR16,
input wire [VAR21-1:0] VAR33,
output wire VAR30,
output wire VAR13,
output wire [VAR21-1:0] VAR23,
output wire [VAR21-1:0] VAR17
);
wir... | mit |
mlab/pvs | hdl_harness/light_up.v | 2,496 | module MODULE1
(
clk,
VAR2,
counter,
VAR7,
VAR18,
VAR20
);
input clk;
input[7:0] VAR2;
input[31:0] counter;
output VAR7;
output VAR18;
output VAR20;
parameter VAR17 = 32'd750; parameter VAR4 = 32'd1800; parameter VAR5 = 8'd4; parameter VAR3 = 8'd6;
reg VAR16;
reg VAR15;
reg[31:0] VAR9;
wire[31:0] VAR14;
wire VAR6;
wire... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_p/sky130_fd_sc_ms__udp_dff_p.blackbox.v | 1,202 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR1 ;
input VAR2;
endmodule | apache-2.0 |
sirchuckalot/zet-ng | rtl/zet_front_prefetch_wb.v | 5,219 | module MODULE1 (
input VAR24,
input VAR8,
input [15:0] VAR4,
output [19:1] VAR23,
output [ 1:0] VAR22,
output VAR11,
output VAR3,
input VAR10,
input VAR6,
input VAR2,
input [15:0] VAR9,
input [15:0] VAR20,
output reg [15:0] VAR21,
output reg [15:0] VAR5,
output reg [15:0] VAR7,
output reg VAR19,
input VAR17
);
wire VAR... | gpl-3.0 |
Canaan-Creative/MM | verilog/superkdf9/components/uart_core/txmitt.v | 19,154 | module MODULE1 #(parameter VAR12 = 8,
parameter VAR44 = 0)
(
reset, clk,
VAR31, VAR23, VAR18, VAR19, VAR24,
VAR35,
VAR28,
VAR37,
VAR41,
VAR3, VAR11,
VAR8,
VAR4,
VAR25,
VAR34);
input reset ;
input clk ;
input [VAR12-1 :0] VAR31;
input VAR23 ;
input [1:0] VAR19;
input [1:0] VAR24;
input VAR35;
input VAR28 ;
input VAR37;
... | unlicense |
alan4186/ParCNN | Hardware/v/shifting_window.v | 2,902 | module MODULE1(
input VAR21,
input reset,
input VAR25, input VAR6, input [VAR23:0] VAR15,
output [VAR9:0] VAR19
);
wire [VAR23:0] VAR3 [VAR12:0][VAR24:0];
genvar VAR22;
genvar VAR14;
generate
for(VAR14=1;VAR14 < VAR20; VAR14=VAR14+1) begin : VAR17
for(VAR22=0; VAR22 < VAR11; VAR22=VAR22+1) begin : VAR5
MODULE2 MODULE3(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp.pp.symbol.v | 1,460 | module MODULE1 (
input VAR7 ,
output VAR1 ,
input VAR4 ,
input VAR3 ,
input VAR8 ,
input VAR2 ,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/syn/v/bsg_mem_1rw_sync_mask_write_byte.v | 4,001 | if (VAR7 == VAR34 && VAR2 == VAR20) \
begin: VAR23 \
VAR19 \
VAR36 \
(.VAR5 (VAR5) \
,.VAR28 (VAR28) \
,.VAR8 (VAR8) \
,.VAR4 (VAR4) \
,.VAR31 (VAR31) \
,.VAR15 (VAR15) \
,.VAR12 (VAR12) \
,.VAR13 (VAR13) \
); \
end: VAR23
if (VAR7 == VAR34 && VAR2 == VAR20) begin: VAR23 \
VAR16 #( \
.VAR2(VAR2) \
,.VAR7(VAR7) \
,.VAR3... | bsd-3-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets.v | 7,502 | module MODULE1
parameter VAR3 = 0 )
(
input clk,
input VAR19,
input VAR6,
output reg VAR11,
output reg [7: 0] VAR7,
output reg [VAR1-1: 0] VAR13,
output reg VAR2,
output reg VAR10,
output reg VAR15,
input VAR8,
input [7: 0] VAR16
);
reg VAR17, VAR21, VAR14;
wire VAR4, VAR18, VAR12, VAR9, VAR20;
wire [7:0] VAR5;
assign ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.symbol.v | 1,360 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/rtc.v | 10,743 | module MODULE1 (
input VAR33,
input VAR23,
input [55:0] VAR37,
input VAR30,
input [59:0] VAR46,
output [59:0] VAR21
);
reg [59:0] VAR22;
reg [59:0] VAR17;
reg [1:0] VAR8;
always @(posedge VAR33) VAR8 <= {VAR8[0], VAR23};
wire VAR14 = (VAR8[1:0] == 2'b01);
reg [2:0] VAR9;
always @(posedge VAR33) VAR9 <= {VAR9[1:0], VAR3... | gpl-2.0 |
P3Stor/P3Stor | DDR3/ip_top/iodelay_ctrl.v | 7,589 | module MODULE1 #
(
parameter VAR17 = 100, parameter VAR16 = "VAR26", parameter VAR14 = "VAR7", parameter VAR28 = 1 )
(
input VAR32,
input VAR2,
input VAR27,
input VAR23,
output VAR34
);
localparam VAR11 = 15;
wire VAR25;
wire VAR1;
wire VAR15;
reg [VAR11-1:0] VAR21 ;
wire VAR37;
wire VAR30;
assign VAR30 = VAR28 ? ~VAR2... | gpl-2.0 |
hoglet67/CoPro6502 | src/amber23/a23_barrel_shift_fpga.v | 10,836 | module MODULE1 (
input [31:0] VAR24,
input VAR29,
input [7:0] VAR31, input VAR25, input [1:0] VAR3,
output [31:0] VAR8,
output VAR10
);
wire [31:0] VAR13;
wire [1:0] VAR39; wire [1:0] VAR35; wire [1:0] VAR15; wire [1:0] VAR21;
reg [32:0] VAR4; reg [32:0] VAR32; reg [15:0] VAR5;
reg [4:0] VAR16;
reg [2:0] VAR22; reg [2:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dlatch_pr/sky130_fd_sc_hvl__udp_dlatch_pr.symbol.v | 1,364 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
alankarkotwal/lca-processor | pipeline/mem_access.v | 2,656 | module MODULE2(VAR49, VAR40, VAR50, VAR34, VAR13, VAR31, VAR60, VAR2, VAR5, VAR15, VAR24
, VAR45, VAR14, VAR11, VAR37);
output [15:0] VAR60, VAR15;
wire [15:0] VAR42;
input [15:0] VAR34, VAR50, VAR45, VAR14, VAR24, , VAR40, VAR49;
input VAR13, VAR31, VAR5, VAR2, VAR11, VAR37;
wire [15:0] VAR35, VAR57, VAR38;
VAR51 VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.symbol.v | 1,211 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3b/sky130_fd_sc_ms__and3b.blackbox.v | 1,295 | module MODULE1 (
VAR4 ,
VAR8,
VAR1 ,
VAR5
);
output VAR4 ;
input VAR8;
input VAR1 ;
input VAR5 ;
supply1 VAR6;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
ychaim/FPGA-Litecoin-Miner | ICARUS-LX150/hub_core.v | 2,270 | module MODULE1 (VAR4, VAR7, VAR2, VAR13, VAR1, VAR14);
parameter VAR8 = 2;
input VAR4;
input [VAR8-1:0] VAR7;
input [VAR8*32-1:0] VAR14;
output [31:0] VAR2;
output VAR13;
input VAR1;
reg VAR12 = 0;
assign VAR13 = VAR12;
reg [VAR8-1:0] VAR10 = 0;
function integer VAR5; input integer VAR9;
begin
VAR9 = VAR9-1;
for (VAR5=... | gpl-3.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/z80/zkbdmus.v | 2,371 | module MODULE1(
input wire VAR4,
input wire VAR18,
input wire [39:0] VAR11, input wire VAR13,
input wire [ 7:0] VAR15,
input wire VAR1,
input wire VAR5,
input wire VAR12,
input wire VAR6,
input wire [7:0] VAR17,
output wire [ 4:0] VAR8,
output wire [ 7:0] VAR2,
output reg [ 4:0] VAR19
);
reg [39:0] VAR3;
reg [ 7:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp.behavioral.pp.v | 2,453 | module MODULE1 (
VAR4 ,
VAR27 ,
VAR10 ,
VAR11 ,
VAR6,
VAR16,
VAR2,
VAR13 ,
VAR14
);
output VAR4 ;
input VAR27 ;
input VAR10 ;
input VAR11 ;
input VAR6;
input VAR16;
input VAR2;
input VAR13 ;
input VAR14 ;
wire VAR9 ;
wire VAR19;
wire VAR5 ;
wire VAR18 ;
wire VAR22 ;
wire VAR25 ;
wire VAR7 ;
wire VAR3 ;
reg VAR12 ;
wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18.functional.pp.v | 1,866 | module MODULE1 (
VAR11 ,
VAR1 ,
VAR6,
VAR5,
VAR4 ,
VAR7
);
output VAR11 ;
input VAR1 ;
input VAR6;
input VAR5;
input VAR4 ;
input VAR7 ;
wire VAR10 ;
wire VAR12;
buf VAR8 (VAR10 , VAR1 );
VAR3 VAR2 (VAR12, VAR10, VAR6, VAR5);
buf VAR9 (VAR11 , VAR12 );
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/RegGPR.v | 2,091 | module MODULE1(
VAR12, reset,
VAR9, VAR1,
VAR17, VAR7,
VAR16, VAR15,
VAR11, VAR3,
VAR5);
input VAR12;
input reset;
input[6:0] VAR9;
input[6:0] VAR17;
input[6:0] VAR16;
input[6:0] VAR11;
output[31:0] VAR1;
output[31:0] VAR7;
output[31:0] VAR15;
input[31:0] VAR3;
input[31:0] VAR5;
reg VAR14;
reg[31:0] VAR13;
reg[31:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd/sky130_fd_sc_hd__tapvgnd.behavioral.v | 1,193 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4/sky130_fd_sc_hd__and4_4.v | 2,242 | module MODULE2 (
VAR2 ,
VAR11 ,
VAR10 ,
VAR1 ,
VAR4 ,
VAR5,
VAR6,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR11 ;
input VAR10 ;
input VAR1 ;
input VAR4 ;
input VAR5;
input VAR6;
input VAR7 ;
input VAR3 ;
VAR8 VAR9 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.... | apache-2.0 |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/synth/ZynqDesign_xbar_1.v | 14,552 | module MODULE1 (
VAR75,
VAR72,
VAR100,
VAR102,
VAR16,
VAR79,
VAR124,
VAR56,
VAR119,
VAR78,
VAR51,
VAR15,
VAR89,
VAR104,
VAR88,
VAR127,
VAR2,
VAR123,
VAR98,
VAR7,
VAR45,
VAR95,
VAR122,
VAR87,
VAR38,
VAR37,
VAR10,
VAR65,
VAR63,
VAR86,
VAR108,
VAR12,
VAR97,
VAR52,
VAR66,
VAR21,
VAR126,
VAR58,
VAR70,
VAR35
);
input wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fa/sky130_fd_sc_lp__fa.pp.symbol.v | 1,286 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR4 ,
output VAR7,
output VAR1 ,
input VAR9 ,
input VAR2,
input VAR5,
input VAR8
);
endmodule | apache-2.0 |
olajep/oh | src/aes/hdl/aes_192.v | 6,013 | module MODULE3 (clk, state, VAR40, out);
input clk;
input [127:0] state;
input [191:0] VAR40;
output [127:0] out;
reg [127:0] VAR61;
reg [191:0] VAR54;
wire [127:0] VAR69, VAR4, VAR50, VAR8, VAR47, VAR18, VAR41, VAR2, VAR29, VAR55, VAR67;
wire [191:0] VAR78, VAR38, VAR37, VAR51, VAR28, VAR7, VAR70, VAR63, VAR22, VAR14,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp.behavioral.v | 2,508 | module MODULE1 (
VAR4 ,
VAR15 ,
VAR10 ,
VAR14 ,
VAR19 ,
VAR11 ,
VAR16,
VAR7
);
output VAR4 ;
input VAR15 ;
input VAR10 ;
input VAR14 ;
input VAR19 ;
input VAR11 ;
input VAR16;
input VAR7;
wire VAR12 ;
reg VAR22 ;
wire VAR8 ;
wire VAR1 ;
wire VAR18;
wire VAR23;
wire VAR20;
wire VAR25 ;
wire VAR5 ;
wire VAR9 ;
wire VAR21... | apache-2.0 |
lloves/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_count_to_128.v | 2,166 | module MODULE1(clk, rst, VAR2, VAR3, VAR4);
input clk, rst, VAR2, VAR3;
output [6:0] VAR4;
wire [6:0] VAR1;
reg [6:0] VAR4;
always@(posedge clk or posedge rst)
begin
if(rst == 1'b1)
VAR4 = 7'h00;
end
else
begin
case({VAR2,VAR3})
2'b00: VAR4 = 7'h00;
2'b01: VAR4 = VAR1;
2'b10: VAR4 = VAR1 - 1;
2'b11: VAR4 = VAR1 + 1;
de... | bsd-2-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/spree/tmp/mul_1.v | 1,584 | module MODULE1 (clk, VAR15,
VAR2, VAR3,
VAR9, VAR13, VAR1);
parameter VAR11=32;
input clk;
input VAR15;
input [VAR11-1:0] VAR2;
input [VAR11-1:0] VAR3;
input VAR9;
output [VAR11-1:0] VAR13;
output [VAR11-1:0] VAR1;
wire VAR8;
assign VAR8=VAR9;
wire VAR5,VAR6;
VAR17 VAR12 (
.VAR14 (~VAR15),
.VAR7 (1'b1),
.clk (clk),
.VA... | mit |
Gilberto-Lopez/Arquitectura-Computadoras | Practica2/compm4.v | 1,064 | module MODULE1(
input VAR10,
input VAR4,
input VAR3,
input VAR7,
input VAR5,
input VAR1,
input VAR8,
input VAR2,
output VAR9,
output VAR6
);
assign VAR9 = {VAR7,VAR3,VAR4,VAR10} > {VAR2,VAR8,VAR1,VAR5};
assign VAR6 = {VAR7,VAR3,VAR4,VAR10} < {VAR2,VAR8,VAR1,VAR5};
endmodule | lgpl-3.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/4-memory/data_access.v | 2,654 | module MODULE1
parameter VAR27=32, parameter VAR7=5 )
(
input wire clk,
input wire [VAR27-1:0] VAR33,
input wire [VAR27-1:0] VAR3,
input wire [5:0] VAR18,
input wire VAR26,
output wire [VAR27-1:0] VAR37
);
wire [3:0] VAR41;
assign VAR41[3]=VAR26;
assign VAR41[2]=VAR26;
assign VAR41[1]=VAR26;
assign VAR41[0]=VAR26;
wire... | gpl-3.0 |
secworks/aes | src/rtl/aes_decipher_block.v | 15,524 | module MODULE1(
input wire clk,
input wire VAR89,
input wire VAR45,
input wire VAR41,
output wire [3 : 0] VAR26,
input wire [127 : 0] VAR80,
input wire [127 : 0] VAR63,
output wire [127 : 0] VAR31,
output wire ready
);
localparam VAR28 = 1'h0;
localparam VAR84 = 1'h1;
localparam VAR21 = 4'ha;
localparam VAR66 = 4'he;
l... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211a/sky130_fd_sc_hdll__o211a_4.v | 2,364 | module MODULE2 (
VAR10 ,
VAR5 ,
VAR11 ,
VAR3 ,
VAR9 ,
VAR7,
VAR8,
VAR4 ,
VAR6
);
output VAR10 ;
input VAR5 ;
input VAR11 ;
input VAR3 ;
input VAR9 ;
input VAR7;
input VAR8;
input VAR4 ;
input VAR6 ;
VAR2 VAR1 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf.functional.v | 1,245 | module MODULE1 (
VAR4,
VAR5
);
output VAR4;
input VAR5;
wire VAR1;
buf VAR2 (VAR1, VAR5 );
buf VAR3 (VAR4 , VAR1 );
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_pipe_eq.v | 35,625 | module MODULE1 #
(
parameter VAR77 = "VAR48",
parameter VAR106 = "VAR61",
parameter VAR53 = 1
)
(
input VAR17,
input VAR92,
input VAR42,
input [ 1:0] VAR27,
input [ 3:0] VAR109,
input [ 3:0] VAR2,
input [ 5:0] VAR4,
input [ 1:0] VAR29,
input [ 2:0] VAR72,
input [ 5:0] VAR95,
input [ 3:0] VAR1,
input VAR134,
input [17:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b_1.v | 2,163 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR4 ,
VAR6,
VAR8,
VAR2 ,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR4 ;
input VAR6;
input VAR8;
input VAR2 ;
input VAR5 ;
VAR7 VAR9 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR3 ,
VAR1,
VAR4
);
output VAR3 ... | apache-2.0 |
subleleks/hardware | mem.v | 7,168 | module MODULE1 (
address,
VAR49,
VAR22,
VAR7,
VAR51);
input [12:0] address;
input VAR49;
input [31:0] VAR22;
input VAR7;
output [31:0] VAR51;
tri1 VAR49;
wire [31:0] VAR54;
wire [31:0] VAR51 = VAR54[31:0];
VAR5 VAR47 (
.VAR1 (address),
.VAR12 (VAR49),
.VAR8 (VAR22),
.VAR11 (VAR7),
.VAR41 (VAR54),
.VAR20 (1'b0),
.VAR9 (... | mit |
xuefei1/ElectronicEngineControl | niosII_system/synthesis/submodules/niosII_system_nios2_0_jtag_debug_module_tck.v | 8,395 | module MODULE1 (
VAR36,
VAR20,
VAR30,
VAR27,
VAR29,
VAR21,
VAR40,
VAR7,
VAR6,
VAR28,
VAR4,
VAR9,
VAR11,
VAR24,
VAR33,
VAR2,
VAR3,
VAR12,
VAR13,
VAR10,
VAR18,
VAR25,
VAR19,
VAR8,
VAR5,
VAR32,
VAR31,
VAR1,
VAR26,
VAR22,
VAR39
)
;
output [ 1: 0] VAR31;
output VAR1;
output [ 37: 0] VAR26;
output VAR22;
output VAR39;
input ... | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/mips/Mult.v | 1,368 | module MODULE1
(
clk,
rst,
VAR9,
VAR11,
VAR4,
VAR8
);
input clk;
input rst;
input [31:0] VAR9;
input [31:0] VAR11;
input [3:0] VAR4;
output reg [31:0] VAR8;
reg[31:0] VAR2,VAR5;
reg VAR7,VAR3;
reg[2:0] VAR6;
wire signed[31:0] VAR10,VAR1;
assign VAR10=VAR9;
assign VAR1=VAR11;
always@(*)
begin
VAR8<=0;
VAR7<=0;
VAR3<=0;
... | gpl-3.0 |
joaocarlos/udlx-verilog | rtl/write_back/write_back.v | 2,455 | module MODULE1
parameter VAR5 = 32,
parameter VAR14 = 5
)
(
input [VAR5-1:0] VAR4,
input [VAR5-1:0] VAR9,
input [VAR5-1:0] VAR16,
input [VAR14-1:0] VAR3,
input [VAR14-1:0] VAR10,
input VAR7,
input VAR6,
input VAR15,
output [VAR14-1:0] VAR11,
output [VAR14-1:0] VAR8,
output [VAR5-1:0] VAR12,
output [VAR5-1:0] VAR2,
outp... | lgpl-3.0 |
alexforencich/hdg2000 | fpga/lib/wb/rtl/wb_reg.v | 4,971 | module MODULE1 #
(
parameter VAR19 = 32, parameter VAR22 = 32, parameter VAR13 = (VAR19/8) )
(
input wire clk,
input wire rst,
input wire [VAR22-1:0] VAR1, input wire [VAR19-1:0] VAR18, output wire [VAR19-1:0] VAR23, input wire VAR27, input wire [VAR13-1:0] VAR2, input wire VAR31, output wire VAR28, output wire VAR14, ... | mit |
hwstar/bdcmotor | pwm8.v | 6,483 | module MODULE4(
output [7:0] VAR14,
input clk,
input VAR22);
reg [7:0] counter = 0;
assign VAR14 = counter;
always @(posedge clk) begin
if(VAR22) begin
counter <= counter + 1;
end
end
endmodule
module MODULE3(
output [7:0] VAR10,
input clk,
input VAR5,
input [7:0] VAR6);
reg [7:0] VAR28 = 8'h00;
assign VAR10 = VAR28;
a... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv_lp.v | 2,044 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR3,
VAR2,
VAR1 ,
VAR5
);
output VAR4 ;
input VAR6 ;
input VAR3;
input VAR2;
input VAR1 ;
input VAR5 ;
VAR8 VAR7 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR3;
supply0 VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311ai/sky130_fd_sc_hd__o311ai.pp.blackbox.v | 1,414 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR7 ,
VAR1 ,
VAR8 ,
VAR4 ,
VAR3,
VAR6,
VAR10 ,
VAR9
);
output VAR5 ;
input VAR2 ;
input VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR3;
input VAR6;
input VAR10 ;
input VAR9 ;
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_top.v | 26,563 | module MODULE1(
VAR203, VAR66, VAR309, VAR400,
VAR69, VAR37, VAR128, VAR311, VAR275, VAR125,
VAR162, VAR198, VAR280, VAR22, VAR334, VAR6,
VAR337,
VAR243, VAR340,
VAR287, VAR224, VAR210, VAR64, VAR62, VAR326,
VAR123, VAR86, VAR202, VAR346, VAR291, VAR83,
VAR399,
VAR137, VAR145,
VAR251, VAR25, VAR368, VAR161, VAR279, VAR... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_fpu_post_norm_addsub.v | 9,602 | module MODULE1
(
VAR49,
VAR4,
VAR36,
VAR22,
VAR34,
VAR12,
VAR30,
VAR17,
VAR26,
VAR41
);
parameter VAR31 = 32;
parameter VAR38 = 0; parameter VAR45 = 11; parameter VAR25 = 23;
parameter VAR21 = 8;
parameter VAR19 = 31'd0;
parameter VAR35 = 31'b1111111100000000000000000000000;
parameter VAR44 = 31'b1111111110000000000000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21a/sky130_fd_sc_hs__o21a.functional.v | 1,917 | module MODULE1 (
VAR9,
VAR12,
VAR2 ,
VAR1 ,
VAR8 ,
VAR10
);
input VAR9;
input VAR12;
output VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR10 ;
wire VAR3 ;
wire VAR5 ;
wire VAR6;
or VAR14 (VAR3 , VAR8, VAR1 );
and VAR11 (VAR5 , VAR3, VAR10 );
VAR7 VAR13 (VAR6, VAR5, VAR9, VAR12);
buf VAR4 (VAR2 , VAR6 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_tag.v | 14,689 | module MODULE1(
VAR111,
clk, VAR6, VAR108, VAR29, VAR37, VAR68,
VAR50, VAR21, VAR102, VAR55, VAR36, VAR75
);
input clk;
input VAR6;
input VAR108;
input VAR29;
input VAR37;
input VAR68;
input [VAR91-1:0] VAR50;
input VAR21;
input [VAR91-1:0] VAR102;
input VAR55;
input [3:0] VAR36;
input [3:0] VAR75;
output VAR111;
wire ... | gpl-2.0 |
cpulabs/mist1032sa | src/dps/device/utim64/comparator_counter.v | 2,417 | module MODULE1(
input wire VAR16,
input wire VAR1,
input wire VAR7,
input wire [63:0] VAR13,
input wire VAR14,
input wire VAR8,
input wire VAR12,
input wire VAR6,
input wire VAR3, input wire VAR5,
input wire [1:0] VAR15,
input wire [63:0] VAR17,
output wire VAR4
);
reg enable;
reg VAR10;
reg [63:0] VAR2;
reg [63:0] cou... | bsd-2-clause |
chenm001/x266 | lib/smul.v | 1,554 | module MODULE1(VAR5, VAR2, VAR1);
parameter VAR4 = 1;
parameter VAR3 = 1;
input [VAR4-1:0] VAR5;
input [VAR3-1:0] VAR2;
output [VAR4+VAR3-2:0] VAR1;
assign VAR1 = (VAR5) * (VAR2);
endmodule | bsd-2-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_upack/util_upack_dsf.v | 8,576 | module MODULE1 (
VAR32,
VAR28,
VAR14,
VAR3,
VAR9,
VAR27,
VAR17);
parameter VAR13 = 4;
parameter VAR22 = 8;
parameter VAR16 = 32;
parameter VAR26 = 4;
localparam VAR25 = VAR16/16;
localparam VAR15 = VAR16*VAR13;
localparam VAR5 = VAR16*VAR22;
localparam VAR29 = VAR16*VAR26;
localparam VAR2 = VAR16*(VAR22+1);
localparam ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b_2.v | 2,173 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR4 ,
VAR5,
VAR9,
VAR1 ,
VAR7
);
output VAR3 ;
input VAR8 ;
input VAR4 ;
input VAR5;
input VAR9;
input VAR1 ;
input VAR7 ;
VAR6 VAR2 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3 ,
VAR8 ,
VAR4
);
output VAR3... | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/emmu/dv/dv_emmu.v | 4,437 | module MODULE1
(input clk,
input reset,
input VAR2);
parameter VAR1 = 32; parameter VAR23 = 32; parameter VAR7 = 12; parameter VAR11 = 64; parameter VAR4 = VAR11-VAR23+VAR7; parameter VAR5 = 1<<VAR7;
reg VAR20;
reg VAR10;
reg [12:0] VAR31;
reg [31:0] VAR26;
reg [3:0] VAR28;
reg VAR8;
reg VAR29;
reg [1:0] VAR13;
reg [3:... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_hdmi_tx/axi_hdmi_tx_core.v | 18,040 | module MODULE1 (
VAR103,
VAR52,
VAR102,
VAR12,
VAR54,
VAR14,
VAR133,
VAR81,
VAR31,
VAR117,
VAR36,
VAR78,
VAR79,
VAR2,
VAR118,
VAR10,
VAR139,
VAR48,
VAR120,
VAR132,
VAR25,
VAR131,
VAR97,
VAR90,
VAR127,
VAR76,
VAR101,
VAR74,
VAR138,
VAR5,
VAR53,
VAR18,
VAR35,
VAR119,
VAR39,
VAR11,
VAR91,
VAR125,
VAR98,
VAR77);
parameter ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.symbol.v | 1,413 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR4 ,
input VAR1,
input VAR3 ,
input VAR5
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/controller/arb_select.v | 19,073 | module MODULE1 #
(
parameter VAR98 = 100,
parameter VAR122 = "VAR1",
parameter VAR128 = 11,
parameter VAR38 = 3,
parameter VAR47 = "8",
parameter VAR17 = 4,
parameter VAR56 = 31,
parameter VAR126 = 8,
parameter VAR81 = "VAR11",
parameter VAR120 = "VAR66",
parameter VAR129 = "VAR66",
parameter VAR86 = 4,
parameter VAR4 ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_1.v | 2,411 | module MODULE2 (
VAR2 ,
VAR9,
VAR10,
VAR11 ,
VAR3 ,
VAR8,
VAR6,
VAR7 ,
VAR5
);
output VAR2 ;
input VAR9;
input VAR10;
input VAR11 ;
input VAR3 ;
input VAR8;
input VAR6;
input VAR7 ;
input VAR5 ;
VAR1 VAR4 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_051.v | 1,517 | module MODULE1 (
VAR7,
VAR9
);
input [31:0] VAR7;
output [31:0]
VAR9;
wire [31:0]
VAR13,
VAR14,
VAR6,
VAR4,
VAR3,
VAR2,
VAR11,
VAR10,
VAR1;
assign VAR13 = VAR7;
assign VAR10 = VAR13 << 10;
assign VAR2 = VAR6 << 3;
assign VAR14 = VAR13 << 5;
assign VAR6 = VAR13 + VAR14;
assign VAR1 = VAR11 - VAR10;
assign VAR4 = VAR13 <... | mit |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ok/okWireIn_sync.v | 2,005 | module MODULE1 (
input wire clk,
input wire VAR8,
input wire [112:0] VAR13,
input wire [7:0] VAR12,
output reg [31:0] VAR2
);
wire [31:0] VAR3;
wire [31:0] VAR11;
wire VAR17;
reg VAR1;
always @( posedge clk ) begin
if ( VAR1 ) begin
VAR2 <= VAR11;
end
VAR1 <= ~VAR17;
end
VAR7 VAR16 (
.VAR9 ( VAR3 ),
.VAR18 ( clk ),
.VA... | gpl-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/AmpTrig.v | 2,284 | module MODULE1(
input clk,
input VAR13,
input VAR7,
input [6:0] VAR10,
output reg VAR3 = 1'b0
);
parameter VAR12 = 5'd26;
reg VAR1 = 1'b0, VAR15 = 1'b0, VAR8 = 1'b0, VAR6 = 1'b0, VAR5 = 1'b0;reg VAR14 = 1'b0;
reg [6:0] VAR11 = 7'd0, VAR4 = 7'd0;
reg [6:0] VAR2 = 7'd0;
reg [4:0] VAR9 = 5'd0;
always @(posedge clk) begin
... | gpl-3.0 |
alexforencich/verilog-ethernet | example/ZCU106/fpga/rtl/fpga.v | 9,156 | module MODULE1 (
input wire VAR100,
input wire VAR97,
input wire reset,
input wire VAR82,
input wire VAR61,
input wire VAR162,
input wire VAR150,
input wire VAR171,
input wire [7:0] VAR11,
output wire [7:0] VAR38,
input wire VAR79,
output wire VAR27,
input wire VAR40,
output wire VAR151,
input wire VAR56,
input wire VA... | mit |
zhangly/azpr_cpu | rtl/cpu/rtl/mem_ctrl.v | 2,624 | module MODULE1 (
input wire VAR22, input wire [VAR21] VAR13, input wire [VAR8] VAR20, input wire [VAR8] VAR19,
input wire [VAR8] VAR18, output wire [VAR6] addr, output reg VAR15, output reg VAR7, output wire [VAR8] VAR3,
output reg [VAR8] out , output reg VAR10 );
wire [VAR2] VAR4;
assign VAR3 = VAR20; assign addr = VA... | mit |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/nios_altmemddr_0_phy_alt_mem_phy_pll.v | 22,778 | module MODULE1 (
VAR34,
VAR82,
VAR116,
VAR73,
VAR78,
VAR54,
VAR55,
VAR18,
VAR102,
VAR31,
VAR59,
VAR51,
VAR2);
input VAR34;
input VAR82;
input [2:0] VAR116;
input VAR73;
input VAR78;
input VAR54;
output VAR55;
output VAR18;
output VAR102;
output VAR31;
output VAR59;
output VAR51;
output VAR2;
tri0 VAR34;
tri0 [2:0] VAR1... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/c2i/rtl/c2i_fctrl.v | 23,557 | module MODULE1 (
VAR145, VAR59, VAR132,
VAR76, VAR133,
VAR68, VAR144, VAR52,
VAR81, VAR107, VAR48,
VAR84, VAR42, VAR18,
VAR58, VAR101, VAR20,
VAR43, VAR2, VAR142,
VAR28, VAR152, VAR147,
VAR103, VAR9, VAR49,
VAR74, VAR141, VAR66,
VAR61, VAR27, VAR24, VAR15, VAR89,
VAR63, VAR100, VAR105, VAR110,
VAR108, VAR70, VAR75,
VAR... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/terasic/src/gen_reset_n.v | 3,317 | module MODULE1(
VAR1,
VAR4,
VAR3
);
parameter VAR2 = 20;
input VAR1;
input VAR4;
output VAR3;
reg VAR3;
reg [VAR2-1:0] VAR5;
always @(posedge VAR1 or negedge VAR4)
begin
if (!VAR4)
begin
VAR3 <= 0;
VAR5 <= 0;
end else begin
if (VAR5 == {VAR2{1'b1}})
begin
VAR3 <= 1'b1; end else begin
VAR5 <= VAR5 + 1;
VAR3 <= 0;
end
en... | mit |
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