repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
theapi/nand2tetris_fpga | hack/rtl/verilog/vga_driver.v | 3,840 | module MODULE1
(
VAR16,
VAR2,
VAR19,
VAR3,
VAR6,
VAR11,
VAR9,
VAR8,
VAR1,
VAR12
);
input VAR16;
input VAR2;
input [2:0] VAR19; output [10:0] VAR3;
output [10:0] VAR6;
output VAR11;
output VAR9;
output VAR8;
output VAR1;
output VAR12;
reg [10:0] VAR7; reg [10:0] VAR5; reg VAR4;
wire VAR14 = (VAR7 == 975);
reg [9:0] VAR1... | mit |
cpulabs/mist1032sa | src/mist1032sa.v | 19,691 | module MODULE1(
input wire VAR167,
input wire VAR106,
input wire VAR204,
input wire VAR42,
input wire VAR199,
output wire VAR157,
input wire VAR258,
output wire VAR78,
input wire VAR47,
output wire [1:0] VAR56, output wire [3:0] VAR262,
output wire VAR6, output wire [31:0] VAR162,
output wire [31:0] VAR52,
input wire V... | bsd-2-clause |
drom/pulsar | src/pulsar.v | 1,259 | module MODULE1 (clk, VAR2);
input clk ;
output VAR2 ;
reg [31:0] VAR6; reg [31:0] VAR3 [0:255]; reg [31:0] VAR1;
reg [31:0] VAR8;
reg [7:0] VAR4; reg VAR7; reg VAR5; | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,103 | module MODULE1 (
clk,
VAR7,
VAR26,
VAR13,
VAR28,
VAR12,
VAR8,
VAR1,
VAR30,
VAR2,
VAR17,
VAR4,
VAR21,
VAR27,
VAR22,
VAR29
)
;
output [ 37: 0] VAR12;
output VAR8;
output VAR1;
output VAR30;
output VAR2;
output VAR17;
output VAR4;
output VAR21;
output VAR27;
output VAR22;
output VAR29;
input clk;
input [ 1: 0] VAR7;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3b/sky130_fd_sc_hd__or3b_2.v | 2,209 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR1 ,
VAR2 ,
VAR6,
VAR3,
VAR10 ,
VAR4
);
output VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR6;
input VAR3;
input VAR10 ;
input VAR4 ;
VAR9 VAR7 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/sys_pll/sys_pll.v | 17,407 | module MODULE1 (
input wire VAR1, input wire rst, output wire VAR5, output wire VAR2, output wire VAR3, output wire VAR7 );
VAR6 VAR4 (
.VAR1 (VAR1), .rst (rst), .VAR5 (VAR5), .VAR2 (VAR2), .VAR3 (VAR3), .VAR7 (VAR7) );
endmodule | gpl-3.0 |
hakehuang/pycpld | ips/ip/i2c_master_two_ad/I2C_MASTER.v | 2,843 | module MODULE1(clk,VAR10,VAR13,VAR14,VAR15,VAR11,VAR2,VAR3
);
input clk;
input VAR3;
input VAR10;
input VAR15;
input VAR11;
reg VAR5,VAR4;
output VAR14;
output VAR2;
inout VAR13;
reg VAR9;
reg VAR2;
reg[7:0] VAR19;
reg[7:0] VAR8;
wire[7:0] VAR1;
reg[7:0] VAR18;
wire ack;
reg[7:0] VAR17[31:0];
reg[7:0] VAR12[31:0];
alwa... | mit |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/start_for_Mat2AXIlbW.v | 3,003 | module MODULE1 (
clk,
VAR15,
VAR10,
VAR22,
VAR13);
parameter VAR20 = 32'd1;
parameter VAR26 = 32'd3;
parameter VAR7 = 32'd6;
input clk;
input [VAR20-1:0] VAR15;
input VAR10;
input [VAR26-1:0] VAR22;
output [VAR20-1:0] VAR13;
reg[VAR20-1:0] VAR24 [0:VAR7-1];
integer VAR19;
always @ (posedge clk)
begin
if (VAR10)
begin
f... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1.pp.symbol.v | 1,357 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR6 ,
input VAR1,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
m13253/riscade | hdl/src/step_ex_cpf.v | 1,493 | module MODULE1(clk, rst, VAR16, VAR7, VAR3,
VAR2, VAR13,
VAR11, VAR17, VAR9, VAR6, VAR15, VAR18, VAR4, VAR10);
input clk;
input rst;
input VAR16;
output VAR7;
input[3:0] VAR3;
output[7:0] VAR2;
output VAR13;
input[7:0] VAR11, VAR17, VAR9, VAR6, VAR15, VAR18, VAR4, VAR10;
reg VAR12;
assign VAR7 = VAR12 ? 1'b0 : 1'VAR5;
... | mit |
cybero/Verilog | src/UART + checker module/rtl/uart_rx.v | 2,479 | module MODULE1
parameter VAR18 = 8, VAR16 = 16 )
(
input wire clk,
input wire reset,
input wire VAR2,
input wire VAR4,
output reg VAR15,
output wire [7:0] VAR7
);
localparam [1:0]
VAR13 = 2'b00,
VAR3 = 2'b01,
VAR11 = 2'b10,
VAR9 = 2'b11;
reg [1:0] VAR1, VAR12;
reg [3:0] VAR17, VAR8;
reg [2:0] VAR5, VAR14;
reg [7:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o.pp.symbol.v | 1,401 | module MODULE1 (
input VAR8 ,
input VAR10 ,
input VAR2 ,
input VAR5 ,
input VAR6 ,
output VAR1 ,
input VAR3 ,
input VAR4,
input VAR7,
input VAR9
);
endmodule | apache-2.0 |
ultraembedded/riscv | top_tcm_axi/src_v/tcm_mem.v | 9,237 | module MODULE1
(
input VAR5
,input VAR34
,input VAR44
,input VAR61
,input VAR24
,input [ 31:0] VAR95
,input [ 31:0] VAR52
,input [ 31:0] VAR64
,input VAR47
,input [ 3:0] VAR15
,input VAR41
,input [ 10:0] VAR88
,input VAR92
,input VAR21
,input VAR65
,input VAR38
,input [ 31:0] VAR46
,input [ 3:0] VAR85
,input [ 7:0] VAR... | bsd-3-clause |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_sw.v | 4,325 | module MODULE1 (
address,
VAR13,
clk,
VAR3,
VAR4,
VAR7,
VAR10,
irq,
VAR15
)
;
output irq;
output [ 31: 0] VAR15;
input [ 1: 0] address;
input VAR13;
input clk;
input [ 3: 0] VAR3;
input VAR4;
input VAR7;
input [ 31: 0] VAR10;
wire VAR8;
reg [ 3: 0] VAR1;
reg [ 3: 0] VAR14;
wire [ 3: 0] VAR9;
reg [ 3: 0] VAR11;
wire VAR... | gpl-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/wb_fpga_nes.v | 18,587 | module MODULE1 (
input clk,
input rst,
input VAR129,
input VAR155,
input [3:0] VAR163,
input [31:0] VAR89,
input VAR147,
output reg VAR150,
output reg [31:0] VAR112,
input [31:0] VAR6,
output VAR131,
output VAR7,
output VAR37,
output [3:0] VAR132,
output [31:0] VAR110,
output [31:0] VAR74,
input [31:0] VAR13,
input VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf.behavioral.pp.v | 1,746 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR10,
VAR7,
VAR11 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR10;
input VAR7;
input VAR11 ;
input VAR2 ;
wire VAR3 ;
wire VAR9;
buf VAR4 (VAR3 , VAR5 );
VAR1 VAR12 (VAR9, VAR3, VAR10, VAR7);
buf VAR8 (VAR6 , VAR9 );
endmodule | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/pll.v | 15,698 | module MODULE1 (
VAR7,
VAR81,
VAR11,
VAR41);
input VAR7;
output VAR81;
output VAR11;
output VAR41;
wire [5:0] VAR69;
wire VAR74;
wire [0:0] VAR58 = 1'h0;
wire [1:1] VAR12 = VAR69[1:1];
wire [0:0] VAR52 = VAR69[0:0];
wire VAR81 = VAR52;
wire VAR11 = VAR12;
wire VAR41 = VAR74;
wire VAR54 = VAR7;
wire [1:0] VAR64 = {VAR58... | gpl-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/top/rtl/clk_gen.v | 1,540 | module MODULE1 (
input wire VAR5, input wire VAR9,
output wire clk, output wire clk,
output wire VAR8 );
wire VAR7; wire VAR11;
assign VAR11 = (VAR9 == VAR13) ? VAR1 : VAR3;
assign VAR8 = ((VAR9 == VAR13) || (VAR7 == VAR3)) ?
VAR12 VAR12 (
.VAR10 (VAR5), .VAR6 (VAR11), .VAR2 (clk), .VAR14 (clk), .VAR4 (VAR7) );
endmodu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfstp/sky130_fd_sc_lp__srsdfstp.blackbox.v | 1,520 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR6 ,
VAR1 ,
VAR11 ,
VAR4 ,
VAR5
);
output VAR12 ;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR11 ;
input VAR4 ;
input VAR5;
supply1 VAR2;
supply1 VAR3 ;
supply0 VAR8 ;
supply1 VAR10 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/sword_bb.v | 4,986 | module MODULE1 (
address,
VAR1,
VAR2);
input [14:0] address;
input VAR1;
output [15:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/top.v | 4,991 | module MODULE2 (
VAR41,
VAR47,
VAR16,
VAR54,
VAR31,
VAR28,
VAR5,
VAR17,
VAR35,
VAR3,
VAR25,
VAR40,
VAR43,
VAR52,
VAR38,
VAR62,
VAR57,
VAR13,
VAR21,
VAR42,
VAR65,
VAR36,
VAR70,
VAR53,
VAR60,
VAR56,
VAR4,
VAR69,
VAR39,
VAR63,
VAR58,
VAR10,
VAR14,
VAR55,
VAR9
);
input wire VAR41;
input wire VAR47;
output wire [3:0] VAR16;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxbp/sky130_fd_sc_hd__dfxbp.behavioral.v | 1,893 | module MODULE1 (
VAR3 ,
VAR9,
VAR4,
VAR2
);
output VAR3 ;
output VAR9;
input VAR4;
input VAR2 ;
supply1 VAR1;
supply0 VAR14;
supply1 VAR11 ;
supply0 VAR8 ;
wire VAR7 ;
reg VAR5 ;
wire VAR6 ;
wire VAR10;
wire VAR17 ;
VAR12 VAR15 (VAR7 , VAR6, VAR10, VAR5, VAR1, VAR14);
assign VAR17 = ( VAR1 === 1'b1 );
buf VAR16 (VAR3 ,... | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/oq_regs_host_iface.v | 6,300 | module MODULE1
parameter VAR27 = 13,
parameter VAR3 = 8,
parameter VAR26 = 2,
parameter VAR10 = 8,
parameter VAR21 = VAR28(VAR10),
parameter VAR14 = 17,
parameter VAR34 = VAR28(VAR14)
)
(
input VAR39,
input VAR20,
input VAR11,
input [VAR1-1:0] VAR6,
input [VAR15-1:0] VAR4,
input [VAR26-1:0] VAR16,
output reg VAR41,
out... | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/SOC_NIOS_II_mult_cell.v | 6,268 | module MODULE1 (
VAR52,
VAR24,
clk,
VAR5,
VAR56
)
;
output [ 31: 0] VAR56;
input [ 31: 0] VAR52;
input [ 31: 0] VAR24;
input clk;
input VAR5;
wire [ 31: 0] VAR56;
wire [ 31: 0] VAR50;
wire [ 15: 0] VAR23;
wire VAR21;
assign VAR21 = ~VAR5;
VAR28 VAR47
(
.VAR34 (VAR21),
.VAR42 (clk),
.VAR20 (VAR52[15 : 0]),
.VAR17 (VAR24... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbp/sky130_fd_sc_hd__dlxbp.behavioral.v | 1,963 | module MODULE1 (
VAR15 ,
VAR1 ,
VAR17 ,
VAR12
);
output VAR15 ;
output VAR1 ;
input VAR17 ;
input VAR12;
supply1 VAR14;
supply0 VAR10;
supply1 VAR7 ;
supply0 VAR13 ;
wire VAR6 ;
wire VAR4;
wire VAR8 ;
reg VAR16 ;
wire VAR2 ;
VAR5 VAR3 (VAR6 , VAR8, VAR4, VAR16, VAR14, VAR10);
buf VAR11 (VAR15 , VAR6 );
not VAR9 (VAR1 ,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/buf/sky130_fd_sc_hdll__buf_8.v | 2,009 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR6,
VAR4,
VAR7 ,
VAR2
);
output VAR5 ;
input VAR3 ;
input VAR6;
input VAR4;
input VAR7 ;
input VAR2 ;
VAR1 VAR8 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR6;
supply0 VAR4;... | apache-2.0 |
somethingnew2-0/CS552-CPU | RoadRunner/off_by_one.tar.gz_extracted/CPU.v | 13,920 | module MODULE1(clk, VAR31, VAR45, VAR141);
input clk;
input VAR31;
output reg VAR45; output [15:0] VAR141;
wire [15:0] VAR67;
wire VAR114, VAR117, VAR22, VAR98, VAR20, VAR43, VAR47;
VAR1 VAR85(
.clk(clk),
.VAR31(VAR31),
.VAR98(VAR98),
.VAR20(VAR20),
.VAR43(VAR43),
.VAR47(VAR47),
.VAR114(VAR114),
.VAR117(VAR117),
.VAR22... | mit |
SymbiFlow/yosys | techlibs/intel/max10/cells_map.v | 2,316 | module \VAR24 (input VAR19, output VAR15);
VAR9 VAR1 (.VAR10(VAR15), .VAR7(VAR19), .VAR21(1'b0));
endmodule
module \VAR5 (input VAR19, output VAR15);
VAR18 VAR1 (.VAR10(VAR15), .VAR7(VAR19), .VAR23(1'b1));
endmodule
module MODULE3 (VAR6, VAR11);
parameter VAR16 = 0;
parameter VAR12 = 0;
input [VAR16-1:0] VAR6;
output V... | isc |
eecsninja/duinocube-core | common/basics.v | 3,353 | module MODULE5(clk, en, reset, VAR15, VAR12);
parameter VAR11=1;
input clk;
input en;
input reset;
input [VAR11-1:0] VAR15;
output [VAR11-1:0] VAR12;
reg [VAR11-1:0] VAR12;
always @ (posedge clk or posedge reset)
if (reset)
VAR12 <= 0;
else if (en)
VAR12 <= VAR15;
endmodule
module MODULE4(clk, reset, VAR15, VAR12);
par... | gpl-3.0 |
asicguy/gplgpu | hdl/hbi/hbi_top.v | 32,323 | module MODULE1
(
input [1:0] VAR265,
input VAR279,
input VAR245, input VAR227, input VAR4,
input [31:0]VAR150,
input [3:0] VAR152,
input VAR29,
input VAR244,
input VAR224,
input [2:0] VAR18,
input VAR6,
input VAR131,
input VAR215,
input VAR168,
input VAR179,
input [31:0]VAR258,
input [31:0]VAR124, input VAR264,
input V... | gpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_06_a/hdl/verilog/user_logic.v | 34,325 | /* VAR31 VAR32:
module MODULE1
(
VAR25,
VAR96,
VAR98,
VAR56,
VAR61,
VAR54,
VAR30,
VAR126,
VAR143,
VAR203,
VAR104,
VAR73,
VAR40,
VAR214,
VAR165,
VAR7,
VAR27,
VAR196,
VAR179,
VAR132,
VAR188,
VAR171,
VAR174,
VAR205,
VAR131,
VAR154,
VAR21,
VAR59,
VAR42,
VAR184,
VAR182,
VAR4,
VAR89,
VAR2,
VAR122,
VAR75,
VAR116,
VAR107,
VAR2... | bsd-2-clause |
olajep/oh | src/adi/hdl/library/common/ad_ss_444to422.v | 4,306 | module MODULE1 #(
parameter VAR1 = 0,
parameter VAR18 = 16) (
input clk,
input VAR21,
input [VAR16:0] VAR6,
input [23:0] VAR10,
output reg [VAR16:0] VAR19,
output reg [15:0] VAR17);
localparam VAR16 = VAR18 - 1;
reg VAR8 = 'd0;
reg [VAR16:0] VAR14 = 'd0;
reg [23:0] VAR12 = 'd0;
reg VAR4 = 'd0;
reg [VAR16:0] VAR13 = 'd0... | mit |
fzyz999/5-stage-MIPS | control/forwardctl.v | 4,395 | module MODULE1 (VAR58,VAR2,VAR6,VAR26,
VAR45,VAR56,
VAR65,VAR23,
VAR9);
input [31:0] VAR58,VAR2,VAR6,VAR26;
output [2:0] VAR45,VAR56;
output [2:0] VAR65,VAR23;
output [1:0] VAR9;
wire VAR16,VAR14,VAR20,VAR32,VAR10,VAR50,VAR7,VAR24,VAR30,VAR22,VAR40,VAR18;
wire VAR44,VAR8,VAR31,VAR42,VAR55,VAR60,VAR43,VAR34,VAR48,VAR52,... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/ipstatic/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axic_srl_fifo.v | 6,589 | module MODULE1 #(
parameter VAR30 = "VAR9",
parameter integer VAR26 = 1,
parameter integer VAR31 = 16 )
(
input wire VAR8, input wire VAR15, input wire [VAR26-1:0] VAR21, input wire VAR27, output reg VAR11, output wire [VAR26-1:0] VAR33, output reg VAR32, input wire VAR2 );
function integer VAR1 (input integer VAR10);
... | mit |
dailypips/miaow | src/verilog/rtl/dispatcher/cam_allocator.v | 1,713 | module MODULE1
(
VAR8,
clk, rst, VAR9, VAR7, VAR3, VAR5,
VAR11
);
parameter VAR14 = 6;
parameter VAR10 = 64;
parameter VAR13 = 10;
parameter VAR4 = 1024;
input clk,rst;
input VAR9;
input [VAR13:0] VAR7;
output [VAR10-1:0] VAR8;
input VAR3;
input [VAR14-1 : 0] VAR5;
input [VAR13:0] VAR11;
reg VAR15;
reg [VAR13:0] VAR16;... | bsd-3-clause |
subailong/miaow | src/verilog/rtl/exec/rd_port_9_to_1.v | 2,065 | module MODULE1 (
VAR13,
VAR9,
VAR19,
VAR14,
VAR15,
VAR2,
VAR21,
VAR8,
VAR5,
VAR18,
VAR12,
VAR7,
VAR17,
VAR10,
VAR4,
VAR16,
VAR20,
VAR1,
VAR3
);
parameter VAR6 = 1;
input VAR13;
input [VAR6 - 1:0] VAR9;
input VAR19;
input [VAR6 - 1:0] VAR14;
input VAR15;
input [VAR6 - 1:0] VAR2;
input VAR21;
input [VAR6 - 1:0] VAR8;
inp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4.behavioral.v | 1,425 | module MODULE1 (
VAR9,
VAR6,
VAR1,
VAR4,
VAR2
);
output VAR9;
input VAR6;
input VAR1;
input VAR4;
input VAR2;
supply1 VAR5;
supply0 VAR11;
supply1 VAR7 ;
supply0 VAR10 ;
wire VAR12;
nor VAR3 (VAR12, VAR6, VAR1, VAR4, VAR2 );
buf VAR8 (VAR9 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfstp/sky130_fd_sc_ms__dfstp_1.v | 2,273 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR3 ,
VAR9,
VAR7 ,
VAR2 ,
VAR4 ,
VAR5
);
output VAR10 ;
input VAR1 ;
input VAR3 ;
input VAR9;
input VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR5 ;
VAR8 VAR6 (
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODU... | apache-2.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/bee3Top/src/c3dClkGen.v | 6,749 | module MODULE1 (
input VAR35,
output VAR44, output VAR18, output VAR14, output VAR32,
output VAR3, output VAR9, output VAR46, output VAR28, output VAR29
);
wire VAR25, VAR60;
VAR30 #(.VAR20("VAR11"), .VAR61(2), .VAR12(0.0), .VAR40(3.2),
.VAR41(4), .VAR67(0.5), .VAR47(0.0),
.VAR15(2), .VAR58(0.5), .VAR66(0.0),
.VAR53(16... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.behavioral.pp.v | 1,236 | module MODULE1( VAR3, VAR1, VAR2, VAR7, VAR8 );
input VAR3, VAR1;
inout VAR7, VAR8;
output VAR2;
VAR4 VAR5(.VAR3(VAR3),.VAR1(VAR1),.VAR2(VAR2),.VAR7(VAR7),.VAR8(VAR8));
VAR4 VAR6(.VAR3(VAR3),.VAR1(VAR1),.VAR2(VAR2),.VAR7(VAR7),.VAR8(VAR8)); | apache-2.0 |
parallella/oh | common/hdl/oh_mux4.v | 1,204 | module MODULE1 #(parameter VAR1 = 1 ) (
input VAR3,
input VAR8,
input VAR5,
input VAR10,
input [VAR1-1:0] VAR7,
input [VAR1-1:0] VAR2,
input [VAR1-1:0] VAR9,
input [VAR1-1:0] VAR6,
output [VAR1-1:0] out );
assign out[VAR1-1:0] = ({(VAR1){VAR10}} & VAR6[VAR1-1:0] |
{(VAR1){VAR5}} & VAR9[VAR1-1:0] |
{(VAR1){VAR8}} & VAR2... | mit |
carstenbru/fpga-log | spartanmc/hardware/contrast_box/src/PushButton_Debouncer.v | 1,473 | module MODULE1#(parameter VAR1 = 16) (
input wire clk,
input wire VAR10,
output reg VAR8, output wire VAR7, output wire VAR3 );
reg VAR5; always @(posedge clk) VAR5 <= VAR10; reg VAR6; always @(posedge clk) VAR6 <= VAR5;
reg [VAR1-1:0] VAR9;
wire VAR2 = (VAR8==VAR6);
wire VAR4 = &VAR9;
always @(posedge clk)
if(VAR2)
VA... | gpl-3.0 |
JY-Kim/CA2016 | Sources/IDEX.v | 1,424 | module MODULE1
(
input VAR18,
input VAR15,
input [31:0] VAR7,
input [31:0] VAR19,
input [31:0] VAR5,
input [4:0] VAR3,
input [31:0] VAR4,
input [4:0] VAR13,
input [2:0] VAR10,
input [1:0] VAR16,
input [4:0] VAR17,
output reg [31:0] VAR2,
output reg [31:0] VAR11,
output reg [31:0] VAR20,
output reg [4:0] VAR12,
output r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o.pp.blackbox.v | 1,465 | module MODULE1 (
VAR5 ,
VAR3,
VAR1,
VAR4 ,
VAR2 ,
VAR9,
VAR7,
VAR6 ,
VAR8
);
output VAR5 ;
input VAR3;
input VAR1;
input VAR4 ;
input VAR2 ;
input VAR9;
input VAR7;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/riffa/fifo_packer_128.v | 5,107 | module MODULE1 (
input VAR12,
input VAR20,
input [127:0] VAR2, input [2:0] VAR6, input VAR7, input VAR13, input VAR24, output [127:0] VAR16, output VAR9, output VAR14, output VAR23, output VAR8 );
reg [2:0] VAR19=0, VAR19=0;
reg VAR17=0, VAR17=0;
reg VAR18=0, VAR18=0;
reg VAR1=0, VAR1=0;
reg VAR11=0, VAR11=0;
reg [223:... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_qpll_reset.v | 14,594 | module MODULE1 #
(
parameter VAR40 = "VAR33", parameter VAR22 = "VAR9", parameter VAR37 = 1, parameter VAR43 = 1
)
(
input VAR3,
input VAR26,
input VAR1,
input [VAR37-1:0] VAR14,
input [(VAR37-1)>>2:0]VAR52,
input [(VAR37-1)>>2:0]VAR17,
input [ 1:0] VAR13,
input [VAR37-1:0] VAR51,
input [VAR37-1:0] VAR42,
output VAR39,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi.behavioral.v | 1,639 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR3 ,
VAR9
);
output VAR1 ;
input VAR11 ;
input VAR3 ;
input VAR9;
supply1 VAR5;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR2 ;
wire VAR13 ;
wire VAR12 ;
wire VAR10;
not VAR14 (VAR13 , VAR9 );
and VAR7 (VAR12 , VAR11, VAR3 );
nor VAR15 (VAR10, VAR13, VAR12 );
buf VAR4 (VAR1 , VAR10 );
endm... | apache-2.0 |
mbus/mbus | layer_controller_v2/verilog/int_action_rom.v | 9,819 | module MODULE1 #(
parameter VAR16 = 13
)
(
output [VAR8*VAR16-1:0] VAR2,
output [(VAR19*3)*VAR16-1:0] VAR32,
output [2*VAR16-1:0] VAR25
);
wire [VAR8-1:0] VAR29 [0:VAR16-1];
wire [(VAR19*3)-1:0] VAR17 [0:VAR16-1];
wire [1:0] VAR24 [0:VAR16-1];
genvar VAR10;
generate
for (VAR10=0; VAR10<VAR16; VAR10=VAR10+1)
begin: VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_2.v | 2,599 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR1 ,
VAR2 ,
VAR6 ,
VAR3,
VAR11 ,
VAR9 ,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR3;
input VAR11 ;
input VAR9 ;
input VAR7 ;
input VAR4 ;
VAR8 VAR12 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR11... | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/firdecim_m5_n20.v | 10,900 | module MODULE1
(
VAR24, VAR8,
VAR23, VAR10, VAR2, VAR26
);
output reg signed [31:0] VAR24 ;
output reg VAR8 ;
input VAR23 ; input VAR10 ;
input VAR2 ;
input signed [15:0] VAR26 ;
reg [4:0] VAR21 ;
reg [2:0] VAR13 ; reg signed [15:0] VAR22 ;
reg VAR9 ;
reg signed [31:0] VAR25 ;
reg signed [31:0] VAR18 ; reg signed [31:0... | gpl-2.0 |
queq/just-stuff | pov/TopFixed/Control_Character.v | 1,640 | module MODULE1(
input VAR1,
input VAR6,
input VAR5,
input VAR4,
output VAR9,
output [6:0]VAR20
);
wire VAR27;
wire VAR24;
wire VAR7;
wire VAR25;
wire VAR28;
wire [7:0]VAR2;
wire [7:0]VAR15;
wire [7:0]VAR13;
wire [6:0]VAR23;
VAR26 VAR22(.VAR1(VAR1), .VAR6(VAR6), .VAR27(VAR27), .VAR28(VAR28), .VAR7(VAR7), .VAR25(VAR25), ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o.functional.v | 1,471 | module MODULE1 (
VAR8 ,
VAR9,
VAR6,
VAR3,
VAR1,
VAR11
);
output VAR8 ;
input VAR9;
input VAR6;
input VAR3;
input VAR1;
input VAR11;
wire VAR5 ;
wire VAR7;
and VAR10 (VAR5 , VAR3, VAR9, VAR6 );
or VAR4 (VAR7, VAR5, VAR11, VAR1);
buf VAR2 (VAR8 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.symbol.v | 1,519 | module MODULE1 (
input VAR5,
output VAR7
);
wire VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/ip/ip_10/synth/bd_350b_slot_2_ar_0.v | 4,561 | module MODULE1 (
VAR24,
VAR21,
dout
);
input wire [0 : 0] VAR24;
input wire [0 : 0] VAR21;
output wire [1 : 0] dout;
VAR29 #(
.VAR33(1),
.VAR36(1),
.VAR19(1),
.VAR10(1),
.VAR54(1),
.VAR46(1),
.VAR48(1),
.VAR49(1),
.VAR58(1),
.VAR11(1),
.VAR8(1),
.VAR35(1),
.VAR43(1),
.VAR66(1),
.VAR62(1),
.VAR47(1),
.VAR12(1),
.VAR18(1... | mit |
cpulabs/mist1032sa | src/core/execute/old_execute/mul_booth32.v | 5,332 | module MODULE1(
input [31:0] VAR14,
input [31:0] VAR37,
output [63:0] VAR34,
output VAR29,
output VAR17,
output VAR2,
output VAR6,
output VAR12,
output VAR21,
output VAR35,
output VAR28,
output VAR23,
output VAR9);
wire [63:0] VAR19;
wire [63:0] VAR16;
wire [63:0] VAR38;
wire [63:0] VAR36;
wire [63:0] VAR33;
wire [63:0... | bsd-2-clause |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ipshared/0b6b/hdl/axi_register_slice_v2_1_vl_rfs.v | 41,990 | module MODULE1 #
(
parameter VAR31 = 2 )
(
input wire clk, input wire [VAR31-1:0] VAR1, input wire VAR8, input wire VAR37, output wire VAR4 );
localparam integer VAR27 = 2**VAR31;
reg [VAR27-1:0] VAR38 = {VAR27{1'b0}};
always @(posedge clk)
if (VAR8)
VAR38 <= {VAR38[VAR27-2:0], VAR37};
assign VAR4 = VAR38[VAR1];
endmod... | mit |
joshtm00/Verificaci-n-de-Circuitos-Digitales | LIFO_FIFO/Fifo_Lifo.v | 2,001 | module MODULE1(
input VAR12, input VAR8, input VAR17, input VAR28, input VAR19, input [15:0] VAR3 , output [15:0] VAR16, output VAR11, output VAR7 );
parameter VAR26 = 0 ; parameter VAR24 = (1 << VAR9) ; parameter VAR1 = 8 ; parameter VAR9 = 3 ;
reg [VAR9-1:0] VAR5;
reg [VAR9-1:0] VAR18;
reg [VAR9 :0] VAR27;
reg [VAR1-... | gpl-3.0 |
tugrulyatagan/RISC-processor | xilinx_processor/branch.v | 1,235 | module MODULE1(
input VAR8,
input [3:0] VAR6,
input VAR4,
input VAR7,
input VAR3,
input VAR1,
output reg VAR2
);
reg VAR5;
always @(*) begin
case (VAR6)
4'h0: VAR5 <= VAR4;
4'h1: VAR5 <= ~VAR4;
4'h2: VAR5 <= VAR1;
4'h3: VAR5 <= ~VAR1;
4'h4: VAR5 <= VAR7;
4'h5: VAR5 <= ~VAR7;
4'h6: VAR5 <= VAR3;
4'h7: VAR5 <= ~VAR3;
4'h... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o.functional.pp.v | 1,965 | module MODULE1 (
VAR13,
VAR16,
VAR5 ,
VAR6 ,
VAR15 ,
VAR12 ,
VAR1 ,
VAR4
);
input VAR13;
input VAR16;
output VAR5 ;
input VAR6 ;
input VAR15 ;
input VAR12 ;
input VAR1 ;
input VAR4 ;
wire VAR1 VAR9 ;
wire VAR2 ;
wire VAR7;
and VAR10 (VAR9 , VAR12, VAR6, VAR15 );
or VAR14 (VAR2 , VAR9, VAR4, VAR1 );
VAR8 VAR3 (VAR7, VAR... | apache-2.0 |
cospan/prometheus_fpga | sandbox/fx3_bus.v | 7,590 | module MODULE1 # (
parameter VAR29 = 8
)(
input clk,
input rst,
inout [31:0] VAR91,
output VAR69,
output VAR46,
output VAR45,
output VAR21,
input VAR101,
input VAR84,
input VAR98,
input VAR95,
output [1:0] VAR73,
input VAR42,
output [7:0] VAR2,
output [7:0] VAR32,
output [31:0] VAR81,
output [31:0] VAR99,
output VAR54,... | gpl-3.0 |
AngelTerrones/MUSB | Boards/xilinx_diligent_s3e/rtl/verilog/clk_generator/clk_generator.v | 5,425 | module MODULE1(
input VAR29, output VAR56, output VAR48 );
localparam real VAR37 = 50.0; localparam integer VAR43 = 4; localparam integer VAR47 = 2; localparam integer VAR32 = 2;
wire clk;
wire VAR30;
wire VAR10;
wire VAR20;
wire VAR34;
wire VAR42;
wire VAR7;
VAR24 VAR9(
.VAR54 ( VAR29 ),
.VAR3 ( clk )
);
VAR8 VAR1(
.V... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_clk_gen/bsg_rp_clk_gen_fine_delay_tuner.v | 2,295 | module MODULE1
( input VAR42
, input VAR10
, input VAR38
, input [1:0] VAR8
, output VAR32
, output VAR20
);
wire [1:0] VAR40;
wire [1:0] VAR43;
wire [3:0] VAR30;
wire VAR4;
VAR36 VAR1 ( .VAR24(VAR30[1]), .VAR39() );
VAR36 VAR23 ( .VAR24(VAR30[2]), .VAR39() );
VAR36 VAR6 ( .VAR24(VAR30[2]), .VAR39() );
VAR36 VAR25 ( .V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o.pp.symbol.v | 1,372 | module MODULE1 (
input VAR7 ,
input VAR6 ,
input VAR5 ,
input VAR4 ,
output VAR2 ,
input VAR1 ,
input VAR9,
input VAR3,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4/sky130_fd_sc_hs__nor4.blackbox.v | 1,272 | module MODULE1 (
VAR5,
VAR4,
VAR2,
VAR6,
VAR1
);
output VAR5;
input VAR4;
input VAR2;
input VAR6;
input VAR1;
supply1 VAR3;
supply0 VAR7;
endmodule | apache-2.0 |
cospan/prometheus_fpga | rtl/slave_fifo/prometheus_fx3_partial.v | 3,591 | module MODULE1(
input VAR4,
input VAR6,
input VAR16,
input VAR8,
input VAR9,
output VAR14,
output VAR18,
output [31:0] VAR17
);
reg [2:0]VAR11;
reg [2:0]VAR10;
parameter [2:0] VAR1 = 3'd0;
parameter [2:0] VAR5 = 3'd1;
parameter [2:0] VAR19 = 3'd2;
parameter [2:0] VAR12 = 3'd3;
parameter [2:0] VAR13 = 3'd4;
reg [3:0] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o.symbol.v | 1,381 | module MODULE1 (
input VAR6,
input VAR7,
input VAR1,
input VAR2,
input VAR8,
output VAR10
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_auto_pc_2/synth/image_processing_2d_design_auto_pc_2.v | 12,869 | module MODULE1 (
VAR22,
VAR105,
VAR54,
VAR112,
VAR85,
VAR82,
VAR20,
VAR21,
VAR9,
VAR79,
VAR98,
VAR72,
VAR40,
VAR101,
VAR92,
VAR91,
VAR10,
VAR73,
VAR90,
VAR64,
VAR70,
VAR16,
VAR63,
VAR95,
VAR6,
VAR39,
VAR44,
VAR61,
VAR99,
VAR18,
VAR87,
VAR31,
VAR58,
VAR12,
VAR51,
VAR81,
VAR8,
VAR26,
VAR48,
VAR17,
VAR111,
VAR13,
VAR33,
V... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/dispatcher.v | 18,590 | module MODULE1 (
clk,
reset,
VAR38,
VAR14,
VAR105,
VAR28,
VAR63,
VAR90,
VAR82,
VAR104,
VAR5,
VAR16,
VAR74,
VAR89,
VAR55, VAR66,
VAR84,
VAR91,
VAR33, VAR112, VAR8,
VAR43,
VAR31,
VAR67,
VAR71,
VAR3,
VAR64,
VAR27,
VAR111,
VAR70,
VAR65,
VAR45,
VAR44,
VAR58,
VAR6,
VAR73
);
function integer VAR50;
input integer VAR54;
begin
... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_dmask_cols_V.v | 2,987 | module MODULE1 (
clk,
VAR27,
VAR1,
VAR7,
VAR9);
parameter VAR12 = 32'd12;
parameter VAR15 = 32'd2;
parameter VAR5 = 32'd3;
input clk;
input [VAR12-1:0] VAR27;
input VAR1;
input [VAR15-1:0] VAR7;
output [VAR12-1:0] VAR9;
reg[VAR12-1:0] VAR23 [0:VAR5-1];
integer VAR21;
always @ (posedge clk)
begin
if (VAR1)
begin
for (VA... | gpl-3.0 |
CospanDesign/nysa-sata | rtl/link/scrambler.v | 12,407 | module MODULE1 (
clk,
rst,
en,
VAR2,
din,
dout
);
input clk;
input rst;
input en;
input VAR2;
input [31:0] din;
output [31:0] dout;
parameter VAR3 = 16'hF0F6;
reg [15:0] context;
wire [31:0] VAR1;
reg [31:0] VAR4;
always @ (posedge clk) begin
if (rst) begin
context <= VAR3;
VAR4 <= 32'h0;
end
else begin
if (en) begin
c... | mit |
MegaShow/college-programming | Homework/Digital Circuits and Logical Design/Watch/TimeCounter.v | 5,298 | module MODULE1(
input clk, input VAR22,
input VAR43,
input VAR36,
input VAR18,
input VAR37,
input VAR64,
input VAR49,
input VAR60,
input VAR65, input VAR63, input VAR12, output reg [3:0] VAR14, output reg VAR20,
output reg VAR13,
output wire [7:0] VAR29, output wire [3:0] VAR61 );
reg VAR2;
reg [15:0] VAR15;
wire [7:0]... | mit |
javierbrito29/papiGB | rtl/dzcpu_ucode_lut.v | 34,682 | module MODULE1
(
input wire[7:0] VAR12,
output reg [9:0] VAR18
);
always @ ( VAR12 )
begin
case ( VAR12 )
default:
VAR18 = 10'd278;
endcase
end
endmodule
module MODULE2
(
input wire[7:0] VAR12,
output reg [8:0] VAR18
);
always @ ( VAR12 )
begin
case ( VAR12 )
8'h7C: VAR18 = 9'd16; 8'h11: VAR18 = 9'd69; 8'h38: VAR18 = 9... | gpl-2.0 |
elegabriel/myzju | junior1/CA/LAB/lab1/single_cpu/alu.v | 1,095 | module MODULE1(VAR3,VAR4,VAR2,VAR1
);
input wire [31:0] VAR3,VAR4;
input wire [4:0] VAR2;
output reg [31:0] VAR1;
always @*
begin
case(VAR2)
5'd0: begin
VAR1=VAR3+VAR4;
end
5'd1: begin
VAR1=VAR3-VAR4;
end
5'd2: begin
VAR1=VAR3&VAR4;
end
5'd3: begin
VAR1=VAR3|VAR4;
end
5'd6: begin
VAR1=VAR4<<VAR3; end
5'd10: begin
VAR1=... | gpl-2.0 |
sehugg/8bitworkshop | presets/verilog/sharedbuffer.v | 3,961 | module MODULE1(clk, reset, VAR30, VAR10, VAR17, VAR12,
VAR2, VAR13, VAR1, VAR8
, output [15:0] VAR5
, output VAR26
, output VAR32
, VAR29
);
input clk, reset;
input VAR17, VAR12;
output VAR30, VAR10;
wire VAR7;
wire [8:0] VAR24;
wire [8:0] VAR31;
assign VAR5 = VAR25.VAR14[VAR25.VAR5];
assign VAR26 = VAR25.VAR26;
assign... | gpl-3.0 |
liqimai/Assignment1-Calculator | Top/Top.v | 4,540 | module MODULE1(
input wire clk,
input wire [5:0] VAR24,
input wire [7:0]VAR32,
output wire [7:0]VAR35,
output wire [7:0]VAR4
);
wire[31:0] VAR30;
wire[63:0] VAR2;
wire[63:0] VAR34;
wire[63:0] VAR16;
wire[63:0] VAR11;
wire[31:0] VAR19;
wire[63:0] VAR7;
wire[63:0] VAR13;
wire[63:0] VAR25;
wire[63:0] VAR9;
wire[63:0] VAR2... | gpl-2.0 |
aap/pdp6 | verilog/core32k.v | 9,620 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR54,
input wire VAR42,
input wire VAR118,
input wire VAR136,
input wire VAR117,
input wire VAR16,
input wire VAR15,
input wire [21:35] VAR98,
input wire [18:21] VAR134,
input wire VAR147,
input wire [0:35] VAR63,
output wire VAR151,
output wire VAR11,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfsbp/sky130_fd_sc_ms__dfsbp.blackbox.v | 1,356 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR8 ,
VAR9 ,
VAR3
);
output VAR2 ;
output VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR3;
supply1 VAR4;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Tao-J/nexys3MIPSSoC | clk_div.v | 1,113 | module MODULE1(
input clk,
input wire rst,
input wire VAR1,
output reg[31:0] MODULE1,
output wire VAR2
);
always @(posedge clk or posedge rst)begin
if (rst) begin
MODULE1 <= 0;
end else begin
MODULE1 <= MODULE1 + 1'b1;
end
end
assign VAR2 = clk;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_psa_pp_sn/sky130_fd_sc_hs__udp_dlatch_psa_pp_sn.blackbox.v | 1,468 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3 ,
VAR5 ,
VAR4 ,
VAR1
);
output VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o.behavioral.pp.v | 2,026 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR8 ,
VAR16 ,
VAR4 ,
VAR17,
VAR5,
VAR10 ,
VAR15
);
output VAR3 ;
input VAR6 ;
input VAR8 ;
input VAR16 ;
input VAR4 ;
input VAR17;
input VAR5;
input VAR10 ;
input VAR15 ;
wire VAR12 ;
wire VAR14 ;
wire VAR2;
and VAR1 (VAR12 , VAR16, VAR6, VAR8 );
or VAR9 (VAR14 , VAR12, VAR4 );
VAR11 VAR... | apache-2.0 |
jimurai/okWishboneMaster | verilog/wb_regmap.v | 3,744 | module MODULE1(
VAR35, VAR33, VAR26, VAR3, VAR36, VAR27, VAR12,
VAR19, VAR24, VAR39, VAR29, VAR15, VAR32,
VAR13
);
input VAR35;
input VAR33;
input [4:0] VAR26;
input [15:0] VAR3;
output [15:0] VAR36;
input [1:0] VAR27;
input [2:0] VAR12;
input VAR19;
input VAR24;
input VAR39;
output VAR29;
output VAR15;
output VAR32;
o... | mit |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/hls_saturation_enbkb.v | 4,433 | module MODULE2
VAR26 = 32,
VAR29 = 32,
VAR13 = 32
)
(
input clk,
input reset,
input VAR19,
input [VAR26-1:0] VAR8,
input [VAR29-1:0] VAR11,
output wire [VAR13-1:0] VAR6,
output wire [VAR13-1:0] VAR2
);
localparam VAR17 = (VAR26 > VAR29)? VAR26 : VAR29;
reg [VAR26-1:0] VAR18[0:VAR26];
reg [VAR29-1:0] VAR23[0:VAR26];
reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a.functional.pp.v | 2,156 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR3 ,
VAR14 ,
VAR9 ,
VAR11,
VAR13,
VAR2 ,
VAR16
);
output VAR1 ;
input VAR10 ;
input VAR3 ;
input VAR14 ;
input VAR9 ;
input VAR11;
input VAR13;
input VAR2 ;
input VAR16 ;
wire VAR4 ;
wire VAR18 ;
wire VAR6 ;
wire VAR19;
or VAR5 (VAR4 , VAR3, VAR10 );
or VAR15 (VAR18 , VAR9, VAR14 );
an... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2_lp2.v | 2,113 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR2 ,
VAR1,
VAR6,
VAR7 ,
VAR3
);
output VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR1;
input VAR6;
input VAR7 ;
input VAR3 ;
VAR5 VAR9 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR8,
VAR4,
VAR2
);
output VAR8;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.v | 2,119 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR6,
VAR5,
VAR3 ,
VAR2
);
output VAR8 ;
input VAR7 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR2 ;
VAR4 VAR1 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8,
VAR7
);
output VAR8;
input VAR7;
supply1 VAR6;
supply0 VAR5;... | apache-2.0 |
tgiv014/ECE441_Proj3 | lfsr.v | 1,261 | module MODULE1(clk, VAR1, VAR4, VAR2);
input clk, VAR1;
output VAR2; output reg [7:0] VAR4;
wire VAR3;
assign VAR3 = VAR4[7]^VAR4[5]^VAR4[4]^VAR4[3]; assign VAR2 = VAR4[7];
always @ (posedge clk or negedge VAR1)
begin
if(~VAR1) begin
VAR4 <= 8'b00000001;
end
else
begin
VAR4 <= { VAR4[6:0], VAR3 };
end
end
endmodule | mit |
SI-RISCV/e200_opensource | rtl/e203/core/e203_ifu_litebpu.v | 5,558 | module MODULE1(
input [VAR30-1:0] VAR28,
input VAR4,
input VAR5,
input VAR1,
input [VAR3-1:0] VAR36,
input [VAR32-1:0] VAR22,
input VAR12,
input VAR8,
input VAR10,
input VAR21,
output VAR20,
output VAR13,
output [VAR30-1:0] VAR26,
output [VAR30-1:0] VAR31,
input VAR6,
output VAR25,
input VAR29,
input [VAR3-1:0] VAR27,
... | apache-2.0 |
MarcoVogt/basil | firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v | 6,896 | module MODULE1
parameter VAR53 = 16,
parameter [1:0] VAR67 = 0,
parameter [0:0] VAR8 = 0
)
(
input wire VAR3,
input wire [13:0] VAR16,
input wire VAR51,
input wire VAR31,
input wire VAR61,
output wire VAR41,
output wire [31:0] VAR44,
input wire VAR58,
input wire [VAR53-1:0] VAR68,
input wire [7:0] VAR83,
output reg [7:... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_4.v | 2,583 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR2 ,
VAR6 ,
VAR8 ,
VAR9,
VAR10 ,
VAR5 ,
VAR12 ,
VAR4
);
output VAR7 ;
input VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR9;
input VAR10 ;
input VAR5 ;
input VAR12 ;
input VAR4 ;
VAR3 VAR11 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR10(V... | apache-2.0 |
kyzhai/NUNY | src/hardware/bg1_new_bb.v | 5,008 | module MODULE1 (
address,
VAR2,
VAR1);
input [14:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/tiel/gf180mcu_fd_sc_mcu7t5v0__tiel.behavioral.pp.v | 1,090 | module MODULE1( VAR3, VAR1, VAR6 );
inout VAR1, VAR6;
output VAR3;
VAR5 VAR2(.VAR3(VAR3),.VAR1(VAR1),.VAR6(VAR6));
VAR5 VAR4(.VAR3(VAR3),.VAR1(VAR1),.VAR6(VAR6)); | apache-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/lsu/lsu_opcode_decoder.v | 8,933 | module MODULE1(
VAR39,
VAR11,
VAR25,
VAR41,
VAR13,
VAR46,
VAR45,
VAR31,
VAR48,
VAR19,
VAR5,
VAR30,
VAR20,
VAR38,
VAR44,
VAR33,
VAR8,
VAR28,
VAR12
);
input VAR39;
input [31:0] VAR11;
input [11:0] VAR25;
input [11:0] VAR41;
input [11:0] VAR13;
input [11:0] VAR46;
output VAR45;
output VAR31;
output [8:0] VAR48;
output [8:... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1n/sky130_fd_sc_hdll__inputiso1n.functional.pp.v | 1,875 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR13,
VAR11 ,
VAR1 ,
VAR8 ,
VAR12
);
output VAR4 ;
input VAR9 ;
input VAR13;
input VAR11 ;
input VAR1 ;
input VAR8 ;
input VAR12 ;
wire VAR5 ;
wire VAR2;
not VAR6 (VAR5 , VAR13 );
or VAR3 (VAR2, VAR9, VAR5 );
VAR7 VAR10 (VAR4 , VAR2, VAR11, VAR1);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp.pp.blackbox.v | 1,367 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR1 ,
VAR2,
VAR4 ,
VAR3 ,
VAR8 ,
VAR6
);
output VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR2;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR6 ;
endmodule | apache-2.0 |
ServerTech/neptune | code/smr_reg_core.v | 1,685 | module MODULE1(clk, rst, VAR4, VAR1, wr, rd);
parameter VAR2 = 'd16; parameter VAR5 = 'd13;
input wire clk , rst ; input wire VAR4 , VAR1 ; input wire [VAR2-1:0] wr ;
output wire [VAR5-1:0] rd ;
reg [VAR2-1:0] VAR3 ;
assign rd [VAR5-1:0] = VAR3 [VAR5-1:0];
always@(posedge clk) begin
end
if(rst) VAR3 [VAR2-1:0] <= {VAR2... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_4.behavioral.pp.v | 2,179 | module MODULE1( VAR6, VAR8, VAR13, VAR7, VAR3 );
input VAR6, VAR8;
inout VAR7, VAR3;
output VAR13;
reg VAR2;
VAR9 VAR4(.VAR6(VAR6),.VAR8(VAR8),.VAR13(VAR13),.VAR7(VAR7),.VAR3(VAR3),.VAR2(VAR2));
VAR9 VAR5(.VAR6(VAR6),.VAR8(VAR8),.VAR13(VAR13),.VAR7(VAR7),.VAR3(VAR3),.VAR2(VAR2));
not VAR11(VAR1,VAR8);
buf VAR10(VAR12,V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and2/sky130_fd_sc_hvl__and2.symbol.v | 1,264 | module MODULE1 (
input VAR4,
input VAR3,
output VAR5
);
supply1 VAR6;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux4/sky130_fd_sc_ls__mux4.functional.pp.v | 1,983 | module MODULE1 (
VAR4 ,
VAR18 ,
VAR11 ,
VAR10 ,
VAR1 ,
VAR17 ,
VAR14 ,
VAR6,
VAR9,
VAR15 ,
VAR3
);
output VAR4 ;
input VAR18 ;
input VAR11 ;
input VAR10 ;
input VAR1 ;
input VAR17 ;
input VAR14 ;
input VAR6;
input VAR9;
input VAR15 ;
input VAR3 ;
wire VAR13 ;
wire VAR5;
VAR7 VAR16 (VAR13 , VAR18, VAR11, VAR10, VAR1, VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.functional.v | 1,666 | module MODULE1( VAR3, VAR12, VAR13, VAR18, VAR19, VAR7 );
input VAR13, VAR12, VAR3, VAR19, VAR7;
output VAR18;
wire VAR8;
not VAR20( VAR8, VAR13 );
wire VAR14;
not VAR1( VAR14, VAR12 );
wire VAR2;
not VAR11( VAR2, VAR3 );
wire VAR15;
and VAR5( VAR15, VAR8, VAR14, VAR2 );
wire VAR6;
not VAR4( VAR6, VAR19 );
wire VAR21;
... | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_spram_256x21.v | 10,827 | module MODULE1(
VAR32, VAR21, VAR37,
clk, rst, VAR19, VAR47, VAR34, addr, VAR18, VAR53
);
parameter VAR42 = 8;
parameter VAR6 = 21;
input VAR32;
input [VAR17 - 1:0] VAR37;
output VAR21;
input clk; input rst; input VAR19; input VAR47; input VAR34; input [VAR42-1:0] addr; input [VAR6-1:0] VAR18; output [VAR6-1:0] VAR53;
... | gpl-2.0 |
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