repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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SymbiFlow/yosys | techlibs/ecp5/dsp_map.v | 1,436 | module \VAR24 (input [17:0] VAR80, input [17:0] VAR53, output [35:0] VAR98);
parameter VAR66 = 18;
parameter VAR14 = 18;
parameter VAR71 = 36;
parameter VAR12 = 0;
parameter VAR3 = 0;
VAR69 VAR56 (
.VAR75(VAR80[0]), .VAR23(VAR80[1]), .VAR91(VAR80[2]), .VAR103(VAR80[3]), .VAR48(VAR80[4]), .VAR83(VAR80[5]), .VAR76(VAR80[... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2_8.v | 2,203 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR9 ,
VAR8 ,
VAR3,
VAR4,
VAR1 ,
VAR6
);
output VAR5 ;
input VAR10 ;
input VAR9 ;
input VAR8 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR6 ;
VAR2 VAR7 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/SCFIFO_40x64_withCount.v | 2,693 | module MODULE1
(
input VAR9 ,
input VAR12 ,
input [39:0] VAR1 ,
input VAR16 ,
output VAR11 ,
output [39:0] VAR14 ,
input VAR13 ,
output VAR3 ,
output [5:0] VAR7
);
VAR2
VAR4
(
.clk (VAR9 ),
.VAR15 (VAR12 ),
.din (VAR1 ),
.VAR5 (VAR16 ),
.VAR17 (VAR11 ),
.dout (VAR14 ),
.VAR10 (VAR13 ),
.VAR8 (VAR3 ),
.VAR6 (VAR7 )
);
e... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/RAMB16_S4_2_altera_bb.v | 7,842 | module MODULE1 (
VAR4,
VAR5,
VAR6,
VAR2,
VAR1,
VAR3);
input VAR4;
input [3:0] VAR5;
input [11:0] VAR6;
input [11:0] VAR2;
input VAR1;
output [3:0] VAR3;
tri1 VAR4;
tri0 VAR1;
endmodule | mit |
cliffordwolf/yosys | techlibs/nexus/arith_map.v | 2,804 | module MODULE1(
module 80nexusalu (VAR6, VAR42, VAR40, VAR34, VAR21, VAR5, VAR16);
parameter VAR4 = 0;
parameter VAR41 = 0;
parameter VAR13 = 1;
parameter VAR37 = 1;
parameter VAR15 = 1;
input [VAR13-1:0] VAR6;
input [VAR37-1:0] VAR42;
output [VAR15-1:0] VAR21, VAR5;
input VAR40, VAR34;
output [VAR15-1:0] VAR16;
wire V... | isc |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/common/rtl/iobdg_jbus_mondo_buf.v | 4,483 | module MODULE1 (
VAR24, VAR13, VAR20, VAR11, VAR6,
VAR10, clk, VAR18, VAR26, VAR21
);
input VAR10;
input clk;
input VAR18;
input [VAR4-1:0] VAR26;
output VAR24;
output [63:0] VAR13;
output [63:0] VAR20;
output [VAR14-1:0] VAR11;
output [VAR7-1:0] VAR6;
input VAR21;
wire [VAR5-1:0] VAR1;
wire [VAR5-1:0] VAR22;
wire [VAR... | gpl-2.0 |
secworks/mkmif | src/rtl/mkmif.v | 8,193 | module MODULE1(
input wire clk,
input wire VAR11,
output wire VAR29,
output wire VAR48,
input wire VAR35,
output wire VAR37,
input wire VAR22,
input wire VAR6,
input wire [7 : 0] address,
input wire [31 : 0] VAR2,
output wire [31 : 0] VAR10
);
localparam VAR14 = 8'h00;
localparam VAR47 = 8'h01;
localparam VAR15 = 8'h02... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o.behavioral.pp.v | 2,290 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR21 ,
VAR19 ,
VAR13 ,
VAR3 ,
VAR10 ,
VAR5,
VAR1
);
output VAR8 ;
input VAR9 ;
input VAR21 ;
input VAR19 ;
input VAR13 ;
input VAR3 ;
input VAR10 ;
input VAR5;
input VAR1;
wire VAR13 VAR14 ;
wire VAR13 VAR18 ;
wire VAR13 VAR4 ;
wire VAR15 ;
wire VAR6;
and VAR12 (VAR14 , VAR19, VAR13 );
a... | apache-2.0 |
emeb/iceRadio | FPGA/rxadc_2/verilog/src/cic_dec_3.v | 2,370 | module MODULE1 #(
parameter VAR6 = 4, VAR8 = 8, VAR7 = 10, VAR2 = (VAR7 + (VAR6 * VAR8)), VAR14 = VAR2 )
(
input clk, input reset, input VAR10, input signed [VAR7-1:0] VAR9, output signed [VAR14-1:0] VAR1, output valid );
wire signed [VAR2-1:0] VAR15 = {{VAR2-VAR7{VAR9[VAR7-1]}},VAR9};
reg signed [VAR2-1:0] VAR11[0:VAR... | mit |
Masahiro000Shimasaki/NeuralNetwork | Hardware/Perceptron_xor/fp_convert.v | 29,289 | module MODULE1
(
VAR6,
VAR8,
VAR17,
VAR13,
VAR10,
VAR2) ;
input VAR6;
input VAR8;
input VAR17;
input [31:0] VAR13;
input [4:0] VAR10;
output [31:0] VAR2;
tri0 VAR6;
tri1 VAR8;
tri0 VAR17;
reg [1:0] VAR16;
reg [31:0] VAR1;
reg [31:0] VAR7;
reg VAR3;
reg VAR4;
wire [5:0] VAR12;
wire VAR9;
wire [15:0] VAR15;
wire [191:0] ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab4/axi_interfaces_prj/solution2/syn/verilog/axi_interfaces.v | 74,343 | module MODULE1 (
VAR172,
VAR92,
VAR46,
VAR265,
VAR189,
VAR195,
VAR225,
VAR222,
VAR272,
VAR104,
VAR156,
VAR257,
VAR210,
VAR59,
VAR293,
VAR111,
VAR47,
VAR276,
VAR19,
VAR370,
VAR237,
VAR170,
VAR150,
VAR154,
VAR208,
VAR109,
VAR139,
VAR202,
VAR106,
VAR246,
VAR137,
VAR8,
VAR220,
VAR196,
VAR50,
VAR322,
VAR102,
VAR117,
VAR163,... | mit |
kyzhai/NUNY | src/hardware/five_new2_bb.v | 5,018 | module MODULE1 (
address,
VAR1,
VAR2);
input [9:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq_rdq_buf.v | 3,034 | module MODULE1(
VAR15,
clk, VAR4, VAR20, VAR18, VAR17, VAR6, VAR3,
VAR2, VAR22, VAR19
);
input clk;
input VAR4;
input VAR20;
input VAR18;
input VAR17;
input VAR6;
input VAR3;
input [VAR21-1:0] VAR2;
input [VAR21-1:0] VAR22;
input [VAR11-1:0] VAR19;
output [VAR11-1:0] VAR15;
wire [VAR11-1:0] VAR15;
wire [3:0] VAR10;
VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b.functional.v | 1,412 | module MODULE1 (
VAR8 ,
VAR5,
VAR9 ,
VAR7 ,
VAR4
);
output VAR8 ;
input VAR5;
input VAR9 ;
input VAR7 ;
input VAR4 ;
wire VAR10 ;
wire VAR2;
not VAR6 (VAR10 , VAR5 );
and VAR3 (VAR2, VAR10, VAR9, VAR7, VAR4);
buf VAR1 (VAR8 , VAR2 );
endmodule | apache-2.0 |
davidkoltak/tawas-core | projects/de0_nano_soc/rtl/de0_nano_soc.v | 3,517 | module MODULE1
(
input VAR18,
input VAR1,
input VAR12,
input [1:0] VAR72,
input [3:0] VAR44,
output [7:0] VAR64,
output VAR52,
input VAR74,
output VAR38,
input VAR9
);
wire VAR7 = VAR18;
wire VAR59 = VAR1;
wire VAR2 = VAR72[0];
wire VAR43;
wire [23:0] VAR42;
wire [31:0] VAR31;
VAR83 VAR83
(
.clk(VAR7),
.addr(VAR42),
.V... | mit |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/nios_nios2_gen2_0_cpu_debug_slave_wrapper.v | 9,385 | module MODULE1 (
VAR49,
VAR22,
clk,
VAR43,
VAR33,
VAR7,
VAR40,
VAR29,
VAR34,
VAR35,
VAR11,
VAR52,
VAR10,
VAR36,
VAR44,
VAR45,
VAR23,
VAR28,
VAR8,
VAR18,
VAR37,
VAR19,
VAR47,
VAR54,
VAR50,
VAR46,
VAR30,
VAR39,
VAR21,
VAR41,
VAR12,
VAR24,
VAR15
)
;
output [ 37: 0] VAR37;
output VAR19;
output VAR47;
output VAR54;
output V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b_m.v | 2,144 | module MODULE2 (
VAR3 ,
VAR9 ,
VAR4 ,
VAR5,
VAR2,
VAR8 ,
VAR1
);
output VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR5;
input VAR2;
input VAR8 ;
input VAR1 ;
VAR7 VAR6 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR3 ,
VAR9,
VAR4
);
output VAR3 ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.behavioral.pp.v | 2,820 | module MODULE1( VAR20, VAR2, VAR21, VAR24, VAR6, VAR17 );
input VAR21, VAR2, VAR20;
inout VAR6, VAR17;
output VAR24;
reg VAR14;
VAR15 VAR13(.VAR20(VAR20),.VAR2(VAR2),.VAR21(VAR21),.VAR24(VAR24),.VAR6(VAR6),.VAR17(VAR17),.VAR14(VAR14));
VAR15 VAR25(.VAR20(VAR20),.VAR2(VAR2),.VAR21(VAR21),.VAR24(VAR24),.VAR6(VAR6),.VAR17... | apache-2.0 |
marmolejo/zet | cores/zet/rtl/zet_jmp_cond.v | 2,051 | module MODULE1 (
input [4:0] VAR6,
input [3:0] VAR5,
input VAR8,
input [15:0] VAR11,
output reg VAR2
);
wire VAR4, VAR10, VAR3, VAR1, VAR7;
wire VAR9;
assign VAR4 = VAR6[4];
assign VAR10 = VAR6[3];
assign VAR3 = VAR6[2];
assign VAR1 = VAR6[1];
assign VAR7 = VAR6[0];
assign VAR9 = ~(|VAR11);
always @(VAR5 or VAR8 or VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai.functional.pp.v | 2,191 | module MODULE1 (
VAR1 ,
VAR17 ,
VAR8 ,
VAR9 ,
VAR12 ,
VAR7 ,
VAR2,
VAR20,
VAR10 ,
VAR11
);
output VAR1 ;
input VAR17 ;
input VAR8 ;
input VAR9 ;
input VAR12 ;
input VAR7 ;
input VAR2;
input VAR20;
input VAR10 ;
input VAR11 ;
wire VAR3 ;
wire VAR6 ;
wire VAR5 ;
wire VAR16;
nor VAR15 (VAR3 , VAR9, VAR17, VAR8 );
nor VAR1... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/iface/ip/SGDMA_dispatcher/fifo_with_byteenables.v | 5,508 | module MODULE1 (
clk,
VAR17,
VAR8,
VAR42,
VAR28,
write,
VAR11,
VAR10,
VAR37,
VAR27,
VAR23,
VAR41
);
parameter VAR43 = 32;
parameter VAR5 = 128;
parameter VAR38 = 7; parameter VAR13 = 1;
input clk;
input VAR17;
input VAR8;
input [VAR43-1:0] VAR42;
input [(VAR43/8)-1:0] VAR28;
input write;
input VAR11; output wire [VAR43... | mit |
leaflabs/rhd2000_dm | rhd2000_dm.v | 9,805 | module MODULE1 #(
parameter VAR3 = 32,
parameter VAR13 = 1,
parameter VAR11 = 0,
parameter VAR9 = 1
)(
input [(16 * VAR3) - 1:0] VAR4,
input VAR1,
input VAR2,
input VAR5,
output reg VAR7,
output reg VAR8
);
reg [7:0] VAR12 [17:0];
reg [7:0] VAR10 [8:0];
integer address = 0;
reg [7:0] VAR6 = 0; | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_clk_wiz_0_0/tutorial_clk_wiz_0_0_clk_wiz.v | 6,474 | module MODULE1
( input VAR38,
output VAR50
);
VAR20 VAR56
(.VAR30 (VAR79),
.VAR77 (VAR38));
wire [15:0] VAR73;
wire VAR62;
wire VAR3;
wire VAR70;
wire VAR28;
wire VAR31;
wire VAR66;
wire VAR47;
wire VAR67;
wire VAR41;
wire VAR40;
wire VAR63;
wire VAR4;
wire VAR64;
wire VAR49;
wire VAR42;
wire VAR35;
wire VAR9;
wire VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp_4.v | 2,339 | module MODULE2 (
VAR9 ,
VAR4 ,
VAR6 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR5,
VAR1
);
output VAR9 ;
input VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR5;
input VAR1;
VAR3 VAR10 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxtp/sky130_fd_sc_hs__sdfxtp.behavioral.v | 2,250 | module MODULE1 (
VAR19 ,
VAR18 ,
VAR2 ,
VAR17 ,
VAR10 ,
VAR9,
VAR8
);
input VAR19 ;
input VAR18 ;
output VAR2 ;
input VAR17 ;
input VAR10 ;
input VAR9;
input VAR8;
wire VAR12 ;
wire VAR3 ;
reg VAR15 ;
wire VAR13 ;
wire VAR22;
wire VAR4;
wire VAR7;
wire VAR16 ;
wire VAR23 ;
wire VAR14 ;
wire VAR21 ;
VAR11 VAR1 (VAR3, VA... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_CKINVDC_SRAM_FF_210930.v | 11,817 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
not (VAR2, VAR1); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi.behavioral.v | 1,516 | module MODULE1 (
VAR5 ,
VAR11,
VAR4,
VAR8
);
output VAR5 ;
input VAR11;
input VAR4;
input VAR8;
supply1 VAR12;
supply0 VAR6;
supply1 VAR9 ;
supply0 VAR1 ;
wire VAR2 ;
wire VAR7;
and VAR3 (VAR2 , VAR11, VAR4 );
nor VAR13 (VAR7, VAR8, VAR2 );
buf VAR10 (VAR5 , VAR7 );
endmodule | apache-2.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/altera_std_synchronizer_nocut.v | 4,868 | module MODULE1 (
clk,
VAR4,
din,
dout
);
parameter VAR1 = 3;
input clk;
input VAR4;
input din;
output dout;
reg VAR3;
reg [VAR1-2:0] VAR2; | gpl-3.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/Coprocesador_CORDIC.v | 9,151 | module MODULE1 #(parameter VAR112 = 32, parameter VAR75=8, parameter VAR38=5, parameter VAR100 = 8, parameter VAR118 = 23,
parameter VAR32 = 9) (
input wire [31:0] VAR1,
input wire VAR15, input wire VAR106, input wire VAR5, input wire VAR123, input wire VAR109, input wire VAR105, input wire VAR25, input wire VAR22, inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtn/sky130_fd_sc_hd__dlrtn.behavioral.v | 2,404 | module MODULE1 (
VAR12 ,
VAR7,
VAR22 ,
VAR20
);
output VAR12 ;
input VAR7;
input VAR22 ;
input VAR20 ;
supply1 VAR18;
supply0 VAR15;
supply1 VAR10 ;
supply0 VAR3 ;
wire VAR13 ;
wire VAR17 ;
reg VAR6 ;
wire VAR9 ;
wire VAR24 ;
wire VAR23 ;
wire VAR16;
wire VAR21 ;
wire VAR5 ;
wire VAR8 ;
wire VAR2 ;
not VAR4 (VAR13 , VA... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_v1_00_a/hdl/verilog/cf_ddsv_intp.v | 9,926 | module MODULE1 (
VAR34,
VAR37,
VAR21,
VAR12,
VAR41,
VAR7,
VAR29,
VAR47,
VAR26,
VAR33,
VAR3,
VAR35,
VAR1,
VAR44,
VAR22,
VAR11,
VAR17,
VAR27,
VAR46,
VAR30);
input VAR34;
output VAR37;
input [95:0] VAR21;
output [13:0] VAR12;
output [13:0] VAR41;
output [13:0] VAR7;
output [13:0] VAR29;
output [13:0] VAR47;
output [13:0] ... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_ddr3_odt_gen.v | 17,824 | module MODULE1
VAR1 = 2,
VAR5 = 1,
VAR31 = 4,
VAR43 = 4
)
(
VAR41,
VAR48,
VAR27,
VAR26,
VAR23,
VAR40,
VAR4,
VAR35,
VAR13,
VAR50,
VAR7,
VAR11
);
localparam integer VAR15 = 2**VAR31;
localparam integer VAR42 = 6; localparam integer VAR30 = 4; localparam integer VAR17 = VAR1 / 2;
input VAR41;
input VAR48;
input [VAR31-1:0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2ai/sky130_fd_sc_hd__o2bb2ai.functional.v | 1,578 | module MODULE1 (
VAR10 ,
VAR12,
VAR8,
VAR3 ,
VAR11
);
output VAR10 ;
input VAR12;
input VAR8;
input VAR3 ;
input VAR11 ;
wire VAR9 ;
wire VAR1 ;
wire VAR5;
nand VAR2 (VAR9 , VAR8, VAR12 );
or VAR4 (VAR1 , VAR11, VAR3 );
nand VAR6 (VAR5, VAR9, VAR1);
buf VAR7 (VAR10 , VAR5 );
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/wb_conmax/wb_conmax_msel.v | 9,501 | module MODULE1(
VAR20, VAR22,
VAR12, req, sel, VAR21
);
parameter [1:0] VAR27 = 2'd0;
input VAR20, VAR22;
input [15:0] VAR12;
input [7:0] req;
output [2:0] sel;
input VAR21;
wire [1:0] VAR29, VAR2, VAR15, VAR10;
wire [1:0] VAR18, VAR24, VAR13, VAR31;
wire [1:0] VAR14;
reg [1:0] VAR6;
wire [7:0] VAR5, VAR16, VAR30, VAR3... | gpl-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_pll_0.v | 2,073 | module MODULE1(
input wire VAR36,
input wire rst,
output wire VAR64,
output wire VAR50
);
VAR2 #(
.VAR49("false"),
.VAR25("100.0 VAR17"),
.VAR21("VAR61"),
.VAR69(1),
.VAR10("100.000000 VAR17"),
.VAR58("0 VAR28"),
.VAR31(50),
.VAR72("0 VAR17"),
.VAR68("0 VAR28"),
.VAR65(50),
.VAR42("0 VAR17"),
.VAR55("0 VAR28"),
.VAR16(... | gpl-3.0 |
walkthetalk/fsref | ip/step_motor/src/step_motor.v | 28,405 | module MODULE1 #(
parameter integer VAR211 = 0,
parameter integer VAR378 = 16,
parameter integer VAR394 = 16,
parameter integer VAR292 = 9,
parameter integer VAR200 = 3,
parameter integer VAR1 = 32, parameter integer VAR253 = 4,
parameter integer VAR154 = 32'hFFFFFFFF,
parameter integer VAR7 = 32'h0
)(
input clk,
input... | gpl-3.0 |
merckhung/zet | cores/speaker/wm8731/speaker_iface.v | 4,122 | module MODULE1
(
input VAR6,
input VAR2,
input signed [15:0] VAR13,
input signed [15:0] VAR1,
output reg signed [15:0] VAR10,
output reg signed [15:0] VAR5,
output reg VAR3,
input VAR12,
input VAR18,
output reg VAR19,
input VAR11
);
reg VAR17;
reg VAR7;
reg VAR16;
reg VAR15;
reg VAR14;
reg VAR9;
reg [15:0] VAR8;
reg [1... | gpl-3.0 |
kyzhai/NUNY | src/hardware/one_new2_bb.v | 5,008 | module MODULE1 (
address,
VAR2,
VAR1);
input [9:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
545/Atari7800 | core/ag_6502/trunk/juke-box/ag_main.v | 7,316 | module MODULE1(input VAR1, input[10:0] VAR7, input VAR9, input VAR4, output[7:0] VAR5, input[7:0] VAR6);
reg[7:0] VAR2[0:2047];
reg[7:0] VAR8;
assign VAR5 = VAR9? VAR8: 8'VAR3; | gpl-2.0 |
azonenberg/antikernel-ipcores | noc/rpcv3/RPCv3Transceiver.v | 16,445 | module MODULE1
parameter VAR30 = 32,
parameter VAR23 = 1,
parameter VAR17 = 16'h8000,
parameter VAR1 = 1
) (
input wire clk,
output reg VAR8,
output reg[VAR30-1:0] VAR25,
input wire VAR10,
input wire VAR4,
input wire[VAR30-1:0] VAR3,
output reg VAR29,
input wire VAR2,
output reg VAR6,
input wire[15:0] VAR11,
input wire... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3/sky130_fd_sc_hd__nor3.pp.symbol.v | 1,314 | module MODULE1 (
input VAR8 ,
input VAR6 ,
input VAR2 ,
output VAR3 ,
input VAR1 ,
input VAR5,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tap/sky130_fd_sc_hdll__tap.pp.blackbox.v | 1,223 | module MODULE1 (
VAR3,
VAR2,
VAR1 ,
VAR4
);
input VAR3;
input VAR2;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi.blackbox.v | 1,400 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR1;
supply1 VAR4;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.behavioral.pp.v | 3,372 | module MODULE1( VAR4, VAR2, VAR5, VAR10, VAR11, VAR6, VAR3, VAR7 );
input VAR11, VAR6, VAR2, VAR5, VAR10;
inout VAR3, VAR7;
output VAR4;
VAR9 VAR1(.VAR4(VAR4),.VAR2(VAR2),.VAR5(VAR5),.VAR10(VAR10),.VAR11(VAR11),.VAR6(VAR6),.VAR3(VAR3),.VAR7(VAR7));
VAR9 VAR8(.VAR4(VAR4),.VAR2(VAR2),.VAR5(VAR5),.VAR10(VAR10),.VAR11(VAR1... | apache-2.0 |
alexforencich/xfcp | example/S10MX_DK/fpga/rtl/fpga_core.v | 17,214 | module MODULE1
(
input wire clk,
input wire rst,
output wire [3:0] VAR178,
input wire VAR258,
input wire VAR158,
output wire [63:0] VAR229,
output wire [7:0] VAR255,
input wire VAR261,
input wire VAR124,
input wire [63:0] VAR205,
input wire [7:0] VAR3,
input wire VAR20,
input wire VAR95,
output wire [63:0] VAR37,
outpu... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_ncrd_timeout.v | 6,427 | module MODULE1 (
VAR15, VAR30, VAR8,
VAR38, VAR42, VAR21, VAR2, VAR33,
VAR17, VAR48, clk, VAR5
);
input VAR38;
input [3:0] VAR42;
input VAR21;
input [3:0] VAR2;
output VAR15;
output [3:0] VAR30;
input VAR33;
input VAR17;
output VAR8;
input [31:0] VAR48; input clk;
input VAR5;
wire VAR22, VAR24, VAR28;
wire [15:0] VAR14... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dmc/bsg_dmc_phy.v | 12,113 | module MODULE5
(input VAR51
,input VAR39
,input [1:0] VAR61
,output logic VAR74
,output logic VAR57);
wire VAR50 = ~VAR51;
logic VAR36;
VAR12 @(posedge VAR50) begin
if(VAR39) begin
VAR36 <= ~VAR36;
if(VAR36) begin
VAR74 <= VAR61[1];
end
else begin
VAR74 <= VAR61[0];
end
VAR57 <= 1'b0;
end
else begin
VAR36 <= 1'b0;
VAR5... | bsd-3-clause |
lbl-cal/StanfordNoC | router/verif/router/ugal_sniffer.v | 5,184 | module MODULE1(
VAR35,
clk, reset, VAR15, VAR26
);
parameter VAR14 = 16;
parameter VAR32 = 1;
parameter VAR30 = 2;
localparam VAR39 = VAR32 * VAR30;
parameter VAR19 = 1;
localparam VAR17 = VAR39 * VAR19;
localparam VAR31 = VAR25(VAR17);
parameter VAR24 = VAR3;
localparam VAR27
= (VAR24 == VAR4) ?
(1 + VAR31 + 1 + 1) :
... | bsd-2-clause |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/NormaliseProdMult.v | 2,223 | module MODULE1(
input [32:0] VAR7,
input [49:0] VAR10,
input VAR4,
input VAR12,
output reg VAR11,
output reg [32:0] VAR9,
output reg [49:0] VAR6
);
parameter VAR1 = 1'b0,
VAR3 = 1'b1;
wire VAR8;
wire [7:0] VAR2;
wire [26:0] VAR5;
assign VAR8 = VAR7[32];
assign VAR2 = VAR7[31:24];
assign VAR5 = {VAR7[23:0]};
always @ (p... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ai/sky130_fd_sc_hdll__o21ai.pp.blackbox.v | 1,367 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR5 ,
VAR7 ,
VAR1,
VAR3,
VAR8 ,
VAR6
);
output VAR4 ;
input VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR1;
input VAR3;
input VAR8 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a_lp.v | 2,419 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR11 ,
VAR6 ,
VAR5,
VAR9,
VAR12 ,
VAR10
);
output VAR1 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR11 ;
input VAR6 ;
input VAR5;
input VAR9;
input VAR12 ;
input VAR10 ;
VAR2 VAR8 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR5(V... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/cores/axis_lfsr_v1_0/src/axis_lfsr.v | 1,110 | module MODULE1 #
(
parameter integer VAR2 = 64
)
(
input wire VAR1,
input wire VAR3,
input wire VAR5,
output wire [VAR2-1:0] VAR7,
output wire VAR10
);
reg [VAR2-1:0] VAR9, VAR4;
reg VAR6, VAR8;
always @(posedge VAR1)
begin
if(~VAR3)
begin
VAR9 <= 64'h5555555555555555;
VAR6 <= 1'b0;
end
else
begin
VAR9 <= VAR4;
VAR6 <=... | gpl-3.0 |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab/alu_beh.v | 1,472 | module MODULE2(VAR3, VAR6, VAR8, VAR4, VAR1);
input [31:0] VAR3, VAR6;
input [2:0] VAR8;
output [31:0] VAR4;
reg [31:0] VAR4;
output VAR1;
reg VAR1;
always @(VAR3 or VAR6 or VAR8)
begin
casez(VAR8)
3'b110: VAR4 = VAR3 - VAR6;
3'b010: VAR4 = VAR3 + VAR6;
3'VAR2: VAR4 = VAR3 & VAR6;
3'VAR7?01: VAR4 = VAR3 | VAR6;
3'VAR7?... | mit |
olajep/oh | src/adi/hdl/library/common/up_pmod.v | 4,428 | module MODULE1 #(
parameter VAR17 = 0) (
input VAR14,
output VAR7,
input [31:0] VAR22,
input VAR6,
input VAR3,
input VAR19,
input [13:0] VAR2,
input [31:0] VAR25,
output reg VAR8,
input VAR23,
input [13:0] VAR10,
output reg [31:0] VAR28,
output reg VAR29);
localparam VAR11 = 32'h00010001;
reg [31:0] VAR1 = 'd0;
reg VAR... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/reorder_queue.v | 12,634 | module MODULE1
parameter VAR82 = 9'd128,
parameter VAR48 = 4'd12,
parameter VAR29 = 512, parameter VAR25 = 5, parameter VAR86 = VAR82/32,
parameter VAR1 = VAR18(VAR86+1),
parameter VAR30 = 2**VAR25,
parameter VAR45 = VAR29/4,
parameter VAR52 = VAR7(VAR45+1),
parameter VAR59 = VAR7(VAR45/VAR86), parameter VAR10 = VAR25 ... | gpl-3.0 |
nickdesaulniers/Omicron | control_unit.v | 6,137 | module MODULE1(
input clk,
input VAR33,
input [3:0] VAR11,
output reg VAR26, output reg VAR2, output reg [10:0] VAR6, output reg VAR13, output reg VAR4, output reg [1:0] VAR17 );
parameter VAR12 = 4'b0000;
parameter VAR28 = 4'b0001;
parameter VAR30 = 4'b0010;
parameter VAR21 = 4'b0011;
parameter VAR31 = 4'b0100;
parame... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.functional.pp.v | 1,611 | module MODULE1( VAR8, VAR12, VAR19, VAR7, VAR13, VAR1, VAR15 );
input VAR12, VAR8, VAR7, VAR13;
inout VAR1, VAR15;
output VAR19;
wire VAR10;
not VAR9( VAR10, VAR12 );
wire VAR20;
not VAR5( VAR20, VAR7 );
wire VAR14;
not VAR4( VAR14, VAR13 );
wire VAR6;
and VAR17( VAR6, VAR10, VAR20, VAR14 );
wire VAR3;
not VAR16( VAR3,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi.behavioral.v | 1,927 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR5,
VAR13
);
output VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR13;
wire VAR4 ;
wire VAR2 ;
wire VAR11;
and VAR9 (VAR4 , VAR7, VAR1 );
nor VAR8 (VAR2 , VAR3, VAR4 );
VAR12 VAR6 (VAR11, VAR2, VAR5, VAR13);
buf VAR14 (VAR10 , VAR11 );
endmodule | apache-2.0 |
donnaware/AGC | rtl/de0/modules/ng_PAR.v | 3,612 | module MODULE1(
input VAR10, input VAR1, input VAR18, input [100:0] VAR15, input [ 5:0] VAR31, input [ 15:0] VAR19, output VAR38, output VAR16 );
wire VAR24 = VAR15[85]; wire VAR4 = VAR15[VAR3(VAR4)]; wire VAR26 = VAR15[36]; wire VAR35 = VAR15[94]; wire VAR37 = VAR15[4]; wire VAR5 = VAR15[13]; wire VAR8 = VAR15[41]; wi... | gpl-3.0 |
jairov4/accel-oil | solution_virtex5/syn/verilog/sample_iterator_next.v | 11,284 | module MODULE1 (
VAR19,
VAR17,
VAR39,
VAR52,
VAR34,
VAR60,
VAR33,
VAR49,
VAR11,
VAR21,
VAR44,
VAR59,
VAR42,
VAR57,
VAR18,
VAR56,
VAR1,
VAR28,
VAR37,
VAR53
);
parameter VAR12 = 1'b1;
parameter VAR45 = 1'b0;
parameter VAR47 = 1'b0;
parameter VAR2 = 32'b1;
parameter VAR55 = 32'b100000;
parameter VAR46 = 32'b101111;
parame... | lgpl-3.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/MULT/MULT_bb.v | 3,474 | module MODULE1 (
VAR2,
VAR1);
input [12:0] VAR2;
output [25:0] VAR1;
endmodule | gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/verilog/axi_vdma_v6_2_axis_dwidth_converter_v1_0_axisc_upsizer.v | 14,845 | module MODULE1 #
(
parameter VAR36 = "VAR41",
parameter integer VAR15 = 32,
parameter integer VAR7 = 96,
parameter integer VAR2 = 1,
parameter integer VAR40 = 1,
parameter integer VAR11 = 1,
parameter integer VAR32 = 3,
parameter [31:0] VAR44 = 32'hFF ,
parameter integer VAR55 = 3 )
(
input wire VAR48,
input wire VAR23... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor3/sky130_fd_sc_hs__xnor3.symbol.v | 1,253 | module MODULE1 (
input VAR2,
input VAR6,
input VAR4,
output VAR5
);
supply1 VAR1;
supply0 VAR3;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/ecc/ecc_merge_enc.v | 5,931 | module MODULE1
parameter VAR12 = 100,
parameter VAR3 = 64,
parameter VAR27 = 72,
parameter VAR6 = 4,
parameter VAR8 = 1,
parameter VAR1 = 64,
parameter VAR14 = 72,
parameter VAR19 = 8,
parameter VAR15 = 4
)
(
VAR10, VAR21,
clk, rst, VAR2, VAR20, VAR13, VAR9, VAR26
);
input clk;
input rst;
input [2*VAR15*VAR3-1:0] VAR2;... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.functional.v | 1,390 | module MODULE1( VAR13, VAR8, VAR12, VAR14, VAR5 );
input VAR14, VAR5, VAR13, VAR12;
output VAR8;
wire VAR7;
not VAR2( VAR7, VAR14 );
wire VAR9;
not VAR6( VAR9, VAR5 );
wire VAR3;
not VAR11( VAR3, VAR13 );
wire VAR10;
not VAR4( VAR10, VAR12 );
or VAR1( VAR8, VAR7, VAR9, VAR3, VAR10 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/source/pcie_blk_ll_tx_arb.v | 10,704 | module MODULE1
(
input clk,
input VAR33,
output reg [63:0] VAR22,
output reg VAR38,
output reg VAR29,
output [7:0] VAR30,
output reg VAR26 = 1'b1,
output reg VAR11 = 1'b1,
input VAR31,
input [63:0] VAR9,
input [7:0] VAR25,
input VAR14,
input VAR6,
input VAR41,
input VAR8,
output reg VAR34 = 1'b1,
output VAR39,
input [6... | lgpl-3.0 |
ineganov/bare_system | hard/alu.v | 4,418 | module MODULE1( input [6:0] VAR25,
input [31:0] VAR14,
input [31:0] VAR9,
input [4:0] VAR24,
output [31:0] VAR3,
output VAR26 );
wire VAR11 = VAR25[3]; wire [31:0] VAR12; wire [31:0] VAR28 = VAR14 + VAR12 + VAR11;
wire [31:0] VAR23;
VAR2 VAR4( .VAR17(VAR25[3]),
.VAR21( VAR9),
.VAR7(~VAR9),
.VAR3 (VAR12) );
wire [4:0] V... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/ui/ui_rd_data.v | 18,487 | module MODULE1 #
(
parameter VAR40 = 100,
parameter VAR9 = 256,
parameter VAR48 = "VAR78",
parameter VAR89 = 2 ,
parameter VAR53 = "VAR4"
)
(
VAR70, VAR95, VAR23, VAR82,
VAR16, VAR47, VAR57, VAR29,
rst, clk, VAR72, VAR32, VAR69, VAR22,
VAR88, VAR35, VAR38
);
input rst;
input clk;
output wire VAR70;
output wire [3:0] VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3.symbol.v | 1,284 | module MODULE1 (
input VAR7,
input VAR2,
input VAR5,
output VAR4
);
supply1 VAR1;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/vga/vga_synch.v | 1,234 | module MODULE1(
input clk,
output reg VAR2,
output reg VAR5,
input wire VAR3
);
localparam VAR4 = 10'd106;
localparam VAR7 = 10'd159;
localparam VAR6 = 10'd896;
reg [9:0] VAR1;
begin
begin
end
begin
end
begin
end | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits_block.v | 1,241 | module MODULE1
(
VAR7,
VAR5
);
input [17:0] VAR7; output [8:0] VAR5;
wire [8:0] VAR1;
VAR6 VAR4 (.VAR3(VAR7), .VAR2(VAR1) );
assign VAR5 = VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrbp/sky130_fd_sc_ms__dfrbp.behavioral.pp.v | 2,354 | module MODULE1 (
VAR1 ,
VAR21 ,
VAR19 ,
VAR11 ,
VAR14,
VAR2 ,
VAR9 ,
VAR22 ,
VAR8
);
output VAR1 ;
output VAR21 ;
input VAR19 ;
input VAR11 ;
input VAR14;
input VAR2 ;
input VAR9 ;
input VAR22 ;
input VAR8 ;
wire VAR5 ;
wire VAR13 ;
reg VAR17 ;
wire VAR23 ;
wire VAR6;
wire VAR15 ;
wire VAR12 ;
wire VAR20 ;
wire VAR10 ;... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_multiplexer_128.v | 16,560 | module MODULE1
parameter VAR45 = 128,
parameter VAR49 = 12,
parameter VAR81 = 5, parameter VAR69 = "VAR105"
)
(
input VAR121,
input VAR20,
input [VAR49-1:0] VAR117, input [(VAR49*VAR77)-1:0] VAR106, input [(VAR49*VAR15)-1:0] VAR70, input [(VAR49*VAR45)-1:0] VAR108, output [VAR49-1:0] VAR47, output [VAR49-1:0] VAR2,
inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probec_p/sky130_fd_sc_hvl__probec_p.pp.symbol.v | 1,286 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR3 ,
input VAR4,
input VAR6,
input VAR1
);
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/arp_eth_tx.v | 13,474 | module MODULE1 #
(
parameter VAR16 = 8,
parameter VAR28 = (VAR16>8),
parameter VAR19 = (VAR16/8)
)
(
input wire clk,
input wire rst,
input wire VAR23,
output wire VAR21,
input wire [47:0] VAR17,
input wire [47:0] VAR9,
input wire [15:0] VAR6,
input wire [15:0] VAR20,
input wire [15:0] VAR11,
input wire [15:0] VAR14,
in... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_muls.v | 9,611 | module MODULE1 (
clk,
VAR25,
VAR37,
VAR9,
VAR43,
VAR13);
parameter VAR15 = 16;
parameter VAR3 = VAR15 - 1;
input clk;
input [15:0] VAR25;
input [15:0] VAR37;
output [15:0] VAR9;
input [VAR3:0] VAR43;
output [VAR3:0] VAR13;
reg [VAR3:0] VAR39 = 'd0;
reg VAR26 = 'd0;
reg [14:0] VAR12 = 'd0;
reg [14:0] VAR19 = 'd0;
reg [V... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/ddr3_s4_amphy_phy.v | 33,505 | module MODULE1 (
VAR133,
VAR125,
VAR27,
VAR107,
VAR121,
VAR73,
VAR48,
VAR45,
VAR49,
VAR68,
VAR115,
VAR1,
VAR82,
VAR116,
VAR100,
VAR56,
VAR134,
VAR117,
VAR76,
VAR57,
VAR94,
VAR103,
VAR20,
VAR41,
VAR58,
VAR36,
VAR43,
VAR89,
VAR104,
VAR124,
VAR25,
VAR122,
VAR17,
VAR38,
VAR55,
VAR131,
VAR9,
VAR105,
VAR83,
VAR92,
VAR50,
VAR... | lgpl-3.0 |
bargei/NoC264 | NoC264_3x3/mkOutPortFIFO.v | 20,764 | module MODULE1(VAR62,
VAR80,
VAR85,
VAR72,
VAR77,
VAR68,
VAR46,
VAR8,
VAR14,
VAR65,
VAR16,
VAR11,
VAR60,
VAR66,
VAR67,
VAR37,
VAR35);
input VAR62;
input VAR80;
input [2 : 0] VAR85;
input VAR72;
output VAR77;
input VAR68;
output VAR46;
output [2 : 0] VAR8;
output VAR14;
output VAR65;
output VAR16;
output VAR11;
output V... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_mclk_pad.v | 4,607 | module MODULE1(
VAR24, VAR22,
VAR21,
VAR19, VAR18, VAR17, VAR23, VAR8, VAR26,
VAR4, VAR3, VAR10, VAR2, VAR11, VAR13, VAR9
);
inout VAR21;
output VAR22; output VAR24;
input VAR9; input [8:1] VAR13; input [8:1] VAR11; input VAR2; input VAR10; input VAR3; input VAR4; input VAR26; input VAR8; input VAR23; input VAR17; inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.v | 2,234 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR9 ,
VAR4 ,
VAR10,
VAR3,
VAR2 ,
VAR1
);
output VAR7 ;
output VAR6 ;
input VAR9 ;
input VAR4 ;
input VAR10;
input VAR3;
input VAR2 ;
input VAR1 ;
VAR5 VAR8 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODUL... | apache-2.0 |
zYeoman/32BIT-MIPS-CPU | pipeline/IF.v | 1,234 | module MODULE1(
input clk, rst, VAR7,
input [31:0] VAR2,
input [2:0] VAR4,
input VAR3,
VAR8,
input [31:0] VAR9,
VAR5,
input [25:0] VAR1,
output reg [31:0] VAR6
);
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR6 <= 0;
end else if(VAR7)
VAR6 <= {VAR6[31], {31{1'b0}}};
end
else if (VAR3) begin
if(VAR8) begi... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/011J1G2/hdl/periferico_BT/peripheral_bt.v | 2,037 | module MODULE1(clk , rst , din , VAR11 , addr , rd , wr, dout, VAR17, VAR5 );
input clk;
input rst;
input [15:0]din;
input VAR11;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
output VAR5;
output VAR17;
reg [5:0] VAR7;
reg VAR16;
reg [7:0] VAR10; wire [7:0] VAR12;
wire VAR3; wire VAR4;
wire VAR20;
VAR6 VA... | gpl-3.0 |
alexforencich/verilog-ethernet | example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v | 2,604 | module MODULE1 #(
parameter VAR4=1, parameter VAR2=3, parameter VAR3=125000 )(
input wire clk,
input wire rst,
input wire [VAR4-1:0] in,
output wire [VAR4-1:0] out
);
reg [23:0] VAR1 = 24'd0;
reg [VAR2-1:0] VAR6[VAR4-1:0];
reg [VAR4-1:0] state;
assign out = state;
integer VAR5;
always @(posedge clk) begin
if (rst) begi... | mit |
yanhongwang/ColorImage | Divider/Divider.v | 1,951 | module MODULE2
(
input[ VAR9 - 1 : 0 ]VAR6,
input[ VAR9 - 1 : 0 ]VAR8,
output reg[ VAR9 - 1 : 0 ]VAR7, output reg[ VAR9 - 1 : 0 ]VAR3
);
integer VAR10;
reg[ VAR9 - 1 : 0 ]VAR4; reg[ VAR9 : 0 ]VAR2;
reg[ VAR9 - 1 : 0 ]VAR5;
always@( VAR6 or VAR8 )
begin
VAR4 = VAR6;
VAR5 = VAR8;
VAR2 = { VAR9'h00, 1'b0 };
for( VAR10 = 0... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_p_dst_rows_V.v | 2,987 | module MODULE2 (
clk,
VAR18,
VAR19,
VAR1,
VAR16);
parameter VAR10 = 32'd12;
parameter VAR17 = 32'd2;
parameter VAR23 = 32'd3;
input clk;
input [VAR10-1:0] VAR18;
input VAR19;
input [VAR17-1:0] VAR1;
output [VAR10-1:0] VAR16;
reg[VAR10-1:0] VAR11 [0:VAR23-1];
integer VAR3;
always @ (posedge clk)
begin
if (VAR19)
begin
f... | gpl-3.0 |
fisherdj/avgai | quartus/avgai/clocking.v | 1,151 | module MODULE2(input clk, VAR4, output reg VAR1);
reg [9:0] VAR3;
always @(posedge clk) begin
if (VAR1 == VAR4)
VAR3 <= 0;
end
else if (VAR3 != -10'b1)
VAR3 <= VAR3+1;
else if (VAR3 == -10'b1)
VAR1 <= VAR4;
end
endmodule
module MODULE1(input clk, output VAR5);
parameter VAR2 = 25;
reg [VAR2-1:0] VAR6 = 0;
assign VAR5 =... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/minimac/rtl/minimac.v | 3,135 | module MODULE1 #(
parameter VAR42 = 4'h0
) (
input VAR49,
input VAR55,
input [13:0] VAR23,
input VAR26,
input [31:0] VAR51,
output [31:0] VAR47,
output VAR22,
output VAR41,
output [31:0] VAR56,
output [2:0] VAR37,
output VAR45,
output VAR15,
input VAR3,
output [31:0] VAR6,
output [31:0] VAR52,
output [2:0] VAR4,
output... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf_8.v | 2,050 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR8,
VAR4,
VAR7 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR8;
input VAR4;
input VAR7 ;
input VAR6 ;
VAR2 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR8;
supply0 VAR4;... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/ACA_I_N32_Q8.v | 2,190 | module MODULE1(
input [31:0] VAR14,
input [31:0] VAR12,
output [32:0] VAR24
);
wire [8:0] VAR5,VAR3,VAR19,VAR17,VAR7,VAR16,VAR26,VAR1,VAR22,VAR10;
wire [8:0] VAR2,VAR9,VAR20,VAR28,VAR13,VAR18,VAR6,VAR4,VAR25;
wire [8:0] VAR15,VAR11,VAR8,VAR23,VAR21,VAR27;
assign VAR5[8:0] = VAR14[7:0] + VAR12[7:0];
assign VAR3[8:0] = V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3_4.v | 2,175 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR9 ,
VAR2 ,
VAR10,
VAR6,
VAR3 ,
VAR7
);
output VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR2 ;
input VAR10;
input VAR6;
input VAR3 ;
input VAR7 ;
VAR8 VAR1 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_20.behavioral.v | 1,121 | module MODULE1( VAR1, VAR3 );
input VAR1;
output VAR3;
VAR2 VAR5(.VAR1(VAR1),.VAR3(VAR3));
VAR2 VAR4(.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o.behavioral.v | 1,585 | module MODULE1 (
VAR3 ,
VAR15,
VAR6,
VAR11,
VAR14,
VAR1
);
output VAR3 ;
input VAR15;
input VAR6;
input VAR11;
input VAR14;
input VAR1;
supply1 VAR4;
supply0 VAR7;
supply1 VAR13 ;
supply0 VAR9 ;
wire VAR12 ;
wire VAR5;
and VAR10 (VAR12 , VAR15, VAR6 );
or VAR2 (VAR5, VAR14, VAR11, VAR12, VAR1);
buf VAR8 (VAR3 , VAR5 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi.symbol.v | 1,369 | module MODULE1 (
input VAR7,
input VAR2,
input VAR3,
input VAR1,
output VAR9
);
supply1 VAR4;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
wyvernSemi/lm32fpga | HDL/rtl/CMD_Decode.v | 18,916 | module MODULE1(
VAR105, VAR87, VAR66, VAR31, VAR99,
VAR29,VAR45,
VAR83, VAR72,
VAR57, VAR81, VAR104,
VAR18, VAR69, VAR14,
VAR92, VAR20, VAR65, VAR79, VAR27, VAR2,
VAR7, VAR22, VAR42, VAR17, VAR94, VAR95,
VAR10, VAR49, VAR3, VAR61, VAR48,
VAR103, VAR12,
VAR33, VAR8, VAR67,
VAR90, VAR56
);
input [7:0] VAR105;
input VAR66... | gpl-3.0 |
linuxbest/lzs | jhash/rtl/verilog/jhash_core.v | 4,478 | module MODULE1(
VAR22, VAR16, VAR13, VAR5,
clk, rst, VAR21, VAR34, VAR23, VAR29,
VAR28, VAR20, VAR33
);
input clk, rst, VAR21;
input [31:0] VAR34,
VAR23,
VAR29;
input VAR28;
input VAR20;
input [1:0] VAR33;
output VAR22;
output [31:0] VAR16;
output VAR13;
output VAR5;
reg VAR13;
reg VAR22;
wire [31:0] VAR9; wire [31:0] ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv_8.v | 1,995 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR7,
VAR5,
VAR2 ,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR7;
input VAR5;
input VAR2 ;
input VAR4 ;
VAR6 VAR1 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR7;
supply0 VAR5;... | apache-2.0 |
romovs/xula-lib-verilog | SdramCtrl.v | 38,105 | module MODULE1 (VAR68, VAR32, VAR49, VAR85, VAR56, VAR36, VAR122, VAR74, VAR97,
VAR17, VAR27, VAR71, VAR116, VAR125, VAR29, VAR95, VAR37, VAR80,
VAR128, VAR22, VAR89, VAR137, VAR113, VAR47);
parameter real VAR8 = 12.0; parameter VAR96 = 0;
localparam VAR4 = 1; localparam VAR53 = 10000; localparam VAR2 = 1;
localparam V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2/sky130_fd_sc_hs__and2.symbol.v | 1,224 | module MODULE1 (
input VAR1,
input VAR2,
output VAR4
);
supply1 VAR5;
supply0 VAR3;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_dram/phy/mig_7series_v2_3_ddr_mc_phy_wrapper.v | 71,915 | module MODULE1 #
(
parameter VAR213 = 100, parameter VAR356 = 2500, parameter VAR344 = "VAR291", parameter VAR218 = "VAR448", parameter VAR489 = "VAR454", parameter VAR176 = "VAR129",
parameter VAR393 = 1,
parameter VAR245 = 4, parameter VAR328 = 1, parameter VAR297 = 3, parameter VAR433 = 1, parameter VAR374 = 1, para... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp.behavioral.pp.v | 2,370 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR5 ,
VAR14 ,
VAR10 ,
VAR4,
VAR9,
VAR20 ,
VAR23
);
output VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR14 ;
input VAR10 ;
input VAR4;
input VAR9;
input VAR20 ;
input VAR23 ;
wire VAR1 ;
wire VAR25 ;
reg VAR15 ;
wire VAR22 ;
wire VAR11;
wire VAR18;
wire VAR16;
wire VAR17 ;
wire VAR13 ;
wire ... | apache-2.0 |
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