repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
kyzhai/NUNY | src/hardware/sun.v | 6,333 | module MODULE1 (
address,
VAR50,
VAR40);
input [11:0] address;
input VAR50;
output [11:0] VAR40;
tri1 VAR50;
wire [11:0] VAR17;
wire [11:0] VAR40 = VAR17[11:0];
VAR5 VAR24 (
.VAR7 (address),
.VAR38 (VAR50),
.VAR32 (VAR17),
.VAR46 (1'b0),
.VAR18 (1'b0),
.VAR33 (1'b1),
.VAR45 (1'b0),
.VAR36 (1'b0),
.VAR10 (1'b1),
.VAR3 (... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai_1.v | 2,424 | module MODULE2 (
VAR10 ,
VAR4 ,
VAR3 ,
VAR11 ,
VAR5 ,
VAR9 ,
VAR8,
VAR1,
VAR2 ,
VAR7
);
output VAR10 ;
input VAR4 ;
input VAR3 ;
input VAR11 ;
input VAR5 ;
input VAR9 ;
input VAR8;
input VAR1;
input VAR2 ;
input VAR7 ;
VAR12 VAR6 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR8(... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/26bit/BinaryKOA/ks10.v | 1,452 | module MODULE1(VAR8, VAR13, VAR10);
input wire [9:0] VAR8;
input wire [9:0] VAR13;
output wire [18:0] VAR10;
wire [2:0] VAR7;
wire [14:0] VAR11;
wire [14:0] VAR5;
wire [7:0] VAR3;
wire [7:0] VAR12;
VAR1 VAR6(VAR8[7:0], VAR13[7:0], VAR11);
VAR9 VAR4(VAR8[9:8], VAR13[9:8], VAR7);
assign VAR3[1:0] = VAR8[9:8] ^ VAR8[1:0];... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/rtl_model/cur_mb_yuv.v | 8,235 | module MODULE1 (
clk ,
VAR4 ,
VAR17 ,
VAR31 ,
VAR22 ,
VAR23 ,
VAR26 ,
VAR2 ,
VAR16 ,
VAR9 ,
VAR1
);
parameter VAR14 = "./VAR15/VAR6.VAR3" ;
input clk ; input VAR4 ; input VAR17 ; output VAR31 ; input VAR22 ; input VAR23 ; input [1 : 0] VAR26 ; input [4 : 0] VAR9 ; input [3 : 0] VAR2 ; input [3 : 0] VAR16 ; output [VAR2... | gpl-3.0 |
TheMadSocrates/vercpu-project | rtl/fpga/pc_system.v | 2,267 | module MODULE1(
input wire [ 7 : 0] VAR6,
input wire VAR7,
input wire clk,
input wire VAR15,
output wire [ 7 : 0] VAR4,
output wire [ 3 : 0] VAR22,
output wire [ 6 : 0] VAR23
);
wire VAR8;
wire [ 7 : 0] VAR19, VAR26, VAR14, VAR24;
wire [15 : 0] VAR1;
assign VAR8 = clk;
VAR17 VAR12 (
.VAR18(VAR1),
.clk(clk),
.VAR15(VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o_1.v | 2,355 | module MODULE1 (
VAR11 ,
VAR9 ,
VAR6 ,
VAR2 ,
VAR1 ,
VAR3,
VAR4,
VAR5 ,
VAR8
);
output VAR11 ;
input VAR9 ;
input VAR6 ;
input VAR2 ;
input VAR1 ;
input VAR3;
input VAR4;
input VAR5 ;
input VAR8 ;
VAR10 VAR7 (
.VAR11(VAR11),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4/sky130_fd_sc_hdll__and4.functional.v | 1,304 | module MODULE1 (
VAR6,
VAR7,
VAR3,
VAR2,
VAR4
);
output VAR6;
input VAR7;
input VAR3;
input VAR2;
input VAR4;
wire VAR5;
and VAR8 (VAR5, VAR7, VAR3, VAR2, VAR4 );
buf VAR1 (VAR6 , VAR5 );
endmodule | apache-2.0 |
HarmonInstruments/hififo | hdl/hififo.v | 10,994 | module MODULE1
(
output [VAR44-1:0] VAR140,
output [VAR44-1:0] VAR112,
input [VAR44-1:0] VAR114,
input [VAR44-1:0] VAR160,
input VAR70,
input VAR149,
input VAR72,
output VAR41,
input [9*VAR44-1:0] VAR158,
input [VAR44-1:0] VAR96,
input [16*VAR44-1:0] VAR68,
output [16*VAR44-1:0] VAR42,
output [VAR44-1:0] VAR107,
input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32oi/sky130_fd_sc_hd__a32oi.behavioral.v | 1,711 | module MODULE1 (
VAR5 ,
VAR9,
VAR7,
VAR1,
VAR6,
VAR17
);
output VAR5 ;
input VAR9;
input VAR7;
input VAR1;
input VAR6;
input VAR17;
supply1 VAR15;
supply0 VAR13;
supply1 VAR2 ;
supply0 VAR12 ;
wire VAR8 ;
wire VAR3 ;
wire VAR10;
nand VAR11 (VAR8 , VAR7, VAR9, VAR1 );
nand VAR4 (VAR3 , VAR17, VAR6 );
and VAR16 (VAR10, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s.blackbox.v | 1,324 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR5;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/ptp_perout.v | 10,488 | module MODULE1 #
(
parameter VAR30 = 1,
parameter VAR68 = 48'h0,
parameter VAR64 = 30'h0,
parameter VAR16 = 16'h0000,
parameter VAR59 = 48'd1,
parameter VAR57 = 30'd0,
parameter VAR22 = 16'h0000,
parameter VAR65 = 48'h0,
parameter VAR45 = 30'd1000,
parameter VAR13 = 16'h0000
)
(
input wire clk,
input wire rst,
input wi... | mit |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T14-regreset/regreset.v | 1,353 | module MODULE1(input wire clk, output wire [3:0] VAR4);
parameter VAR12 = 23; parameter VAR5 = 4'b1001; parameter VAR8 = 4'b0111;
wire VAR14;
wire [3:0] VAR15;
wire [3:0] VAR2;
reg rst = 0;
always @(posedge(VAR14))
rst <= 1;
register #(.VAR13(VAR5))
VAR10 (
.clk(VAR14),
.rst(rst),
.din(VAR2),
.dout(VAR15)
);
register #... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2.pp.blackbox.v | 1,274 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR5,
VAR7,
VAR6 ,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR7;
input VAR6 ;
input VAR2 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dmc/bsg_dmc.v | 11,464 | module MODULE1
import VAR22::*;
import VAR2::*;
,parameter VAR16( VAR161 )
,parameter VAR16( VAR67 ) ,parameter VAR16( VAR132 ) ,parameter VAR16( VAR127 ) ,parameter VAR16( VAR43 ) ,parameter VAR16( VAR3 ) ,localparam VAR38 = VAR67 >> 3
,localparam VAR87 = VAR127 << 1
,localparam VAR166 = (VAR127 >> 3) << 1
,localparam... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtp/sky130_fd_sc_hd__dlxtp.behavioral.pp.v | 1,841 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR8,
VAR4,
VAR1,
VAR11 ,
VAR7
);
output VAR10 ;
input VAR3 ;
input VAR8;
input VAR4;
input VAR1;
input VAR11 ;
input VAR7 ;
wire VAR13 ;
wire VAR14;
wire VAR5 ;
reg VAR2 ;
wire VAR12 ;
VAR15 VAR6 (VAR13 , VAR5, VAR14, VAR2, VAR4, VAR1);
buf VAR9 (VAR10 , VAR13 );
assign VAR12 = ( VAR4 =... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio_macro/sky130_fd_io__top_sio_macro.symbol.v | 2,860 | module MODULE1 (
input VAR41 ,
input [1:0] VAR16 ,
output [1:0] VAR29 ,
input [1:0] VAR4 ,
output [1:0] VAR26 ,
input [1:0] VAR8 ,
inout [1:0] VAR28 ,
inout [1:0] VAR36 ,
inout [1:0] VAR15 ,
inout [1:0] VAR39 ,
inout VAR14 ,
inout VAR24 ,
input [2:0] VAR3 ,
input [2:0] VAR34 ,
input VAR42 ,
input VAR22 ,
input [1:0] VA... | apache-2.0 |
tommythorn/yari | Icarus/rtl/pll.v | 1,210 | module MODULE2(input wire VAR5,
output wire VAR1,
output wire VAR2,
output wire VAR3,
output wire VAR4);
assign VAR1 = VAR5;
assign VAR2 = VAR5;
assign VAR3 = 1;
assign VAR4 = VAR5;
endmodule
module MODULE1(input wire VAR5,
output wire VAR1,
output wire VAR2,
output wire VAR3,
output wire VAR4);
assign VAR1 = VAR5;
ass... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_pcie_pipe_misc.v | 8,299 | module MODULE1 #
(
parameter VAR1 = 0 )
(
input wire VAR12 , input wire VAR24 , input wire VAR23 , input wire VAR10 , input wire [2:0] VAR9 , input wire VAR21 ,
output wire VAR30 , output wire VAR7 , output wire VAR28 , output wire VAR29 , output wire [2:0] VAR8 , output wire VAR6 ,
input wire VAR15 , input wire VAR13 ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111ai/sky130_fd_sc_hs__o2111ai.symbol.v | 1,365 | module MODULE1 (
input VAR5,
input VAR6,
input VAR7,
input VAR2,
input VAR8,
output VAR1
);
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.behavioral.pp.v | 3,162 | module MODULE1( VAR6, VAR4, VAR7, VAR2, VAR1, VAR9, VAR5 );
input VAR4, VAR2, VAR7;
inout VAR9, VAR5;
output VAR1, VAR6;
VAR10 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2),.VAR1(VAR1),.VAR9(VAR9),.VAR5(VAR5));
VAR10 VAR8(.VAR6(VAR6),.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2),.VAR1(VAR1),.VAR9(VAR9),.VAR5(VAR5)); | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_decoder_dor.v | 2,938 | module MODULE1
,parameter VAR28=VAR29
,parameter VAR22=0 , parameter int VAR2[VAR28:0] = '{ 5, 4, 0 }
, parameter VAR11=2*VAR29+1
)
(input [VAR2[VAR29]-1:0] VAR4
, input [VAR2[VAR29]-1:0] VAR12
, output [VAR11-1:0] VAR34
);
genvar VAR27;
logic [VAR29-1:0] VAR18, VAR23, VAR5;
for (VAR27 = 0; VAR27 < VAR29; VAR27=VAR27+1... | bsd-3-clause |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/addr_gen.v | 5,993 | module MODULE1(
clk,
rst,
VAR3,
VAR7,
VAR14,
VAR5,
VAR2,
VAR11,
VAR10,
VAR4
);
input clk;
input rst;
input VAR3;
input VAR7;
input VAR2;
output[23:0] VAR14;
output[7:0] VAR5;
output[4:0] VAR11;
output VAR10;
output VAR4;
reg VAR4;
reg [7:0] VAR8;
reg [1:0] VAR15;
reg VAR1;
reg VAR13;
reg VAR6;
reg VAR9;
wire [1:0] VAR1... | lgpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/enet_if/ethernet_controller.v | 17,677 | module MODULE1 #(parameter VAR117 = 48'h001F293A10FD,VAR105 = 48'hAABBCCDDEEFF,VAR123 = 16'd1024,VAR106=48'hAABBCCDDEEFF)
(
input VAR32,
input VAR14,
input VAR82,
input VAR24,
output VAR80,
input VAR60,
output [7:0] VAR44,
output VAR79,
output VAR76,
output VAR21,
input [7:0] VAR49,
input VAR40,
input VAR8,
input VAR65... | mit |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_compare.v | 8,167 | module MODULE1
(
input VAR32,
input VAR68,
input VAR3,
input [17:0] VAR59,
input [17:0] VAR19,
input [17:0] VAR26,
input [17:0] VAR56,
input [3:0] VAR60,
input [26:0] VAR15,
input [26:0] VAR48,
input [26:0] VAR58,
input [26:0] VAR46,
input VAR33,
input [2:0] VAR51,
input VAR70,
input VAR54,
output [3:0] VAR28,
output r... | gpl-3.0 |
skarpenko/ultiparc | rtl/src/fabric2_mswitch.v | 6,140 | module MODULE1 #(
parameter VAR6 = 11
)
(
VAR29,
VAR24, VAR5, VAR3, VAR38, VAR15, VAR33, VAR39,
VAR42, VAR28, VAR14, VAR9, VAR1, VAR31, VAR37,
VAR17, VAR41, VAR22, VAR2, VAR43, VAR45, VAR30,
VAR26, VAR25, VAR8, VAR27, VAR13, VAR19, VAR20,
VAR44, VAR10, VAR34, VAR40, VAR11, VAR4, VAR16,
VAR46, VAR32, VAR18, VAR47, VAR35... | bsd-2-clause |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361_rx.v | 24,663 | module MODULE1 (
VAR105,
VAR110,
VAR54,
VAR75,
VAR101,
VAR70,
VAR3,
VAR68,
VAR8,
VAR99,
VAR44,
VAR4,
VAR53,
VAR66,
VAR72,
VAR31,
VAR1,
VAR111,
VAR100,
VAR117,
VAR2,
VAR141,
VAR23,
VAR129,
VAR63,
VAR142,
VAR77,
VAR89,
VAR27,
VAR81,
VAR56,
VAR62,
VAR11,
VAR147,
VAR136,
VAR98,
VAR88,
VAR29,
VAR131);
parameter VAR114 = 0;
... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/mem_stage.v | 6,914 | module MODULE1 (
input wire clk,
input wire reset,
input wire VAR14,
input wire VAR16,
output wire VAR48,
output wire [VAR35] VAR46,
input wire [VAR35] VAR2,
output wire [VAR5] VAR45,
output wire VAR37,
output wire VAR31,
output wire [VAR35] VAR42,
input wire [VAR35] VAR41,
input wire VAR24,
input wire VAR8,
output wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxbp/sky130_fd_sc_ls__sedfxbp.blackbox.v | 1,432 | module MODULE1 (
VAR6 ,
VAR5,
VAR11,
VAR10 ,
VAR9 ,
VAR7,
VAR1
);
output VAR6 ;
output VAR5;
input VAR11;
input VAR10 ;
input VAR9 ;
input VAR7;
input VAR1;
supply1 VAR2;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
manu3193/GatoTDD | verificador_gato.v | 5,051 | module MODULE1(
VAR8,
VAR12,
VAR14,
VAR6,
VAR17,
VAR4,
VAR15,
VAR18,
VAR19,
VAR5,
VAR10,
VAR7,
VAR16,
VAR11,
VAR9,
VAR2,
VAR13,
VAR3,
VAR1
);
input VAR8;
input [1:0] VAR10, VAR7, VAR16, VAR11, VAR9, VAR2, VAR13, VAR3, VAR1;
output reg VAR12, VAR14, VAR6, VAR17, VAR4, VAR15;
output reg [1:0] VAR18, VAR19, VAR5;
always @... | mit |
anderson1008/NOCulator | hring/hw/buffered/src/c_crossbar.v | 4,350 | module MODULE1
(VAR15, VAR23, VAR20);
parameter VAR9 = 5;
parameter VAR1 = 5;
parameter VAR14 = 32;
parameter VAR4 = VAR12;
input [0:VAR9*VAR1-1] VAR15;
input [0:VAR9*VAR14-1] VAR23;
output [0:VAR1*VAR14-1] VAR20;
wire [0:VAR1*VAR14-1] VAR20;
wire [0:VAR1*VAR9-1] VAR21;
VAR6
.VAR18(VAR9))
VAR17
(.VAR5(VAR15),
.VAR7(VAR... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_read_en_rx.v | 2,282 | module MODULE1 (
address,
VAR5,
clk,
VAR3,
VAR2,
VAR9,
VAR6,
VAR8
)
;
output VAR6;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR3;
input VAR2;
input [ 31: 0] VAR9;
wire VAR7;
reg VAR1;
wire VAR6;
wire VAR4;
wire [ 31: 0] VAR8;
assign VAR7 = 1;
assign VAR4 = {1 {(address == 0)}} & VAR1;
a... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/oq_regs_eval_empty.v | 3,574 | module MODULE1
parameter VAR24 = 13,
parameter VAR5 = 8,
parameter VAR14 = 2,
parameter VAR9 = 8,
parameter VAR11 = VAR25(VAR9),
parameter VAR15 = 11,
parameter VAR23 = VAR15-VAR25(VAR5),
parameter VAR8 = 2048/VAR5, parameter VAR17 = 60/VAR5 + 1,
parameter VAR3 = VAR25((2**VAR24)/VAR17)
)
(
input VAR19,
input [VAR11-1:... | mit |
aj-michael/Digital-Systems | Lab6-Part2/ControllerI2C.v | 3,590 | module MODULE1(VAR20,VAR27,VAR7,VAR28,VAR21,VAR19,VAR17,VAR15,VAR30,VAR8);
input VAR20, VAR27, VAR7, VAR28;
output reg VAR21, VAR19, VAR17, VAR15, VAR30, VAR8;
parameter VAR16 = 3'd0;
parameter VAR26 = 3'd1;
parameter VAR5 = 3'd2;
parameter VAR24 = 3'd3;
parameter VAR22 = 3'd4;
parameter VAR18 = 3'd5;
parameter VAR9 = ... | mit |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/n64adv_controller.v | 9,943 | module MODULE1 (
VAR40,
VAR35,
VAR3,
VAR13,
VAR18,
VAR43,
VAR19,
VAR6,
VAR9,
VAR37,
VAR17,
VAR27,
VAR49,
VAR51,
VAR31
);
parameter [11:0] VAR42 = 12'h000;
input [2:0] VAR40;
inout VAR35;
input [2:0] VAR3;
input VAR13;
input [12:0] VAR18;
input [ 7:0] VAR43;
output reg VAR19;
output reg [68:0] VAR6;
input VAR9;
output [... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_dp_maca_r.v | 4,145 | module MODULE1(
VAR19, VAR24, VAR7,
VAR1, VAR18, VAR13,
VAR23, VAR29, VAR28, VAR27,
VAR22, VAR10
);
output [129:0] VAR19; output VAR24;
output VAR7;
input VAR1; input VAR18; input VAR13; input VAR23; input VAR29;
input [129:0] VAR28;
input VAR27;
input VAR22;
input VAR10;
wire VAR6;
wire [129:0] VAR31;
wire [129:0] VAR... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_clk_gen/bsg_clk_gen.v | 6,615 | module MODULE1
import VAR18::VAR44;
, VAR43 = 2
, VAR35 = 1 )
(input VAR44 VAR32
,input VAR44 VAR21 ,input VAR44 VAR22
,input VAR46
,input VAR11
,input [1:0] VAR2
,output logic VAR20
);
localparam VAR17 = 0;
logic VAR23; logic VAR10;
VAR3 #(.VAR43(VAR43)) VAR25
(
.VAR19 (VAR32 )
,.VAR47 (VAR21)
,.VAR37 (VAR46 )
,.VAR20... | bsd-3-clause |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_bank_mach.v | 31,504 | module MODULE1 #
(
parameter VAR24 = 100,
parameter VAR81 = "VAR68",
parameter VAR60 = "1T",
parameter VAR107 = 3,
parameter VAR62 = 2,
parameter VAR33 = "8",
parameter VAR118 = 12,
parameter VAR156 = 4,
parameter VAR70 = 5,
parameter VAR11 = 5,
parameter VAR23 = 8,
parameter VAR177 = "VAR21",
parameter VAR37 = "VAR68"... | mit |
Separius/Custom-Single-Cycle-MIPS | Stack.v | 1,274 | module MODULE1(input clk,rst,input[1:0] VAR1, input[11:0] VAR3, output[11:0] VAR4);
reg[2:0] VAR5;
reg[11:0] VAR2[0:7];
always@(posedge clk , posedge rst) if(~rst)
begin
if(VAR1==2'b01) begin
VAR2[VAR5] = VAR3+1;
VAR5 = VAR5+1;
end
else if(VAR1 == 2'b10) begin
VAR5 = VAR5-1;
end
end
else
VAR5 = 3'b000;
assign VAR4 = VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b_1.v | 2,327 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR3 ,
VAR8 ,
VAR4 ,
VAR6,
VAR7,
VAR1 ,
VAR11
);
output VAR2 ;
input VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR4 ;
input VAR6;
input VAR7;
input VAR1 ;
input VAR11 ;
VAR10 VAR5 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR11... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2_2.v | 2,113 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR7 ,
VAR2,
VAR6,
VAR1 ,
VAR3
);
output VAR9 ;
input VAR4 ;
input VAR7 ;
input VAR2;
input VAR6;
input VAR1 ;
input VAR3 ;
VAR8 VAR5 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR9,
VAR4,
VAR7
);
output VAR9;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai.behavioral.pp.v | 2,159 | module MODULE1 (
VAR12 ,
VAR6 ,
VAR10 ,
VAR3 ,
VAR16 ,
VAR19,
VAR5,
VAR14 ,
VAR13
);
output VAR12 ;
input VAR6 ;
input VAR10 ;
input VAR3 ;
input VAR16 ;
input VAR19;
input VAR5;
input VAR14 ;
input VAR13 ;
wire VAR11 ;
wire VAR15 ;
wire VAR7 ;
wire VAR1;
nor VAR8 (VAR11 , VAR3, VAR16 );
nor VAR9 (VAR15 , VAR6, VAR10 )... | apache-2.0 |
MarcoVogt/basil | firmware/modules/rrp_arbiter/rrp_arbiter.v | 2,743 | module MODULE1
parameter VAR13 = 4
)
(
input wire VAR21,
input wire VAR19,
input wire [VAR13-1:0] VAR7, input wire [VAR13-1:0] VAR1, input wire [VAR13*32-1:0] VAR5,
output wire[VAR13-1:0] VAR20,
input wire VAR3,
output wire VAR12,
output wire [31:0] VAR17
);
integer VAR2;
reg [VAR13-1:0] VAR15; reg [VAR13-1:0] select;
... | bsd-3-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fetch/fetch_cur_luma.v | 31,488 | module MODULE1 (
clk ,
VAR45 ,
VAR97 ,
VAR72 ,
VAR63 ,
VAR131 ,
VAR27 ,
VAR132 ,
VAR16 ,
VAR115 ,
VAR18 ,
VAR116 ,
VAR144 ,
VAR98 ,
VAR57 ,
VAR129 ,
VAR31 ,
VAR119 ,
VAR120 ,
VAR34 ,
VAR99 ,
VAR17 ,
VAR62 ,
VAR101 ,
VAR7 ,
VAR122 ,
VAR127 ,
VAR135 ,
VAR106 ,
VAR105 ,
VAR48 ,
VAR6 ,
VAR49 ,
VAR1 ,
VAR95 ,
VAR36 ,
VAR11 ... | gpl-3.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_mux_64_4.v | 11,263 | module MODULE1 #
(
parameter VAR60 = 64,
parameter VAR35 = (VAR60/8)
)
(
input wire clk,
input wire rst,
input wire [VAR60-1:0] VAR28,
input wire [VAR35-1:0] VAR22,
input wire VAR56,
output wire VAR30,
input wire VAR5,
input wire VAR57,
input wire [VAR60-1:0] VAR1,
input wire [VAR35-1:0] VAR41,
input wire VAR37,
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3b/sky130_fd_sc_lp__or3b_2.v | 2,209 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR1 ,
VAR4 ,
VAR8,
VAR3,
VAR2 ,
VAR10
);
output VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR8;
input VAR3;
input VAR2 ;
input VAR10 ;
VAR9 VAR6 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.behavioral.pp.v | 2,831 | module MODULE1 (
VAR12 ,
VAR19 ,
VAR29 ,
VAR6 ,
VAR21 ,
VAR1,
VAR30 ,
VAR24 ,
VAR31 ,
VAR17
);
output VAR12 ;
input VAR19 ;
input VAR29 ;
input VAR6 ;
input VAR21 ;
input VAR1;
input VAR30 ;
input VAR24 ;
input VAR31 ;
input VAR17 ;
wire VAR22 ;
wire VAR25 ;
wire VAR10 ;
reg VAR27 ;
wire VAR8 ;
wire VAR14 ;
wire VAR20 ... | apache-2.0 |
alr46664/lab4 | verilog_source/pipeline.v | 3,052 | module MODULE1(
VAR43,
VAR8
);
input VAR43, VAR8;
wire VAR3;
wire [VAR36-1:0] VAR32, VAR16;
wire [VAR56-1:0] VAR1;
wire [VAR15-1:0] VAR49;
wire [VAR6-1:0] VAR51;
wire VAR41;
wire [VAR15-1:0] VAR25, VAR55;
wire [VAR6-1:0] VAR34, VAR5, VAR18;
wire [VAR36-1:0] VAR35;
wire [VAR57-1:0] VAR17;
wire VAR42;
wire [VAR6-1:0] VAR... | gpl-3.0 |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/db/adc_pll_altpll.v | 3,935 | module MODULE1
(
clk,
VAR33) ;
output [4:0] clk;
input [1:0] VAR33;
tri0 [1:0] VAR33;
wire [4:0] VAR15;
wire VAR10;
VAR17 VAR2
(
.VAR35(),
.clk(VAR15),
.VAR21(),
.VAR16(VAR10),
.VAR18(VAR10),
.VAR33(VAR33),
.VAR36(),
.VAR23(),
.VAR31(),
.VAR14(),
.VAR29(),
.VAR3()
,
.VAR5(1'b0),
.VAR6(1'b0),
.VAR32(1'b0),
.VAR1(1'b1),
... | gpl-3.0 |
sam-falvo/polaris | ramcon/bench/verilog/ramcon.v | 8,398 | module MODULE1();
reg [15:0] VAR4;
reg VAR23, VAR12;
wire VAR17;
wire VAR9, VAR28;
wire VAR13, VAR32;
wire VAR33, VAR36;
wire VAR25;
wire [15:0] VAR22;
wire [22:0] VAR18;
reg VAR34;
wire [15:0] VAR30;
reg [15:0] VAR15;
wire VAR5;
reg VAR7;
reg [1:0] VAR3;
reg [22:0] VAR39;
reg VAR6, VAR19;
reg [15:0] VAR24;
assign VAR2... | mpl-2.0 |
sorgelig/Apogee_MIST | k580vv55.v | 1,909 | module MODULE1
(
input reset,
input VAR13,
input [1:0] addr,
input VAR9,
input [7:0] VAR5,
output reg[7:0] VAR15,
input [7:0] VAR10,
output [7:0] VAR8,
input [7:0] VAR12,
output [7:0] VAR4,
input [7:0] VAR1,
output [7:0] VAR7
);
reg [7:0] VAR2;
reg [7:0] VAR11;
reg [7:0] VAR14;
reg [7:0] VAR6;
assign VAR8 = VAR2[4] ? 8... | bsd-2-clause |
nishtahir/arty-blaze | src/bd/system/ip/system_auto_us_0/system_auto_us_0_stub.v | 5,253 | module MODULE1(VAR25, VAR3, VAR65,
VAR17, VAR10, VAR49, VAR63, VAR37, VAR42,
VAR46, VAR68, VAR15, VAR60, VAR20, VAR21,
VAR12, VAR72, VAR41, VAR67, VAR8, VAR14,
VAR27, VAR11, VAR18, VAR24, VAR69, VAR39,
VAR38, VAR51, VAR50, VAR71, VAR45, VAR29,
VAR16, VAR23, VAR59, VAR19, VAR30, VAR64,
VAR33, VAR9, VAR5, VAR70, VAR2, VA... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/nios_system.v | 80,297 | module MODULE1 (
output wire [31:0] VAR44, output wire [31:0] VAR273, input wire VAR237, output wire [2:0] VAR378, input wire VAR343, input wire [31:0] VAR198, input wire VAR106, input wire VAR479, input wire VAR248, output wire [3:0] VAR111, output wire [3:0] VAR33, output wire [3:0] VAR418, output wire [3:0] VAR320, ... | gpl-3.0 |
nickdesaulniers/Omicron | memory.v | 2,447 | module MODULE1(
input VAR1,
input VAR17,
input [15:0] VAR6,
input [15:0] VAR2,
input [2:0] VAR9,
input VAR4,
input [1:0] VAR14,
input VAR11,
output [15:0] VAR19,
output [15:0] VAR5,
output [2:0] VAR8,
output reg VAR10
);
parameter VAR15 = 2'b00; parameter VAR20 = 2'b01;
parameter VAR7 = 2'b10;
parameter VAR16 = 2'b11;
... | gpl-3.0 |
asicguy/gplgpu | hdl/de_temp/ded_cactrl_rd.v | 15,032 | module MODULE1
(
input VAR58,
input VAR26,
input VAR62,
input VAR21,
input VAR25,
input VAR69,
input VAR5,
input VAR37,
input [9:0] din,
input [8:0] VAR42,
input [4:0] VAR52,
input [6:0] VAR57,
input [1:0] VAR41,
input [1:0] VAR11,
input [1:0] VAR7,
input [1:0] VAR75,
input VAR35,
input VAR44,
input VAR16,
input [2:0] ... | gpl-3.0 |
Microsoft/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_CRC_gen.v | 3,733 | module MODULE1 ( VAR2, VAR1);
input [47:0] VAR2;
output [7:0] VAR1;
assign VAR1[0] = VAR2[46] ^ VAR2[42] ^ VAR2[41] ^ VAR2[37] ^ VAR2[36] ^ VAR2[35] ^ VAR2[34] ^
VAR2[33] ^ VAR2[31] ^ VAR2[30] ^ VAR2[29] ^ VAR2[27] ^ VAR2[26] ^ VAR2[24] ^
VAR2[20] ^ VAR2[18] ^ VAR2[17] ^ VAR2[16] ^ VAR2[15] ^ VAR2[14] ^ VAR2[13] ^
VAR2... | bsd-2-clause |
mshaklunov/usb_devtrsac | rtl/usb_decoder.v | 15,880 | module MODULE1 (
input clk,
input VAR63,
input VAR16,
input VAR30,
input VAR58,
input VAR27,
input VAR82,
output reg VAR17,
output reg VAR47,
output reg VAR69,
input[6:0] VAR36,
input[15:0] VAR84,
output[3:0] VAR3,
output VAR77,
output VAR39,
output VAR75,
output VAR66,
output VAR8,
output VAR83,
output VAR87,
output V... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_044.v | 1,482 | module MODULE1 (
VAR1,
VAR12
);
input [31:0] VAR1;
output [31:0]
VAR12;
wire [31:0]
VAR8,
VAR2,
VAR10,
VAR9,
VAR4,
VAR11,
VAR13,
VAR6;
assign VAR8 = VAR1;
assign VAR6 = VAR13 << 1;
assign VAR4 = VAR10 - VAR9;
assign VAR2 = VAR8 << 9;
assign VAR10 = VAR8 + VAR2;
assign VAR9 = VAR8 << 6;
assign VAR11 = VAR4 << 4;
assign ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb_4.v | 2,323 | module MODULE2 (
VAR10 ,
VAR9 ,
VAR7 ,
VAR5 ,
VAR2 ,
VAR4,
VAR8,
VAR11 ,
VAR6
);
output VAR10 ;
input VAR9 ;
input VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR11 ;
input VAR6 ;
VAR3 VAR1 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR11(VAR11),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuflp/sky130_fd_sc_lp__clkbuflp.functional.pp.v | 1,793 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR12,
VAR8,
VAR5 ,
VAR2
);
output VAR3 ;
input VAR11 ;
input VAR12;
input VAR8;
input VAR5 ;
input VAR2 ;
wire VAR7 ;
wire VAR9;
buf VAR6 (VAR7 , VAR11 );
VAR1 VAR10 (VAR9, VAR7, VAR12, VAR8);
buf VAR4 (VAR3 , VAR9 );
endmodule | apache-2.0 |
Nrpickle/ECE272 | Lab6_FinalDesign/section6_FinalDesign/interpretADC_prim.v | 18,755 | module MODULE1 (VAR121, VAR49) ; input [7:0]VAR121; output [8:0]VAR49;
wire [7:0]VAR86; wire [8:0]VAR26;
wire VAR16, VAR118, VAR36;
wire [15:0]VAR4;
wire VAR1, VAR52, VAR44, VAR48, VAR134, VAR141, VAR100;
wire [11:0]VAR155;
wire VAR58;
wire [11:0]VAR56;
wire VAR62, VAR43, VAR152, VAR45, VAR149, VAR127, VAR22, VAR76, VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221a/sky130_fd_sc_hdll__o221a.functional.v | 1,574 | module MODULE1 (
VAR4 ,
VAR5,
VAR1,
VAR12,
VAR8,
VAR10
);
output VAR4 ;
input VAR5;
input VAR1;
input VAR12;
input VAR8;
input VAR10;
wire VAR3 ;
wire VAR9 ;
wire VAR2;
or VAR6 (VAR3 , VAR8, VAR12 );
or VAR13 (VAR9 , VAR1, VAR5 );
and VAR7 (VAR2, VAR3, VAR9, VAR10);
buf VAR11 (VAR4 , VAR2 );
endmodule | apache-2.0 |
pavel-demin/red-pitaya-notes | projects/red_pitaya_0_92/red_pitaya_daisy.v | 11,837 | module MODULE1
(
output [ 2-1: 0] VAR9 , output [ 2-1: 0] VAR7 , input [ 2-1: 0] VAR55 , input [ 2-1: 0] VAR42 ,
input VAR79 , input VAR99 , input VAR95 , input VAR57 , output VAR82 , input VAR29 , input [ 16-1: 0] VAR30 , output VAR23 , output VAR61 , output VAR28 , output [ 16-1: 0] VAR52 ,
output [ 8-1: 0] VAR53 ,
i... | mit |
AngelTerrones/MUSB | Hardware/fifo/fifo.v | 4,325 | module MODULE1#(
parameter VAR16 = 8, parameter VAR17 = 8 )(
input clk,
input rst,
input VAR10, input VAR18, input [(VAR16-1):0] VAR1, output [(VAR16-1):0] VAR5, output reg [(VAR17):0] VAR14, output VAR2, output VAR6 );
wire VAR13;
wire VAR8;
wire [(VAR16-1):0] VAR15;
reg [(VAR17-1):0] VAR9; reg [(VAR17-1):0] VAR19;
as... | mit |
Tao-J/nexys3MIPSSoC | vcache.v | 5,423 | module MODULE1(
VAR17, VAR6, VAR25, VAR18, VAR9, VAR33, VAR20,
VAR5, VAR1,
VAR19, VAR7, VAR32, VAR16, VAR34, VAR35,
VAR28
);
input wire VAR19;
input wire VAR7;
input wire VAR32;
output [7:0] VAR17;
output VAR6; output VAR25;
input wire VAR16; input wire VAR34; input wire VAR35; input wire [31:0] VAR28; output VAR18; ou... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_pipe_drp.v | 22,301 | module MODULE1 #
(
parameter VAR16 = "1.1", parameter VAR76 = "VAR18", parameter VAR32 = "VAR1", parameter VAR77 = "VAR95", parameter VAR37 = 0, parameter VAR81 = 0, parameter VAR107 = 4'd11
)
(
input VAR53,
input VAR94,
input VAR115,
input [ 1:0] VAR71,
input VAR104,
input [15:0] VAR26,
input VAR45,
output [ 8:0] VAR2... | lgpl-3.0 |
MarcoVogt/basil | firmware/modules/bram_fifo/bram_fifo_core.v | 4,831 | module MODULE1
parameter VAR2 = 32'h8000,
parameter VAR16 = 95, parameter VAR17 = 5, parameter VAR11 = 32
) (
input wire VAR32,
input wire VAR13,
input wire [VAR11-1:0] VAR29,
input wire [7:0] VAR24,
input wire VAR33,
input wire VAR4,
output reg [7:0] VAR14,
input wire VAR39,
output reg [31:0] VAR21,
input wire VAR43,
... | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController4L/src/pcie_rx_recv.v | 13,606 | module MODULE1 # (
parameter VAR16 = 128
)
(
input VAR59,
input VAR35,
input [VAR16-1:0] VAR56,
input [(VAR16/8)-1:0] VAR13,
input VAR23,
input VAR14,
output VAR47,
input [21:0] VAR19,
output VAR42,
output VAR18,
output VAR29,
output VAR5,
output [VAR16-1:0] VAR64,
output [7:0] VAR2,
output [VAR16-1:0] VAR32,
output VA... | gpl-3.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/etc/hardware/nes_snes_controller/snes_controller.v | 9,087 | module MODULE1(
VAR35, VAR19, VAR26, VAR30, VAR14 );
input VAR19;
input VAR30;
output VAR35;
output VAR26;
output [12:0] VAR14;
reg [12:0] VAR24; reg VAR6; reg pulse; reg VAR29; reg [17:0] VAR4;
reg [5:0] VAR21;
parameter VAR8 = 1;
parameter VAR3 = 2;
parameter VAR23 = 3;
parameter VAR27 = 4;
parameter VAR22 = 5;
param... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_lsu.v | 8,075 | module MODULE1(
clk, rst,
VAR20, VAR19, VAR29, VAR40, VAR22, VAR7, VAR46,
VAR14, VAR4, VAR11, VAR15, VAR36,
VAR38, VAR24, VAR37, VAR42, VAR12, VAR2,
VAR32, VAR39, VAR8, VAR16, VAR10
);
parameter VAR18 = VAR9;
parameter VAR17 = VAR33;
input clk;
input rst;
input [31:0] VAR20;
input [31:0] VAR19;
input [VAR34-1:0] VAR29;... | gpl-3.0 |
m-labs/milkymist | cores/minimac2/rtl/minimac2_tx.v | 2,275 | module MODULE1(
input VAR13,
input VAR16,
output reg VAR3,
input [10:0] VAR7,
input [7:0] VAR15,
output [10:0] VAR11,
output reg VAR21,
output reg [3:0] VAR2
);
reg VAR6;
reg VAR18;
wire [3:0] VAR5 = VAR18 ? VAR15[7:4] : VAR15[3:0];
always @(posedge VAR13) begin
VAR21 <= VAR6;
VAR2 <= VAR5;
end
reg [10:0] VAR9;
reg VAR... | lgpl-3.0 |
m-labs/milkymist | cores/fmlmeter/rtl/fmlmeter.v | 3,002 | module MODULE1 #(
parameter VAR13 = 4'h0,
parameter VAR12 = 26
) (
input VAR20,
input VAR19,
input [13:0] VAR1,
input VAR24,
input [31:0] VAR9,
output reg [31:0] VAR17,
input VAR4,
input VAR28,
input VAR16,
input [VAR12-1:0] VAR15
);
reg VAR11;
reg VAR6;
reg VAR14;
reg [VAR12-1:0] VAR7;
always @(posedge VAR20) begin
VA... | lgpl-3.0 |
tmatsuya/milkymist-ml401 | cores/ac97/rtl/ac97_transceiver.v | 2,258 | module MODULE1(
input VAR28,
input VAR16,
input VAR30,
input VAR23,
input VAR1,
output reg VAR31,
output reg VAR10,
output VAR26,
input VAR7,
output VAR5,
output VAR34,
output VAR2,
input VAR25,
input VAR3,
input VAR14
);
reg VAR13;
always @(negedge VAR30) VAR13 <= VAR1;
reg VAR21;
always @(negedge VAR30) VAR21 <= VAR1... | lgpl-3.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/fifo/afifo_gray.v | 9,896 | module MODULE1
parameter VAR19 = VAR10-1,
parameter VAR14 = 4,
parameter VAR15 = VAR14-1,
parameter VAR2 = 1 << VAR14,
parameter VAR23 = 3)
( input VAR17,
input VAR28,
input VAR26,
input VAR5,
input [VAR19:0] VAR18,
input VAR3,
output [VAR19:0] VAR27,
output reg VAR16 = 1'b0,
output reg VAR25 = 1'b1
);
wire [VAR14:0] V... | lgpl-3.0 |
peteasa/oh | src/mio/hdl/mtx_io.v | 3,418 | module MODULE1 (
VAR8, VAR9, VAR15,
VAR6, VAR14, VAR13, VAR24, VAR7, VAR21, VAR19
);
parameter VAR20 = 16;
input VAR6; input VAR14; input VAR13; input VAR24;
output [VAR20-1:0] VAR8; output VAR9; input VAR7;
input VAR21; input [2*VAR20-1:0] VAR19; output VAR15;
reg VAR9;
wire [VAR20-1:0] VAR10;
reg [VAR20-1:0] VAR5;
re... | mit |
jamesbowman/verilog1802 | cdp1802.v | 7,255 | module MODULE1 (
input VAR15,
input VAR43,
output reg VAR4, input [3:0] VAR11,
input [7:0] VAR5, output [7:0] VAR1, output [2:0] VAR2, output VAR45, output VAR18,
output VAR27,
output VAR30, output VAR40, output [15:0] VAR37, input [7:0] VAR38, output [7:0] VAR19 );
reg [2:0] state, VAR44;
localparam VAR28 = 3'd0; loca... | bsd-3-clause |
Digilent/vivado-library | ip/Pmods/PmodHYGRO_v1_0/src/PmodHYGRO.v | 13,442 | module MODULE1
(VAR27,
VAR79,
VAR142,
VAR10,
VAR187,
VAR192,
VAR150,
VAR36,
VAR188,
VAR40,
VAR26,
VAR109,
VAR161,
VAR73,
VAR178,
VAR180,
VAR16,
VAR38,
VAR195,
VAR19,
VAR67,
VAR7,
VAR41,
VAR116,
VAR85,
VAR122,
VAR112,
VAR22,
VAR113,
VAR20,
VAR160,
VAR84,
VAR34,
VAR175,
VAR4,
VAR1,
VAR69,
VAR61,
VAR143,
VAR155,
VAR165,
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor3/sky130_fd_sc_lp__xor3.behavioral.pp.v | 1,845 | module MODULE1 (
VAR6 ,
VAR13 ,
VAR3 ,
VAR7 ,
VAR2,
VAR10,
VAR1 ,
VAR12
);
output VAR6 ;
input VAR13 ;
input VAR3 ;
input VAR7 ;
input VAR2;
input VAR10;
input VAR1 ;
input VAR12 ;
wire VAR9 ;
wire VAR5;
xor VAR4 (VAR9 , VAR13, VAR3, VAR7 );
VAR8 VAR11 (VAR5, VAR9, VAR2, VAR10);
buf VAR14 (VAR6 , VAR5 );
endmodule | apache-2.0 |
domahony/ButtonCount | RS232TX.v | 2,046 | module MODULE2 (
input clk,
input VAR20,
input [23:0] VAR2,
output VAR18,
output VAR3
);
wire VAR10;
wire[7:0] VAR14 = VAR2[7:0];
MODULE1 MODULE1(
.clk(clk),
.enable(VAR3),
.VAR9(VAR10)
);
reg[3:0] VAR15 = 0;
wire VAR7 = (VAR15==0);
assign VAR3 = ~VAR7;
reg[7:0] VAR16 = 0;
always @(posedge clk)
begin
if (VAR7 & VAR20)
... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_sb.v | 6,850 | module MODULE1(
clk, rst,
VAR7, VAR14, VAR30, VAR36, VAR37, VAR9, VAR24,
VAR15, VAR40, VAR41,
VAR13, VAR35, VAR10, VAR39, VAR3, VAR11, VAR26,
VAR31, VAR16, VAR18
);
parameter VAR29 = VAR33;
parameter VAR21 = VAR33;
input clk; input rst;
input [VAR29-1:0] VAR7; input [VAR21-1:0] VAR14; input VAR30; input VAR36; input VA... | gpl-3.0 |
m-labs/milkymist | cores/softusb/rtl/softusb_hostif.v | 1,830 | module MODULE1 #(
parameter VAR6 = 4'h0,
parameter VAR15 = 12
) (
input VAR17,
input VAR20,
input VAR14,
output reg VAR4,
input [13:0] VAR7,
input VAR8,
input [31:0] VAR11,
output reg [31:0] VAR3,
output irq,
input VAR9,
input [5:0] VAR18,
input [VAR15-1:0] VAR10
);
wire VAR5 = VAR7[13:10] == VAR6;
reg VAR1;
always @(p... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/diode/sky130_fd_sc_hs__diode.pp.blackbox.v | 1,226 | module MODULE1 (
VAR5,
VAR4 ,
VAR1 ,
VAR3 ,
VAR2
);
input VAR5;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/Tube/ph_byte.v | 2,411 | module MODULE1 (
input VAR24,
input VAR2,
input VAR15,
input VAR9,
input [7:0] VAR10,
input VAR21,
input VAR3,
input VAR11,
output [7:0] VAR20,
output VAR23,
output VAR4
);
reg [7:0] VAR6 ;
wire [7:0] VAR12 ;
assign VAR20 = VAR6;
assign VAR12 = ( VAR21 & !VAR11) ? VAR10 : VAR6;
VAR8 VAR16 (
.VAR5(VAR24),
.VAR13(VAR2),
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai.blackbox.v | 1,397 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR3;
supply1 VAR2;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/buf/sky130_fd_sc_hvl__buf_32.v | 2,007 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR3,
VAR1,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR7 ;
input VAR3;
input VAR1;
input VAR4 ;
input VAR2 ;
VAR8 VAR6 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR5,
VAR7
);
output VAR5;
input VAR7;
supply1 VAR3;
supply0 VAR1;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.behavioral.v | 1,502 | module MODULE1( VAR4, VAR2, VAR7, VAR3 );
input VAR4, VAR2;
output VAR7, VAR3;
VAR5 VAR6(.VAR4(VAR4),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3));
VAR5 VAR1(.VAR4(VAR4),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_8.behavioral.v | 1,170 | module MODULE1( VAR2, VAR4, VAR6 );
input VAR2, VAR4;
output VAR6;
VAR5 VAR3(.VAR2(VAR2),.VAR4(VAR4),.VAR6(VAR6));
VAR5 VAR1(.VAR2(VAR2),.VAR4(VAR4),.VAR6(VAR6)); | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_aon_porrst.v | 1,749 | module MODULE1(
output VAR1
);
endmodule | apache-2.0 |
dagrende/rpistepper | spi_slave.v | 1,706 | module MODULE1(input clk, input rst, input VAR8, input VAR25, output VAR2, input VAR23, output VAR24, input [VAR18-1:0] din, output [VAR18-1:0] dout);
parameter VAR18=8; parameter VAR17 = 6;
reg VAR15, VAR14;
reg VAR1, VAR19;
reg VAR3, VAR4;
reg VAR20, VAR22;
reg [VAR18-1:0] VAR6, VAR21;
reg VAR7, VAR11;
reg [VAR17-1:0... | lgpl-3.0 |
olgirard/opengfx430 | core/rtl/verilog/interfaces/ogfx_if_lt24_reg.v | 26,856 | module MODULE1 (
VAR6, VAR25,
VAR102, VAR49, VAR100, VAR57, VAR21, VAR124, VAR73, VAR20, VAR28, VAR12, VAR115, VAR103, VAR10,
VAR129, VAR51, VAR7, VAR97, VAR35,
VAR40,
VAR114, VAR107,
VAR99, VAR52, VAR64, VAR62,
VAR63, VAR5, VAR33, VAR127, VAR121,
VAR44, VAR22, VAR8, VAR27 );
parameter [14:0] VAR113 = 15'h0280; output ... | bsd-3-clause |
Dennis-Chhun/Pong-Game | VGAFrequency/VGAFrequency_bb.v | 11,153 | module MODULE1 (
VAR2,
VAR1,
VAR3);
input VAR2;
input VAR1;
output VAR3;
tri0 VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.v | 2,480 | module MODULE2 (
VAR2 ,
VAR11 ,
VAR1,
VAR8 ,
VAR6 ,
VAR4 ,
VAR10 ,
VAR5 ,
VAR3
);
output VAR2 ;
output VAR11 ;
input VAR1;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR10 ;
input VAR5 ;
input VAR3 ;
VAR7 VAR9 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR5(VAR5)... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_1.behavioral.pp.v | 8,324 | module MODULE1( VAR6, VAR12, VAR9, VAR4, VAR8, VAR5, VAR1, VAR7, VAR11 );
input VAR1, VAR5, VAR6, VAR9, VAR12, VAR8;
inout VAR7, VAR11;
output VAR4;
VAR2 VAR3(.VAR6(VAR6),.VAR12(VAR12),.VAR9(VAR9),.VAR4(VAR4),.VAR8(VAR8),.VAR5(VAR5),.VAR1(VAR1),.VAR7(VAR7),.VAR11(VAR11));
VAR2 VAR10(.VAR6(VAR6),.VAR12(VAR12),.VAR9(VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_pr_pp_pg/sky130_fd_sc_hs__udp_dlatch_pr_pp_pg.symbol.v | 1,457 | module MODULE1 (
input VAR6 ,
output VAR4 ,
input VAR3,
input VAR2 ,
input VAR1 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21boi/sky130_fd_sc_hs__a21boi_4.v | 2,205 | module MODULE2 (
VAR8 ,
VAR2 ,
VAR1 ,
VAR4,
VAR7,
VAR6
);
output VAR8 ;
input VAR2 ;
input VAR1 ;
input VAR4;
input VAR7;
input VAR6;
VAR5 VAR3 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR8 ,
VAR2 ,
VAR1 ,
VAR4
);
output VAR8 ;
input VAR2 ;
input VAR1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi.pp.blackbox.v | 1,393 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR4 ,
VAR2 ,
VAR8 ,
VAR1,
VAR7,
VAR6 ,
VAR9
);
output VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR1;
input VAR7;
input VAR6 ;
input VAR9 ;
endmodule | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_tristate_conduit_pin_sharer_0.v | 7,593 | module MODULE1 (
input wire VAR33, input wire VAR9, output wire request, input wire VAR8, output wire [0:0] VAR7, output wire [21:0] VAR10, output wire [0:0] VAR31, output wire [0:0] VAR1, output wire [7:0] VAR17, input wire [7:0] VAR29, output wire VAR4, output wire [0:0] VAR2, output wire [0:0] VAR24, input wire VAR3... | apache-2.0 |
hoglet67/CoPro6502 | src/Tube/ph_fifo_core_spartan6.v | 13,728 | module MODULE1(
rst,
VAR310,
VAR45,
din,
VAR156,
VAR48,
dout,
VAR29,
VAR291
);
input rst;
input VAR310;
input VAR45;
input [7 : 0] din;
input VAR156;
input VAR48;
output [7 : 0] dout;
output VAR29;
output VAR291;
VAR405 #(
.VAR369(0),
.VAR125(0),
.VAR354(0),
.VAR116(0),
.VAR299(0),
.VAR398(0),
.VAR147(0),
.VAR217(32),
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbp/sky130_fd_sc_hs__sdfbbp_1.v | 2,682 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR10 ,
VAR7 ,
VAR12 ,
VAR11 ,
VAR3 ,
VAR4,
VAR9 ,
VAR2
);
output VAR6 ;
output VAR8 ;
input VAR10 ;
input VAR7 ;
input VAR12 ;
input VAR11 ;
input VAR3 ;
input VAR4;
input VAR9 ;
input VAR2 ;
VAR5 VAR1 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR12(VAR12),
.VAR11(VAR11),
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b.functional.pp.v | 1,995 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR12 ,
VAR14 ,
VAR8,
VAR9,
VAR4 ,
VAR7
);
output VAR10 ;
input VAR5 ;
input VAR12 ;
input VAR14 ;
input VAR8;
input VAR9;
input VAR4 ;
input VAR7 ;
wire VAR2 ;
wire VAR6 ;
wire VAR13;
nor VAR16 (VAR2 , VAR5, VAR12 );
and VAR3 (VAR6 , VAR14, VAR2 );
VAR15 VAR11 (VAR13, VAR6, VAR8, VAR9);... | apache-2.0 |
liuyenting/CA-Project | src/L1_Cache_Controller.v | 2,617 | module MODULE1
(
input clk,
input rst,
input VAR1,
input VAR9,
input VAR20,
input VAR4,
output VAR10,
output VAR2,
output VAR8,
output VAR21,
output VAR15,
output VAR14
);
wire VAR19 = VAR5.VAR19;
reg VAR18;
reg VAR17;
reg VAR3;
reg VAR12;
assign VAR21 = VAR18;
assign VAR15 = VAR17;
assign VAR14 = VAR12;
wire VAR11;
as... | gpl-3.0 |
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