repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2_0.v | 2,187 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR4 ,
VAR9 ,
VAR8,
VAR10,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR9 ;
input VAR8;
input VAR10;
input VAR6 ;
input VAR1 ;
VAR2 VAR5 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_p_src_data_stream_0_V.v | 3,017 | module MODULE2 (
clk,
VAR27,
VAR20,
VAR21,
VAR10);
parameter VAR8 = 32'd8;
parameter VAR9 = 32'd1;
parameter VAR22 = 32'd2;
input clk;
input [VAR8-1:0] VAR27;
input VAR20;
input [VAR9-1:0] VAR21;
output [VAR8-1:0] VAR10;
reg[VAR8-1:0] VAR23 [0:VAR22-1];
integer VAR13;
always @ (posedge clk)
begin
if (VAR20)
begin
for (... | gpl-3.0 |
theapi/de0-nano | keyboard/ps2controller_0.v | 2,389 | module MODULE1 (
input clk,
input reset,
input VAR4,
input VAR1,
output VAR2,
output [7:0] VAR5
);
reg [9:0] buffer;
reg [3:0] counter;
reg VAR8;
reg VAR7;
reg [31:0] VAR6;
reg ready;
wire VAR3;
assign VAR5 = buffer[9:2];
assign VAR3 = buffer[1];
assign VAR2 = ready;
always @(negedge VAR4) begin
VAR8 <= 1;
VAR7 <= 0;
e... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai.behavioral.pp.v | 2,181 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR1 ,
VAR3 ,
VAR14 ,
VAR17,
VAR11,
VAR9 ,
VAR19
);
output VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR3 ;
input VAR14 ;
input VAR17;
input VAR11;
input VAR9 ;
input VAR19 ;
wire VAR13 ;
wire VAR8 ;
wire VAR12 ;
wire VAR6;
nor VAR7 (VAR13 , VAR3, VAR14 );
nor VAR18 (VAR8 , VAR10, VAR1 );
... | apache-2.0 |
franmolinaca/papiGB | rtl/io.v | 2,732 | module MODULE1
(
input wire VAR25,
input wire VAR16,
input wire [5:0] VAR8, output wire [5:0] VAR10, output wire VAR1 );
wire [5:0] VAR5;
wire [5:0] VAR20;
wire [5:0] VAR2;
wire [5:0] VAR17;
wire [5:0] VAR26;
wire [5:0] VAR7;
wire [5:0] VAR15;
reg [5:0] VAR24;
assign VAR10 = VAR24;
VAR11 # ( 6 ) VAR3
(
.VAR25(VAR25),
.... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.behavioral.v | 3,306 | module MODULE1( VAR7, VAR8, VAR6, VAR4, VAR3, VAR9 );
input VAR3, VAR9, VAR4, VAR6, VAR8;
output VAR7;
VAR1 VAR5(.VAR7(VAR7),.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9));
VAR1 VAR2(.VAR7(VAR7),.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3_1.v | 2,135 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR7,
VAR2,
VAR3 ,
VAR4
);
output VAR1 ;
input VAR8 ;
input VAR7;
input VAR2;
input VAR3 ;
input VAR4 ;
VAR6 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR1,
VAR8
);
output VAR1;
input VAR8;
supply1 VAR7;
supply0 VAR2;... | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/Add-Subt/FPU_Add_Subtract_Function.v | 12,654 | module MODULE1
wire [VAR20-1:0] VAR9;
assign VAR9 = ~VAR8;
VAR13 #(.VAR20(VAR20),.VAR11(VAR11)) VAR16 (
.clk(clk),
.rst(VAR6),
.VAR36(VAR19),
.VAR38(VAR9),
.VAR21(VAR17)
);
VAR28 VAR25(
.clk(clk),
.VAR15(VAR10[1:0]),
.VAR37(VAR34),
.VAR31(VAR7),
.VAR29(VAR5)
);
VAR1 #(.VAR14(VAR14),.VAR32(VAR32),.VAR23(VAR23)) VAR2(
.c... | gpl-3.0 |
alanachtenberg/CSCE-350 | Lab6/lab6_5mux.v | 1,473 | module MODULE1(VAR4, VAR15, VAR6);
output VAR4; reg VAR4;
input [3:0] VAR15; input [1:0] VAR6;
always @ (VAR15 or VAR6)
case (VAR6)
2'b00: VAR4=VAR15[0];
2'b01: VAR4=VAR15[1];
2'b10: VAR4=VAR15[2];
2'b11: VAR4=VAR15[3];
endcase
endmodule
module MODULE2(VAR7, VAR2,VAR8,VAR1,VAR12);
input VAR8, VAR1;
input VAR12;
output ... | gpl-2.0 |
mfkiwl/parallella-platform | hdl/pulse2pulse.v | 1,697 | module MODULE1(
out,
VAR1, VAR7, in, reset
);
input VAR1;
input VAR7;
input in;
output out;
input reset;
wire VAR6;
wire VAR5;
VAR2 VAR2(
.out (VAR6),
.clk (VAR1),
.in (in),
.reset (reset));
VAR3 #(1) VAR3(
.out (VAR5),
.in (VAR6),
.clk (VAR7),
.reset (reset));
VAR4 VAR4(
.out (out),
.clk (VAR7),
.in (VAR5),
.reset (re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3_4.v | 2,215 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR1 ,
VAR3 ,
VAR10,
VAR7,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR10;
input VAR7;
input VAR4 ;
input VAR8 ;
VAR6 VAR9 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.behavioral.pp.v | 1,244 | module MODULE1( VAR1, VAR2, VAR5, VAR3, VAR7 );
input VAR2, VAR1;
inout VAR3, VAR7;
output VAR5;
VAR6 VAR8(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7));
VAR6 VAR4(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_hps.v | 16,152 | module MODULE1 #(
parameter VAR69 = 0,
parameter VAR79 = 0
) (
output wire VAR34, input wire VAR6, output wire [11:0] VAR23, output wire [20:0] VAR85, output wire [3:0] VAR58, output wire [2:0] VAR77, output wire [1:0] VAR56, output wire [1:0] VAR71, output wire [3:0] VAR48, output wire [2:0] VAR36, output wire VAR32, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22oi/sky130_fd_sc_hdll__a22oi.functional.pp.v | 2,186 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR8 ,
VAR4 ,
VAR13 ,
VAR12,
VAR1,
VAR19 ,
VAR18
);
output VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR4 ;
input VAR13 ;
input VAR12;
input VAR1;
input VAR19 ;
input VAR18 ;
wire VAR2 ;
wire VAR17 ;
wire VAR6 ;
wire VAR3;
nand VAR9 (VAR2 , VAR8, VAR7 );
nand VAR16 (VAR17 , VAR13, VAR4 );
an... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_ic_top.v | 10,356 | module MODULE1(
clk, rst,
VAR17, VAR73, VAR68, VAR57, VAR47, VAR39, VAR10,
VAR35, VAR30, VAR8,
VAR56,
VAR32, VAR13, VAR71,
VAR2, VAR49,
VAR1, VAR24, VAR65, VAR19, VAR46,
VAR3, VAR21, VAR40,
VAR60, VAR43, VAR62
);
parameter VAR53 = VAR69;
input clk;
input rst;
output [VAR53-1:0] VAR17;
output [31:0] VAR73;
output VAR68;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b_4.v | 2,254 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR4 ,
VAR2 ,
VAR9,
VAR6,
VAR8 ,
VAR1
);
output VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR9;
input VAR6;
input VAR8 ;
input VAR1 ;
VAR10 VAR3 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (... | apache-2.0 |
jeremyherbert/real_time_stdev | sqrt_remainder/hdl/sqrt_remainder.v | 4,013 | module MODULE1
parameter VAR5 = 8,
parameter VAR8 = 3
)
(
input wire [VAR13-1:0] VAR22,
input wire [VAR1-1:0] VAR7,
input wire [(VAR21-1 + VAR23):0] VAR11,
output reg [VAR3-1:0] VAR18,
output reg signed [VAR20-1:0] VAR4,
output reg [VAR2-1:0] VAR12,
input wire reset,
input wire clk
);
reg VAR19;
wire signed [VAR20-1:0]... | mit |
trivoldus28/pulsarch-verilog | design/sys/edk_bee3/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_chbond_count_dec.v | 2,629 | module MODULE1 (
VAR2,
VAR1,
VAR4
);
parameter VAR3 = 6'b100111;
input [5:0] VAR2;
output VAR1;
input VAR4;
reg VAR1;
always @(posedge VAR4)
VAR1 <= (VAR2 == VAR3);
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22a/sky130_fd_sc_hs__o22a.pp.blackbox.v | 1,332 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR2 ,
VAR3 ,
VAR6 ,
VAR5,
VAR4
);
output VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR5;
input VAR4;
endmodule | apache-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/FIFO_pixelq_op_img_data_stream_2_V.v | 2,997 | module MODULE1 (
clk,
VAR8,
VAR3,
VAR21,
VAR10);
parameter VAR5 = 32'd8;
parameter VAR25 = 32'd1;
parameter VAR16 = 32'd2;
input clk;
input [VAR5-1:0] VAR8;
input VAR3;
input [VAR25-1:0] VAR21;
output [VAR5-1:0] VAR10;
reg[VAR5-1:0] VAR23 [0:VAR16-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR3)
begin
for (VAR... | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/fdc.v | 17,750 | module MODULE1 (
input VAR8,
input VAR67,
input VAR6,
input [7:0] VAR99,
output [7:0] VAR70,
input VAR104, input VAR71,
input VAR39,
output VAR49,
input VAR21,
input VAR59,
input [3:0] VAR1,
input [7:0] VAR100,
output [7:0] VAR54,
input VAR17,
input VAR56,
input VAR76,
output VAR38 );
parameter VAR92 = 6'd0, VAR16 = 6'... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah.blackbox.v | 1,297 | module MODULE1 (
VAR9,
VAR8 ,
VAR7 ,
VAR1 ,
VAR5
);
output VAR9;
output VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
supply1 VAR2;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_mux_128to1_sel7_6_1.v | 18,745 | module MODULE1 #(
parameter
VAR272 = 0,
VAR288 = 1,
VAR50 = 32,
VAR299 = 32,
VAR4 = 32,
VAR125 = 32,
VAR90 = 32,
VAR87 = 32,
VAR22 = 32,
VAR242 = 32,
VAR249 = 32,
VAR207 = 32,
VAR11 = 32,
VAR54 = 32,
VAR172 = 32,
VAR328 = 32,
VAR132 = 32,
VAR38 = 32,
VAR37 = 32,
VAR106 = 32,
VAR367 = 32,
VAR8 = 32,
VAR320 = 32,
VAR312 ... | apache-2.0 |
queq/just-stuff | pov/TopMobile/LEDS/top_RAM.v | 1,424 | module MODULE1( clk, VAR14, VAR16, VAR37,VAR25,VAR27,VAR9);
input clk;
input VAR14; input [15:0] VAR25;
input VAR9;
input VAR16;
output [15:0] VAR37;
output [7:0] VAR27;
wire rst;
wire VAR29;
wire VAR21;
wire VAR38;
wire VAR2;
wire VAR28;
wire VAR31;
wire VAR3;
wire VAR5;
wire VAR32;
wire VAR7;
wire VAR36;
wire VAR8;
w... | mit |
toomij/DE2Labs | Lab4/counter_16bit.v | 1,315 | module MODULE1 (VAR15, VAR9, VAR7, VAR12);
input VAR15, VAR9, VAR7;
output [15:0] VAR12;
wire [15:0] VAR19, VAR3;
VAR16 VAR8 (VAR15, VAR9, VAR7, VAR3[0]);
assign VAR19[0] = VAR15 & VAR3[0];
VAR16 VAR13 (VAR19[0], VAR9, VAR7, VAR3[1]);
assign VAR19[1] = VAR19[0] & VAR3[1];
VAR16 VAR20 (VAR19[1], VAR9, VAR7, VAR3[2]);
as... | gpl-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_Pipistrello/src/hub_mem.v | 2,847 | module MODULE1
(
input VAR11,
input VAR6,
input VAR5,
input [3:0] VAR7,
input [13:0] VAR2,
input [31:0] VAR10,
output [31:0] VAR1
);
reg [7:0] VAR3 [16*1024-1:0]; reg [7:0] VAR4 [16*1024-1:0];
reg [7:0] VAR9 [16*1024-1:0];
reg [7:0] VAR8 [16*1024-1:0];
begin
begin
begin
begin
begin | gpl-3.0 |
bluecmd/mexiko | rtl/gic/gic_slave.v | 6,096 | module MODULE1 #(
parameter VAR1 = 4'b1111
) (
output [31:0] VAR5,
output VAR38,
output VAR9,
output [3:0] VAR2,
output VAR20,
output [2:0] VAR31,
output [1:0] VAR16,
output [31:0] VAR30,
input VAR21,
input VAR11,
input [31:0] VAR19,
input VAR43,
input VAR23,
input VAR12,
input [3:0] VAR36,
output [3:0] VAR41
);
localp... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/DE4_SOPC_burst_3.v | 15,486 | module MODULE1 (
clk,
VAR1,
VAR9,
VAR35,
VAR37,
VAR55,
VAR23,
VAR34,
VAR13,
VAR46,
VAR59,
VAR3,
VAR22,
VAR67,
VAR17,
VAR24,
VAR21,
VAR66,
VAR15,
VAR61,
VAR29,
VAR31,
VAR4,
VAR39,
VAR16
)
;
output [ 13: 0] VAR67;
output [ 10: 0] VAR17;
output VAR24;
output [ 3: 0] VAR21;
output VAR66;
output [ 13: 0] VAR15;
output VAR61... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/pre_i/counter.v | 9,007 | module MODULE1(
VAR31,
clk,
VAR66,
VAR12,
VAR9,
VAR2,
VAR10,
VAR25,
VAR47,
VAR34,
VAR16,
VAR62,
VAR28,
VAR30,
VAR29,
VAR18,
VAR67,
VAR41,
VAR64,
VAR42,
VAR65,
VAR40,
VAR36,
VAR6,
VAR61,
VAR11,
VAR22,
VAR1,
VAR15,
VAR54,
VAR27,
VAR37,
VAR55,
VAR3,
VAR32,
VAR19,
VAR50,
VAR59
);
parameter VAR21=21;
input VAR31;
input clk;... | gpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/bench/verilog/wb_master_behavioral.v | 23,268 | module MODULE1
(
VAR42,
VAR16,
VAR58,
VAR36,
VAR57,
VAR34,
VAR21,
VAR32,
VAR27,
VAR47,
VAR33,
VAR17,
VAR40,
VAR43,
VAR46
);
input VAR42;
input VAR16;
input VAR49 VAR58;
output VAR49 VAR36;
input VAR57;
output VAR25 VAR34;
output VAR21;
input VAR12 VAR32;
output VAR12 VAR27;
input VAR47;
input VAR33;
output VAR64 VAR17;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_psa_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_sn.blackbox.v | 1,613 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR3 ,
VAR9 ,
VAR1 ,
VAR6,
VAR7 ,
VAR2 ,
VAR4
);
output VAR8 ;
input VAR5 ;
input VAR3 ;
input VAR9 ;
input VAR1 ;
input VAR6;
input VAR7 ;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Lab2-Part2-Controller7SegmentDisplayKeypadScanner/Clock50MHz.v | 5,606 | module MODULE1
( input VAR27,
output VAR12,
output VAR46
);
VAR3 VAR39
(.VAR30 (VAR28),
.VAR15 (VAR27));
wire VAR24;
wire VAR22;
wire [7:0] VAR16;
wire VAR34;
wire VAR11;
wire VAR14;
VAR17
.VAR18 (1),
.VAR26 (4),
.VAR20 ("VAR23"),
.VAR33 (10.0),
.VAR31 ("VAR1"),
.VAR5 ("1X"),
.VAR8 ("VAR32"),
.VAR35 (0),
.VAR48 ("VAR23... | mit |
xuwenyihust/MapReduce_NoC | RTL/mapper_noc.v | 5,250 | module MODULE1(clk, rst, VAR24, VAR26, VAR17, VAR14, VAR36);
parameter VAR30 = 4'b0000;
parameter VAR22 = 4'b1111;
parameter VAR39 = 4'b0001;
parameter VAR28 = 4'b0010;
parameter VAR19 = 4'b0011;
parameter VAR7 = 10;
input clk;
input rst;
input [31:0] VAR24;
input VAR26;
input VAR17;
output reg [31:0] VAR14;
output reg... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_port_channel_gate_32.v | 7,035 | module MODULE1 #(
parameter VAR38 = 9'd32,
parameter VAR30 = 8,
parameter VAR14 = VAR38+1
)
(
input VAR40,
input VAR37, output [VAR14-1:0] VAR8, output VAR29, input VAR27,
input VAR41, input VAR42, output VAR35, input VAR19, input [31:0] VAR22, input [30:0] VAR23, input [VAR38-1:0] VAR32, input VAR6, output VAR2 );
reg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfsbp/sky130_fd_sc_hs__dfsbp_2.v | 2,246 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR8 ,
VAR6 ,
VAR2,
VAR7 ,
VAR3
);
input VAR4 ;
input VAR5 ;
output VAR8 ;
output VAR6 ;
input VAR2;
input VAR7 ;
input VAR3 ;
VAR1 VAR9 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4 ,
VAR5 ,
VAR8 ,
VAR6 ,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_ps/sky130_fd_sc_hvl__udp_dff_ps.symbol.v | 1,315 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/system_acl_iface_hps_hps_io.v | 6,777 | module MODULE1 (
output wire [14:0] VAR12, output wire [2:0] VAR13, output wire VAR23, output wire VAR43, output wire VAR24, output wire VAR22, output wire VAR26, output wire VAR5, output wire VAR34, output wire VAR2, inout wire [31:0] VAR1, inout wire [3:0] VAR36, inout wire [3:0] VAR9, output wire VAR16, output wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.pp.blackbox.v | 1,363 | module MODULE1 (
VAR4 ,
VAR3,
VAR5 ,
VAR6 ,
VAR2 ,
VAR7 ,
VAR1
);
output VAR4 ;
input VAR3;
input VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_pointer_basic_0_1/synth/design_1_pointer_basic_0_1.v | 9,882 | module MODULE1 (
VAR19,
VAR17,
VAR14,
VAR21,
VAR20,
VAR7,
VAR4,
VAR9,
VAR8,
VAR1,
VAR5,
VAR3,
VAR2,
VAR10,
VAR6,
VAR13,
VAR23,
VAR16,
VAR22,
interrupt
);
input wire [4 : 0] VAR19;
input wire VAR17;
output wire VAR14;
input wire [31 : 0] VAR21;
input wire [3 : 0] VAR20;
input wire VAR7;
output wire VAR4;
output wire [1 ... | mit |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_timing_param.v | 65,943 | module MODULE1 #
( parameter
VAR188 = 2,
VAR121 = "VAR69",
VAR64 = 3,
VAR178 = 5,
VAR37 = 4, VAR141 = 3, VAR27 = 4, VAR3 = 4, VAR103 = 6, VAR76 = 8, VAR87 = 13, VAR99 = 4, VAR90 = 4, VAR2 = 4, VAR23 = 4, VAR25 = 4, VAR175 = 5, VAR124 = 6, VAR95 = 3, VAR185 = 3, VAR114 = 10, VAR145 = 4, VAR80 = 16, VAR97 = 4,
VAR44 = 4,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/buf/sky130_fd_sc_hvl__buf.blackbox.v | 1,206 | module MODULE1 (
VAR3,
VAR6
);
output VAR3;
input VAR6;
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4.blackbox.v | 1,277 | module MODULE1 (
VAR8,
VAR9,
VAR5,
VAR2,
VAR6
);
output VAR8;
input VAR9;
input VAR5;
input VAR2;
input VAR6;
supply1 VAR7;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/new/main_array.v | 21,707 | module MODULE1(
input clk,
output reg VAR22,
output VAR6,
input [12:0] VAR38,
input [15:0] VAR55,
output reg [15:0] VAR88,
output VAR87,
output VAR77,
output reg [11:0] VAR18,
output VAR57,
output VAR56,
output VAR90,
output [7:0] VAR29,
output [7:0] VAR24,
output VAR69
);
assign VAR69 = VAR12[0];
assign VAR57 = 1'b0;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp.symbol.v | 1,387 | module MODULE1 (
input VAR7 ,
output VAR8 ,
input VAR2,
input VAR1
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.functional.v | 1,158 | module MODULE1( VAR5, VAR1, VAR12 );
input VAR1, VAR5;
output VAR12;
wire VAR2;
and VAR11( VAR2, VAR1, VAR5 );
wire VAR3;
not VAR4( VAR3, VAR1 );
wire VAR8;
not VAR9( VAR8, VAR5 );
wire VAR7;
and VAR10( VAR7, VAR3, VAR8 );
or VAR6( VAR12, VAR2, VAR7 );
endmodule | apache-2.0 |
revaldinho/opc | system/src/uart.v | 2,104 | module MODULE1 ( input[15:0] din, output[15:0] dout, input VAR12, input VAR9, input clk, input VAR3, input VAR13, input VAR8, output VAR1);
parameter VAR18 = 32000000;
parameter VAR19 = 115200;
parameter VAR4 = VAR18 / VAR19;
reg [15:0] VAR10 = 0;
reg [15:0] VAR6;
reg [10:0] VAR5;
reg [9:0] VAR14;
reg VAR7;
reg VAR2;
r... | gpl-3.0 |
parallella/oh | common/hdl/oh_add.v | 1,181 | module MODULE1 #(parameter VAR7 = 1 )
(
input [VAR7-1:0] VAR4, input [VAR7-1:0] VAR9, input VAR2, input VAR5, output [VAR7-1:0] sum, output VAR8, output VAR3, output neg, output VAR6 );
wire [VAR7-1:0] VAR1;
assign VAR1[VAR7-1:0] = {(VAR7){VAR2}} ^ VAR9[VAR7-1:0];
assign {VAR8,sum[VAR7-1:0]} = VAR4[VAR7-1:0] +
VAR1[VAR... | mit |
Canaan-Creative/MM | verilog/superkdf9/components/alink/txc.v | 4,559 | module MODULE1(
input clk ,
input rst ,
input VAR11 ,
input [VAR16-1:0] VAR13 ,
input VAR20 ,
input [31:0] VAR4 ,
input VAR9 ,
output VAR1,
output reg [VAR16-1:0]VAR5 ,
input VAR10 ,
output reg [1:0] VAR6 ,
output reg [1:0] VAR17 ,
output [32*VAR16-1:0] VAR21 ,output [VAR16-1:0] VAR3
);
parameter VAR15 = 2'b00 ;
parame... | unlicense |
MegaShow/college-programming | Homework/Computer Organization and Interfacing/Multi Cycle CPU/Multi Cycle CPU.srcs/sources_1/new/CPU.v | 4,842 | module MODULE1(
input clk,
input reset,
output wire [2:0] state,
output wire [31:0] VAR57,
output wire [31:0] VAR72,
output wire [31:0] VAR95,
output wire [31:0] VAR1,
output wire [31:0] VAR23,
output wire [31:0] VAR31,
output wire [31:0] VAR45,
output wire [31:0] VAR30
);
reg VAR20;
wire [31:0] VAR87;
wire [31:0] VAR4... | mit |
eda-globetrotter/PicenoDecoders | extra_credit/syn/netlist/ham_15_11_decoder.syn.v | 1,230 | module MODULE1 ( VAR4, VAR37 );
input [10:0] VAR4;
output [14:0] VAR37;
wire VAR24, VAR18, VAR14, VAR38, VAR13, VAR26, VAR20, VAR7, VAR25, VAR27, VAR17, VAR36, VAR16, VAR15;
assign VAR37[14] = VAR4[10];
assign VAR37[13] = VAR4[9];
assign VAR37[12] = VAR4[8];
assign VAR37[11] = VAR4[7];
assign VAR37[10] = VAR4[6];
assig... | mit |
marqs85/ossc | ip/i2c_opencores/i2c_master_byte_ctrl.v | 12,096 | module MODULE1 (
clk, rst, VAR41, VAR32, VAR7, VAR6, VAR23, read, write, VAR22, VAR25, din,
VAR39, VAR2, dout, VAR3, VAR46, VAR30, VAR48, VAR42, VAR49, VAR19, VAR44, VAR38 );
parameter VAR35 = 0;
input clk; input rst; input VAR41; input VAR32;
input [15:0] VAR7;
input VAR6;
input VAR23;
input read;
input write;
input V... | gpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/mem_if/onchip_ram_top.v | 4,332 | module MODULE1 (
input VAR12,
input VAR18,
input [31:0] VAR15,
output [31:0] VAR5,
input [31:0] VAR30,
input [3:0] VAR8,
input VAR26,
input VAR32,
input VAR6,
output VAR7,
output VAR3
);
parameter VAR23 = 12;
wire VAR27;
wire [3:0] VAR4;
reg VAR28;
reg VAR1;
assign VAR7 = VAR1 | VAR28;
assign VAR3 = VAR32 & VAR6 & (| V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.pp.symbol.v | 1,523 | module MODULE1 (
input VAR5 ,
output VAR1 ,
output VAR7 ,
input VAR9,
input VAR6 ,
input VAR4 ,
input VAR8 ,
input VAR11 ,
input VAR3 ,
input VAR2 ,
input VAR10
);
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de/der_rdmux.v | 10,120 | module MODULE1
(
input [8:2] VAR57, input [1:0] VAR53, input [1:0] VAR4, input [4:0] VAR13, input VAR41, input [14:0] VAR10, input [31:0] VAR14, input [31:0] VAR2, input [11:0] VAR52, input [11:0] VAR54, input [3:0] VAR46, input [3:0] VAR18, input [4:0] VAR51, input [3:0] VAR9, input [2:0] hdf1, input [2:0] VAR32, inpu... | gpl-3.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_slave_statem.v | 3,202 | module MODULE1 (VAR17, VAR19, VAR8, VAR10, VAR25, VAR14
VAR13, VAR15, VAR6, VAR4, VAR22,
VAR24, VAR12, VAR23, VAR16, VAR7,
VAR5, VAR11
);
input VAR17;
input VAR19;
input VAR8;
input VAR25;
input VAR10;
input VAR14; input VAR13; input VAR15;
input VAR6;
input VAR4; input VAR22;
output VAR24;
output VAR23;
output VAR12;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2.behavioral.pp.v | 1,902 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR15 ,
VAR12 ,
VAR1,
VAR4,
VAR14 ,
VAR5
);
output VAR13 ;
input VAR8 ;
input VAR15 ;
input VAR12 ;
input VAR1;
input VAR4;
input VAR14 ;
input VAR5 ;
wire VAR3 ;
wire VAR9;
VAR10 VAR6 (VAR3 , VAR8, VAR15, VAR12 );
VAR7 VAR11 (VAR9, VAR3, VAR1, VAR4);
buf VAR2 (VAR13 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a.functional.pp.v | 2,072 | module MODULE1 (
VAR1,
VAR9,
VAR4 ,
VAR2,
VAR10,
VAR5 ,
VAR7
);
input VAR1;
input VAR9;
output VAR4 ;
input VAR2;
input VAR10;
input VAR5 ;
input VAR7 ;
wire VAR7 VAR13 ;
wire VAR7 VAR12 ;
wire VAR16 ;
wire VAR6;
nand VAR15 (VAR13 , VAR10, VAR2 );
or VAR14 (VAR12 , VAR7, VAR5 );
and VAR17 (VAR16 , VAR13, VAR12 );
VAR8 ... | apache-2.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/fifo_w16_d1_A.v | 2,973 | module MODULE2 (
clk,
VAR10,
VAR3,
VAR22,
VAR20);
parameter VAR15 = 32'd16;
parameter VAR13 = 32'd1;
parameter VAR21 = 32'd2;
input clk;
input [VAR15-1:0] VAR10;
input VAR3;
input [VAR13-1:0] VAR22;
output [VAR15-1:0] VAR20;
reg[VAR15-1:0] VAR24 [0:VAR21-1];
integer VAR2;
always @ (posedge clk)
begin
if (VAR3)
begin
fo... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2.symbol.v | 1,284 | module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_mux_4to2/sky130_fd_sc_hd__udp_mux_4to2.blackbox.v | 1,298 | module MODULE1 (
VAR3 ,
VAR2,
VAR6,
VAR5,
VAR1,
VAR7,
VAR4
);
output VAR3 ;
input VAR2;
input VAR6;
input VAR5;
input VAR1;
input VAR7;
input VAR4;
endmodule | apache-2.0 |
SymbiFlow/yosys | techlibs/ice40/abc9_model.v | 3,717 | module \VAR16 (
output VAR5,
output VAR6,
input VAR14, VAR12,
input VAR4,
input VAR7, VAR3
);
parameter VAR13 = 0;
parameter VAR8 = 0;
wire VAR18 = VAR8 ? VAR4 : VAR3;
VAR2 VAR1 (
.VAR7(VAR14),
.VAR9(VAR12),
.VAR4(VAR4),
.VAR5(VAR5)
);
VAR10 #(
.VAR17(VAR13)
) VAR11 (
.VAR7(VAR7),
.VAR9(VAR14),
.VAR15(VAR12),
.VAR3(VAR... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor3/sky130_fd_sc_hs__xnor3.behavioral.pp.v | 1,725 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR12 ,
VAR1 ,
VAR5,
VAR9
);
output VAR8 ;
input VAR11 ;
input VAR12 ;
input VAR1 ;
input VAR5;
input VAR9;
wire VAR6 ;
wire VAR3;
xnor VAR2 (VAR6 , VAR11, VAR12, VAR1 );
VAR4 VAR7 (VAR3, VAR6, VAR5, VAR9);
buf VAR10 (VAR8 , VAR3 );
endmodule | apache-2.0 |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab/components.v | 3,907 | module MODULE2(VAR3, VAR7, clk, VAR6, VAR5);
input [31:0] VAR3;
output [31:0] VAR7;
input clk, VAR6, VAR5;
reg [31:0] register;
always @(posedge clk or posedge VAR6)
begin
if(VAR6)
register = 0;
end
else
if(VAR5 == 1)
register = VAR3;
end
assign VAR7 = register;
endmodule
module MODULE1;
reg [31:0] VAR4;
wire [31:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ha/sky130_fd_sc_ls__ha.symbol.v | 1,274 | module MODULE1 (
input VAR6 ,
input VAR5 ,
output VAR4,
output VAR1
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222oi/sky130_fd_sc_hs__a222oi_2.v | 2,415 | module MODULE1 (
VAR11 ,
VAR8 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR7 ,
VAR1,
VAR9
);
output VAR11 ;
input VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR1;
input VAR9;
VAR5 VAR10 (
.VAR11(VAR11),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VA... | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/phyInitial.v | 7,821 | module MODULE1 (
input clk,reset,
input VAR22,
input [3:0]VAR55,
input [31:0] VAR65,
input [15:0]VAR63,
inout VAR51,
inout VAR43,
output VAR25,
output reg [3: 0] VAR58,
output reg VAR35,
output reg [12:0]VAR31,
output [15:0]VAR40,
output VAR38,
output VAR19
);
wire VAR68;
wire VAR10, VAR18, VAR4, VAR21;
wire [15:0] VAR... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_oqdp.v | 29,789 | module MODULE1(
VAR6, VAR92, VAR173, VAR108,
VAR157, VAR44, VAR125,
VAR29, VAR42, VAR75,
VAR101, VAR128, VAR24,
VAR100, VAR119, VAR25,
VAR115, VAR46, VAR70,
VAR104, VAR18, VAR48,
VAR40, VAR140, VAR33,
VAR15, VAR83, VAR175, VAR97,
VAR74, VAR87, VAR1,
VAR117, VAR131, VAR78, VAR11,
VAR137, VAR93, VAR86,
VAR53, VAR61, VAR8... | gpl-2.0 |
rkrajnc/minimig-de1 | rtl/soc/minimig_mist_top.v | 14,284 | module MODULE1 (
input wire [ 2-1:0] VAR181, input wire [ 2-1:0] VAR199, input wire [ 2-1:0] VAR179, output wire VAR90, output wire VAR32, input wire VAR175, output wire VAR85, output wire VAR28, output wire [ 6-1:0] VAR71, output wire [ 6-1:0] VAR123, output wire [ 6-1:0] VAR157, inout wire [ 16-1:0] VAR225, output wi... | gpl-3.0 |
tofuman/nand-proz | Prozessor/ALU.v | 1,039 | module MODULE1 (VAR2, VAR7, VAR6, VAR8, VAR4, enable);
input wire [7:0] VAR2, VAR7;
output reg [7:0] VAR6;
input wire [4:0] VAR4;
output reg [2:0] VAR8;
input wire enable;
wire [8:0] VAR1, VAR5, VAR3;
always @ (posedge enable )
begin
case (VAR4)
2'b00000 :begin
VAR1 = {1'b0, VAR2};
VAR5 = {1'b0, VAR7};
VAR3 = VAR1 + VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor2/sky130_fd_sc_hd__xor2.pp.blackbox.v | 1,291 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR6 ,
VAR7,
VAR2,
VAR5 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR7;
input VAR2;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | tdpram.v | 4,639 | module MODULE1
integer VAR6;
reg [VAR15-1:0] VAR12 [0:VAR14-1]; VAR8
if (VAR7)
for (VAR6=0; VAR6<VAR14; VAR6=VAR6+1) VAR12[VAR6] = {VAR15{1'b0}};
else
if (VAR9 != "")
always @(posedge clk) begin
if (VAR5) begin
VAR12[VAR11] <= VAR2; VAR13 <= VAR2; end else
VAR13 <= VAR12[VAR11]; end
always @(posedge clk) begin
if (VAR3... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a.functional.pp.v | 2,047 | module MODULE1 (
VAR13 ,
VAR17 ,
VAR11 ,
VAR16 ,
VAR14 ,
VAR12 ,
VAR15,
VAR18,
VAR8 ,
VAR4
);
output VAR13 ;
input VAR17 ;
input VAR11 ;
input VAR16 ;
input VAR14 ;
input VAR12 ;
input VAR15;
input VAR18;
input VAR8 ;
input VAR4 ;
wire VAR2 ;
wire VAR3 ;
wire VAR1;
or VAR5 (VAR2 , VAR14, VAR16, VAR11, VAR17 );
and VAR1... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mig_37.v | 34,114 | module MODULE1 #
(
parameter VAR175 = 200,
parameter VAR31 = "VAR127",
parameter VAR140 = "VAR224",
parameter VAR80 = 6,
parameter VAR142 = 2,
parameter VAR255 = 3,
parameter VAR69 = 2,
parameter VAR254 = 2500,
parameter VAR11 = "VAR93",
parameter VAR246 = "VAR65",
parameter VAR14 = 1,
parameter VAR199 = 3,
parameter V... | lgpl-3.0 |
ChrisPVille/RL02 | FPGA/driveControl.v | 9,879 | module MODULE1(
input clk,
input rst,
input [15:0] VAR2,
input VAR6,
input VAR7,
input [5:0] VAR16,
input [8:0] VAR39,
input VAR14,
input VAR28,
input VAR44,
input VAR20,
input VAR29,
input VAR15,
input VAR43,
output reg VAR4,
output reg VAR12,
output reg VAR41,
output reg VAR40,
output reg VAR27,
output VAR35
);
reg [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbn/sky130_fd_sc_ls__dlxbn.blackbox.v | 1,339 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR7
);
output VAR4 ;
output VAR1 ;
input VAR2 ;
input VAR7;
supply1 VAR8;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/axis_xgmii_rx_32.v | 11,996 | module MODULE1 #
(
parameter VAR16 = 32,
parameter VAR7 = (VAR16/8),
parameter VAR14 = (VAR16/8),
parameter VAR17 = 0,
parameter VAR11 = 96,
parameter VAR4 = (VAR17 ? VAR11 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR16-1:0] VAR6,
input wire [VAR14-1:0] VAR2,
output wire [VAR16-1:0] VAR8,
output wire [V... | mit |
jotego/jt12 | hdl/mixer/jt12_comb.v | 1,627 | module MODULE1 #(parameter
VAR1=16, VAR5=1 )(
input rst,
input clk,
input VAR9,
input signed [VAR1-1:0] VAR3,
output reg signed [VAR1-1:0] VAR6
);
wire signed [VAR1-1:0] VAR8;
generate
genvar VAR2;
reg signed [VAR1-1:0] VAR7[0:VAR5-1];
assign VAR8=VAR7[VAR5-1];
for(VAR2=0;VAR2<VAR5;VAR2=VAR2+1) begin : VAR4
always @(po... | gpl-3.0 |
chahuja/hilbert-fpga | mpuc1307.v | 1,784 | module MODULE1 ( VAR10,VAR19 ,VAR12, VAR22,VAR18,VAR11 ,VAR8 ,VAR21 );
parameter VAR2 = 32;
input VAR10 ;
wire VAR10 ;
input VAR19 ;
wire VAR19 ;
input VAR12; input VAR22 ; wire VAR22 ;
input [VAR2-1:0] VAR18 ;
wire signed [VAR2-1:0] VAR18 ;
input [VAR2-1:0] VAR11 ;
wire signed [VAR2-1:0] VAR11 ;
output [VAR2:0] VAR8 ;... | gpl-2.0 |
m-labs/milkymist | cores/ac97/rtl/ac97_ctlif.v | 4,605 | module MODULE1 #(
parameter VAR17 = 4'h0
) (
input VAR18,
input VAR5,
input [13:0] VAR7,
input VAR16,
input [31:0] VAR10,
output reg [31:0] VAR20,
output reg VAR32,
output reg VAR38,
output reg VAR29,
output reg VAR2,
input VAR3,
input VAR33,
output reg VAR30,
output reg [19:0] VAR15,
output reg VAR11,
output reg [19:0... | lgpl-3.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T29-tristate/tristate2.v | 1,852 | module MODULE1 (
input wire clk, output wire VAR8);
parameter VAR6 = VAR7;
wire VAR1;
wire VAR4;
reg VAR11 = 0;
reg [3:0] VAR12;
reg VAR2;
always @(posedge clk)
VAR2 <= 1'b1;
reg VAR13;
always @(posedge clk)
VAR13 <= 1'b0;
reg VAR3;
always @(posedge clk)
VAR3 <= 1'b1;
assign VAR4 = (VAR12[0]) ? VAR2 : 1'VAR5;
assign VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.v | 2,678 | module MODULE2 (
VAR6 ,
VAR12 ,
VAR5 ,
VAR9 ,
VAR11 ,
VAR10,
VAR3 ,
VAR7 ,
VAR1 ,
VAR13 ,
VAR8
);
output VAR6 ;
input VAR12 ;
input VAR5 ;
input VAR9 ;
input VAR11 ;
input VAR10;
input VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR13 ;
input VAR8 ;
VAR4 VAR2 (
.VAR6(VAR6),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR11(VA... | apache-2.0 |
joaocarlos/udlx-verilog | rtl/common/mux_sdram.v | 1,024 | module MODULE1
parameter VAR4 = 32,
parameter VAR3 = 32
)
(
input VAR5,
input [VAR4-1:0] VAR6,
input [VAR3-1:0] VAR2,
output reg [VAR4-1:0] VAR8,
output reg VAR1,
output reg [VAR4-1:0] VAR7,
output reg VAR9
);
always @(*) begin
if (VAR5) begin
if(VAR2[VAR3-1]==1) begin
VAR8 = VAR6;
VAR1 =1;
VAR9 = 0;
VAR7 = {VAR4{1'b0}... | lgpl-3.0 |
stevenokm/mor1kx | rtl/verilog/mor1kx_fetch_prontoespresso.v | 18,958 | module MODULE1
(
VAR89, VAR10, VAR95, VAR93, VAR17,
VAR26, VAR47, VAR76, VAR53,
VAR81, VAR2, VAR96,
VAR34, VAR59, VAR21,
clk, rst, VAR14, VAR24, VAR48, VAR77, VAR51,
VAR86, VAR66, VAR8, VAR79,
VAR13, VAR58, VAR46,
VAR42, VAR7, VAR25, VAR11, VAR50,
VAR3, VAR29, VAR4, VAR75
);
parameter VAR33 = 32;
parameter VAR20 = 5;
p... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp.pp.symbol.v | 1,336 | module MODULE1 (
input VAR8 ,
input VAR7 ,
input VAR1,
output VAR2,
input VAR3 ,
input VAR6,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/addsub/FPU_ADD_Substract_PIPELINED.v | 24,837 | module MODULE1
/*#(parameter VAR120 = 32, parameter VAR25 = 8, parameter VAR101 = 23,
parameter VAR155=26, parameter VAR149 = 5)
parameter VAR155 = 55, parameter VAR149 = 6) (
input wire clk,
input wire rst,
input wire VAR38,
input wire [VAR120-1:0] VAR141,
input wire [VAR120-1:0] VAR1,
input wire VAR81,
output wire VA... | gpl-3.0 |
peteg944/music-fpga | Microphone code (not used)/Microphone.v | 2,865 | module MODULE1(
output VAR20, output VAR19, output reg VAR30, input VAR9, input clk,
input rst,
input VAR24, output reg VAR16, output reg [9:0] VAR22
);
reg VAR1;
reg [9:0] VAR8;
reg VAR14, VAR29;
reg VAR2;
reg [7:0] VAR13, VAR6;
wire [7:0] VAR17;
wire VAR15;
VAR12 #(6) VAR4(clk, rst, VAR9, VAR19, VAR20, VAR14, VAR13, ... | mit |
fabianmcg/usbc_tcpc | src/tcpci.v | 3,680 | module MODULE1(output wire VAR6,
output wire VAR26,
output wire VAR29,
output wire VAR24,
output wire VAR36,
output wire VAR50,
output wire VAR52,
output wire VAR37,
output wire VAR22,
output wire VAR23,
output wire VAR40,
output wire VAR48,
output wire VAR21,
output wire [7:0] VAR10,
output wire [7:0] VAR44,
output wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi_1.v | 2,361 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR11 ,
VAR7 ,
VAR8,
VAR10,
VAR2 ,
VAR6
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR11 ;
input VAR7 ;
input VAR8;
input VAR10;
input VAR2 ;
input VAR6 ;
VAR9 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.... | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_decerr_slave.v | 9,276 | module MODULE1 #
(
parameter integer VAR21 = 1,
parameter integer VAR9 = 32,
parameter integer VAR44 = 1,
parameter integer VAR30 = 1,
parameter integer VAR41 = 0,
parameter integer VAR37 = 2'b11
)
(
input wire VAR7,
input wire VAR47,
input wire [(VAR21-1):0] VAR36,
input wire VAR33,
output wire VAR15,
input wire VAR34... | gpl-3.0 |
CospanDesign/python | game/panda/panda_path/example_project/rtl/dependencies/uart_fifo.v | 4,519 | module MODULE1 (
clk,
rst,
VAR9,
VAR29,
VAR31,
VAR15,
VAR6,
VAR26,
VAR14,
VAR27,
VAR22,
VAR32,
VAR28
);
parameter VAR20 = 10;
input clk;
input rst;
output wire [31:0] VAR9;
input VAR29;
output wire [31:0] VAR31;
input [7:0] VAR15;
input VAR6;
output reg [31:0] VAR26;
output wire [7:0] VAR14;
output reg VAR27;
output re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b_1.v | 2,300 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR1 ,
VAR8 ,
VAR5 ,
VAR2,
VAR10,
VAR4 ,
VAR6
);
output VAR3 ;
input VAR11 ;
input VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR10;
input VAR4 ;
input VAR6 ;
VAR7 VAR9 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR4(VAR4),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.behavioral.v | 1,262 | module MODULE1( VAR4, VAR3, VAR2, VAR7 );
input VAR7, VAR2, VAR3;
output VAR4;
VAR5 VAR1(.VAR4(VAR4),.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7));
VAR5 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
skarpenko/ultiparc | rtl/src/cpu/uparc_ifu.v | 3,426 | module MODULE1(
clk,
VAR5,
addr,
VAR7,
VAR1,
VAR2,
VAR4,
VAR8,
VAR16,
VAR14,
VAR3,
VAR17,
VAR12
);
localparam VAR6 = 1'b0;
localparam VAR11 = 1'b1;
input wire clk;
input wire VAR5;
input wire [VAR15-1:0] addr;
output wire [VAR10-1:0] VAR7;
input wire VAR1;
output wire VAR2;
output wire VAR4;
output wire VAR8;
output re... | bsd-2-clause |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_data_shift.v | 13,735 | module MODULE1
parameter VAR1 = 1,
parameter VAR19 = 1,
parameter VAR71 = 128,
parameter VAR17 = "VAR77"
)
(
input VAR47,
input VAR70,
input VAR75,
input [VAR71-1:0] VAR80,
input VAR37,
input [VAR61(VAR71/32)-1:0] VAR26,
input VAR60,
input [VAR61(VAR71/32)-1:0] VAR35,
output VAR69,
input VAR39,
output [VAR71-1:0] VAR28... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai.functional.v | 1,600 | module MODULE1 (
VAR10 ,
VAR6,
VAR9,
VAR1,
VAR11,
VAR12
);
output VAR10 ;
input VAR6;
input VAR9;
input VAR1;
input VAR11;
input VAR12;
wire VAR3 ;
wire VAR7 ;
wire VAR13;
or VAR5 (VAR3 , VAR11, VAR1 );
or VAR8 (VAR7 , VAR9, VAR6 );
nand VAR4 (VAR13, VAR7, VAR3, VAR12);
buf VAR2 (VAR10 , VAR13 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_bb.v | 3,233 | module MODULE1 (
VAR19,
VAR8,
VAR36,
VAR14,
VAR13,
VAR5,
VAR18,
VAR37,
VAR2,
VAR33,
VAR21,
VAR17,
VAR16,
VAR31,
VAR1,
VAR34,
VAR20,
VAR26,
VAR23,
VAR25,
VAR10,
VAR28,
VAR6,
VAR32,
VAR35,
VAR27,
VAR22,
VAR11,
VAR7,
VAR4,
VAR9,
VAR30,
VAR3,
VAR29,
VAR12,
VAR24,
VAR15);
input [23:0] VAR19;
input VAR8;
input VAR36;
input V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1n/sky130_fd_sc_hd__lpflow_inputiso1n.functional.pp.v | 1,899 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR13,
VAR12 ,
VAR1 ,
VAR2 ,
VAR8
);
output VAR7 ;
input VAR10 ;
input VAR13;
input VAR12 ;
input VAR1 ;
input VAR2 ;
input VAR8 ;
wire VAR3 ;
wire VAR11;
not VAR4 (VAR3 , VAR13 );
or VAR5 (VAR11, VAR10, VAR3 );
VAR9 VAR6 (VAR7 , VAR11, VAR12, VAR1);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.pp.symbol.v | 1,474 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR5,
input VAR8 ,
input VAR1 ,
input VAR2 ,
input VAR7 ,
input VAR3
);
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/ddr_dq_iobs.v | 3,770 | module MODULE1 (
VAR5,
VAR13,
VAR18,
VAR3,
VAR8,
VAR16,
VAR17,
VAR1
);
input VAR5;
input VAR13;
input VAR18;
input VAR3;
input VAR8;
inout [7:0] VAR16;
input [15:0] VAR17;
output [15:0] VAR1;
VAR15 VAR20 (
.VAR10 (VAR5),
.VAR6 (~VAR5),
.VAR18 (VAR18),
.VAR9 (VAR3),
.VAR4 (VAR8),
.VAR17 ({VAR17 [8], VAR17 [0]}),
.VAR1 (... | lgpl-3.0 |
jhennessy/parallella-hw-old | fpga/hdl/parallella-I/parallella_z7_top.v | 36,165 | module MODULE1 (
VAR261,
VAR133, VAR56, VAR12,
VAR148, VAR157, VAR32, VAR14, VAR237,
VAR114, VAR62, VAR41, VAR205, VAR242,
VAR91, VAR238,
VAR274, VAR81,
VAR96, VAR140,
VAR146, VAR250,
VAR116, VAR110,
VAR124, VAR135,
VAR94, VAR172,
VAR117, VAR121,
VAR248, VAR226, VAR76,
VAR90, VAR147,
VAR190,
VAR34, VAR270, VAR150, VAR2... | gpl-3.0 |
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