repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41ai/sky130_fd_sc_hd__o41ai_2.v | 2,424 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR2 ,
VAR12 ,
VAR9 ,
VAR4 ,
VAR7,
VAR5,
VAR8 ,
VAR1
);
output VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR12 ;
input VAR9 ;
input VAR4 ;
input VAR7;
input VAR5;
input VAR8 ;
input VAR1 ;
VAR11 VAR10 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR... | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/afifo.v | 6,425 | module MODULE1(
din,
VAR3,
VAR11,
VAR37,
VAR27,
VAR14,
dout,
VAR32,
VAR1,
VAR23,
VAR15,
VAR17,
VAR28,
VAR22);
parameter VAR30 =16;
parameter VAR4 =8;
parameter VAR29 =8;
parameter VAR16 =8;
input [VAR30-1:0] din;
input VAR3;
input VAR11;
input VAR37;
input VAR27;
input VAR14;
output [VAR30-1:0] dout;
output VAR32;
outp... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_4.functional.pp.v | 3,028 | module MODULE1( VAR25, VAR37, VAR36, VAR8, VAR6, VAR9, VAR10, VAR1, VAR5 );
input VAR10, VAR9, VAR8, VAR6, VAR36, VAR37;
inout VAR1, VAR5;
output VAR25;
wire VAR27;
not VAR13( VAR27, VAR10 );
wire VAR2;
not VAR14( VAR2, VAR8 );
wire VAR3;
not VAR15( VAR3, VAR36 );
wire VAR29;
and VAR12( VAR29, VAR27, VAR2, VAR3 );
wire... | apache-2.0 |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | bin2bcd16.v | 3,173 | module MODULE1 (
input [15:0] VAR1, output reg [19:0] VAR2 );
reg [35:0] VAR4;
integer VAR3;
always @(VAR1) begin
for(VAR3 = 0; VAR3 <= 35; VAR3 = VAR3+1) VAR4[VAR3] = 0;
VAR4[18:3] = VAR1;
for(VAR3 = 0; VAR3 <= 12; VAR3 = VAR3+1) begin
if(VAR4[19:16] > 4) VAR4[19:16] = VAR4[19:16] + 3;
if(VAR4[23:20] > 4) VAR4[23:20] ... | bsd-3-clause |
keith-epidev/VHDL-lib | top/mono_radio/ip/multi_QI/multi_QI_stub.v | 1,200 | module MODULE1(VAR2, VAR3, VAR4, VAR1)
;
input VAR2;
input [15:0]VAR3;
input [15:0]VAR4;
output [31:0]VAR1;
endmodule | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/fifo_packer_128.v | 5,107 | module MODULE1 (
input VAR18,
input VAR1,
input [127:0] VAR8, input [2:0] VAR15, input VAR16, input VAR5, input VAR20, output [127:0] VAR7, output VAR11, output VAR22, output VAR12, output VAR19 );
reg [2:0] VAR23=0, VAR23=0;
reg VAR24=0, VAR24=0;
reg VAR14=0, VAR14=0;
reg VAR6=0, VAR6=0;
reg VAR3=0, VAR3=0;
reg [223:0... | gpl-3.0 |
asicguy/gplgpu | hdl/ramdac_sp/ram_ctl.v | 3,653 | module MODULE1
(
input VAR10,
input VAR14,
input VAR4,
input VAR16,
input [7:0] VAR8,
input [7:0] VAR2,
input [7:0] VAR3,
input [7:0] VAR17,
input [7:0] VAR9,
input [7:0] VAR13,
output reg [7:0] VAR7, output reg [7:0] VAR15, output reg [7:0] VAR1, output reg [7:0] VAR5,
output reg [7:0] VAR11,
output reg [7:0] VAR12
);... | gpl-3.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/PackSum_y.v | 1,928 | module MODULE1(
input [1:0] VAR6,
input [31:0] VAR1,
input [1:0] VAR12,
input VAR3,
input [27:0] VAR11,
input [7:0] VAR5,
input VAR9,
output reg [31:0] VAR8,
output reg VAR17 = 1'b0
);
parameter VAR4 =2'b01,
VAR7 =2'b00,
VAR10=2'b11;
parameter VAR14 = 2'b00,
VAR16 = 2'b01,
VAR2 = 2'b10;
wire VAR15;
wire [7:0] VAR13;
as... | apache-2.0 |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkCSR_MIE.v | 5,900 | module MODULE1(VAR6,
VAR2,
VAR13,
VAR9,
VAR36,
VAR17,
VAR7,
VAR8,
VAR3,
VAR16,
VAR12,
VAR27,
VAR32);
input VAR6;
input VAR2;
input VAR13;
output [63 : 0] VAR9;
input [27 : 0] VAR36;
input [63 : 0] VAR17;
input VAR7;
output [63 : 0] VAR8;
output [63 : 0] VAR3;
input [27 : 0] VAR16;
input [63 : 0] VAR12;
input VAR27;
out... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_6sig_x2.v | 8,691 | module MODULE1(VAR58 ,VAR6 ,VAR47 ,
VAR91 ,VAR2 ,VAR15 ,VAR123 ,VAR31 ,
VAR101 ,VAR32 ,VAR23 ,VAR92 ,VAR122 ,
VAR53 ,VAR67 ,VAR13 ,VAR20 ,VAR115 ,
VAR106 ,VAR55 ,VAR73 ,VAR69 ,VAR64 ,
VAR119 ,VAR29 ,VAR4 ,VAR63 ,
VAR83 ,VAR22 ,
VAR46 ,VAR104 ,VAR54 , VAR18,
VAR85 ,VAR51 ,VAR25 ,
VAR97 ,VAR9 ,VAR82 ,VAR11 ,VAR117 ,
VAR2... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_sym_dec.v | 17,758 | module MODULE1
(
VAR9,
VAR34,
VAR56,
VAR64,
VAR10,
VAR21,
VAR36,
VAR26,
VAR40,
VAR62,
VAR57,
VAR29,
VAR1,
VAR3,
VAR47,
VAR14
);
parameter VAR30 = 4'hb;
parameter VAR51 = 4'hc;
parameter VAR16 = 4'h4;
parameter VAR19 = 4'ha;
parameter VAR55 = 4'h2;
parameter VAR18 = 4'hc;
parameter VAR2 = 4'hb;
parameter VAR49 = 4'h5;
p... | gpl-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/T_Rot/TOP_Rotation_tst.v | 2,552 | module MODULE1;
reg clk;
reg rst;
reg [15:0] VAR15;
reg [15:0] VAR2;
reg [15:0] VAR8;
reg [31:0] VAR1;
reg enable;
reg [7:0] VAR16;
reg VAR10;
reg VAR13;
reg [31:0] VAR6;
wire VAR7;
wire [31:0] VAR12;
wire [31:0] VAR11;
wire [31:0] VAR3;
reg [15:0] VAR9;
reg [15:0] VAR4;
reg[8:0] VAR17;
VAR5 VAR14 (
.clk(clk),
.rst(rst... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3_4.v | 2,198 | module MODULE2 (
VAR4 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR1,
VAR7,
VAR3 ,
VAR10
);
output VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR1;
input VAR7;
input VAR3 ;
input VAR10 ;
VAR8 VAR2 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcon/sky130_fd_sc_hs__fahcon.pp.symbol.v | 1,324 | module MODULE1 (
input VAR1 ,
input VAR3 ,
input VAR6 ,
output VAR7,
output VAR5 ,
input VAR2 ,
input VAR4
);
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | rtl/minimig/Copper.v | 16,884 | module MODULE1
(
input clk, input reset, input VAR17, output VAR22, input VAR5, input VAR23, input VAR51, input VAR43, input [7:0] VAR39, input [8:0] VAR28, input [15:0] VAR48, input [8:1] VAR15, output reg [8:1] VAR53, output reg [20:1] VAR41 );
parameter VAR14 = 9'h080;
parameter VAR19 = 9'h082;
parameter VAR9 = 9'h0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b.blackbox.v | 1,322 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR5;
supply1 VAR6;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/niosII_system/submodules/niosII_system_video_vga_controller_0.v | 9,855 | module MODULE1 (
clk,
reset,
VAR52,
VAR51,
VAR24,
VAR18,
valid,
ready,
VAR25,
VAR10,
VAR5,
VAR39,
VAR49,
VAR17,
VAR54,
VAR42
);
parameter VAR33 = 9;
parameter VAR27 = 29;
parameter VAR30 = 29;
parameter VAR53 = 20;
parameter VAR47 = 19;
parameter VAR28 = 10;
parameter VAR45 = 9;
parameter VAR35 = 0;
parameter VAR55 = 6... | gpl-2.0 |
hakehuang/pycpld | ips/ip/ir_recieve/ir_recieve.v | 2,431 | module MODULE1(
clk, rst, VAR7, VAR2,VAR10
);
input clk;
input rst;
input VAR7;
output VAR2;
output [10:0] VAR10;
reg[1:0] VAR8;
wire VAR6;
wire VAR1;
reg[10:0] VAR10;
reg[7:0] VAR4;
reg[7:0] VAR5;
reg VAR2;
reg [31:0] VAR11;
reg [2:0] VAR3;
reg VAR9;
always @(posedge clk or negedge rst)begin
if(!rst)begin
VAR3 <= 'h0;... | mit |
LSaldyt/qnp | output/vs/opt_var7_multi.v | 3,695 | module MODULE1(VAR4, VAR1, VAR7, VAR3, VAR5, VAR6, VAR2, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022;
wire 023;
wire 024;
wire ... | mit |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,553 | module MODULE1
parameter VAR30 = 8,
VAR38 = 8,
VAR1 = 0,
VAR26 = 0,
VAR6 = 1,
VAR7 = 0,
VAR36 = 1,
VAR18 = 2,
VAR3 = 2,
VAR45 = 1,
VAR39 = VAR30 / VAR38,
VAR43 = VAR2(VAR39)
)
(
input VAR24,
input VAR17,
input VAR29,
input VAR22,
output VAR37,
input VAR33,
input [VAR30 - 1 : 0] VAR20,
input [VAR6 - 1 : 0] VAR40,
input ... | gpl-3.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T06-multiples-prescalers/mpres.v | 1,937 | module MODULE1(input VAR12, output VAR1, output VAR19, output VAR18, output VAR14);
wire VAR12;
wire VAR1;
wire VAR19;
wire VAR18;
wire VAR14;
parameter VAR4 = 21; parameter VAR9 = 1;
parameter VAR10 = 2;
parameter VAR5 = 1;
parameter VAR16 = 2;
wire VAR17;
VAR2 #(.VAR8(VAR4))
VAR6(
.VAR12(VAR12),
.VAR13(VAR17)
);
VAR2... | gpl-2.0 |
zYeoman/32BIT-MIPS-CPU | Single/Control.v | 5,053 | module MODULE1 (
input irq, VAR14,
input [5:0] VAR16, VAR5,
output [2:0] VAR18,
output [1:0] VAR19, VAR6, VAR22,
output VAR11, VAR35, VAR7, VAR24,
VAR33, VAR27, VAR4, VAR28, VAR29,
output reg [5:0] VAR23
);
wire VAR17; reg [5:0] VAR15;
parameter VAR8 = 6'b000000;
parameter VAR25 = 6'b000001;
parameter VAR13 = 6'b011000... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311oi/sky130_fd_sc_lp__a311oi.pp.symbol.v | 1,402 | module MODULE1 (
input VAR10 ,
input VAR4 ,
input VAR2 ,
input VAR5 ,
input VAR9 ,
output VAR6 ,
input VAR1 ,
input VAR8,
input VAR3,
input VAR7
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_1.functional.v | 1,378 | module MODULE1( VAR8, VAR3, VAR13, VAR12, VAR11 );
input VAR11, VAR12, VAR13, VAR8;
output VAR3;
wire VAR14;
not VAR4( VAR14, VAR11 );
wire VAR7;
not VAR6( VAR7, VAR12 );
wire VAR9;
not VAR5( VAR9, VAR13 );
wire VAR1;
not VAR2( VAR1, VAR8 );
and VAR10( VAR3, VAR14, VAR7, VAR9, VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2.symbol.v | 1,322 | module MODULE1 (
input VAR3,
output VAR5
);
supply1 VAR6;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3.pp.symbol.v | 1,357 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR6 ,
input VAR5,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
Franderg/CE-4301-Arqui1 | Processor/unsaved/synthesis/submodules/unsaved_onchip_memory2_0.v | 3,237 | module MODULE1 (
address,
VAR9,
VAR20,
clk,
VAR39,
VAR34,
VAR4,
reset,
VAR16,
write,
VAR22,
VAR44
)
;
output [ 31: 0] VAR44;
input [ 4: 0] address;
input [ 3: 0] VAR9;
input VAR20;
input clk;
input VAR39;
input VAR34;
input VAR4;
input reset;
input VAR16;
input write;
input [ 31: 0] VAR22;
wire VAR28;
wire [ 31: 0] VA... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/HardFloat/source/recFNToRecFN.v | 4,789 | module
MODULE1#(
parameter VAR21 = 3,
parameter VAR13 = 3,
parameter VAR8 = 3,
parameter VAR15 = 3
) (
input [(VAR10 - 1):0] VAR11,
input [(VAR21 + VAR13):0] in,
input [2:0] VAR5,
output [(VAR8 + VAR15):0] out,
output [4:0] VAR7
);
wire VAR23, VAR22, VAR19, VAR1;
wire signed [(VAR21 + 1):0] VAR16;
wire [VAR13:0] VAR3;
... | bsd-3-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ip_compiler_for_pci_express-library/altpcie_pll_250_100.v | 10,974 | module MODULE1 (
VAR41,
VAR11,
VAR32);
input VAR41;
input VAR11;
output VAR32;
wire [5:0] VAR14;
wire [0:0] VAR26 = 1'h0;
wire [0:0] VAR37 = 1'h1;
wire [0:0] VAR10 = VAR14[0:0];
wire VAR32 = VAR10;
wire [5:0] VAR47 = {VAR26, VAR26, VAR26, VAR26, VAR26, VAR37};
wire VAR29 = VAR11;
wire [1:0] VAR1 = {VAR26, VAR29};
wire ... | mit |
alexforencich/xfcp | lib/eth/rtl/axis_eth_fcs_insert.v | 11,227 | module MODULE1 #
(
parameter VAR34 = 0,
parameter VAR17 = 64
)
(
input wire clk,
input wire rst,
input wire [7:0] VAR58,
input wire VAR3,
output wire VAR55,
input wire VAR35,
input wire VAR23,
output wire [7:0] VAR46,
output wire VAR62,
input wire VAR15,
output wire VAR49,
output wire VAR38,
output wire VAR30
);
localp... | mit |
CalvinHsu1223/LinuxCNC-EtherCAT-HAL-Driver | src/hal/drivers/pluto_servo_firmware/quad.v | 1,769 | module MODULE1(clk, VAR8, VAR12, VAR13, VAR3, out);
parameter VAR15=14;
input clk, VAR8, VAR12, VAR13, VAR3;
reg [(VAR15-1):0] VAR9, VAR2; reg VAR10;
output [2*VAR15:0] out = { VAR10, VAR2, VAR9 };
reg [2:0] VAR1, VAR17;
reg [2:0] VAR16;
always @(posedge clk) VAR1 <= {VAR1[1:0], VAR8};
always @(posedge clk) VAR17 <= {V... | gpl-2.0 |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/ppu/gamma_module.v | 4,602 | module MODULE1(
VAR30,
VAR31,
VAR18,
VAR5,
VAR19,
VAR6,
VAR15
);
input VAR30;
input VAR31;
input [ 3:0] VAR18;
input VAR5;
input [VAR11] VAR19;
output reg VAR6;
output reg [VAR11] VAR15 = {VAR3{1'b0}};
wire VAR14 = ~(VAR18 == VAR7);
wire [3:0] VAR27 = (VAR18 < VAR7) ? VAR18 :
VAR18 - 1'b1;
wire [2:0] VAR1 = VAR27[2:0];... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/mem_lipo_1p_bw.v | 12,985 | module MODULE1 (
clk ,
VAR54 ,
VAR38 ,
VAR40 ,
VAR7 ,
VAR48 ,
VAR43 ,
VAR47 ,
VAR42 ,
VAR55 ,
VAR25 ,
VAR35
);
localparam VAR26 = 2'b00,
VAR50 = 2'b01,
VAR49 = 2'b10,
VAR9 = 2'b11;
input clk ; input VAR54 ;
input [3:0] VAR38 ; input [7:0] VAR40 ; input [VAR34*32-1:0] VAR7 ;
input VAR48 ; input VAR43 ; input [1:0] VAR47... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_src0_data_stream_0_V.v | 3,013 | module MODULE2 (
clk,
VAR5,
VAR8,
VAR25,
VAR18);
parameter VAR20 = 32'd8;
parameter VAR3 = 32'd1;
parameter VAR7 = 32'd2;
input clk;
input [VAR20-1:0] VAR5;
input VAR8;
input [VAR3-1:0] VAR25;
output [VAR20-1:0] VAR18;
reg[VAR20-1:0] VAR21 [0:VAR7-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR8)
begin
for (VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor2/sky130_fd_sc_ls__xnor2_4.v | 2,132 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR9,
VAR8,
VAR7 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR9;
input VAR8;
input VAR7 ;
input VAR3 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4,
VAR1,
VAR2
);
output VAR4;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxbp/sky130_fd_sc_ms__edfxbp.pp.symbol.v | 1,447 | module MODULE1 (
input VAR6 ,
output VAR5 ,
output VAR2 ,
input VAR7 ,
input VAR3 ,
input VAR9 ,
input VAR1,
input VAR8,
input VAR4
);
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de/ded_cactrl.v | 8,036 | module MODULE1
(
input VAR53,
input VAR28,
input VAR30, input VAR20,
input VAR35,
input VAR31,
input VAR9,
input VAR36, input VAR38, input VAR7, input [9:0] VAR18, input [8:0] VAR44, input [4:0] VAR5, input [6:0] VAR42, input VAR19, input [1:0] VAR61, input [1:0] VAR1, input [1:0] VAR58, input [1:0] VAR29, input [2:0] ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_1.behavioral.v | 1,173 | module MODULE1( VAR2, VAR3, VAR4 );
input VAR2, VAR3;
output VAR4;
VAR5 VAR1(.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4));
VAR5 VAR6(.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/synthesis/submodules/ik_swift_master_0_timing_adt.v | 1,773 | module MODULE1 (
input clk,
input VAR3,
input VAR6,
input [ 7: 0] VAR1,
output reg VAR8,
output reg [ 7: 0] VAR9,
input VAR7
);
reg [ 7: 0] VAR4;
reg [ 7: 0] VAR5;
reg [ 0: 0] ready;
reg VAR2;
always @(negedge VAR2) begin
end
always @* begin
VAR4 = {VAR1};
{VAR9} = VAR5;
end
always @* begin
ready[0] = VAR7;
VAR8 = VAR6... | mit |
VerticalResearchGroup/miaow | src/verilog/rtl/issue/alu_issue_logic.v | 6,708 | module MODULE1
(
VAR41, VAR7, VAR3,
VAR23, VAR2, VAR15,
VAR19, VAR10, VAR26,
VAR35, VAR1, VAR25,
clk, rst, VAR36, VAR18, VAR6,
VAR12, VAR5, VAR40,
VAR4, VAR14, VAR11,
VAR17, VAR16, VAR24, VAR22,
VAR9, VAR21, VAR38, VAR39,
VAR33
);
input clk,rst;
input VAR36, VAR18,
VAR6,VAR12,
VAR5,VAR40,
VAR4,VAR14,
VAR11,VAR17;
input... | bsd-3-clause |
olofk/oh | xilibs/hdl/PLLE2_ADV.v | 5,488 | module MODULE1 #(
parameter VAR16 = "VAR52",
parameter integer VAR40 = 5,
parameter real VAR39 = 0.000,
parameter real VAR62 = 0.000,
parameter real VAR46 = 0.000,
parameter integer VAR49 = 1,
parameter real VAR15 = 0.500,
parameter real VAR11 = 0.000,
parameter integer VAR12 = 1,
parameter real VAR47 = 0.500,
paramete... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_colortable.v | 2,282 | module MODULE1
(
input wire clk, input wire VAR28, input wire [ 9-1:1] VAR8, input wire [ 12-1:0] VAR23, input wire [ 8-1:0] select, input wire [ 8-1:0] VAR22, input wire [ 3-1:0] VAR24, input wire VAR4, input wire VAR3, output reg [ 24-1:0] VAR20 );
parameter VAR10 = 9'h180;
wire [ 8-1:0] VAR9 = select;
wire [ 8-1:0] ... | gpl-3.0 |
ptracton/vscale_soc | rtl/wb_intercon-1.0/rtl/verilog/wb_mux.v | 6,154 | module MODULE1
parameter [VAR22*VAR23-1:0] VAR21 = 0)
(input VAR39,
input VAR25,
input [VAR23-1:0] VAR18,
input [VAR4-1:0] VAR28,
input [3:0] VAR24,
input VAR14,
input VAR20,
input VAR35,
input [2:0] VAR26,
input [1:0] VAR17,
output [VAR4-1:0] VAR9,
output VAR38,
output VAR2,
output VAR27,
output [VAR22*VAR23-1:0] VAR1... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N16_R2_P4_syn.v | 4,336 | module MODULE1 ( VAR15, VAR68, VAR21 );
input [15:0] VAR15;
input [15:0] VAR68;
output [16:0] VAR21;
wire VAR117, VAR124, VAR78, VAR44, VAR90,
VAR135, VAR88, VAR89, VAR6, VAR103, VAR139, VAR42, VAR63, VAR57, VAR82, VAR71, VAR104, VAR29, VAR111, VAR74,
VAR105, VAR128, VAR112, VAR76, VAR108, VAR49, VAR59, VAR35, VAR23, V... | gpl-3.0 |
asicguy/gplgpu | hdl/de/ded_ca_top.v | 4,015 | module MODULE1
(
input VAR12,
input VAR4,
input VAR13,
input VAR11,
input [4:0] VAR9,
input [(VAR3*8)-1:0] VAR7,
output [31:0] VAR10,
output [4:0] VAR1,
output [4:0] VAR6,
output [4:0] VAR14
);
wire [2:0] VAR5;
assign VAR5 = VAR8 + 3'h1;
assign VAR10 = VAR7[VAR9[1:0]*32 +: 32];
assign VAR2[0] = VAR11 & (VAR9[1:0] == 2'... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2b/sky130_fd_sc_hs__or2b.functional.pp.v | 1,823 | module MODULE1 (
VAR8,
VAR3,
VAR5 ,
VAR9 ,
VAR13
);
input VAR8;
input VAR3;
output VAR5 ;
input VAR9 ;
input VAR13 ;
wire VAR5 VAR10 ;
wire VAR1 ;
wire VAR12;
not VAR4 (VAR10 , VAR13 );
or VAR2 (VAR1 , VAR10, VAR9 );
VAR7 VAR6 (VAR12, VAR1, VAR8, VAR3);
buf VAR11 (VAR5 , VAR12 );
endmodule | apache-2.0 |
cpulabs/mist1032sa | src/core/fetch/fetch.v | 6,862 | module MODULE1(
input wire VAR50,
input wire VAR43,
input wire VAR10,
input wire VAR14,
input wire VAR25,
input wire [31:0] VAR40,
input wire VAR47,
input wire VAR46,
input wire VAR33,
input wire [5:0] VAR28,
input wire [31:0] VAR6,
input wire VAR35,
input wire [5:0] VAR49,
input wire [31:0] VAR18,
output wire VAR13,
o... | bsd-2-clause |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_sincos_double.v | 1,417 | module MODULE1(VAR3, VAR10, enable, VAR15, VAR5, VAR12);
input VAR3, VAR10, enable;
input [63:0] VAR15;
output [63:0] VAR5; output [63:0] VAR12;
VAR11 VAR14(
.VAR9(1'b1),
.VAR7(8'd0),
.VAR6(VAR15),
.en(enable),
.VAR2(),
.VAR4(),
.VAR8(VAR5),
.VAR1(VAR12),
.clk(VAR3),
.VAR13(~VAR10));
endmodule | mit |
BoolLi/Pollard-s-p-1-algorithm | exponent_finder.v | 1,532 | module MODULE1(
input clk,
input [63:0] VAR4,
input VAR6,
input [8:0] VAR1,
output reg [7:0] VAR8,
output reg ready
);
reg [7:0] VAR7;
reg VAR5;
reg [10:0] VAR2;
reg [10:0] VAR3; | mit |
CprE488/Final | repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/verilog/phsaligner.v | 8,662 | module MODULE1 # (
parameter VAR9 = 3, parameter VAR26 = 7, parameter VAR7 = 12 )
(
input wire rst,
input wire clk,
input wire [9:0] VAR15,
input wire [9:0] VAR25, output reg VAR1,
output reg VAR11,
output reg VAR6 );
reg VAR30, VAR20;
reg VAR22;
always @ (posedge clk) begin
VAR30 <=(VAR25 == VAR15);
VAR20 <=VAR30;
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2/sky130_fd_sc_ls__or2_2.v | 2,075 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR7 ,
VAR8,
VAR5,
VAR3 ,
VAR9
);
output VAR2 ;
input VAR1 ;
input VAR7 ;
input VAR8;
input VAR5;
input VAR3 ;
input VAR9 ;
VAR4 VAR6 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR2,
VAR1,
VAR7
);
output VAR2;
... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_rdata_path.v | 51,917 | module MODULE1
parameter
VAR194 = 8,
VAR89 = 2,
VAR280 = 3, VAR257 = 3,
VAR155 = 32,
VAR32 = 5,
VAR40 = 2,
VAR207 = 3,
VAR244 = 13,
VAR243 = 10,
VAR73 = 4, VAR68 = "VAR138", VAR13 = 2,
VAR241 = 3,
VAR229 = 2,
VAR251 = 1,
VAR277 = 8,
VAR74 = 3,
VAR24 = 1,
VAR131 = 1,
VAR268 = 1,
VAR183 = 5,
VAR196 = 2,
VAR118 = 9,
VAR41... | gpl-3.0 |
GREO/GNU-Radio | usrp/fpga/sdr_lib/ext_fifo.v | 3,847 | module MODULE2 (reset,VAR1,write,VAR23,VAR10,VAR13,VAR2,VAR33,VAR15);
parameter VAR9=32;
parameter VAR18=10;
input reset; input [VAR9-1:0] VAR1;
input write;
input VAR23;
output [VAR18-1:0] VAR10;
output [VAR9-1:0] VAR13;
input VAR2;
input VAR33;
output [VAR18-1:0] VAR15;
reg [VAR18-1:0] VAR11, VAR4,
VAR34, VAR30,
VAR2... | gpl-3.0 |
ultraembedded/riscv | top_cache_axi/src_v/dcache_core_data_ram.v | 3,710 | module MODULE1
(
input VAR8
,input VAR14
,input [ 10:0] VAR9
,input [ 31:0] VAR12
,input [ 3:0] VAR3
,input VAR2
,input VAR11
,input [ 10:0] VAR6
,input [ 31:0] VAR7
,input [ 3:0] VAR4
,output [ 31:0] VAR5
,output [ 31:0] VAR10
);
reg [31:0] VAR15 [2047:0] ;
reg [31:0] VAR1;
reg [31:0] VAR13;
always @ (posedge VAR8)
be... | bsd-3-clause |
GREO/GNU-Radio | usrp/fpga/inband_lib/chan_fifo_reader.v | 7,796 | module MODULE1
(reset, VAR5, VAR17, VAR28, VAR20,
VAR29, VAR23, VAR32, VAR25, VAR12, VAR1,
VAR31, VAR33, VAR30, VAR21, VAR24, VAR22) ;
input wire reset ;
input wire VAR5 ;
input wire VAR17 ; input wire [31:0] VAR28 ; input wire [3:0] VAR20 ; input wire [31:0] VAR29 ; input wire VAR23 ; output reg VAR32 ; output reg VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux4/sky130_fd_sc_ls__mux4.blackbox.v | 1,339 | module MODULE1 (
VAR11 ,
VAR4,
VAR8,
VAR10,
VAR1,
VAR3,
VAR9
);
output VAR11 ;
input VAR4;
input VAR8;
input VAR10;
input VAR1;
input VAR3;
input VAR9;
supply1 VAR5;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
curtiszimmerman/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/ftl_wbs.v | 4,571 | module MODULE1 (
input wire VAR28,
input wire VAR40,
input wire VAR27,
input wire [31:0] VAR30,
output wire [31:0] VAR37,
input wire [31:0] VAR38,
input wire [3:0] VAR35,
input wire VAR44,
input wire VAR7,
input wire VAR46,
output wire VAR5,
output wire VAR19,
output wire [15:0] VAR45,
output reg VAR33,
output reg [31:... | apache-2.0 |
tdene/synth_opt_adders | src/pptrees/mappings/sky130_fd_sc_hs_map.v | 4,263 | module MODULE19
(
VAR1, VAR4
);
output VAR1;
input VAR4;
VAR5 MODULE19(.VAR1(VAR1), .VAR4(VAR4));
endmodule
module MODULE8
(
VAR1, VAR4
);
output VAR1;
input VAR4;
VAR10 MODULE8(.VAR20(VAR1), .VAR4(VAR4));
endmodule
module MODULE17
(
VAR1, VAR4, VAR18
);
output VAR1;
input VAR4, VAR18;
VAR35 MODULE17(.VAR1(VAR1), .VAR4... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_dram_ctrl.v | 6,340 | module MODULE1
import VAR21::*;
import VAR77::*;
, parameter VAR38(VAR6)
, parameter VAR38(VAR84)
, parameter VAR38(VAR85)
, localparam VAR46=(VAR84>>3)
, localparam VAR15=VAR2(VAR34)
, localparam VAR59=VAR36(VAR6)
, parameter VAR38(VAR81)
, parameter VAR5=(VAR6+VAR15)
, localparam VAR3=(VAR85/VAR81)
)
(
input VAR66
, ... | bsd-3-clause |
trivoldus28/pulsarch-verilog | verif/model/verilog/mem/dram/dimm.v | 10,028 | module MODULE1( clk, VAR28, VAR27, VAR45, VAR14, VAR1, addr, VAR6,
VAR31, VAR25, VAR21, VAR10
);
parameter VAR13=17,
VAR47=2,
VAR47=3,
VAR35=9;
input [2:0] clk;
input [1:0] VAR28;
input VAR27, VAR45, VAR14;
input [(VAR47-1):0] VAR1;
input [(VAR13-1):0] addr;
input [7:0] VAR6;
inout [63:0] VAR31;
inout [7:0] VAR25;
inou... | gpl-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/fake_mii.v | 4,382 | module MODULE1
(input VAR11,
inout VAR13);
reg [15:0] VAR3[0:31];
reg [15:0] VAR12;
reg VAR15;
reg VAR1;
reg VAR8;
reg VAR6;
reg [1:0] VAR10;
reg [4:0] VAR4;
reg [4:0] VAR9;
integer VAR7;
always @(VAR13) VAR8 <= VAR13;
assign VAR13 = VAR1 ? VAR15 : 1'VAR2;
integer VAR14, VAR5;
begin
begin | apache-2.0 |
felixmo/Pong | pll108MHz_bb.v | 10,692 | module MODULE1 (
VAR2,
VAR1);
input VAR2;
output VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4/sky130_fd_sc_hd__or4.pp.blackbox.v | 1,308 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR4 ,
VAR1 ,
VAR5 ,
VAR2,
VAR7,
VAR8 ,
VAR6
);
output VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR2;
input VAR7;
input VAR8 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtn/sky130_fd_sc_ms__sdfrtn.behavioral.v | 2,952 | module MODULE1 (
VAR5 ,
VAR23 ,
VAR25 ,
VAR16 ,
VAR24 ,
VAR17
);
output VAR5 ;
input VAR23 ;
input VAR25 ;
input VAR16 ;
input VAR24 ;
input VAR17;
supply1 VAR27;
supply0 VAR31;
supply1 VAR26 ;
supply0 VAR8 ;
wire VAR10 ;
wire VAR32 ;
wire VAR9 ;
wire VAR30 ;
reg VAR6 ;
wire VAR7 ;
wire VAR19 ;
wire VAR4 ;
wire VAR33;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.blackbox.v | 1,399 | module MODULE1 (
VAR9 ,
VAR2,
VAR10 ,
VAR4 ,
VAR8,
VAR7
);
output VAR9 ;
input VAR2;
input VAR10 ;
input VAR4 ;
input VAR8;
input VAR7;
supply1 VAR6;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
richard42/CoCo3FPGA | uart_6850.v | 7,316 | module MODULE1(
VAR39,
VAR59,
VAR7,
VAR21,
VAR25,
VAR52,
VAR47,
VAR46,
VAR28,
VAR1,
VAR26,
VAR36,
VAR16,
VAR14,
VAR4
);
input VAR39;
input VAR59;
input VAR7;
input VAR21;
input [7:0] VAR25;
output [7:0] VAR52;
output VAR47;
input VAR46;
input VAR1;
input VAR28;
output VAR26;
input VAR36;
output VAR16;
input VAR14;
inpu... | bsd-3-clause |
javierbrito29/papiGB | rtl/mmu.v | 13,246 | module MODULE1
(
input wire VAR48,
input wire VAR11,
input wire VAR37,
input wire [15:0] VAR88,
input wire VAR84,
input wire [7:0] VAR2,
output wire [7:0] VAR62,
output wire [7:0] VAR86,
input wire VAR83,
input wire [15:0] VAR30,
output wire [3:0] VAR102,
output wire [2:0] VAR92,
output wire [7:0] VAR81,
input wire [7:... | gpl-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/new/ADC_interface_AXI_XADC.v | 7,607 | module MODULE1 (
input VAR57,
input VAR90,
input VAR10,
output VAR7,
input [32-1:0] VAR54,
input [3-1:0] VAR42,
input VAR40,
output VAR65,
input [32-1:0] VAR36,
input [4-1:0] VAR95,
output reg VAR19,
input VAR18,
input VAR48,
output VAR84,
input [32-1:0] VAR89,
input [3-1:0] VAR3,
output reg VAR41,
input VAR37,
output ... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_rank_timer.v | 113,359 | module MODULE1 #
( parameter
VAR12 = 2,
VAR24 = 4,
VAR56 = "VAR136",
VAR102 = 1,
VAR35 = 1,
VAR163 = 4,
VAR98 = 2,
VAR164 = 0,
VAR29 = 0,
VAR156 = 0,
VAR90 = 0,
VAR126 = 5,
VAR123 = 0,
VAR204 = 0,
VAR100 = 0,
VAR39 = 0,
VAR112 = 0,
VAR114 = 0,
VAR181 = 0,
VAR69 = 0,
VAR139 = 0,
VAR132 = 0,
VAR61 = 0,
VAR36 = 0
)
(
VAR2... | lgpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/timing_synch_fsm.v | 22,772 | module MODULE1 #(parameter VAR77 = 2.8) (
input VAR35,
input VAR36,
input VAR3, input VAR24,
input VAR27,
input [11:0] VAR64,
input [6:0] VAR46,
input [9:0] VAR2,
input [7:0] VAR44,
input VAR8,
input [6:0] VAR75,
input [6:0] VAR41,
output reg VAR82 = 1'b0,
output reg VAR10 = 1'b0,
output reg VAR53 = 1'b0,
output reg VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill/sky130_fd_sc_hs__fill.pp.symbol.v | 1,175 | module MODULE1 (
input VAR4 ,
input VAR2,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.system.dma.ok/Qsys/soc_design/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,579 | module MODULE1 (
clk,
reset,
VAR7,
VAR15,
VAR2,
VAR8,
VAR1,
VAR4
);
parameter VAR14 = 1;
parameter VAR6 = 8;
parameter VAR3 = 1;
localparam VAR5 = VAR14 * VAR6;
input clk;
input reset;
output VAR7;
input VAR15;
input [VAR5-1:0] VAR2;
input VAR8;
output VAR1;
output [VAR5-1:0] VAR4;
reg VAR11;
reg VAR12;
reg [VAR5-1:0] ... | gpl-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_tristate_conduit_pin_sharer_0.v | 4,868 | module MODULE1 (
input wire VAR21, input wire VAR19, output wire request, input wire VAR17, output wire [18:0] VAR30, output wire [1:0] VAR38, output wire [0:0] VAR20, output wire [0:0] VAR15, output wire [15:0] VAR22, input wire [15:0] VAR3, output wire VAR25, output wire [0:0] VAR11, input wire VAR26, output wire VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i_1.v | 2,087 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR5 ,
VAR7 ,
VAR4,
VAR1
);
output VAR3 ;
input VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR1;
VAR6 VAR2 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR3 ,
VAR8,
VAR5,
VAR7
);
output VAR3 ;
input VAR8;
input VAR5;
... | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/MEMWB_Stage.v | 3,239 | module MODULE1(
input VAR6,
input reset,
input VAR8,
input VAR2,
input VAR13,
input VAR12,
input VAR18,
input [31:0] VAR14,
input [31:0] VAR4,
input [4:0] VAR5,
input VAR1,
input VAR10,
input [31:0] VAR17,
input [31:0] VAR7,
input [4:0] VAR9,
output reg VAR11,
output reg VAR15,
output reg [31:0] VAR19,
output reg [31:0... | lgpl-3.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hls_cores/vector_add/vectoradd_prj/solution1/impl/ip/hdl/verilog/vectoradd.v | 17,628 | module MODULE1 (
VAR19,
VAR17,
VAR45,
VAR73,
VAR64,
VAR49,
VAR72,
VAR77,
VAR54,
VAR50,
VAR35,
VAR42,
VAR67,
VAR28,
VAR56,
VAR37,
VAR58,
VAR48,
VAR74,
VAR40,
VAR57,
VAR31,
VAR5,
VAR18,
VAR38,
VAR43,
VAR47,
VAR68,
VAR53
);
parameter VAR9 = 1'b1;
parameter VAR10 = 1'b0;
parameter VAR65 = 3'b000;
parameter VAR8 = 3'b1;
par... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a.pp.blackbox.v | 1,406 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR2 ,
VAR3 ,
VAR7 ,
VAR9 ,
VAR1,
VAR4,
VAR5 ,
VAR8
);
output VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR1;
input VAR4;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b_2.v | 2,234 | module MODULE2 (
VAR8 ,
VAR2 ,
VAR6 ,
VAR5 ,
VAR4,
VAR1,
VAR10 ,
VAR9
);
output VAR8 ;
input VAR2 ;
input VAR6 ;
input VAR5 ;
input VAR4;
input VAR1;
input VAR10 ;
input VAR9 ;
VAR7 VAR3 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/custom_math.v | 1,685 | module MODULE1 (
input wire [7:0] VAR6, input wire VAR2, output wire [31:0] VAR4, input wire VAR3, input wire [31:0] VAR13, output wire VAR11, input wire VAR5, input wire VAR8, output wire VAR12, output wire [7:0] VAR7, output wire VAR9, input wire VAR1, input wire [31:0] VAR10, output wire VAR15, output wire [31:0] VA... | gpl-2.0 |
ElegantLin/My-CPU | Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/ctrl.v | 3,474 | module MODULE1(
input wire rst,
input wire[31:0] VAR3,
input wire[VAR10] VAR4,
input wire VAR5,
input wire VAR1,
input wire VAR8,
output reg[VAR10] VAR12,
output reg VAR9,
output reg[5:0] VAR13
);
always @ (*) begin
if(rst == VAR11) begin
VAR13 <= 6'b000000;
VAR9 <= 1'b0;
VAR12 <= VAR2;
end else if(VAR3 != VAR2) begin
... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_qsys_sequencer_sequencer_ram.v | 4,217 | module MODULE1 (
address,
VAR34,
VAR2,
clk,
VAR10,
reset,
write,
VAR26,
VAR24
)
;
parameter VAR31 = "../MODULE1.VAR17";
output [ 31: 0] VAR24;
input [ 8: 0] address;
input [ 3: 0] VAR34;
input VAR2;
input clk;
input VAR10;
input reset;
input write;
input [ 31: 0] VAR26;
wire [ 31: 0] VAR24;
wire VAR27;
assign VAR27 = V... | lgpl-3.0 |
eda-globetrotter/MarcheProcessor | final/src/pipe3.v | 1,421 | module MODULE1(VAR12, VAR1, VAR5, VAR8,
VAR13, VAR11, VAR10, VAR2,
VAR4, VAR9, VAR6, VAR7,
VAR3, VAR14, clk, reset);
input [0:127] VAR12;
input [0:15] VAR5;
input VAR13;
input [0:4] VAR10;
input VAR4;
input [0:127] VAR6;
input [0:31] VAR3;
input clk, reset;
output [0:127] VAR1;
output [0:15] VAR8;
output VAR11;
output ... | mit |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/mig_interface_model.v | 4,854 | module MODULE1
(
input [27:0] VAR21,
input [2:0] VAR34,
input VAR20,
input [511:0] VAR18,
input VAR28,
input [63:0] VAR15,
input VAR31,
output wire [511:0] VAR32,
output wire VAR11,
output wire VAR12,
output wire VAR5,
output wire VAR26,
output reg VAR25,
output reg VAR27,
output reg VAR19,
input VAR2
);
parameter VAR7... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_axi_basic_rx_pipeline.v | 26,674 | module MODULE1 #(
parameter VAR66 = 128, parameter VAR16 = "VAR75", parameter VAR52 = 1,
parameter VAR67 = (VAR66 == 128) ? 2 : 1, parameter VAR31 = VAR66 / 8 ) (
output reg [VAR66-1:0] VAR7, output reg VAR64, input VAR83, output [VAR31-1:0] VAR63, output VAR72, output reg [21:0] VAR55,
input [VAR66-1:0] VAR57, input V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai.behavioral.v | 1,674 | module MODULE1 (
VAR6 ,
VAR1,
VAR5,
VAR13 ,
VAR4
);
output VAR6 ;
input VAR1;
input VAR5;
input VAR13 ;
input VAR4 ;
supply1 VAR7;
supply0 VAR11;
supply1 VAR14 ;
supply0 VAR10 ;
wire VAR12 ;
wire VAR8 ;
wire VAR16;
nand VAR2 (VAR12 , VAR5, VAR1 );
or VAR3 (VAR8 , VAR4, VAR13 );
nand VAR9 (VAR16, VAR12, VAR8);
buf VAR15... | apache-2.0 |
mashanz/FinalProject | Code/module/selesai/alu_min.v | 7,675 | module MODULE1( VAR2, VAR3, VAR1, VAR6, VAR5, VAR4, VAR8, VAR9);
input VAR2, VAR3, VAR1;
input [7:0]VAR9;
input [7:0]VAR6;
input [7:0]VAR5;
output [7:0]VAR4;
input [1:0]VAR8;
reg [7:0]VAR4;
reg [11:0]VAR7;
always@(posedge VAR3)begin
if(VAR2) VAR4 = 0;
end
else begin
case(VAR9)
8'b00000001: VAR4 = 0;
8'b00000010: VAR4 <... | gpl-3.0 |
CeesWolfs/ceespu | src/ceespu_branch_predictor.v | 2,781 | module MODULE1 (
input clk,
input rst,
input [31:0] VAR17,
input [13:0] VAR16,
input [13:0] VAR3,
input [1:0] VAR4,
input VAR6,
input VAR1,
output [1:0] VAR11,
output reg VAR8
);
parameter VAR10 = 6; localparam VAR7 = 0, VAR2 = 1, VAR12 = 2, VAR5 = 3;
reg [1:0] VAR15 [(2 ** VAR10) - 1:0];
reg [VAR10-1:0] VAR14 = 0;
reg... | mit |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/master_clock/master_clock_0002.v | 2,145 | module MODULE1(
input wire VAR72,
input wire rst,
output wire VAR3,
output wire VAR11,
output wire VAR67
);
VAR54 #(
.VAR43("false"),
.VAR29("50.0 VAR71"),
.VAR51("VAR5"),
.VAR59(2),
.VAR16("150.000000 VAR71"),
.VAR50("0 VAR64"),
.VAR47(50),
.VAR2("40.000000 VAR71"),
.VAR48("0 VAR64"),
.VAR20(50),
.VAR68("0 VAR71"),
.V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2.functional.pp.v | 1,768 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR5,
VAR1
);
output VAR8 ;
input VAR7 ;
input VAR5;
input VAR1;
wire VAR6 ;
wire VAR9;
not VAR10 (VAR6 , VAR7 );
VAR4 VAR3 (VAR9, VAR6, VAR5, VAR1);
buf VAR2 (VAR8 , VAR9 );
endmodule | apache-2.0 |
carstenbru/fpga-log | spartanmc/hardware/uart_light/src/uart_light_clk_gen.v | 3,201 | module MODULE1
parameter VAR6 = 5,
parameter VAR4 = 6,
parameter VAR7 = 3
)(
output wire VAR3,
output wire VAR9,
input wire VAR8,
input wire reset
);
reg [VAR4-1:0] VAR5;
reg [VAR7-1:0] VAR1;
assign VAR9 = VAR5[VAR4-1];
assign VAR3 = VAR1[VAR7-1];
always @(posedge VAR8, posedge reset) begin
if(reset) begin
VAR5 <= {(VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp.functional.pp.v | 2,104 | module MODULE1 (
VAR10 ,
VAR15 ,
VAR8 ,
VAR14 ,
VAR16 ,
VAR2 ,
VAR7,
VAR19,
VAR6 ,
VAR17
);
output VAR10 ;
output VAR15 ;
input VAR8 ;
input VAR14 ;
input VAR16 ;
input VAR2 ;
input VAR7;
input VAR19;
input VAR6 ;
input VAR17 ;
wire VAR5 ;
wire VAR11;
VAR4 VAR18 (VAR11, VAR14, VAR16, VAR2 );
VAR13 VAR9 VAR3 (VAR5 , VAR... | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/FSM_2.v | 106,216 | module MODULE1(
input [31:0] VAR40, input [31:0] VAR16, input [31:0] VAR55, input [31:0] VAR50, input [31:0] VAR25,
input [31:0] VAR35,
input [31:0] VAR38,
input [1:0] VAR60, input VAR53, input VAR31,
input reset,
input VAR10,
input [1:0] VAR47, input [7:0] address,
input [3:0] VAR34, input [7:0] VAR52,
output reg [31:... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sd_host/rtl/sd_host_stack.v | 13,082 | module MODULE1 #(
parameter VAR119 = 0,
parameter VAR22 = 0,
parameter VAR86 = 0,
parameter VAR78 = 11 )(
input clk,
input rst,
output VAR32,
input VAR66,
input [15:0] VAR91,
input VAR107,
output VAR6,
output VAR130,
output [7:0] VAR7,
input VAR139,
input [5:0] VAR73,
input [31:0] VAR62,
output VAR103,
input VAR99,
out... | mit |
hakehuang/pycpld | ips/ip/pwm_capture/captuer_tx.v | 2,234 | module MODULE1(
clk,VAR2,VAR9,VAR6,VAR11,VAR3,VAR12,VAR4,VAR1,VAR5,VAR8
);
input clk;
input VAR2;
input VAR6;
input VAR4;
input VAR8;
input VAR1;
input[31:0] VAR11;
input[31:0] VAR3;
output VAR9;
output VAR5;
output [7:0] VAR12;
reg VAR9;
reg[15:0] VAR13;
reg[3:0] VAR10;
reg[7:0] VAR12;
reg VAR5;
always @ (posedge clk ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21ai/sky130_fd_sc_hvl__o21ai.symbol.v | 1,353 | module MODULE1 (
input VAR6,
input VAR3,
input VAR1,
output VAR7
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.functional.pp.v | 1,072 | module MODULE1( VAR6, VAR3, VAR5, VAR9, VAR4 );
input VAR5, VAR6;
inout VAR9, VAR4;
output VAR3;
wire VAR8;
not VAR1( VAR8, VAR5 );
wire VAR7;
not VAR2( VAR7, VAR6 );
or VAR10( VAR3, VAR8, VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.v | 2,334 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR7 ,
VAR4,
VAR8,
VAR3 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR4;
input VAR8;
input VAR3 ;
input VAR1 ;
VAR10 VAR11 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(V... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9234/axi_ad9234_pnmon.v | 10,780 | module MODULE1 (
VAR7,
VAR3,
VAR15,
VAR5,
VAR14);
input VAR7;
input [63:0] VAR3;
output VAR15;
output VAR5;
input [ 3:0] VAR14;
reg [63:0] VAR12 = 'd0;
reg [63:0] VAR11 = 'd0;
wire [63:0] VAR1;
function [63:0] VAR13;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[22] ^ din[17];
dout[62] = din[21] ^ din[16];
do... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbp/sky130_fd_sc_ms__sdfbbp.pp.blackbox.v | 1,562 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR8 ,
VAR1 ,
VAR10 ,
VAR6 ,
VAR2 ,
VAR11,
VAR3 ,
VAR7 ,
VAR12 ,
VAR4
);
output VAR9 ;
output VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR11;
input VAR3 ;
input VAR7 ;
input VAR12 ;
input VAR4 ;
endmodule | apache-2.0 |
hoang26/processor_verilog | memory.v | 2,901 | module MODULE1(
VAR5,
VAR2,
VAR14,
VAR6,
VAR13,
VAR11,
VAR1
);
input [4*8:1] VAR5;
output [31:0] VAR2;
input [4*8:1] VAR14;
input [31:0] VAR6;
input VAR13;
input VAR11;
output [31:0] VAR1;
parameter VAR9=32'h00004000;
integer VAR7;
integer VAR8, VAR10;
reg [7:0] memory [0:VAR9-1];
reg [31:0] VAR12, VAR4;
reg [12*8:1] V... | gpl-2.0 |
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