repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
olofk/oh | elink/hdl/elink.v | 10,298 | module MODULE1(
VAR36, VAR54, VAR2, VAR81,
VAR52, VAR3, VAR57, VAR61, VAR21,
VAR69, VAR13, VAR67, VAR24, VAR84, VAR10,
VAR77, timeout, VAR85, VAR50, VAR40,
VAR28, VAR53, VAR18, VAR43, VAR62,
VAR74,
VAR22, VAR49, VAR8, VAR1, VAR56,
VAR7, VAR48, VAR33, VAR60, VAR65,
VAR88, VAR82, VAR80, VAR63, VAR64,
VAR42, VAR15, VAR31,... | gpl-3.0 |
tmeissner/cryptocores | des/rtl/verilog/des.v | 19,059 | module MODULE1
(
input VAR84, input VAR65, input VAR56, input [0:63] VAR89, input [0:63] VAR50, input VAR49, output reg VAR69,
output reg [0:63] VAR62, output VAR30, input VAR36
);
reg [0:18] valid;
reg [0:17] VAR79;
reg [0:27] VAR26;
reg [0:27] VAR85;
reg [0:27] VAR106;
reg [0:27] VAR76;
reg [0:27] VAR80;
reg [0:27] V... | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/syn/verilog/FIFO_image_filter_img_0_data_stream_2_V.v | 3,017 | module MODULE1 (
clk,
VAR18,
VAR14,
VAR24,
VAR6);
parameter VAR1 = 32'd8;
parameter VAR19 = 32'd1;
parameter VAR11 = 32'd2;
input clk;
input [VAR1-1:0] VAR18;
input VAR14;
input [VAR19-1:0] VAR24;
output [VAR1-1:0] VAR6;
reg[VAR1-1:0] VAR2 [0:VAR11-1];
integer VAR16;
always @ (posedge clk)
begin
if (VAR14)
begin
for (V... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_auto_us_cc_df_0/synth/OpenSSD2_auto_us_cc_df_0.v | 14,826 | module MODULE1 (
VAR1,
VAR14,
VAR56,
VAR96,
VAR5,
VAR72,
VAR35,
VAR2,
VAR42,
VAR3,
VAR52,
VAR4,
VAR91,
VAR69,
VAR15,
VAR79,
VAR29,
VAR16,
VAR73,
VAR9,
VAR94,
VAR59,
VAR77,
VAR75,
VAR84,
VAR18,
VAR86,
VAR45,
VAR98,
VAR85,
VAR19,
VAR49,
VAR48,
VAR23,
VAR82,
VAR17,
VAR81,
VAR65,
VAR95,
VAR13,
VAR80,
VAR66,
VAR87,
VAR12,
V... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_21.v | 17,390 | module MODULE4 (
clk,
reset,
VAR45,
VAR26,
VAR63,
VAR103,
VAR7
);
parameter VAR65 = 18;
parameter VAR81 = 21;
parameter VAR28 = 11;
localparam VAR129 = 27;
input clk;
input reset;
input VAR45;
input VAR26;
input [VAR65-1:0] VAR63; output VAR103;
output [VAR65-1:0] VAR7;
localparam VAR87 = 18; localparam VAR19 = 36; loc... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.blackbox.v | 1,424 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR3 ,
VAR2,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR6 ;
input VAR3 ;
input VAR2;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtn/sky130_fd_sc_ls__dlxtn.functional.v | 1,581 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR3
);
output VAR8 ;
input VAR6 ;
input VAR3;
wire VAR1 ;
wire VAR7;
not VAR4 (VAR1 , VAR3 );
VAR5 VAR2 (VAR7 , VAR6, VAR1 );
buf VAR9 (VAR8 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf_16.v | 2,056 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR6,
VAR5,
VAR3 ,
VAR2
);
output VAR8 ;
input VAR4 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR2 ;
VAR7 VAR1 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8,
VAR4
);
output VAR8;
input VAR4;
supply1 VAR6;
supply0 VAR5;... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/ppu/ppu_spr.v | 22,436 | module MODULE1
(
input wire VAR135, input wire VAR111, input wire VAR120, input wire VAR42, input wire VAR92, input wire VAR30, input wire [ 7:0] VAR109, input wire [ 7:0] VAR10, input wire VAR132, input wire [ 9:0] VAR39, input wire [ 9:0] VAR133, input wire [ 9:0] VAR95, input wire VAR13, input wire [ 7:0] VAR122, ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbp/sky130_fd_sc_ls__sdfbbp.blackbox.v | 1,532 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR12 ,
VAR6 ,
VAR1 ,
VAR5 ,
VAR2 ,
VAR11
);
output VAR8 ;
output VAR9 ;
input VAR12 ;
input VAR6 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR11;
supply1 VAR3;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
dwaipayanBiswas/ECG-feature-extraction-using-DWT | ecg_signal_max.v | 6,292 | module MODULE1(VAR11,VAR15,VAR6,VAR19,VAR14,
VAR7,VAR22,clk,VAR4);
output [15:0] VAR11,VAR15;
reg signed [15:0] VAR10,VAR26,VAR11,VAR15;
input signed [15:0] VAR22;
input [15:0] VAR14,VAR7;
input [3:0] VAR6;
input [8:0] VAR19;
input clk, VAR4;
wire clk, VAR4;
reg [15:0] VAR2,VAR3,VAR17,VAR5,VAR25,VAR18;
always @(posedge... | gpl-3.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/toplevel/mrfm/mrfm_compensator.v | 2,793 | module MODULE1 (input VAR18, input reset, input VAR20,
input VAR15, input [6:0] VAR37, input [31:0] VAR19,
input [15:0] VAR41, input [15:0] VAR8, output reg [15:0] VAR14, output reg [15:0] VAR36);
wire [15:0] VAR23,VAR34,VAR33,VAR13;
reg [15:0] VAR44, VAR30;
wire [30:0] VAR7;
reg [3:0] VAR35;
wire [15:0] VAR32,VAR5;
wi... | gpl-3.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/arbiter_IN_node.v | 8,010 | module MODULE1( clk,
rst,
VAR35,
VAR29,
VAR48,
VAR21,
VAR28,
VAR17,
VAR23,
VAR12,
VAR7,
VAR25,
VAR26,
VAR44,
VAR36,
VAR40,
VAR15,
VAR34,
VAR2,
VAR11,
VAR19,
VAR37
);
input clk;
input rst;
input VAR35;
input VAR29;
input [1:0] VAR48;
input [1:0] VAR21;
input [15:0] VAR28;
input [15:0] VAR17;
input [1:0] VAR23;
input [1:... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4b/sky130_fd_sc_hdll__or4b_4.v | 2,307 | module MODULE2 (
VAR8 ,
VAR6 ,
VAR5 ,
VAR1 ,
VAR4 ,
VAR10,
VAR3,
VAR9 ,
VAR2
);
output VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR10;
input VAR3;
input VAR9 ;
input VAR2 ;
VAR11 VAR7 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_normal_filter_1.v | 7,184 | module MODULE1(
VAR16,
VAR27 , VAR55 , VAR89 ,
VAR20 , VAR53 , VAR13 ,
VAR57 , VAR4 , VAR54 ,
VAR17 , VAR15 , VAR91 ,
VAR14 , VAR87 , VAR3 ,
VAR29 , VAR19 , VAR22 ,
VAR72 , VAR38 , VAR39 ,
VAR8 , VAR50 , VAR76 ,
VAR64 ,
VAR95 ,
VAR81 ,
VAR74 ,
VAR94
);
input [4:0] VAR16 ;
input [7:0] VAR27 , VAR55 , VAR89 ,
VAR20 , VAR... | gpl-3.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_ndeep_srl.v | 5,193 | module MODULE1 #
(
parameter VAR32 = "VAR28", parameter VAR23 = 1 )
(
input wire VAR7, input wire [VAR23-1:0] VAR10, input wire VAR21, input wire VAR2, output wire VAR6 );
localparam integer VAR11 = 5;
localparam integer VAR13 = 32;
localparam integer VAR24 = (VAR23>VAR11) ? (2**(VAR23-VAR11)) : 1;
localparam integer V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o_2.v | 2,437 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR2 ,
VAR12 ,
VAR10 ,
VAR7 ,
VAR3,
VAR11,
VAR4 ,
VAR5
);
output VAR8 ;
input VAR6 ;
input VAR2 ;
input VAR12 ;
input VAR10 ;
input VAR7 ;
input VAR3;
input VAR11;
input VAR4 ;
input VAR5 ;
VAR9 VAR1 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b.behavioral.pp.v | 1,995 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR5 ,
VAR16 ,
VAR9,
VAR4,
VAR12 ,
VAR13
);
output VAR10 ;
input VAR8 ;
input VAR5 ;
input VAR16 ;
input VAR9;
input VAR4;
input VAR12 ;
input VAR13 ;
wire VAR1 ;
wire VAR11 ;
wire VAR7;
nor VAR14 (VAR1 , VAR8, VAR5 );
and VAR2 (VAR11 , VAR16, VAR1 );
VAR15 VAR3 (VAR7, VAR11, VAR9, VAR4)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbn/sky130_fd_sc_hs__dlxbn.pp.blackbox.v | 1,301 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR3 ,
VAR4,
VAR2 ,
VAR1
);
output VAR5 ;
output VAR6 ;
input VAR3 ;
input VAR4;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_decerr_slave.v | 9,277 | module MODULE1 #
(
parameter integer VAR6 = 1,
parameter integer VAR47 = 32,
parameter integer VAR20 = 1,
parameter integer VAR14 = 1,
parameter integer VAR41 = 0,
parameter integer VAR30 = 2'b11
)
(
input wire VAR11,
input wire VAR1,
input wire [(VAR6-1):0] VAR24,
input wire VAR32,
output wire VAR40,
input wire VAR28,... | gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_addr_arbiter_sasd.v | 13,349 | module MODULE1 #
(
parameter VAR48 = "none",
parameter integer VAR62 = 1,
parameter integer VAR1 = 1,
parameter integer VAR36 = 1,
parameter VAR66 = 0,
parameter [VAR62*32-1:0] VAR6 = {VAR62{32'h00000000}}
)
(
input wire VAR71,
input wire VAR75,
input wire [VAR62*VAR36-1:0] VAR63,
input wire [VAR62*VAR36-1:0] VAR27,
in... | gpl-3.0 |
jakubfi/mera400f | src/fpa.v | 3,523 | module MODULE1(
input VAR13,
input VAR2,
input VAR60,
input [0:15] VAR47,
input VAR40,
output VAR65,
input VAR66,
input VAR19,
input VAR31,
input VAR38,
input VAR36,
input VAR45,
output VAR17,
output VAR5,
output VAR22,
output VAR55,
output VAR48,
output VAR16,
output VAR11,
input VAR51,
input VAR56,
input VAR24,
input... | gpl-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/ddr2/alt_ddrx_ddr2_odt_gen.v | 11,608 | module MODULE1
VAR4 = 2,
VAR17 = 8,
VAR9 = 3,
VAR18 = 0,
VAR7 = 4
)
(
VAR14,
VAR27,
VAR3,
VAR10,
VAR16,
VAR21,
VAR5,
VAR22
);
input VAR14;
input VAR27;
input [VAR7-1:0] VAR3;
input [VAR9-1:0] VAR10;
input VAR16;
input VAR21;
output VAR5;
output VAR22;
localparam VAR6 = 2**VAR7; localparam VAR11 = 2;
localparam VAR20 = ... | apache-2.0 |
fallen/milkymist-mmu | cores/csrbrg/rtl/csrbrg.v | 1,941 | module MODULE1(
input VAR13,
input VAR4,
input [31:0] VAR8,
input [31:0] VAR1,
output reg [31:0] VAR9,
input VAR16,
input VAR2,
input VAR18,
output reg VAR5,
output reg [13:0] VAR15,
output reg VAR10,
output reg [31:0] VAR12,
input [31:0] VAR17
);
always @(posedge VAR13) begin
VAR9 <= VAR17;
end
reg VAR19;
always @(pos... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_6sig_x4.v | 13,696 | module MODULE1(VAR29 ,VAR137 ,VAR74 ,VAR126 ,
VAR8 ,VAR115 ,VAR118 ,VAR95 ,
VAR23 ,VAR101 ,VAR147 ,VAR123 ,VAR30 ,
VAR124 ,VAR6 ,VAR119 ,VAR100 ,VAR78 ,VAR16
,VAR48 ,VAR134 ,VAR108 ,
VAR139 ,VAR107 ,VAR62 , VAR111,
VAR135 ,VAR41 ,VAR35 ,
VAR109 ,VAR50 ,VAR125 ,VAR4 ,VAR59 ,
VAR68 ,VAR146 ,VAR45 ,VAR132 ,VAR21 ,
VAR28 ,... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_channel_init_sm.v | 10,581 | module MODULE1
(
VAR9,
VAR33,
VAR5,
VAR15,
VAR19,
VAR23,
VAR46,
VAR35,
VAR8,
VAR50,
VAR28,
VAR25,
VAR39
);
input VAR9;
output VAR33;
input VAR5;
input [0:1] VAR15;
input VAR19;
output VAR23;
input VAR46;
input VAR35;
output VAR8;
output VAR50;
input VAR28;
output VAR25;
input VAR39;
reg VAR50;
reg VAR37;
reg [0:15] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2/sky130_fd_sc_ls__and2.behavioral.v | 1,350 | module MODULE1 (
VAR9,
VAR8,
VAR3
);
output VAR9;
input VAR8;
input VAR3;
supply1 VAR2;
supply0 VAR10;
supply1 VAR5 ;
supply0 VAR1 ;
wire VAR6;
and VAR4 (VAR6, VAR8, VAR3 );
buf VAR7 (VAR9 , VAR6 );
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,203 | module MODULE1 (
clk,
VAR22,
VAR9,
VAR29,
VAR23,
VAR18,
VAR30,
VAR7,
VAR2,
VAR14,
VAR25,
VAR24,
VAR6,
VAR19,
VAR16,
VAR27
)
;
output [ 37: 0] VAR18;
output VAR30;
output VAR7;
output VAR2;
output VAR14;
output VAR25;
output VAR24;
output VAR6;
output VAR19;
output VAR16;
output VAR27;
input clk;
input [ 1: 0] VAR22;
in... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.behavioral.pp.v | 1,164 | module MODULE1( VAR2, VAR4, VAR7, VAR6 );
input VAR2;
inout VAR7, VAR6;
output VAR4;
VAR1 VAR3(.VAR2(VAR2),.VAR4(VAR4),.VAR7(VAR7),.VAR6(VAR6));
VAR1 VAR5(.VAR2(VAR2),.VAR4(VAR4),.VAR7(VAR7),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22o/sky130_fd_sc_lp__a22o.behavioral.pp.v | 2,151 | module MODULE1 (
VAR17 ,
VAR6 ,
VAR16 ,
VAR5 ,
VAR14 ,
VAR15,
VAR12,
VAR11 ,
VAR3
);
output VAR17 ;
input VAR6 ;
input VAR16 ;
input VAR5 ;
input VAR14 ;
input VAR15;
input VAR12;
input VAR11 ;
input VAR3 ;
wire VAR18 ;
wire VAR2 ;
wire VAR8 ;
wire VAR19;
and VAR13 (VAR18 , VAR5, VAR14 );
and VAR4 (VAR2 , VAR6, VAR16 )... | apache-2.0 |
8l/kestrel | 2/nexys2/computer/M_kestrel2.v | 62,105 | module MODULE1(
output VAR30,
output VAR3,
output VAR32,
output VAR2,
output VAR12,
output VAR21,
output VAR7,
output VAR14,
output VAR4,
output VAR23,
output VAR28,
output VAR13,
output VAR29,
output VAR10,
output [2:0] VAR20,
output [2:0] VAR16,
output [2:1] VAR25,
input VAR15,
input VAR1,
input VAR8,
input VAR5
);
r... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtp/sky130_fd_sc_hdll__dlrtp.functional.pp.v | 1,946 | module MODULE1 (
VAR6 ,
VAR13,
VAR15 ,
VAR10 ,
VAR7 ,
VAR8 ,
VAR12 ,
VAR4
);
output VAR6 ;
input VAR13;
input VAR15 ;
input VAR10 ;
input VAR7 ;
input VAR8 ;
input VAR12 ;
input VAR4 ;
wire VAR2;
wire VAR3;
not VAR11 (VAR2 , VAR13 );
VAR5 VAR9 VAR14 (VAR3 , VAR15, VAR10, VAR2, , VAR7, VAR8);
buf VAR1 (VAR6 , VAR3 );
en... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtp/sky130_fd_sc_hs__dfrtp.behavioral.pp.v | 2,177 | module MODULE1 (
VAR15 ,
VAR11 ,
VAR4 ,
VAR13 ,
VAR8 ,
VAR18
);
input VAR15 ;
input VAR11 ;
output VAR4 ;
input VAR13 ;
input VAR8 ;
input VAR18;
wire VAR14 ;
wire VAR5 ;
reg VAR6 ;
wire VAR1 ;
wire VAR10;
wire VAR9 ;
wire VAR2 ;
wire VAR12 ;
wire VAR7 ;
not VAR3 (VAR5 , VAR10 );
VAR17 VAR19 (VAR14 , VAR1, VAR9, VAR5, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp.behavioral.v | 1,842 | module MODULE1 (
VAR2,
VAR9,
VAR6
);
output VAR2;
input VAR9;
input VAR6 ;
supply1 VAR1;
supply0 VAR14;
supply1 VAR15 ;
supply0 VAR5 ;
wire VAR16 ;
wire VAR4 ;
wire VAR10 ;
wire VAR8;
reg VAR3 ;
not VAR7 (VAR4 , VAR10 );
VAR13 VAR11 (VAR16 , VAR8, VAR4, VAR3, VAR1, VAR14);
and VAR12 (VAR2 , VAR16, VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv_1.v | 1,995 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR6,
VAR1,
VAR8 ,
VAR7
);
output VAR3 ;
input VAR5 ;
input VAR6;
input VAR1;
input VAR8 ;
input VAR7 ;
VAR4 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR6;
supply0 VAR1;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_4.behavioral.v | 1,178 | module MODULE1( VAR4, VAR5, VAR3 );
input VAR5, VAR4;
output VAR3;
VAR2 VAR1(.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3));
VAR2 VAR6(.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.cache/ip/2018.2/69064d299950f876/gcd_zynq_snick_auto_pc_0_stub.v | 4,581 | module MODULE1(VAR19, VAR28, VAR18, VAR25,
VAR52, VAR9, VAR21, VAR55, VAR6, VAR44,
VAR15, VAR42, VAR48, VAR49, VAR53, VAR37, VAR40,
VAR41, VAR14, VAR51, VAR54, VAR17, VAR45, VAR26,
VAR16, VAR36, VAR1, VAR56, VAR32, VAR24,
VAR3, VAR57, VAR27, VAR30, VAR4, VAR58, VAR50,
VAR29, VAR11, VAR10, VAR31, VAR34, VAR5,
VAR23, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4.pp.blackbox.v | 1,261 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR2 ,
VAR6 ,
VAR3 ,
VAR4,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR4;
input VAR7;
endmodule | apache-2.0 |
SiLab-Bonn/pyBAR | firmware/mio/src/top.v | 31,323 | module MODULE1 (
input wire VAR235,
inout wire [7:0] VAR234,
input wire [15:0] VAR129,
input wire VAR134,
input wire VAR191,
inout wire [7:0] VAR259,
input wire VAR3,
input wire VAR221,
input wire VAR188,
output wire [10:0] VAR227,
output wire [4:0] VAR126,
output wire [19:0] VAR106,
inout wire [15:0] VAR268,
output wi... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211ai/sky130_fd_sc_hdll__o211ai.behavioral.v | 1,572 | module MODULE1 (
VAR8 ,
VAR7,
VAR10,
VAR6,
VAR11
);
output VAR8 ;
input VAR7;
input VAR10;
input VAR6;
input VAR11;
supply1 VAR5;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
wire VAR13 ;
wire VAR9;
or VAR12 (VAR13 , VAR10, VAR7 );
nand VAR14 (VAR9, VAR11, VAR13, VAR6);
buf VAR4 (VAR8 , VAR9 );
endmodule | apache-2.0 |
ellore/processor | top_level.v | 4,208 | module
MODULE1(
input wire VAR25, output wire[1:0] VAR27, inout wire[7:0] VAR9,
output wire VAR29, output wire VAR23, input wire VAR15,
output wire VAR12, input wire VAR19, output wire VAR32,
output wire[7:0] VAR26
);
wire[6:0] VAR22;
wire[7:0] VAR11; wire VAR7; wire VAR20;
wire[7:0] VAR28; wire VAR16; wire VAR3;
wire ... | mit |
kyzhai/NUNY | src/hardware/ninja1_bb.v | 4,986 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
chriz2600/DreamcastHDMI | Core/source/hdmi_video_reconfig.v | 4,740 | module MODULE1(
input VAR6,
input [7:0] VAR4,
output VAR1,
output VAR5 VAR2
);
reg [7:0] VAR3 = 0;
VAR5 VAR7;
VAR5 VAR7;
reg VAR8;
reg VAR8; | mit |
cpulabs/mist1032isa | src/core/pipeline_control/pipeline_control_hundler_read.v | 2,662 | module MODULE1(
input wire VAR7,
input wire VAR19,
input wire VAR27,
input wire [31:0] VAR17,
input wire VAR23,
input wire [6:0] VAR12,
output wire VAR22,
output wire [31:0] VAR2,
output wire VAR1,
output wire VAR9,
input wire VAR26,
output wire [1:0] VAR10, output wire VAR6, output wire [13:0] VAR3,
output wire [1:0] ... | bsd-2-clause |
secworks/sha512 | src/rtl/sha512.v | 10,374 | module MODULE1(
input wire clk,
input wire VAR19,
input wire VAR20,
input wire VAR15,
input wire [7 : 0] address,
input wire [31 : 0] VAR54,
output wire [31 : 0] VAR53,
output wire VAR55
);
parameter VAR28 = 8'h00;
parameter VAR8 = 8'h01;
parameter VAR9 = 8'h02;
parameter VAR25 = 8'h08;
parameter VAR3 = 0;
parameter VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22a/sky130_fd_sc_hdll__o22a_4.v | 2,355 | module MODULE2 (
VAR3 ,
VAR10 ,
VAR8 ,
VAR2 ,
VAR9 ,
VAR7,
VAR1,
VAR6 ,
VAR4
);
output VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR7;
input VAR1;
input VAR6 ;
input VAR4 ;
VAR5 VAR11 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR... | apache-2.0 |
Daniel-Norman/FDPaint | sesame.v | 16,250 | module MODULE1(
input clk,
input [7:0] VAR35,
input VAR70,
input VAR102,
input VAR101,
input VAR112,
input VAR96,
input VAR9,
output VAR72,
output VAR98,
output VAR34,
output reg [2:0] VAR103,
output reg [2:0] VAR15,
output reg [2:1] VAR25,
output reg VAR26,
output reg VAR60
);
wire [9:0] VAR92 = 240;
wire [9:0] VAR52 ... | mit |
LSaldyt/qnp | output/vs/opt_var8_multi.v | 7,124 | module MODULE1(VAR3, VAR5, VAR7, VAR1, VAR6, VAR4, VAR8, VAR2, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022;
wire 023;
wire 024;... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_4.behavioral.pp.v | 8,945 | module MODULE1( VAR56, VAR75, VAR74, VAR16, VAR90, VAR40, VAR32 );
input VAR56, VAR75, VAR16, VAR74;
inout VAR40, VAR32;
output VAR90;
reg VAR88;
VAR28 VAR11(.VAR56(VAR56),.VAR75(VAR75),.VAR74(VAR74),.VAR16(VAR16),.VAR90(VAR90),.VAR40(VAR40),.VAR32(VAR32),.VAR88(VAR88));
VAR28 VAR61(.VAR56(VAR56),.VAR75(VAR75),.VAR74(V... | apache-2.0 |
CprE488/Final | system/hdl/system_v_axi4s_vid_out_0_wrapper.v | 2,533 | module MODULE1
(
VAR31,
rst,
VAR26,
VAR35,
VAR14,
VAR4,
VAR17,
VAR24,
VAR2,
VAR9,
VAR1,
VAR30,
VAR29,
VAR27,
VAR12,
VAR18,
VAR32,
VAR10,
VAR20,
VAR11,
VAR6,
VAR7,
VAR19,
VAR33,
VAR25,
VAR21
);
input VAR31;
input rst;
input VAR26;
input VAR35;
input [15:0] VAR14;
input VAR4;
output VAR17;
input VAR24;
input VAR2;
input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21o/sky130_fd_sc_ls__a21o.functional.v | 1,406 | module MODULE1 (
VAR9 ,
VAR1,
VAR6,
VAR4
);
output VAR9 ;
input VAR1;
input VAR6;
input VAR4;
wire VAR3 ;
wire VAR8;
and VAR5 (VAR3 , VAR1, VAR6 );
or VAR2 (VAR8, VAR3, VAR4 );
buf VAR7 (VAR9 , VAR8 );
endmodule | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab3/laboratorio3/Memoria.v | 1,237 | module MODULE1(VAR3, VAR2, VAR4, VAR6 );
input VAR3;
input [3:0] VAR2;
inout [3:0] VAR4;
output [3:0] VAR6;
reg [3:0] VAR1[0:15];
integer VAR5;
begin
begin
begin | mit |
mlarouche/sd2snes | verilog/sd2snes/bsx.v | 8,808 | module MODULE1(
input VAR46,
input VAR5,
input VAR50,
input VAR40,
input [23:0] VAR10,
input [7:0] VAR13,
output [7:0] VAR57,
input [7:0] VAR2,
input [7:0] VAR41,
output [14:0] VAR6,
input VAR49,
input VAR56,
output VAR15,
output VAR22,
input [59:0] VAR29,
output [9:0] VAR21, output VAR48,
output [8:0] VAR53
);
wire [3... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2_4.v | 1,990 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR6 ,
VAR3,
VAR7
);
output VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR3;
input VAR7;
VAR1 VAR4 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR5,
VAR2,
VAR6
);
output VAR5;
input VAR2;
input VAR6;
supply1 VAR3;
supply0 VAR7;
VAR1 VAR4 (
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/conb/sky130_fd_sc_hd__conb.blackbox.v | 1,238 | module MODULE1 (
VAR1,
VAR6
);
output VAR1;
output VAR6;
supply1 VAR5;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
bluespec/Flute | src_bsc_lib_RTL/BRAM1BE.v | 4,281 | module MODULE1(VAR4,
VAR3,
VAR10,
VAR15,
VAR6,
VAR14
);
parameter VAR1 = 0;
parameter VAR9 = 1;
parameter VAR5 = 1;
parameter VAR12 = 1;
parameter VAR11 = 1;
parameter VAR13 = 1;
input VAR4;
input VAR3;
input [VAR11-1:0] VAR10;
input [VAR9-1:0] VAR15;
input [VAR5-1:0] VAR6;
output [VAR5-1:0] VAR14;
reg [VAR5-1:0] VAR2[... | apache-2.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_stub.v | 1,364 | module MODULE1(VAR1, VAR3, VAR4, VAR2, VAR5, VAR6)
;
input [0:9]VAR1;
input VAR3;
input VAR4;
input VAR2;
input VAR5;
output [0:9]VAR6;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b.pp.blackbox.v | 1,293 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR5 ,
VAR3,
VAR2,
VAR4 ,
VAR6
);
output VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR3;
input VAR2;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_dmask_data_stream_0_V.v | 3,017 | module MODULE2 (
clk,
VAR4,
VAR9,
VAR16,
VAR3);
parameter VAR12 = 32'd8;
parameter VAR25 = 32'd1;
parameter VAR20 = 32'd2;
input clk;
input [VAR12-1:0] VAR4;
input VAR9;
input [VAR25-1:0] VAR16;
output [VAR12-1:0] VAR3;
reg[VAR12-1:0] VAR6 [0:VAR20-1];
integer VAR17;
always @ (posedge clk)
begin
if (VAR9)
begin
for (VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcon/sky130_fd_sc_hd__fahcon.pp.blackbox.v | 1,396 | module MODULE1 (
VAR4,
VAR8 ,
VAR5 ,
VAR7 ,
VAR6 ,
VAR9 ,
VAR1 ,
VAR2 ,
VAR3
);
output VAR4;
output VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR9 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2/sky130_fd_sc_ms__nand2_2.v | 2,097 | module MODULE2 (
VAR4 ,
VAR3 ,
VAR2 ,
VAR8,
VAR6,
VAR7 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR8;
input VAR6;
input VAR7 ;
input VAR1 ;
VAR5 VAR9 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR4,
VAR3,
VAR2
);
output VAR4;
... | apache-2.0 |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_2/synth/design_1_auto_us_2.v | 10,494 | module MODULE1 (
VAR89,
VAR1,
VAR75,
VAR72,
VAR65,
VAR63,
VAR26,
VAR36,
VAR97,
VAR18,
VAR85,
VAR43,
VAR60,
VAR44,
VAR94,
VAR11,
VAR66,
VAR7,
VAR15,
VAR82,
VAR54,
VAR95,
VAR62,
VAR9,
VAR74,
VAR8,
VAR56,
VAR93,
VAR80,
VAR51,
VAR98,
VAR64,
VAR29,
VAR33,
VAR71,
VAR40,
VAR6,
VAR2,
VAR58,
VAR81
);
input wire VAR89;
input wir... | gpl-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_gt_common_1.v | 7,376 | module MODULE1 (
VAR17,
VAR48,
VAR5,
VAR42,
VAR32,
VAR36,
VAR23,
VAR9,
VAR53,
VAR64,
VAR51,
VAR29,
VAR8,
VAR52,
VAR68,
VAR27,
VAR39);
parameter integer VAR31 = 0;
parameter integer VAR25 = 0;
parameter integer VAR57 = 1;
parameter integer VAR54 = 2;
parameter [26:0] VAR3 = 27'h06801C1;
parameter integer VAR60 = 1'b1;
p... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3b/sky130_fd_sc_hs__or3b.blackbox.v | 1,255 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR4;
supply1 VAR6;
supply0 VAR3;
endmodule | apache-2.0 |
origintfj/riscv | rv32i/rtl/merlin_pfu32ic.v | 12,027 | module MODULE1
parameter VAR16 = 0,
parameter VAR23 = 2, parameter VAR20 = 30'b0
)
(
input wire VAR3,
input wire VAR24,
input wire VAR51,
output wire VAR47,
output wire [1:0] VAR9,
output wire [31:0] VAR6, output wire VAR1,
input wire VAR17,
input wire VAR4,
input wire [31:0] VAR26,
output wire VAR52, input wire VAR35,... | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | spi_master/peripherical_spi_master.v | 2,502 | module MODULE1(clk , rst , din , VAR13 , addr , rd , wr, dout,VAR8 ,VAR1, VAR4, VAR5);
input clk;
input rst;
input [15:0]din;
input VAR13;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
input VAR1;
output VAR8, VAR4, VAR6;
reg [6:0] VAR3;
reg [7:0] VAR7=0;
reg VAR9=0;
reg reset=0;
reg VAR14=1;
wire [7:0] V... | mit |
jotego/jt51 | hdl/jt51_noise.v | 2,828 | module MODULE1(
input rst,
input clk,
input VAR4, input [ 4:0] VAR6,
input [ 4:0] VAR8,
input [ 9:0] VAR1, input VAR3,
output out,
output reg [11:0] VAR9
);
reg VAR5, VAR12;
reg [ 4:0] VAR7;
reg [15:0] VAR11;
reg VAR14;
wire VAR10, VAR13;
wire VAR2;
assign out = VAR11[0];
always @(posedge clk, posedge rst) begin
if( rs... | gpl-3.0 |
brianbennett/fpga_nes | hw/src/ppu/ppu_bg.v | 13,110 | module MODULE1
(
input wire VAR2, input wire VAR12, input wire VAR18, input wire VAR34, input wire [ 2:0] VAR15, input wire [ 4:0] VAR8, input wire VAR5, input wire [ 2:0] VAR1, input wire [ 4:0] VAR16, input wire VAR24, input wire VAR9, input wire [ 9:0] VAR47, input wire [ 9:0] VAR46, input wire [ 9:0] VAR40, input w... | bsd-2-clause |
freecores/tiny_tate_bilinear_pairing | group_size_is_911_bits/rtl/rom.v | 15,121 | module MODULE1 (clk, addr, out);
input clk;
input [8:0] addr;
output reg [28:0] out;
always @(posedge clk)
case (addr)
0: out <= 29'h1860042;
1: out <= 29'h30d0041;
2: out <= 29'h38f0041;
3: out <= 29'h60046;
4: out <= 29'hb01b180;
5: out <= 29'hb810041;
6: out <= 29'hb8bb197;
7: out <= 29'hc0bb187;
8: out <= 29'hcb1b1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4/sky130_fd_sc_hs__nor4.functional.pp.v | 1,768 | module MODULE1 (
VAR3,
VAR10,
VAR8 ,
VAR4 ,
VAR5 ,
VAR9 ,
VAR12
);
input VAR3;
input VAR10;
output VAR8 ;
input VAR4 ;
input VAR5 ;
input VAR9 ;
input VAR12 ;
wire VAR2 ;
wire VAR7;
nor VAR11 (VAR2 , VAR4, VAR5, VAR9, VAR12 );
VAR1 VAR13 (VAR7, VAR2, VAR3, VAR10);
buf VAR6 (VAR8 , VAR7 );
endmodule | apache-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/system/wb_ddr3_bridge.v | 8,044 | module MODULE1
(
input VAR24,
input [31:0] VAR22,
input [3:0] VAR19,
input VAR5,
output reg [31:0] VAR14 = 'd0,
input [31:0] VAR8,
input VAR17,
input VAR16,
output VAR4,
output VAR9,
output reg VAR23 = 'd0, output reg [2:0] VAR30 = 'd0, output reg [29:0] VAR36 = 'd0, input VAR3,
input VAR39, output reg VAR2 = 'd0, outp... | gpl-2.0 |
litex-hub/pythondata-cpu-lm32 | pythondata_cpu_lm32/verilog/rtl/lm32_interrupt.v | 11,379 | module MODULE1 (
VAR39,
VAR6,
interrupt,
VAR15,
VAR38,
VAR10,
VAR8,
VAR1,
VAR29,
VAR9,
VAR31,
VAR35,
VAR16,
VAR37
);
parameter VAR24 = VAR27;
input VAR39; input VAR6;
input [VAR24-1:0] interrupt;
input VAR15;
input VAR38; input VAR10; else
input VAR8; VAR13
input VAR1; VAR33 VAR18
input VAR29; VAR13
input [VAR14] VAR9;... | epl-1.0 |
kevintownsend/inara-hdl-libraries | reorder_queue/reorder_queue.v | 3,153 | module MODULE1(rst, clk, VAR22, VAR4, VAR25, VAR10, VAR21, VAR19, valid, VAR17);
parameter VAR23 = 64;
parameter VAR18 = 64;
parameter VAR16 = 0;
parameter VAR13 = VAR14(VAR18-1);
input rst, clk;
input VAR22;
output [VAR13:0] VAR4;
output VAR25;
input VAR10;
input [VAR23-1:0] VAR21;
output reg [VAR23-1:0] VAR19;
output... | apache-2.0 |
cr88192/bgbtech_bjx1core | bwjx1c64a/Dc2Tile.v | 6,352 | module MODULE1(
VAR24, reset,
VAR17, VAR43,
VAR4, VAR14,
VAR39, VAR1,
VAR7,
VAR21, VAR18, VAR38,
VAR13, VAR29, VAR16,
VAR41, VAR23, VAR33,
VAR26, VAR20, VAR27
);
input VAR24; input reset; input[63:0] VAR17; input[127:0] VAR43; input VAR39; input VAR1; input[4:0] VAR7;
output[127:0] VAR4; output[1:0] VAR14;
input[127:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tap/sky130_fd_sc_ms__tap.behavioral.v | 1,152 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_018bits.v | 1,917 | module MODULE1 (
clk,
VAR20, VAR9, VAR28, VAR7, VAR19, VAR27, VAR22, VAR31,
sum,
);
input clk;
input [VAR13+0-1:0] VAR20, VAR9, VAR28, VAR7, VAR19, VAR27, VAR22, VAR31;
output [VAR13 :0] sum;
reg [VAR13 :0] sum;
wire [VAR13+3-1:0] VAR15;
wire [VAR13+2-1:0] VAR26, VAR33;
wire [VAR13+1-1:0] VAR30, VAR18, VAR4, VAR11;
reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3b/sky130_fd_sc_lp__and3b.functional.v | 1,381 | module MODULE1 (
VAR5 ,
VAR3,
VAR6 ,
VAR9
);
output VAR5 ;
input VAR3;
input VAR6 ;
input VAR9 ;
wire VAR7 ;
wire VAR2;
not VAR4 (VAR7 , VAR3 );
and VAR8 (VAR2, VAR9, VAR7, VAR6 );
buf VAR1 (VAR5 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o.pp.symbol.v | 1,366 | module MODULE1 (
input VAR1 ,
input VAR7 ,
input VAR3 ,
input VAR9 ,
output VAR6 ,
input VAR8 ,
input VAR2,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtp/sky130_fd_sc_ls__dlxtp.behavioral.v | 1,821 | module MODULE1 (
VAR14 ,
VAR15 ,
VAR7
);
output VAR14 ;
input VAR15 ;
input VAR7;
supply1 VAR6;
supply0 VAR13;
supply1 VAR1 ;
supply0 VAR12 ;
wire VAR9 ;
wire VAR5;
wire VAR8 ;
reg VAR11 ;
wire VAR3 ;
VAR4 VAR10 (VAR9 , VAR8, VAR5, VAR11, VAR6, VAR13);
buf VAR2 (VAR14 , VAR9 );
assign VAR3 = ( VAR6 === 1'b1 );
endmodul... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/de1/rtl/verilog/clkgen.v | 3,722 | module MODULE1
(
input VAR2,
input VAR5,
output VAR6,
output VAR8,
output VAR22,
input VAR18,
output VAR3,
output VAR17,
output VAR13
);
wire VAR10;
wire VAR12;
assign VAR12 = VAR5;
assign VAR10 = ~VAR12;
assign VAR6 = ~VAR12;
assign VAR3 = VAR18;
wire VAR15;
wire VAR9;
VAR14 VAR19 (
.VAR21 (VAR10),
.VAR11 (VAR2),
.VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4b/sky130_fd_sc_hd__nand4b.pp.blackbox.v | 1,347 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR2,
VAR9,
VAR8 ,
VAR1
);
output VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR2;
input VAR9;
input VAR8 ;
input VAR1 ;
endmodule | apache-2.0 |
YosysHQ/yosys | techlibs/intel_alm/common/alm_map.v | 1,504 | module MODULE1 (VAR7, VAR15);
parameter VAR2 = 1;
parameter VAR1 = 0;
input [VAR2-1:0] VAR7;
output VAR15;
generate
if (VAR2 == 1) begin
generate
if (VAR1 == 2'b00) begin
assign VAR15 = 1'b0;
end
else if (VAR1 == 2'b01) begin
VAR10 VAR13(
.VAR7(VAR7[0]), .VAR5(VAR15)
);
end
else if (VAR1 == 2'b10) begin
assign VAR15 = ... | isc |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/jasons_v/sasc_top.v | 10,297 | module MODULE1( clk, VAR47,
VAR42, VAR9, VAR36, VAR45,
VAR2, VAR49,
VAR11, VAR22, VAR29, VAR19, VAR25, VAR17);
input clk;
input VAR47;
input VAR42;
output VAR9;
input VAR36;
output VAR45;
input VAR2;
input VAR49;
input [7:0] VAR11;
output [7:0] VAR22;
input VAR29, VAR19;
output VAR25, VAR17;
parameter VAR18 = 1'b0,
VAR... | gpl-2.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_daala_4x4_transpose_0_0/work/hdl/daala_4x4_transpose_v1_0.v | 2,386 | module MODULE1 #
(
parameter integer VAR1 = 256,
parameter integer VAR12 = 256
)
(
input wire VAR6,
input wire VAR9,
output wire VAR10,
input wire [VAR1-1 : 0] VAR3,
input wire VAR4,
input wire VAR8,
output wire VAR11,
output wire [VAR12-1 : 0] VAR7,
output wire VAR5,
input wire VAR2
);
assign VAR10 = VAR2;
assign VAR5... | bsd-2-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_noc_repeater_node.v | 2,180 | module MODULE1
, parameter VAR10 = VAR7(VAR22)
)
( input VAR20
, input VAR12
, input [VAR10-1:0] VAR9
, output [VAR10-1:0] VAR25
, input [VAR10-1:0] VAR26
, output [VAR10-1:0] VAR1
);
VAR24 VAR6, VAR14;
VAR24 VAR11, VAR18;
assign VAR6 = VAR9;
assign VAR14 = VAR26;
assign VAR25 = VAR11;
assign VAR1 = VAR18;
VAR8 #(.VAR2... | bsd-3-clause |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/wasca_external_sdram_controller.v | 24,344 | module MODULE1 (
clk,
rd,
VAR31,
wr,
VAR51,
VAR17,
VAR44,
VAR58,
VAR16,
VAR3
)
;
output VAR17;
output VAR44;
output VAR58;
output VAR16;
output [ 42: 0] VAR3;
input clk;
input rd;
input VAR31;
input wr;
input [ 42: 0] VAR51;
wire VAR17;
wire VAR44;
wire VAR58;
reg [ 1: 0] VAR61;
reg [ 42: 0] VAR13;
reg [ 42: 0] VAR23;
... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_gclk_inv_224x.v | 1,296 | module MODULE1 (
VAR2,
VAR1 );
output VAR2;
input VAR1;
assign VAR2 = ~( VAR1 );
endmodule | gpl-2.0 |
YurongYou/MIPS_CPU | ForwardControl.v | 3,279 | module MODULE1 (
input rst,
input[VAR4-1:0] VAR33,
input[VAR4-1:0] VAR20,
input[VAR4-1:0] VAR15,
input[VAR4-1:0] VAR6,
input[VAR4-1:0] VAR7,
input VAR27,
input[VAR4-1:0] VAR16,
input[VAR4-1:0] VAR31,
input VAR13,
input VAR23,
input VAR8,
input VAR3,
input[VAR4-1:0] VAR11,
input VAR34,
input VAR1,
input VAR26,
output re... | mpl-2.0 |
bangonkali/quartus-sockit | pll_vga.v | 15,405 | module MODULE1 (
input wire VAR3, input wire rst, output wire VAR1 );
VAR2 VAR5 (
.VAR3 (VAR3), .rst (rst), .VAR1 (VAR1), .VAR4 () );
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcon/sky130_fd_sc_hs__fahcon.symbol.v | 1,322 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR2 ,
output VAR7,
output VAR1
);
supply1 VAR5;
supply0 VAR4;
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/spi_master.v | 6,395 | module MODULE1
parameter VAR18 = 8)
(input VAR74, output VAR20, output VAR13,
input [VAR18-1:0] VAR68, input VAR69,
output [VAR18-1:0] VAR32, output VAR24,
output VAR62, output VAR31, input VAR34, output VAR46);
assign VAR32 = 8'h0;
assign VAR24 = 1'b0;
wire [VAR18-1:0] VAR25;
d1 #(8) VAR63(.VAR74(VAR74), .VAR3(VAR68),... | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_phy_10g_rx.v | 4,171 | module MODULE1 #
(
parameter VAR3 = 64,
parameter VAR17 = (VAR3/8),
parameter VAR4 = 2,
parameter VAR2 = 0,
parameter VAR12 = 0,
parameter VAR20 = 0,
parameter VAR5 = 0,
parameter VAR9 = 1,
parameter VAR6 = 8,
parameter VAR19 = 125000/6.4
)
(
input wire clk,
input wire rst,
output wire [VAR3-1:0] VAR15,
output wire [VA... | mit |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/submodules/nios_system_hex_0.v | 2,244 | module MODULE1 (
address,
VAR7,
clk,
VAR8,
VAR6,
VAR3,
VAR1,
VAR4
)
;
output [ 3: 0] VAR1;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR7;
input clk;
input VAR8;
input VAR6;
input [ 31: 0] VAR3;
wire VAR9;
reg [ 3: 0] VAR2;
wire [ 3: 0] VAR1;
wire [ 3: 0] VAR5;
wire [ 31: 0] VAR4;
assign VAR9 = 1;
assign VAR5 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor2/sky130_fd_sc_ms__xor2_2.v | 2,117 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR6 ,
VAR5,
VAR3,
VAR4 ,
VAR2
);
output VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR5;
input VAR3;
input VAR4 ;
input VAR2 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR7,
VAR9,
VAR6
);
output VAR7;
... | apache-2.0 |
donnaware/AGC | rtl/de0/modules/ng_MON.v | 3,171 | module MODULE1(
input VAR7, input VAR9, input VAR5, input VAR16, input VAR19, input VAR17, input VAR6, input VAR14, output VAR21, output VAR13, output VAR8, output VAR12, output VAR20, output VAR18, output VAR10 );
VAR15 VAR2(.clk(VAR14), .VAR1(!VAR7), .VAR3(VAR21));
assign VAR8 = !VAR9; assign VAR12 = !VAR5; assign VA... | gpl-3.0 |
Canaan-Creative/MM | verilog/superkdf9/components/lm32_top/jtag_lm32.v | 82,068 | module MODULE1 (
input VAR47,
input VAR13,
output VAR67,
input VAR115,
input VAR65,
input VAR92,
input VAR22,
input VAR52,
input VAR167,
output VAR113,
input [7:0] VAR245,
input [2:0] VAR172,
output [VAR242-1:0] VAR173,
output [7:0] VAR173,
output [2:0] VAR228);
wire [VAR242+1:0] VAR236 ;
wire [9:0] VAR236 ;
VAR202 VAR... | unlicense |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ui/ui_wr_data.v | 20,211 | module MODULE1 #
(
parameter VAR77 = 100,
parameter VAR54 = 256,
parameter VAR17 = 32,
parameter VAR4 = "VAR69",
parameter VAR64 = "VAR69",
parameter VAR113 = 5
)
(
VAR57, VAR86, VAR83, VAR97, VAR112,
VAR66,
rst, clk, VAR41, VAR60, VAR18, VAR32,
VAR14, VAR70, VAR52, VAR49, VAR25,
VAR15, VAR73
);
input rst;
input clk;
i... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfstp/sky130_fd_sc_ls__sdfstp.behavioral.v | 2,775 | module MODULE1 (
VAR8 ,
VAR26 ,
VAR1 ,
VAR30 ,
VAR24 ,
VAR15
);
output VAR8 ;
input VAR26 ;
input VAR1 ;
input VAR30 ;
input VAR24 ;
input VAR15;
supply1 VAR29;
supply0 VAR13;
supply1 VAR19 ;
supply0 VAR11 ;
wire VAR17 ;
wire VAR10 ;
wire VAR14 ;
reg VAR21 ;
wire VAR2 ;
wire VAR28 ;
wire VAR4 ;
wire VAR31;
wire VAR3 ;
... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/FIFO_OPENFLOW/ram_32_1.v | 9,544 | module MODULE1 (
VAR23,
VAR58,
VAR42,
VAR29,
VAR22,
VAR28,
VAR6,
VAR30);
input VAR23;
input VAR58;
input [0:0] VAR42;
input [4:0] VAR29;
input VAR22;
input [4:0] VAR28;
input VAR6;
output [0:0] VAR30;
tri0 VAR23;
tri1 VAR58;
tri1 VAR22;
tri0 VAR6;
wire [0:0] VAR52;
wire [0:0] VAR30 = VAR52[0:0];
VAR32 VAR7 (
.VAR50 (VA... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/pad_misc.v | 14,036 | module MODULE1(VAR65 ,VAR205 ,VAR63 ,VAR196 ,
VAR115 ,VAR69 ,VAR43 ,
VAR68 ,VAR103 ,VAR90 ,VAR87 ,
VAR185 ,VAR132 ,VAR174 ,VAR6 ,VAR9 ,
VAR162 ,VAR57 ,VAR41 ,VAR143 ,VAR141
,VAR159 ,VAR123 ,VAR170 ,VAR130 ,VAR183 ,
VAR83 ,VAR7 ,VAR134 ,VAR32
,VAR42 ,VAR106 ,VAR84 ,VAR45 ,
VAR44 ,VAR151 ,VAR51 ,VAR55 ,VAR210 ,
VAR211 ,V... | gpl-2.0 |
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