repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nvme/nvme_host_ctrl_8lane-1.0.0/pcie_irq_gen.v | 6,403 | module MODULE1 # (
parameter VAR27 = 128,
parameter VAR16 = 36
)
(
input VAR32,
input VAR29,
input [15:0] VAR33,
output VAR18,
input VAR12,
output VAR17,
output [7:0] VAR24,
input [7:0] VAR23,
input [2:0] VAR25,
input VAR26,
input VAR3,
input VAR21,
output VAR6,
output [4:0] VAR7,
input VAR34,
input VAR1,
input [2:0] V... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_csc_1_add.v | 5,863 | module MODULE1 (
clk,
VAR19,
VAR1,
VAR14,
VAR15,
VAR25,
VAR12,
VAR26);
parameter VAR22 = 16;
localparam VAR21 = VAR22 - 1;
input clk;
input [24:0] VAR19;
input [24:0] VAR1;
input [24:0] VAR14;
input [24:0] VAR15;
output [ 7:0] VAR25;
input [VAR21:0] VAR12;
output [VAR21:0] VAR26;
reg [VAR21:0] VAR8 = 'd0;
reg [24:0] VA... | mit |
mashanz/FinalProject | Code/module/controller.v | 7,185 | module MODULE1(
VAR29, VAR34, VAR36, VAR30, VAR1, VAR35, VAR37, VAR49,
VAR4, VAR10, VAR16, VAR13, VAR2, VAR38, VAR53, VAR19,
VAR40, VAR28,
VAR45, VAR43, reset, VAR3, VAR31, VAR24, VAR44, VAR26, VAR47, VAR18
);
input VAR45, VAR43;
input reset;
input VAR3, VAR31, VAR24, VAR44, VAR26, VAR47;
input VAR18;
output reg VAR29;... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync.v | 3,067 | module MODULE1 #(parameter VAR20(VAR34)
, parameter VAR20(VAR2)
, parameter VAR11=0
, parameter VAR27=VAR28(VAR2)
, parameter VAR40=0
, parameter VAR18=0
)
(input VAR4
, input VAR26
, input VAR13
, input [VAR27-1:0] VAR14
, input [VAR34-1:0] VAR41
, input VAR35
, input [VAR27-1:0] VAR23
, output logic [VAR22(VAR34, 1):... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbn/sky130_fd_sc_ms__dlrbn.blackbox.v | 1,405 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR9,
VAR3 ,
VAR2
);
output VAR5 ;
output VAR7 ;
input VAR9;
input VAR3 ;
input VAR2 ;
supply1 VAR6;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_dqs_edgelogic.v | 2,706 | module MODULE1(
VAR10, VAR22, VAR19, VAR1,
clk, VAR13, VAR6,
VAR25, VAR15,
VAR16, VAR9, VAR3
);
input clk;
input VAR3;
input VAR13;
input VAR6;
input VAR25;
input VAR15;
input VAR16;
input VAR9;
output VAR10;
output VAR22;
output VAR19;
output VAR1;
wire VAR21 = VAR3 ? ~clk : clk;
VAR5 #(1) VAR7(
.din(VAR25),
.VAR17(VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ba/sky130_fd_sc_lp__o21ba.symbol.v | 1,386 | module MODULE1 (
input VAR4 ,
input VAR7 ,
input VAR8,
output VAR2
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
benjaminfjones/fpga-led-counter | src/blinker.v | 1,118 | module MODULE1(
input clk,
input rst,
output VAR3
);
reg [24:0] VAR1, VAR2;
reg VAR4;
assign VAR3 = VAR2[24];
always@(VAR1) begin
if (VAR4) begin
VAR2 = VAR1 - 1'b1;
end else begin
VAR2 = VAR1 + 1'b1;
end
end
always@(posedge clk) begin
if (rst) begin
VAR1 <= 25'b0;
VAR4 <= 1'b0;
end else begin
VAR1 <= VAR2;
end
end
end... | gpl-3.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFBox_Top.v | 5,329 | module MODULE1(VAR18,
VAR14,
VAR28,
VAR20,
VAR26,
VAR27,
VAR3,
VAR15,
VAR31,
VAR16,
VAR19,
VAR38,
VAR7,
VAR10,
VAR1,
valid,
VAR29,
VAR34);
input [3 : 0] VAR18;
input VAR14;
input VAR28;
input VAR20;
output VAR26;
input VAR27;
output VAR3;
input [6 : 0] VAR15;
input [6 : 0] VAR31;
input [2 : 0] VAR16;
input [4 : 0] VAR1... | apache-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/toplevel/mrfm/biquad_2stage.v | 4,656 | module MODULE1 (input VAR13, input reset, input VAR29,
input VAR47, input [6:0] VAR21, input [31:0] VAR14,
input wire [15:0] VAR44, output reg [15:0] VAR28, output wire [63:0] VAR1);
wire [3:0] VAR31, VAR20;
wire [3:0] VAR32, VAR23;
reg [3:0] VAR37, VAR16, VAR22;
wire [15:0] VAR42, VAR55, VAR3, VAR46;
wire VAR49;
reg V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o_1.v | 2,212 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR8 ,
VAR9,
VAR7
);
output VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR8 ;
input VAR9;
input VAR7;
VAR4 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR1 ,
VAR5,
VAR3,
VAR6,
VAR8
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22o/sky130_fd_sc_hd__a22o.pp.blackbox.v | 1,385 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR1,
VAR2,
VAR5 ,
VAR6
);
output VAR7 ;
input VAR4 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR1;
input VAR2;
input VAR5 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux4/sky130_fd_sc_hvl__mux4_1.v | 2,452 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR8 ,
VAR7 ,
VAR1 ,
VAR6 ,
VAR10 ,
VAR2,
VAR5,
VAR13 ,
VAR12
);
output VAR11 ;
input VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR6 ;
input VAR10 ;
input VAR2;
input VAR5;
input VAR13 ;
input VAR12 ;
VAR9 VAR3 (
.VAR11(VAR11),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4/sky130_fd_sc_hd__or4.blackbox.v | 1,269 | module MODULE1 (
VAR9,
VAR7,
VAR6,
VAR2,
VAR3
);
output VAR9;
input VAR7;
input VAR6;
input VAR2;
input VAR3;
supply1 VAR1;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v | 53,473 | module MODULE1 (
VAR116,
VAR146,
VAR107,
VAR23,
VAR163,
VAR112,
VAR46,
VAR161,
VAR123,
VAR159,
VAR103,
VAR58,
VAR41,
VAR109,
VAR151,
VAR10,
VAR101,
VAR45,
VAR66,
VAR82,
VAR171,
VAR141,
VAR85,
VAR90,
VAR70,
VAR122,
VAR113
);
parameter VAR177 = 0;
parameter VAR81 = 0;
parameter VAR29 = 32;
parameter VAR53 = 20;
parameter... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvp/sky130_fd_sc_hdll__einvp.functional.pp.v | 1,881 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR9 ,
VAR4,
VAR8,
VAR1 ,
VAR7
);
output VAR2 ;
input VAR5 ;
input VAR9 ;
input VAR4;
input VAR8;
input VAR1 ;
input VAR7 ;
wire VAR12 ;
wire VAR10;
VAR6 VAR11 (VAR12 , VAR5, VAR4, VAR8 );
VAR6 VAR3 (VAR10, VAR9, VAR4, VAR8 );
notif1 VAR13 (VAR2 , VAR12, VAR10);
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/altera/common/ad_mul.v | 3,149 | module MODULE1 #(
parameter VAR22 = 17,
parameter VAR19 = 17,
parameter VAR5 = 16) (
input clk,
input [ VAR22-1:0] VAR23,
input [ VAR19-1:0] VAR10,
output [VAR22 + VAR19-1:0] VAR6,
input [(VAR5-1):0] VAR15,
output reg [(VAR5-1):0] VAR13);
reg [(VAR5-1):0] VAR8 = 'd0;
reg [(VAR5-1):0] VAR2 = 'd0;
always @(posedge clk) b... | mit |
timtian090/Playground | UVM/UVMPlayground/Lab4/Lab4-Project/CDC_Input_Synchronizer.v | 1,981 | module MODULE1
parameter VAR5 = 2
)
(
input VAR2,
output VAR3,
input VAR1
);
reg VAR4;
begin
begin
begin
begin
end
begin
begin
begin
begin
end
begin
begin | mit |
efabless/openlane | designs/151/src/Memory141.v | 4,297 | module MODULE1(
input clk,
input reset,
input [31:0] VAR14,
input [31:0] VAR34,
input [3:0] VAR28,
input VAR13,
input VAR8,
input [31:0] VAR26,
output VAR39,
output [31:0] VAR32,
output [31:0] VAR12,
output VAR42,
output VAR25,
input VAR51,
output VAR38,
output [VAR40-1:0] VAR46,
output [VAR10-1:0] VAR4,
output VAR37,
... | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/TECH/altera/duram.v | 2,405 | module MODULE1(
VAR43,
VAR28,
VAR8,
VAR49,
VAR27,
VAR47,
VAR32,
VAR25,
VAR41,
VAR39);
parameter VAR54 = 32;
parameter VAR40 = 5;
parameter VAR59 = "VAR18";
parameter VAR29 = "VAR42";
parameter VAR2 = 2**VAR40;
input [VAR54 -1:0] VAR43;
input VAR8;
input [VAR40 -1:0] VAR27;
input VAR32;
output [VAR54 -1:0] VAR41;
input ... | apache-2.0 |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_ivc_ctrl.v | 34,328 | module MODULE1
(clk, reset, VAR148, VAR137, VAR170, VAR140,
VAR214, VAR210, VAR117, VAR80, VAR107, VAR13,
VAR60, VAR64, VAR113, VAR208, VAR14, VAR145,
VAR73, VAR65, VAR120, VAR136, VAR204,
VAR200, VAR144, VAR10, VAR21, VAR221,
VAR110, VAR9);
parameter VAR152 = 8;
localparam VAR68 = VAR228(VAR152);
parameter VAR167 = 4;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a.pp.symbol.v | 1,383 | module MODULE1 (
input VAR8,
input VAR9,
input VAR3 ,
input VAR7 ,
output VAR4 ,
input VAR5 ,
input VAR1,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
eSedano/vrudy | rtl/dpth_alu.v | 3,587 | module MODULE1 (
input wire [15:0] VAR4,
input wire [15:0] VAR3,
output reg [15:0] out,
input wire VAR5,
input wire enable,
output wire VAR2,
output wire VAR1
);
always @(*)
begin
if (enable == 1'b0) out = VAR3;
end
else
case (VAR5)
2'b00: out = VAR4 + VAR3;
2'b01: out = VAR4 - VAR3;
2'b10: out = {VAR3[15], VAR3[15:1]}... | mit |
ptracton/wb_soc_template | rtl/ZIP/rtl/prefetch.v | 4,719 | module MODULE1(VAR16, VAR20, VAR9, VAR11, VAR22, VAR15,
VAR2, VAR17, VAR12, VAR10,
VAR1, VAR7, VAR3, VAR21, VAR13,
VAR5, VAR23, VAR19, VAR14);
parameter VAR8=32;
localparam VAR18=VAR8;
input wire VAR16, VAR20, VAR9, VAR11,
VAR22;
input wire [(VAR18-1):0] VAR15;
output reg [31:0] VAR2;
output wire [(VAR18-1):0] VAR17;
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2.pp.blackbox.v | 1,303 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6 ,
VAR7 ,
VAR8,
VAR3,
VAR5 ,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR8;
input VAR3;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/user_data_path.v | 19,437 | module MODULE1
parameter VAR116=VAR29/8,
parameter VAR104 = 2,
parameter VAR45 = 8,
parameter VAR123 = 8,
parameter VAR149 = VAR29+VAR116,
parameter VAR42 = 19)
(
input [VAR29-1:0] VAR54,
input [VAR116-1:0] VAR69,
input VAR110,
output VAR31,
input [VAR29-1:0] VAR75,
input [VAR116-1:0] VAR115,
input VAR90,
output VAR84,... | mit |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_uart_0.v | 28,074 | module MODULE1 (
VAR86,
VAR77,
clk,
VAR13,
VAR79,
VAR11,
VAR90,
VAR54,
VAR2,
VAR16,
VAR33,
VAR72,
VAR5
)
;
output VAR16;
output VAR33;
output VAR72;
output VAR5;
input [ 8: 0] VAR86;
input VAR77;
input clk;
input VAR13;
input VAR79;
input VAR11;
input VAR90;
input [ 7: 0] VAR54;
input VAR2;
reg VAR73;
reg [ 8: 0] VAR71... | gpl-2.0 |
asicguy/gplgpu | hdl/hbi/pci_wom.v | 14,169 | module MODULE1
(
input VAR89,
input VAR49,
input VAR57,
input VAR45,
input VAR65,
input VAR71,
input VAR10,
input VAR76,
input VAR85,
input VAR8,
input VAR56,
input VAR12,
input VAR24,
input VAR26,
input VAR55,
input VAR61,
input VAR38,
input VAR52,
input VAR28, input [31:2] VAR42,
input [21:0] VAR23,
output [31:0] VAR... | gpl-3.0 |
YosysHQ/yosys | techlibs/fabulous/prims.v | 10,227 | module MODULE12(output VAR105, input VAR136);
parameter [1:0] VAR34 = 0;
assign VAR105 = VAR136 ? VAR34[1] : VAR34[0];
endmodule
module MODULE1(output VAR105, input VAR136, VAR100);
parameter [3:0] VAR34 = 0;
wire [ 1: 0] VAR98 = VAR100 ? VAR34[ 3: 2] : VAR34[ 1: 0];
assign VAR105 = VAR136 ? VAR98[1] : VAR98[0];
endmod... | isc |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/BCHDecoderX.v | 11,152 | module MODULE1
(
parameter VAR62 = 32,
parameter VAR52 = 2,
parameter VAR50 = 9,
parameter VAR59 = 12,
parameter VAR60 = 27,
parameter VAR47 = 15
)
(
VAR25 ,
VAR20 ,
VAR14 ,
VAR22 ,
VAR26 ,
VAR43 ,
VAR33 ,
VAR7 ,
VAR64 ,
VAR32 ,
VAR39 ,
VAR49 ,
VAR42 ,
VAR11 ,
VAR46 ,
VAR15 ,
VAR1 ,
VAR45 ,
VAR61 ,
VAR57 ,
VAR35 ,
VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbn/sky130_fd_sc_hs__dfbbn.behavioral.pp.v | 2,891 | module MODULE1 (
VAR25 ,
VAR23 ,
VAR13 ,
VAR20 ,
VAR21 ,
VAR24,
VAR26 ,
VAR4
);
output VAR25 ;
output VAR23 ;
input VAR13 ;
input VAR20 ;
input VAR21 ;
input VAR24;
input VAR26 ;
input VAR4 ;
wire VAR15 ;
wire VAR18 ;
wire VAR2 ;
wire VAR17 ;
wire VAR8 ;
wire VAR19;
wire VAR28 ;
reg VAR1 ;
wire VAR3 ;
wire VAR27 ;
wire... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_16.behavioral.pp.v | 1,241 | module MODULE1( VAR4, VAR6, VAR8, VAR5, VAR2 );
input VAR4, VAR6;
inout VAR5, VAR2;
output VAR8;
VAR7 VAR3(.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR5(VAR5),.VAR2(VAR2));
VAR7 VAR1(.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_2.behavioral.pp.v | 1,069 | module MODULE1( VAR1, VAR5 );
inout VAR1, VAR5;
VAR2 VAR4(.VAR1(VAR1),.VAR5(VAR5));
VAR2 VAR3(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
mda-ut/AquaTux | fpga/fpga_hw/top_level/ip/TARASIC_SPI_3WIRE/TERASIC_SPI_3WIRE.v | 2,424 | module MODULE1(
clk,
VAR7,
VAR11,
VAR25,
VAR19,
VAR9,
VAR6,
VAR3,
VAR23,
VAR5,
VAR16
);
input clk;
input VAR7;
input VAR11;
input [3:0] VAR25;
input VAR19;
input [7:0] VAR9;
input VAR6;
output reg [7:0] VAR3;
output VAR23;
output VAR5;
inout VAR16;
always @ (posedge clk or negedge VAR7)
begin
if (~VAR7)
begin
VAR15 <= ... | gpl-2.0 |
DigitalLogicSummerTerm2015/mips-cpu-pipeline | ppcpu/controlunit.v | 15,721 | module MODULE1(VAR1,VAR17,VAR16,VAR6,VAR5,VAR4,VAR8,VAR13,VAR14,VAR9,VAR10,VAR12,VAR7,VAR19,VAR3,VAR15,VAR2,VAR11,VAR18);
input [31:0] VAR1;
input VAR17;
input VAR16;
input [31:0] VAR6;
output [31:0] VAR5;
output [2:0] VAR4;
reg [2:0] VAR4;
output [1:0] VAR8;
reg [1:0] VAR8;
output VAR13;
reg VAR13;
output VAR14;
reg V... | mit |
mrehkopf/sd2snes | verilog/sd2snes_base/msu.v | 5,555 | module MODULE1(
input VAR46,
input enable,
input [13:0] VAR16,
input [7:0] VAR30,
input VAR18,
input [2:0] VAR27,
input [7:0] VAR7,
output [7:0] VAR29,
input VAR35,
input VAR40,
input VAR13,
output [7:0] VAR21,
output [7:0] VAR10,
output VAR23,
output [31:0] VAR22,
output [15:0] VAR32,
input [5:0] VAR39,
input [5:0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2_8.v | 2,086 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR7 ,
VAR8,
VAR6,
VAR3 ,
VAR5
);
output VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR8;
input VAR6;
input VAR3 ;
input VAR5 ;
VAR1 VAR9 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR2,
VAR4,
VAR7
);
output VAR2;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2/sky130_fd_sc_ms__mux2_2.v | 2,187 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR4,
VAR6,
VAR10 ,
VAR3
);
output VAR9 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR4;
input VAR6;
input VAR10 ;
input VAR3 ;
VAR5 VAR2 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22ai/sky130_fd_sc_ls__o22ai.behavioral.pp.v | 2,159 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR7 ,
VAR15 ,
VAR3 ,
VAR8,
VAR1,
VAR17 ,
VAR19
);
output VAR6 ;
input VAR9 ;
input VAR7 ;
input VAR15 ;
input VAR3 ;
input VAR8;
input VAR1;
input VAR17 ;
input VAR19 ;
wire VAR2 ;
wire VAR16 ;
wire VAR10 ;
wire VAR4;
nor VAR13 (VAR2 , VAR15, VAR3 );
nor VAR5 (VAR16 , VAR9, VAR7 );
or VA... | apache-2.0 |
1995parham/AlteraDE2-RS232 | src/main.v | 1,489 | module MODULE1 (VAR14, VAR1, clk);
input VAR14;
input clk;
output VAR1;
parameter [3:0] VAR5 = 3'b001, VAR15 = 3'b011, VAR10 = 3'b101, VAR11 = 3'b111,
VAR3 = 3'b000, VAR7 = 3'b010, VAR16 = 3'b100, VAR4 = 3'b110;
reg [3:0] VAR8 = VAR3;
reg [3:0] VAR6 = VAR3;
reg [7:0] VAR17;
reg VAR2;
wire VAR13;
VAR9 VAR12(clk, VAR2, V... | gpl-2.0 |
kylemsguy/FPGA-Litecoin-Miner | source/salsa.v | 7,613 | module MODULE1 (clk, VAR24, VAR27, VAR62, VAR14);
input clk;
input VAR24;
input [511:0]VAR27;
input [511:0]VAR62;
output [511:0]VAR14;
wire [511:0]VAR52;
wire [511:0]VAR30;
reg [511:0]VAR67;
MODULE2 MODULE1 (clk, VAR24 ? VAR67 : VAR52, VAR30);
genvar VAR22;
generate
for (VAR22 = 0; VAR22 < 16; VAR22 = VAR22 + 1) begin ... | gpl-3.0 |
martinmiranda14/Digitales | Lab_6/new/clock_divider.v | 1,120 | module MODULE1(
input clk,
input rst,
output reg VAR1
);
localparam VAR3 = 8000;
reg [63:0] VAR2;
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1)
VAR2 <= 32'd0;
end
else if (VAR2 == (VAR3 - 32'd1))
VAR2 <= 32'd0;
else
VAR2 <= VAR2 + 32'b1;
end
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb.behavioral.v | 1,512 | module MODULE1 (
VAR6 ,
VAR5,
VAR3,
VAR12 ,
VAR4
);
output VAR6 ;
input VAR5;
input VAR3;
input VAR12 ;
input VAR4 ;
supply1 VAR13;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR14 ;
wire VAR7 ;
wire VAR2;
nor VAR8 (VAR7 , VAR5, VAR3 );
and VAR11 (VAR2, VAR7, VAR12, VAR4 );
buf VAR10 (VAR6 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222oi/sky130_fd_sc_hs__a222oi.blackbox.v | 1,391 | module MODULE1 (
VAR6 ,
VAR3,
VAR1,
VAR4,
VAR5,
VAR7,
VAR8
);
output VAR6 ;
input VAR3;
input VAR1;
input VAR4;
input VAR5;
input VAR7;
input VAR8;
supply1 VAR9;
supply0 VAR2;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/ethmac.v | 34,551 | module MODULE1
(
VAR82, VAR305, VAR8, VAR264,
VAR123, VAR262, VAR293, VAR275, VAR44, VAR113, VAR163,
VAR26, VAR61, VAR142,
VAR159, VAR201, VAR38,
VAR162, VAR79, VAR263,
VAR219, VAR12,
VAR284, VAR118, VAR45, VAR128,
VAR257, VAR229, VAR23, VAR246, VAR73, VAR260,
VAR124, VAR87, VAR211, VAR192,
VAR116
,
VAR210, VAR252, VAR... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_impctl_clkgen.v | 2,187 | module MODULE1(VAR19 ,VAR4 ,VAR20 ,VAR18 ,VAR14 ,
VAR2 ,VAR3 ,VAR7 ,clk ,VAR1 ,VAR16 ,
VAR5 ,VAR13 );
output VAR4 ;
output VAR20 ;
output VAR18 ;
output VAR3 ;
output VAR7 ;
output VAR16 ;
output VAR13 ;
input VAR19 ;
input VAR14 ;
input VAR2 ;
input clk ;
input VAR1 ;
input VAR5 ;
wire VAR6 ;
wire VAR15 ;
VAR8 VAR9 (
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcin/sky130_fd_sc_hs__fahcin.pp.blackbox.v | 1,289 | module MODULE1 (
VAR2,
VAR4 ,
VAR3 ,
VAR6 ,
VAR7 ,
VAR1,
VAR5
);
output VAR2;
output VAR4 ;
input VAR3 ;
input VAR6 ;
input VAR7 ;
input VAR1;
input VAR5;
endmodule | apache-2.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/edge_detector.v | 1,281 | module MODULE1(
clk,
VAR3,
in, out, VAR1 );
input clk;
input VAR3;
input in;
input VAR1;
output reg out;
reg VAR4;
always @(posedge clk or negedge VAR3) begin
if (~VAR3)
begin
out <= #VAR2 1'b0;
VAR4 <= #VAR2 1'b0;
end
else
begin
VAR4 <= #VAR2 in;
if (VAR1 == VAR5)
begin
if (VAR4 == 0 && in == 1)
out <= #VAR2 1'b1;
end... | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/axis_eth_fcs_insert_64.v | 22,421 | module MODULE1 #
(
parameter VAR89 = 0,
parameter VAR38 = 64
)
(
input wire clk,
input wire rst,
input wire [63:0] VAR39,
input wire [7:0] VAR42,
input wire VAR29,
output wire VAR1,
input wire VAR10,
input wire VAR57,
output wire [63:0] VAR70,
output wire [7:0] VAR35,
output wire VAR91,
input wire VAR7,
output wire VAR... | mit |
ychaim/FPGA-Litecoin-Miner | experimental/CM1/hashvoodoo.v | 11,641 | module MODULE1 (
VAR138,
VAR116,
VAR134,
VAR31,
VAR89,
VAR148,
VAR44,
VAR124,
VAR137,
VAR100
);
function integer VAR146; input integer VAR55;
begin
VAR55 = VAR55-1;
for (VAR146=0; VAR55>0; VAR146=VAR146+1)
VAR55 = VAR55>>1;
end
endfunction
parameter VAR26 = 25000000; parameter VAR102 = 10; parameter VAR139 = 70; parame... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i_2.v | 2,214 | module MODULE2 (
VAR3 ,
VAR10 ,
VAR8 ,
VAR1 ,
VAR2,
VAR6,
VAR9 ,
VAR7
);
output VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR1 ;
input VAR2;
input VAR6;
input VAR9 ;
input VAR7 ;
VAR4 VAR5 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
bigeagle/riffa | fpga/altera/de4/riffa_wrapper_de4.v | 36,280 | module MODULE1
parameter VAR343 = 128,
parameter VAR223 = 256,
parameter VAR10 = 5
)
(
input [VAR343-1:0] VAR19,
input [0:0] VAR266,
input [0:0] VAR187,
input [0:0] VAR172,
output VAR337,
input [0:0] VAR316,
output [VAR343-1:0] VAR180,
output [0:0] VAR252,
input VAR14,
output [0:0] VAR338,
output [0:0] VAR2,
output [0:... | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nvme/nvme_host_ctrl_8lane-1.0.0/pcie_cntl_rx_fifo.v | 6,094 | module MODULE1 # (
parameter VAR34 = 128,
parameter VAR24 = 5
)
(
input clk,
input VAR26,
input VAR3,
input [VAR34-1:0] VAR53,
output VAR51,
output VAR16,
input VAR20,
output [VAR34-1:0] VAR21,
output VAR15
);
localparam VAR9 = 0;
reg [VAR24:0] VAR35;
reg [VAR24:0] VAR41;
wire [VAR24-1:0] VAR29;
reg [VAR24:0] VAR46;
re... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/common/ad_dds.v | 4,902 | module MODULE1 #(
parameter VAR3 = 0,
parameter VAR17 = 16,
parameter VAR12 = 16,
parameter VAR7 = 1,
parameter VAR23 = 16,
parameter VAR25 = 16,
parameter VAR31 = 1) (
input clk,
input VAR27,
input VAR1,
input VAR9,
input [ 15:0] VAR16,
input [ 15:0] VAR15,
input [ 15:0] VAR24,
input [ 15:0] VAR11,
input [ VAR12-1:0] ... | mit |
secworks/sha256 | src/rtl/sha256_k_constants.v | 4,885 | module MODULE1(
input wire [5 : 0] VAR4,
output wire [31 : 0] VAR2
);
reg [31 : 0] VAR3;
assign VAR2 = VAR3;
always @*
begin : VAR1
case(VAR4)
00: VAR3 = 32'h428a2f98;
01: VAR3 = 32'h71374491;
02: VAR3 = 32'hb5c0fbcf;
03: VAR3 = 32'he9b5dba5;
04: VAR3 = 32'h3956c25b;
05: VAR3 = 32'h59f111f1;
06: VAR3 = 32'h923f82a4;
07... | bsd-2-clause |
romovs/xula-lib-verilog | camera/RGB565Receive.v | 2,408 | module MODULE1 (VAR6, VAR4, VAR2, VAR7, VAR8, VAR1, VAR5);
input [7:0] VAR6; input VAR4; input VAR2; input VAR7; input VAR8; output reg VAR1; output reg [15:0] VAR5;
reg VAR3 = 0;
reg VAR9 = 0;
always @(posedge VAR7) begin
VAR1 <= 0;
if (VAR8 == 0) begin
VAR3 <= 0;
VAR9 <= 0;
end else begin
if (VAR9 == 1 && VAR4 == 0 &... | gpl-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_ob_adv7180.v | 9,832 | module MODULE1 (
VAR18,
VAR21
);
parameter VAR2 = 16'h0000;
parameter VAR45 = 16'h01C8;
parameter VAR49 = 16'h030C;
parameter VAR43 = 16'h0445;
parameter VAR14 = 16'h077F;
parameter VAR50 = 16'h0A00;
parameter VAR22 = 16'h0B00;
parameter VAR9 = 16'h0C36;
parameter VAR13 = 16'h0D7C;
parameter VAR3 = 16'h0F00;
parameter ... | mit |
silverneko/dsdl | lab2/TopLevel.v | 1,960 | module MODULE1(clk,
VAR20,
VAR9,
VAR13,
VAR10,
VAR7,
VAR2,
VAR1,
VAR11,
VAR15,
VAR18,
VAR17
);
input [3:0] VAR20;
input clk; input VAR9; input [15:0] VAR13; input VAR10; output [63:0] VAR7;
wire [63:0] VAR19;
assign VAR7 = ~VAR19;
output VAR2, VAR1, VAR11, VAR15, VAR18;
output [7:0] VAR17;
assign VAR2 = 1;
assign VAR1 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp.functional.v | 2,073 | module MODULE1 (
VAR16 ,
VAR10 ,
VAR18 ,
VAR14 ,
VAR8 ,
VAR1 ,
VAR6
);
output VAR16 ;
output VAR10 ;
input VAR18 ;
input VAR14 ;
input VAR8 ;
input VAR1 ;
input VAR6;
wire VAR7 ;
wire VAR2 ;
wire VAR3;
not VAR9 (VAR2 , VAR6 );
VAR11 VAR15 (VAR3, VAR14, VAR8, VAR1 );
VAR13 VAR5 VAR12 (VAR7 , VAR3, VAR18, VAR2);
buf VAR4... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/hrfp_align.v | 1,551 | module MODULE1
(input wire clk,
input wire [2:0] VAR3,
input wire VAR1,
output reg VAR10,
input wire [VAR8:0] VAR7, VAR2,
output reg [VAR8:0] VAR4, VAR6,
output reg [30:0] VAR9, VAR11
);
always @(posedge clk) begin
VAR10 <= VAR3[2];
case(VAR3[1:0])
0: VAR9 <= {1'b0, VAR5, 3'b0};
1: VAR9 <= {5'b0, VAR2[26:2] , |VAR2[1:0... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_reg.v | 5,097 | module MODULE1 (
VAR4,
clk, VAR28, VAR7, VAR39, VAR5, VAR34
) ;
parameter VAR2 = 3;
input clk;
input VAR28;
input [3:0] VAR7;
input VAR39;
input [3:0] VAR5;
input [VAR2 -1:0] VAR34;
output [VAR2-1:0] VAR4;
wire [VAR2-1:0] VAR14;
wire [VAR2-1:0] VAR21;
wire [VAR2-1:0] VAR11;
wire [VAR2-1:0] VAR41;
wire [VAR2-1:0] VAR25;... | gpl-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_rate_limit.v | 8,814 | module MODULE1 #
(
parameter VAR18 = 8,
parameter VAR16 = (VAR18>8),
parameter VAR50 = (VAR18/8),
parameter VAR32 = 1,
parameter VAR55 = 0,
parameter VAR64 = 8,
parameter VAR15 = 0,
parameter VAR25 = 8,
parameter VAR38 = 1,
parameter VAR20 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR18-1:0] VAR41,
input wire... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController/src/pcie_sq_cmd_fifo.v | 4,948 | module MODULE1 # (
parameter VAR24 = 11,
parameter VAR7 = 2
)
(
input clk,
input VAR41,
input VAR11,
input [VAR24-1:0] VAR1,
output VAR42,
input VAR45,
output [VAR24-1:0] VAR25,
output VAR5
);
localparam VAR8 = 0;
reg [VAR7:0] VAR19;
reg [VAR7:0] VAR4;
wire [VAR7-1:0] VAR9;
reg [VAR7:0] VAR6;
assign VAR42 = ~((VAR6[VAR... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/Debounce_A.v | 1,408 | module MODULE1
(
VAR3,
reset,
VAR10,
VAR4,
VAR8
);
input VAR3;
input reset;
input VAR10;
input VAR4;
output VAR8;
wire [7:0] VAR11; wire VAR2;
assign VAR11 = 8'd25;
VAR6 VAR5 (.VAR3(VAR3),
.reset(reset),
.VAR10(VAR10),
.VAR1(VAR4),
.VAR7(VAR11), .VAR9(VAR2)
);
assign VAR8 = VAR2;
endmodule | gpl-3.0 |
chebykinn/university | io/lab3/v-src/Prescaler.v | 1,193 | module MODULE1(VAR3,VAR1,VAR8,VAR6,VAR2);
output VAR3;
input VAR1;
input [2:0] VAR8;
input VAR6;
input VAR2;
reg VAR3;
reg VAR9;
reg [4:0] VAR5;
reg [4:0] VAR4;
reg [4:0] VAR7;
always @(VAR8 )
begin
case(VAR8 )
'h1, 'h2, 'h3 :
begin
VAR5 =('h1);
end
'h4, 'h6 :
begin
VAR5 =('h4);
end
'h5, 'h7 :
begin
VAR5 =('h10);
end
d... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.pp.blackbox.v | 1,345 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR3,
VAR5,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR6 ;
input VAR3;
input VAR5;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
sundw2014/carADS | fpga_firmware/show_num.v | 1,384 | module MODULE1(VAR1,clk,VAR9,sel,VAR6);
input[27:0]VAR1;
input clk,VAR6;
output reg[6:0]VAR9;
output reg[3:0]sel;
wire[6:0]VAR5,VAR4,VAR3,VAR8;
reg [6:0]VAR2;
reg[1:0]VAR7;
always @(posedge clk or negedge VAR6)
begin
if(!VAR6)begin VAR7<=0;end
else begin
if(VAR7==2'd3)begin VAR7<=0; end
else begin VAR7<=VAR7+1;end
end
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111ai/sky130_fd_sc_hs__o2111ai.behavioral.v | 1,980 | module MODULE1 (
VAR14 ,
VAR8 ,
VAR2 ,
VAR3 ,
VAR1 ,
VAR16 ,
VAR4,
VAR6
);
output VAR14 ;
input VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR1 ;
input VAR16 ;
input VAR4;
input VAR6;
wire VAR1 VAR15 ;
wire VAR5 ;
wire VAR13;
or VAR9 (VAR15 , VAR2, VAR8 );
nand VAR7 (VAR5 , VAR1, VAR3, VAR16, VAR15 );
VAR12 VAR11 (VAR13, V... | apache-2.0 |
nliu96/openHMC_Altera | src/openhmc_sync_fifo_reg_stage.v | 4,462 | module MODULE1 #(parameter VAR9 = 8)(
input wire clk,
input wire VAR2,
input wire [VAR9-1:0] din,
input wire [VAR9-1:0] VAR8,
input wire VAR4, input wire VAR7, input wire VAR1,
input wire VAR5,
output reg VAR3, output reg [VAR9-1:0] dout
);
wire en, VAR6;
assign en = (VAR1 & VAR5 & VAR3) | (VAR1 & ~VAR5 & ~VAR3 && VAR7... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv.functional.pp.v | 1,774 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR3,
VAR10,
VAR12 ,
VAR8
);
output VAR1 ;
input VAR9 ;
input VAR3;
input VAR10;
input VAR12 ;
input VAR8 ;
wire VAR6 ;
wire VAR5;
not VAR11 (VAR6 , VAR9 );
VAR4 VAR7 (VAR5, VAR6, VAR3, VAR10);
buf VAR2 (VAR1 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ba/sky130_fd_sc_hd__o21ba_2.v | 2,316 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR4 ,
VAR6,
VAR1,
VAR5,
VAR8 ,
VAR7
);
output VAR9 ;
input VAR2 ;
input VAR4 ;
input VAR6;
input VAR1;
input VAR5;
input VAR8 ;
input VAR7 ;
VAR3 VAR10 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
V... | apache-2.0 |
zhijian-liu/mips-cpu | src/cpu/stage/stage_mem.v | 14,179 | module MODULE1(
input reset ,
input [31:0] VAR19 ,
input [ 7:0] VAR27 ,
input [31:0] VAR18 ,
input [31:0] VAR25 ,
output reg VAR22 ,
output reg [31:0] VAR16 ,
input [31:0] VAR20 ,
output reg VAR24 ,
output reg [31:0] VAR29 ,
output reg [3:0] VAR5 ,
output reg [31:0] VAR28 ,
input VAR30 ,
output reg VAR13 ,
input [ 4:0]... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Convert_Data_Type1.v | 1,122 | module MODULE1
(
VAR3,
VAR2
);
input signed [35:0] VAR3; output signed [17:0] VAR2;
wire signed [17:0] VAR1;
assign VAR1 = VAR3[35:18];
assign VAR2 = VAR1;
endmodule | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_async_edgelogic.v | 1,667 | module MODULE1(
VAR2,
VAR1
);
input VAR1;
output VAR2;
wire VAR3 = VAR1;
assign VAR2 = VAR3;
endmodule | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/wb_bridge_16_32.v | 1,749 | module MODULE1
(input VAR4, input VAR13,
input VAR8, input VAR5, input VAR2, input [3:0] VAR9,
input [VAR10-1:0] VAR15, input [31:0] VAR6, output [31:0] VAR11, output VAR17,
output VAR21, output VAR1, output VAR14, output [1:0] VAR16,
output [VAR10-1:0] VAR12, output [15:0] VAR19, input [15:0] VAR20, input VAR7
);
reg ... | gpl-2.0 |
firemark/katp91 | src/board.v | 2,532 | module MODULE1(VAR19, VAR31, VAR6, VAR1, VAR7, VAR23, VAR3, VAR12);
input VAR19 ;
reg reset;
VAR11 reset = 1;
output [5:0] VAR31;
output VAR3, VAR12;
input [4:0] VAR7;
wire VAR2;
wire [15:0] VAR32;
wire [15:0] VAR30;
wire [7:0] VAR4;
wire clk;
wire write, read;
wire VAR20; assign VAR20 = read && VAR30[15:12] == 4'hB;
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4b/sky130_fd_sc_hs__nor4b.symbol.v | 1,287 | module MODULE1 (
input VAR5 ,
input VAR4 ,
input VAR2 ,
input VAR1,
output VAR7
);
supply1 VAR3;
supply0 VAR6;
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/ram_wb/ram_wb_b3.v | 6,219 | module MODULE1
parameter VAR13 = 32,
parameter VAR16 = "",
parameter VAR31 = 32'h00005000, parameter VAR39 = 15) (input VAR33,
input VAR5,
input [VAR13-1:0] VAR14,
input [VAR41-1:0] VAR19,
input [3:0] VAR1,
input VAR35,
input [1:0] VAR34,
input [2:0] VAR11,
input VAR10,
input VAR27,
output VAR32,
output VAR29,
output V... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/DE4_SOPC_burst_1.v | 15,487 | module MODULE1 (
clk,
VAR23,
VAR4,
VAR33,
VAR35,
VAR51,
VAR6,
VAR61,
VAR66,
VAR34,
VAR57,
VAR5,
VAR56,
VAR39,
VAR41,
VAR9,
VAR26,
VAR14,
VAR12,
VAR46,
VAR53,
VAR29,
VAR31,
VAR32,
VAR36
)
;
output [ 28: 0] VAR39;
output [ 10: 0] VAR41;
output VAR9;
output [ 3: 0] VAR26;
output VAR14;
output [ 28: 0] VAR12;
output VAR46;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4.functional.pp.v | 1,828 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR11,
VAR2,
VAR7 ,
VAR9
);
output VAR10 ;
input VAR8 ;
input VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR11;
input VAR2;
input VAR7 ;
input VAR9 ;
wire VAR4 ;
wire VAR12;
or VAR13 (VAR4 , VAR3, VAR1, VAR6, VAR8 );
VAR15 VAR14 (VAR12, VAR4, VAR11, VAR2);
buf VAR5 (VAR1... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/default/prcfg_dac.v | 3,509 | module MODULE1(
clk,
VAR6,
VAR1,
VAR7,
VAR5,
VAR8,
VAR9,
VAR4,
VAR3,
VAR11,
VAR2
);
localparam VAR12 = 8'hA0;
parameter VAR10 = 0;
input clk;
input [31:0] VAR6;
output [31:0] VAR1;
output VAR7;
input [31:0] VAR5;
input VAR8;
input VAR9;
input VAR4;
output [31:0] VAR3;
output VAR11;
output VAR2;
reg VAR7;
reg [31:0] VAR... | gpl-3.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_sub.v | 130,366 | module MODULE1
(
VAR2,
VAR4,
VAR5,
VAR3,
VAR1,
VAR9) ;
input VAR2;
input VAR4;
input VAR5;
input [25:0] VAR3;
input [4:0] VAR1;
output [25:0] VAR9;
tri0 VAR2;
tri1 VAR4;
tri0 VAR5;
reg [0:0] VAR14;
reg [25:0] VAR12;
wire [5:0] VAR7;
wire VAR8;
wire [15:0] VAR11;
wire [155:0] VAR6;
wire [4:0] VAR10;
wire [129:0] VAR13; | mit |
stevenokm/mor1kx | rtl/verilog/mor1kx_fetch_cappuccino.v | 20,627 | module MODULE1
parameter VAR72 = 32,
parameter VAR54 = {{(VAR72-13){1'b0}},
parameter VAR18 = 5,
parameter VAR82 = "VAR35",
parameter VAR21 = 5,
parameter VAR112 = 9,
parameter VAR49 = 2,
parameter VAR78 = 32,
parameter VAR50 = "VAR35",
parameter VAR70 = "VAR35",
parameter VAR109 = 6,
parameter VAR9 = 1
)
(
input clk,
... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill_1.v | 1,840 | module MODULE2 (
VAR6,
VAR5,
VAR1 ,
VAR3
);
input VAR6;
input VAR5;
input VAR1 ;
input VAR3 ;
VAR2 VAR4 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR6;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR3 ;
VAR2 VAR4 ();
endmodule | apache-2.0 |
lvd2/ngs | fpga/obsolete/fpgaE_dma/dma/dma_access.v | 6,712 | module MODULE1(
input clk,
input VAR5,
input VAR7, input [20:0] VAR24, input VAR19, input [7:0] VAR16, output reg [7:0] VAR25,
output reg VAR13, output reg VAR15, output reg VAR12,
output wire VAR22, output wire [20:0] VAR1, output wire [7:0] VAR20, input [7:0] VAR31, output wire VAR9, output reg VAR14, output reg VAR2... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/d_BCH_SC_X.v | 7,698 | module MODULE1
(
parameter VAR14 = 2,
parameter VAR16 = 12
)
(
VAR34,
VAR47,
VAR41,
VAR39,
VAR22,
VAR4,
VAR37,
VAR48,
VAR9,
VAR33,
VAR23,
VAR42,
VAR2,
VAR12,
VAR20,
VAR44,
VAR25,
VAR5,
VAR3,
VAR51,
VAR11,
VAR19,
VAR40,
VAR7,
VAR26,
VAR38,
VAR28,
VAR31,
VAR18,
VAR15,
VAR13,
VAR49,
VAR30,
VAR10,
VAR43,
VAR8,
VAR17,
VAR21... | gpl-3.0 |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/cordic_jorge/Mux_3x1_b_v2.v | 1,033 | module MODULE1 #(parameter VAR5=32)
(
input wire [1:0] select,
input wire [VAR5-1:0] VAR1,
input wire [VAR5-1:0] VAR4,
input wire [VAR5-1:0] VAR3,
output reg [VAR5-1:0] VAR2
);
always @*
begin
case(select)
2'b00: VAR2 <= {VAR5{1'b0}};
2'b01: VAR2 <= VAR1;
2'b10: VAR2 <= VAR4;
2'b11: VAR2 <= VAR3;
default : VAR2 <= VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2i/sky130_fd_sc_ls__mux2i.symbol.v | 1,344 | module MODULE1 (
input VAR7,
input VAR4,
output VAR2 ,
input VAR5
);
supply1 VAR1;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Anirudh94/Connect4-FPGA | Connect4/player2_bb.v | 4,904 | module MODULE1 (
address,
VAR2,
VAR1);
input [10:0] address;
input VAR2;
output [2:0] VAR1;
tri1 VAR2;
endmodule | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9649_v1_00_a/hdl/verilog/user_logic.v | 7,322 | module MODULE1 (
VAR3,
VAR27,
VAR1,
VAR37,
VAR18,
VAR35,
VAR28,
VAR11,
VAR41,
VAR15,
VAR24,
VAR5,
VAR43,
VAR31,
VAR7,
VAR34,
VAR25,
VAR8,
VAR23,
VAR21,
VAR16,
VAR42,
VAR38,
VAR39,
VAR10,
VAR13,
VAR30);
parameter VAR20 = 32;
parameter VAR17 = 32;
parameter VAR12 = 0;
input VAR3;
input [13:0] VAR27;
input VAR1;
input VAR... | mit |
AngelTerrones/ADA | rtl/ada_exu_div.v | 4,283 | module MODULE1(
input clk, input rst, input VAR5, input VAR9, input [31:0] VAR13, input [31:0] VAR1, output [31:0] VAR11, output [31:0] VAR6, output VAR10 );
reg VAR8; reg VAR4; reg [4:0] VAR12;
reg [31:0] VAR7; reg [31:0] VAR3; reg [31:0] VAR14;
wire [32:0] VAR2;
assign VAR11 = !VAR4 ? VAR7 : -VAR7;
assign VAR6 = VAR1... | mit |
alan4186/Hardware-CNN | Hardware/v/window_ctrl.v | 2,034 | module MODULE1 (
input VAR11,
input reset,
input [VAR3:0] VAR12,
input [VAR7:0] VAR5,
input [VAR3:0] VAR9, input [VAR7:0] VAR10,
output reg VAR1,
output reg VAR4,
output reg VAR13
);
always@(posedge VAR11 or negedge reset) begin
if(reset == 1'b0) begin
VAR4 <= 1'd0;
end else if( VAR9 >= VAR12 &&
VAR9 < VAR12 + VAR2'VAR... | mit |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/start_for_Loop_lojbC.v | 3,003 | module MODULE1 (
clk,
VAR6,
VAR26,
VAR21,
VAR15);
parameter VAR14 = 32'd1;
parameter VAR23 = 32'd2;
parameter VAR7 = 32'd4;
input clk;
input [VAR14-1:0] VAR6;
input VAR26;
input [VAR23-1:0] VAR21;
output [VAR14-1:0] VAR15;
reg[VAR14-1:0] VAR4 [0:VAR7-1];
integer VAR2;
always @ (posedge clk)
begin
if (VAR26)
begin
for (... | mit |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/cpu_0_jtag_debug_module_wrapper.v | 9,785 | module MODULE1 (
VAR18,
VAR12,
clk,
VAR56,
VAR3,
VAR27,
VAR13,
VAR37,
VAR50,
VAR43,
VAR15,
VAR47,
VAR20,
VAR4,
VAR1,
VAR55,
VAR25,
VAR39,
VAR10,
VAR41,
VAR57,
VAR52,
VAR35,
VAR40,
VAR6,
VAR26,
VAR16,
VAR17,
VAR5,
VAR2,
VAR14,
VAR28,
VAR29,
VAR48,
VAR36,
VAR32
)
;
output [ 37: 0] VAR57;
output VAR52;
output VAR35;
outpu... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_ecc_decoder_32_syn.v | 31,892 | module MODULE1
(
VAR83,
VAR135) ;
input [5:0] VAR83;
output [63:0] VAR135;
tri0 [5:0] VAR83;
wire [5:0] VAR8;
wire [63:0] VAR66;
wire [63:0] VAR24;
wire [3:0] VAR133;
wire [3:0] VAR140;
wire [3:0] VAR86;
wire [3:0] VAR72;
wire [3:0] VAR18;
wire [3:0] VAR73;
wire [3:0] VAR2;
wire [3:0] VAR21;
wire [3:0] VAR64;
wire [3:0... | gpl-3.0 |
ehab93/MIPS-Processor | lib/mux32bits_32to1.v | 16,159 | module MODULE1 (
input [4:0 ] VAR9,
input [31:0] VAR22, VAR59, VAR30, VAR57, VAR39, VAR19, VAR53, VAR34, VAR26,VAR14, VAR60, VAR2, VAR55, VAR31, VAR44, VAR6,
input [31:0] VAR15, VAR24, VAR41, VAR8, VAR50, VAR65, VAR56, VAR16, VAR45,VAR32, VAR66, VAR12, VAR10, VAR7, VAR51, VAR17,
output [31:0] VAR52);
VAR54 VAR64 (.VAR5... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nvme/nvme_host_ctrl_4lane-1.0.0/pcie_dma_cmd_fifo.v | 4,948 | module MODULE1 # (
parameter VAR8 = 34,
parameter VAR12 = 5
)
(
input clk,
input VAR38,
input VAR28,
input [VAR8-1:0] VAR23,
output VAR40,
input VAR9,
output [VAR8-1:0] VAR4,
output VAR17
);
localparam VAR36 = 2;
reg [VAR12:0] VAR16;
reg [VAR12:0] VAR43;
wire [VAR12-1:0] VAR31;
reg [VAR12:0] VAR26;
assign VAR40 = ~((VA... | gpl-3.0 |
titorgalaxy/Titor | rtl/verilog/util/Negedge.v | 1,217 | module MODULE1(
VAR3,
VAR1,
reset,
clk
);
input VAR3;
output VAR1;
reg VAR2;
input reset;
input clk;
always @(posedge clk) begin
VAR2 <= VAR3;
end
assign VAR1 = ((VAR2) && (!VAR3));
endmodule | gpl-3.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_serialize.v | 3,060 | module MODULE1 #(
parameter VAR25 = 26
) (
input VAR32,
input VAR15,
output reg VAR6,
input VAR11,
output reg VAR2,
input [VAR25-5-1:0] VAR19,
input [VAR25-5-1:0] VAR13,
input [VAR25-5-1:0] VAR31,
input [VAR25-5-1:0] VAR27,
input VAR30,
input VAR22,
input VAR26,
input VAR3,
output reg VAR33,
input VAR29,
output reg [VA... | lgpl-3.0 |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/coregen/ram_8x512_hi.v | 3,951 | module MODULE1(
addr,
clk,
din,
dout,
en,
VAR23);
input [8 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input VAR23;
VAR2 #(
.VAR37(9),
.VAR29("0"),
.VAR44(512),
.VAR4(0),
.VAR27(1),
.VAR35(1),
.VAR34(1),
.VAR28(0),
.VAR26(0),
.VAR41(0),
.VAR39(0),
.VAR8(0),
.VAR31(1),
.VAR36(18),
.VAR6("VAR2... | bsd-3-clause |
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