repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_2.behavioral.v | 1,170 | module MODULE1( VAR4, VAR5, VAR3 );
input VAR4, VAR5;
output VAR3;
VAR2 VAR6(.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3));
VAR2 VAR1(.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
sorgelig/Apogee_MIST | k580vt57.v | 3,991 | module MODULE1
(
input clk,
input VAR18,
input reset,
input [3:0] VAR4,
input [7:0] VAR29,
input [3:0] VAR5,
input VAR26,
input VAR15,
input VAR8,
output VAR9,
output [3:0] VAR20,
output [7:0] VAR34,
output [15:0] VAR3,
output VAR30,
output VAR17,
output VAR33,
output VAR2
);
parameter VAR11 = 0;
parameter VAR6 = 1;
pa... | bsd-2-clause |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/sqrt_stub.v | 1,429 | module MODULE1(VAR1, VAR3,
VAR5, VAR2, VAR4)
;
input VAR1;
input VAR3;
input [15:0]VAR5;
output VAR2;
output [15:0]VAR4;
endmodule | mit |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_scaler_shrink.v | 7,628 | module MODULE1 (
clk,
reset,
VAR5,
VAR6,
VAR13,
VAR12,
VAR2,
VAR19,
VAR25,
VAR15,
VAR14,
VAR27
);
parameter VAR24 = 15; parameter VAR11 = 9; parameter VAR17 = 9;
parameter VAR22 = 640;
parameter VAR21 = 4'b0101;
parameter VAR26 = 4'b0000;
input clk;
input reset;
input [VAR24: 0] VAR5;
input VAR6;
input VAR13;
input VAR... | gpl-3.0 |
ehab93/MIPS-Processor | lib/mux_16to1.v | 1,725 | module MODULE1 (
input [3:0] VAR3,
input VAR23, VAR19, VAR15, VAR35, VAR31, VAR1, VAR6, VAR5, VAR36,VAR22, VAR33, VAR20, VAR37, VAR25, VAR21, VAR14,
output VAR8);
wire VAR27 , VAR7 , VAR29 , VAR38 , VAR26 , VAR34 , VAR32 , VAR24;
wire VAR9 , VAR17 , VAR28, VAR4, VAR18, VAR12, VAR2, VAR30;
not (VAR16, VAR3[0]);
not (VAR... | mit |
walkthetalk/fsref | ip/axis_scaler/src/include/scaler_spliter.v | 7,493 | module MODULE1 # (
parameter integer VAR47 = 12,
parameter integer VAR39 = 12,
parameter integer VAR51 = 0 ,
parameter integer VAR23 = 0 ,
parameter integer VAR55 = 0 , parameter integer VAR6 = 2,
parameter integer VAR33 = 0
) (
input wire clk,
input wire VAR49,
input [VAR39-1:0] VAR24,
input wire enable,
input wire VA... | gpl-3.0 |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC/clckctrl/synthesis/submodules/clckctrl_altclkctrl_0.v | 4,250 | module MODULE1
(
VAR20,
VAR14,
VAR16) ;
input VAR20;
input [3:0] VAR14;
output VAR16;
tri1 VAR20;
tri0 [3:0] VAR14;
wire VAR3;
wire [1:0] VAR6;
wire [1:0] VAR8;
wire [3:0] VAR2;
VAR10 VAR9
(
.VAR6(VAR8),
.VAR20(VAR20),
.VAR14(VAR2),
.VAR16(VAR3)
,
.VAR13(1'b1),
.VAR1(1'b1)
);
VAR9.VAR12 = "VAR5 VAR7",
VAR9.VAR21 = "VA... | bsd-3-clause |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cpu/apu/apu_div.v | 2,988 | module MODULE1
parameter VAR8 = 16
)
(
input VAR6, input VAR9, input VAR1, input VAR5, input [VAR8-1:0] VAR2, output VAR3 );
reg [VAR8-1:0] VAR7;
wire [VAR8-1:0] VAR4;
always @(posedge VAR6)
begin
if (VAR9)
VAR7 <= 0;
end
else
VAR7 <= VAR4;
end
assign VAR4 = (VAR5 || (VAR1 && (VAR7 == 0))) ? VAR2 :
(VAR1) ? VAR7 - 1'h1... | mit |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_drp_cntrl.v | 6,269 | module MODULE1 (
VAR8,
VAR17,
VAR25,
VAR29,
VAR5,
VAR13,
VAR24,
VAR28,
VAR11,
VAR26,
VAR3,
VAR20,
VAR15,
VAR1,
VAR7,
VAR30,
VAR19,
VAR4);
input VAR8;
input VAR17;
output VAR25;
output VAR29;
output [11:0] VAR5;
output [15:0] VAR13;
input [15:0] VAR24;
input VAR28;
input VAR11;
input VAR26;
input VAR3;
input VAR20;
inpu... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi.blackbox.v | 1,403 | module MODULE1 (
VAR9 ,
VAR5,
VAR10,
VAR8,
VAR6,
VAR4
);
output VAR9 ;
input VAR5;
input VAR10;
input VAR8;
input VAR6;
input VAR4;
supply1 VAR1;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp.behavioral.pp.v | 2,517 | module MODULE1 (
VAR17 ,
VAR9 ,
VAR22 ,
VAR8 ,
VAR13 ,
VAR2 ,
VAR1,
VAR21
);
output VAR17 ;
input VAR9 ;
input VAR22 ;
input VAR8 ;
input VAR13 ;
input VAR2 ;
input VAR1;
input VAR21;
wire VAR23 ;
reg VAR18 ;
wire VAR27 ;
wire VAR19 ;
wire VAR4;
wire VAR11;
wire VAR14;
wire VAR3 ;
wire VAR15 ;
wire VAR20 ;
wire VAR26 ;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_1.behavioral.v | 1,620 | module MODULE1( VAR2, VAR5, VAR3, VAR1 );
input VAR1, VAR5, VAR3;
output VAR2;
VAR4 VAR6(.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3),.VAR1(VAR1));
VAR4 VAR7(.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill_8.v | 1,840 | module MODULE1 (
VAR4,
VAR5,
VAR6 ,
VAR3
);
input VAR4;
input VAR5;
input VAR6 ;
input VAR3 ;
VAR1 VAR2 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 ();
supply1 VAR4;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
VAR1 VAR2 ();
endmodule | apache-2.0 |
oblivioncth/DE0-Verilog-Processor | src/ALU_Cell_1bit.v | 2,728 | module MODULE1(
VAR33,
VAR35,
VAR18,
VAR17,
VAR30,
VAR5,
VAR31
);
input wire VAR33;
input wire VAR35;
input wire VAR18;
input wire VAR17;
input wire [4:0] VAR30;
output wire VAR5;
output wire VAR31;
wire [1:0] VAR12;
wire VAR16;
wire VAR26;
wire VAR28;
wire VAR8;
wire VAR27;
wire VAR1;
wire VAR25;
wire VAR34;
wire VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp_1.v | 2,631 | module MODULE2 (
VAR1 ,
VAR13 ,
VAR3 ,
VAR6 ,
VAR11 ,
VAR10 ,
VAR7,
VAR2 ,
VAR12 ,
VAR5 ,
VAR4
);
output VAR1 ;
output VAR13 ;
input VAR3 ;
input VAR6 ;
input VAR11 ;
input VAR10 ;
input VAR7;
input VAR2 ;
input VAR12 ;
input VAR5 ;
input VAR4 ;
VAR9 VAR8 (
.VAR1(VAR1),
.VAR13(VAR13),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR11(V... | apache-2.0 |
jairov4/puj-ca-de1-audio-pump | ip/i2c_opencores/i2c_master_bit_ctrl.v | 17,277 | module MODULE1(
clk, rst, VAR43,
VAR27, VAR8, VAR15, VAR31, VAR41, VAR28, din, dout,
VAR13, VAR35, VAR18, VAR9, VAR37, VAR14
);
input clk;
input rst;
input VAR43;
input VAR8;
input [15:0] VAR27;
input [3:0] VAR15;
output VAR31; reg VAR31;
output VAR41; reg VAR41;
output VAR28; reg VAR28;
input din;
output dout;
reg dou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2b/sky130_fd_sc_hd__nor2b.behavioral.v | 1,489 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR10
);
output VAR4 ;
input VAR5 ;
input VAR10;
supply1 VAR11;
supply0 VAR12;
supply1 VAR9 ;
supply0 VAR7 ;
wire VAR6 ;
wire VAR8;
not VAR2 (VAR6 , VAR5 );
and VAR1 (VAR8, VAR6, VAR10 );
buf VAR3 (VAR4 , VAR8 );
endmodule | apache-2.0 |
jhoward321/pacman | usb_system/synthesis/submodules/usb_system_mm_interconnect_1.v | 16,612 | module MODULE1 (
input wire VAR8, input wire VAR94, input wire [21:0] VAR63, output wire VAR77, input wire [0:0] VAR70, input wire [3:0] VAR73, input wire VAR97, output wire [31:0] VAR10, output wire VAR18, input wire VAR59, input wire [31:0] VAR14, input wire VAR17, output wire [1:0] VAR96, output wire VAR29, output w... | mit |
FAST-Switch/fast | projects/SDTS/example/hw-src/sfp/triple_speed_ethernet-library/altera_tse_pcs_pma_gige.v | 12,499 | module MODULE1 (
address,
clk,
VAR101,
VAR2,
VAR58,
VAR96,
VAR126,
VAR117,
VAR23,
VAR19,
read,
VAR5,
VAR105,
VAR111,
reset,
VAR21,
VAR68,
VAR7,
write,
VAR37,
VAR98,
VAR31,
VAR54,
VAR13,
VAR121,
VAR71,
VAR45,
VAR46,
VAR42,
VAR51,
VAR33,
VAR72,
VAR20,
VAR113,
VAR6,
VAR17,
VAR88,
VAR57,
VAR10,
VAR15,
VAR77,
VAR74,
VAR3,
V... | apache-2.0 |
fpgasystems/Centaur | rtl/fthread/afu.v | 16,803 | module MODULE1 #(parameter VAR20 = VAR27, parameter VAR58 = 1536,
parameter VAR53 = VAR44,
parameter VAR38 = VAR44,
parameter VAR41 = 4,
parameter VAR8 = 4,
parameter VAR56 = 1,
parameter VAR4 = 1
) (
input wire clk,
input wire VAR36,
input wire VAR10,
input wire VAR34,
input wire [VAR58-1:0] VAR22,
output wire VAR9,
o... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/out_switch.v | 18,251 | module MODULE1(
input clk,
input reset,
output [239:0] VAR24,
input [63:0] VAR48,
input [23:0] VAR34,
input VAR124,
input VAR108,
output VAR21,
input [1:0] VAR71,
input VAR96,
input VAR98,
output VAR14,
input VAR127,
input [63:0] VAR85,
input [23:0] VAR89,
input VAR17,
input VAR61,
output VAR113,
input [1:0] VAR139,
in... | mit |
AlvaroNaranjo/Embedded-Systems-Design | Automatic_Pet_Feeder/src/control.v | 4,081 | module MODULE1 (
input VAR17,
input VAR30,
input [3:0] VAR2,
input [3:0] VAR41,
output [17:0] VAR23,
output [7:6] VAR28,
output [2:0] VAR19,
output [6:0] VAR8,VAR24,VAR45,VAR27,VAR13,VAR15,VAR32,VAR37,
output VAR25,
output VAR11,
output VAR39,
output VAR40,
output VAR44,
inout [7:0] VAR20,
input VAR33,
inout VAR6,
inou... | gpl-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/uart16550/raminfr.v | 6,004 | module MODULE1
(clk, VAR7, VAR9, VAR6, VAR1, VAR8);
parameter VAR4 = 4;
parameter VAR3 = 8;
parameter VAR5 = 16;
input clk;
input VAR7;
input [VAR4-1:0] VAR9;
input [VAR4-1:0] VAR6;
input [VAR3-1:0] VAR1;
output [VAR3-1:0] VAR8;
reg [VAR3-1:0] VAR2 [VAR5-1:0];
wire [VAR3-1:0] VAR8;
wire [VAR3-1:0] VAR1;
wire [VAR4-1:0]... | apache-2.0 |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | bcam_reg.v | 4,447 | module MODULE1
reg [VAR10-1:0] VAR9;
always @
for (VAR3=0; VAR3<VAR10; VAR3=VAR3+1)
VAR6[VAR3] = (VAR7[VAR3] == {1'b1,VAR11});
VAR12 VAR13 (
.clk( clk ), .rst( rst ), .VAR4( VAR6 ), .VAR5( VAR8 ), .VAR2( VAR1 ) );
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.behavioral.v | 1,405 | module MODULE1 (
VAR9,
VAR7
);
output VAR9;
input VAR7;
supply1 VAR8;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
wire VAR6;
buf VAR1 (VAR6, VAR7 );
buf VAR5 (VAR9 , VAR6 );
endmodule | apache-2.0 |
UA3MQJ/fpga-synth | modules/voice.v | 2,366 | module MODULE1(clk, VAR33, VAR6, VAR2, VAR26, VAR10, VAR43, VAR21, VAR41);
input wire clk;
input wire VAR33;
input wire [6:0] VAR6;
input wire [7:0] VAR26;
input wire [6:0] VAR10;
input wire [6:0] VAR43;
input wire [13:0] VAR2;
output wire [7:0] VAR41;
input wire [2:0] VAR21;
parameter VAR30 = 3'b000;
parameter VAR39 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_l_pp_g/sky130_fd_sc_hd__udp_pwrgood_l_pp_g.blackbox.v | 1,259 | module MODULE1 (
VAR3,
VAR1 ,
VAR2
);
output VAR3;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
jmassucco17/full_mips | processor/SingleCycleDatapath/Datapath.v | 7,697 | module MODULE1(input VAR51,
input VAR54);
wire[31:0] VAR106;
wire[31:0] VAR24;
VAR18 VAR104(
VAR51,
VAR54,
VAR106,
VAR24);
wire[31:0] VAR52;
wire[31:0] VAR110;
VAR31 VAR75(
VAR51,
VAR54,
VAR52,
VAR110);
assign VAR52 = VAR24;
wire[31:0] VAR5;
wire[31:0] VAR89;
VAR80 VAR69(VAR5,
VAR89);
assign VAR5 = VAR24;
wire[31:0] VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_2.functional.v | 1,909 | module MODULE1( VAR24, VAR21, VAR25, VAR16, VAR13, VAR2, VAR20 );
input VAR2, VAR20, VAR16, VAR13, VAR21, VAR25;
output VAR24;
wire VAR9;
not VAR3( VAR9, VAR2 );
wire VAR19;
not VAR18( VAR19, VAR20 );
wire VAR11;
and VAR7( VAR11, VAR9, VAR19 );
wire VAR10;
not VAR23( VAR10, VAR16 );
wire VAR14;
not VAR12( VAR14, VAR13 ... | apache-2.0 |
kevintownsend/R3 | coregen/fifo_32x512.v | 14,926 | module MODULE2 (
clk, VAR40, rst, VAR17, VAR121, VAR93, dout, din
);
input clk;
input VAR40;
input rst;
output VAR17;
input VAR121;
output VAR93;
output [31 : 0] dout;
input [31 : 0] din;
wire VAR61;
wire VAR11;
wire \VAR95/VAR82/VAR119.VAR31/VAR90.VAR27/VAR69/VAR72 ;
wire \VAR95/VAR82/VAR119.VAR31/VAR90.VAR27/VAR69/VA... | mit |
gbraad/minimig-de1 | bench/sram/qmem_master.v | 4,085 | module MODULE1 #(
parameter VAR3 = 32, parameter VAR7 = 32, parameter VAR11 = VAR7/8, parameter VAR9 = 10 )(
input wire clk, rst,
output reg VAR1,
output reg VAR8,
output reg [VAR11-1:0] sel,
output reg [VAR3-1:0] VAR2,
output reg [VAR7-1:0] VAR4,
input wire [VAR7-1:0] VAR6,
input wire ack,
input wire VAR5,
output reg ... | gpl-3.0 |
asicguy/gplgpu | hdl/hbi/hbi_control.v | 26,481 | module MODULE1
(
input VAR113, input VAR112, input VAR10, input VAR103, input VAR75, input VAR65, input VAR120, input VAR114, input VAR12, input VAR107, input VAR9, input VAR98, input VAR125, input VAR28, input VAR40, input VAR41, input VAR33, input VAR6,
input VAR99, input VAR62, input VAR55, input VAR95, input VAR90,... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | HW_SW.v | 6,503 | module MODULE1 (
address,
VAR34,
VAR16);
input [7:0] address;
input VAR34;
output [127:0] VAR16;
wire [127:0] VAR6;
wire [127:0] VAR16 = VAR6[127:0];
VAR2 VAR10 (
.VAR4 (VAR34),
.VAR12 (address),
.VAR53 (VAR6),
.VAR11 (1'b0),
.VAR50 (1'b0),
.VAR29 (1'b1),
.VAR19 (1'b0),
.VAR21 (1'b0),
.VAR17 (1'b1),
.VAR13 (1'b1),
.VAR... | mit |
DougFirErickson/parallella-hw | boards/archive/gen1.1/fpga/hdl/fpgacfg.v | 20,334 | module MODULE1 (
VAR51, VAR11, VAR110, VAR52,
VAR39, VAR29, VAR60,
VAR69, VAR95, VAR84,
VAR79, VAR2, VAR66, VAR18,
VAR17, VAR63, VAR54, VAR132,
VAR123, VAR96,
VAR46, VAR5, reset, VAR10, VAR70,
VAR13, VAR36, VAR45,
VAR100, VAR8, VAR16,
VAR102, VAR4, VAR101, VAR88,
VAR30, VAR7, VAR65, VAR78,
VAR38, VAR15
);
input VAR46;
... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/quadblk.v | 1,082 | module MODULE1(VAR14, sel, VAR15);
input wire [232:0] VAR14;
input wire [3:0] sel;
output reg [232:0] VAR15;
wire [232:0] d1;
wire [232:0] d2;
wire [232:0] d3;
wire [232:0] d4;
wire [232:0] d5;
wire [232:0] d6;
wire [232:0] d7;
wire [232:0] d8;
wire [232:0] d9;
wire [232:0] d10;
wire [232:0] d11;
wire [232:0] d12;
wire... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hs__udp_dff_ps_pp_pg_n.symbol.v | 1,478 | module MODULE1 (
input VAR6 ,
output VAR2 ,
input VAR4 ,
input VAR7 ,
input VAR3,
input VAR5 ,
input VAR1
);
endmodule | apache-2.0 |
jz0229/open-ephys-pcie | kc705-host-firmware/Sources/Verilog/MISO_phase_selector.v | 6,863 | module MODULE1(
input wire [3:0] VAR1, input wire [73:0] VAR3, output reg [15:0] VAR2 );
always @ begin
case (VAR1)
0: VAR2 <= {VAR3[2], VAR3[6], VAR3[10], VAR3[14], VAR3[18], VAR3[22], VAR3[26], VAR3[30], VAR3[34], VAR3[38], VAR3[42], VAR3[46], VAR3[50], VAR3[54], VAR3[58], VAR3[62]};
1: VAR2 <= {VAR3[3], VAR3[7], VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111a/sky130_fd_sc_ls__o2111a.functional.v | 1,492 | module MODULE1 (
VAR10 ,
VAR5,
VAR4,
VAR2,
VAR7,
VAR9
);
output VAR10 ;
input VAR5;
input VAR4;
input VAR2;
input VAR7;
input VAR9;
wire VAR1 ;
wire VAR6;
or VAR11 (VAR1 , VAR4, VAR5 );
and VAR8 (VAR6, VAR2, VAR7, VAR1, VAR9);
buf VAR3 (VAR10 , VAR6 );
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/slaveController/fifoMux.v | 6,363 | module MODULE1 (
VAR22,
VAR18,
VAR12,
VAR16,
VAR3,
VAR23,
VAR26,
VAR4,
VAR24,
VAR14,
VAR8,
VAR10,
VAR13,
VAR25,
VAR1,
VAR6,
VAR5,
VAR2,
VAR20,
VAR21,
VAR9,
VAR19,
VAR11,
VAR7,
VAR15,
VAR17
);
input [3:0] VAR22;
input VAR18;
output VAR12;
output VAR16;
output VAR3;
output VAR23;
output [7:0] VAR26;
input [7:0] VAR4;
inp... | gpl-3.0 |
HSID/Sora | FPGA/MIMO/rtl/Sora_RCB.v | 61,652 | module MODULE1
parameter VAR196 = 0
)
(
output wire [(VAR326 - 1):0] VAR56,
output wire [(VAR326 - 1):0] VAR242,
input wire [(VAR326 - 1):0] VAR193,
input wire [(VAR326 - 1):0] VAR121,
input wire VAR73,
input wire VAR50,
input wire VAR170,
input VAR308,
input wire VAR32,
input wire VAR353,
input wire VAR312,
input wire... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp_2.v | 2,273 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR5 ,
VAR2,
VAR10 ,
VAR6 ,
VAR3 ,
VAR4
);
output VAR7 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR10 ;
input VAR6 ;
input VAR3 ;
input VAR4 ;
VAR1 VAR9 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo_2.v | 2,318 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR6 ,
VAR1,
VAR8,
VAR10,
VAR9 ,
VAR5
);
output VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR1;
input VAR8;
input VAR10;
input VAR9 ;
input VAR5 ;
VAR7 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE1 ... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_mac_1g_gmii.v | 6,905 | module MODULE1 #
(
parameter VAR23 = "VAR33",
parameter VAR67 = "VAR60",
parameter VAR37 = "VAR65",
parameter VAR52 = 1,
parameter VAR17 = 64
)
(
input wire VAR38,
input wire VAR22,
output wire VAR47,
output wire VAR32,
output wire VAR11,
output wire VAR16,
input wire [7:0] VAR21,
input wire VAR4,
output wire VAR46,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb.functional.v | 1,427 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR8 ,
VAR3,
VAR7
);
output VAR6 ;
input VAR9 ;
input VAR8 ;
input VAR3;
input VAR7;
wire VAR5 ;
wire VAR1;
nor VAR4 (VAR5 , VAR9, VAR8 );
and VAR2 (VAR1, VAR5, VAR3, VAR7);
buf VAR10 (VAR6 , VAR1 );
endmodule | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_RGB_to_YCrCb_converter.v | 14,692 | module MODULE1 (
clk,
VAR9,
reset,
VAR64,
VAR66,
VAR7,
VAR48,
VAR32,
VAR57,
VAR38,
VAR62,
VAR68,
VAR28,
VAR30,
VAR35,
VAR10,
VAR53
);
input clk;
input VAR9;
input reset;
input [ 7: 0] VAR64;
input [ 7: 0] VAR66;
input [ 7: 0] VAR7;
input VAR48;
input VAR32;
input VAR57;
input VAR38;
output reg [ 7: 0] VAR62;
output reg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b.symbol.v | 1,323 | module MODULE1 (
input VAR7 ,
input VAR8 ,
input VAR1 ,
input VAR9,
output VAR3
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Cognoscan/BoostDSP | verilog/src/smallFilters/SmallHpf2nd.v | 3,909 | module MODULE1 #(
parameter VAR4 = 8, parameter VAR13 = 8, parameter VAR8 = 16, parameter VAR10 = 1 )
(
input clk, input rst, input en, input signed [VAR8-1:0] VAR7, output signed [VAR8-1:0] VAR6 );
reg signed [VAR8+VAR4-1:0] VAR11;
reg signed [VAR8+VAR13-1:0] VAR9;
reg signed [VAR8-1:0] VAR12;
wire signed [VAR8-1:0] V... | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_stat_counter.v | 12,301 | module MODULE1 #
(
parameter VAR37 = 64,
parameter VAR67 = (VAR37>8),
parameter VAR60 = (VAR37/8),
parameter VAR11 = 1,
parameter VAR69 = 16,
parameter VAR24 = 1,
parameter VAR39 = 32,
parameter VAR66 = 1,
parameter VAR58 = 32,
parameter VAR46 = 1,
parameter VAR16 = 32
)
(
input wire clk,
input wire rst,
input wire [VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrbp/sky130_fd_sc_ls__dfrbp.behavioral.v | 2,313 | module MODULE1 (
VAR5 ,
VAR20 ,
VAR12 ,
VAR9 ,
VAR21
);
output VAR5 ;
output VAR20 ;
input VAR12 ;
input VAR9 ;
input VAR21;
supply1 VAR22;
supply0 VAR6;
supply1 VAR11 ;
supply0 VAR17 ;
wire VAR1 ;
wire VAR16 ;
reg VAR3 ;
wire VAR2 ;
wire VAR15;
wire VAR10 ;
wire VAR14 ;
wire VAR7 ;
wire VAR4 ;
not VAR13 (VAR16 , VAR15... | apache-2.0 |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RWire.v | 1,527 | module MODULE1(VAR5, VAR1, VAR2, VAR4);
parameter VAR3 = 1;
input [VAR3 - 1 : 0] VAR2;
input VAR4;
output [VAR3 - 1 : 0] VAR5;
output VAR1;
assign VAR5 = VAR2;
assign VAR1 = VAR4;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb.pp.blackbox.v | 1,365 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR2 ,
VAR4 ,
VAR5 ,
VAR3,
VAR6,
VAR1 ,
VAR8
);
output VAR7 ;
input VAR9 ;
input VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR3;
input VAR6;
input VAR1 ;
input VAR8 ;
endmodule | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/offset_flag_to_one_hot.v | 2,660 | module MODULE1
parameter VAR3 = 4
)
(
input [VAR2(VAR3)-1:0] VAR1,
input VAR4,
output [VAR3-1:0] VAR5
);
assign VAR5 = {{(VAR3-1){1'b0}},VAR4} << VAR1;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregsbp/sky130_fd_sc_lp__sregsbp.functional.pp.v | 2,232 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR10 ,
VAR16 ,
VAR21 ,
VAR1 ,
VAR8,
VAR22 ,
VAR13 ,
VAR20 ,
VAR12
);
output VAR9 ;
output VAR3 ;
input VAR10 ;
input VAR16 ;
input VAR21 ;
input VAR1 ;
input VAR8;
input VAR22 ;
input VAR13 ;
input VAR20 ;
input VAR12 ;
wire VAR19 ;
wire VAR11 ;
wire VAR4;
not VAR14 (VAR11 , VAR8 );
VAR1... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_007.v | 1,470 | module MODULE2 (
VAR8,
VAR7
);
input [31:0] VAR8;
output [31:0]
VAR7;
wire [31:0]
VAR12,
VAR10,
VAR1,
VAR9,
VAR13,
VAR5,
VAR6,
VAR3;
assign VAR12 = VAR8;
assign VAR3 = VAR6 << 5;
assign VAR1 = VAR10 - VAR12;
assign VAR10 = VAR12 << 5;
assign VAR9 = VAR1 << 4;
assign VAR13 = VAR1 + VAR9;
assign VAR6 = VAR13 + VAR5;
assi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1.symbol.v | 1,330 | module MODULE1 (
input VAR3,
output VAR4
);
supply1 VAR2;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
m13253/riscade | hdl/src/step_ex_cpt.v | 2,123 | module MODULE1(clk, rst, VAR3, VAR2, VAR24,
VAR25,
VAR15, VAR19, VAR21, VAR7, VAR17, VAR20, VAR5, VAR11,
VAR18, VAR6, VAR13, VAR9, VAR12, VAR8, VAR10, VAR23);
input clk;
input rst;
input VAR3;
output VAR2;
input[3:0] VAR24;
input[7:0] VAR25;
output[7:0] VAR15, VAR19, VAR21, VAR7, VAR17, VAR20, VAR5, VAR11;
output VAR18... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ba/sky130_fd_sc_hdll__o21ba.behavioral.v | 1,571 | module MODULE1 (
VAR12 ,
VAR4 ,
VAR7 ,
VAR5
);
output VAR12 ;
input VAR4 ;
input VAR7 ;
input VAR5;
supply1 VAR2;
supply0 VAR10;
supply1 VAR13 ;
supply0 VAR3 ;
wire VAR8 ;
wire VAR6;
nor VAR11 (VAR8 , VAR4, VAR7 );
nor VAR1 (VAR6, VAR5, VAR8 );
buf VAR9 (VAR12 , VAR6 );
endmodule | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_jtag_uart_0.v | 17,294 | module MODULE3 (
clk,
VAR3,
VAR38,
VAR27,
VAR52,
VAR20,
VAR54
)
;
output VAR27;
output [ 7: 0] VAR52;
output VAR20;
output [ 5: 0] VAR54;
input clk;
input [ 7: 0] VAR3;
input VAR38;
wire VAR27;
wire [ 7: 0] VAR52;
wire VAR20;
wire [ 5: 0] VAR54;
always @(posedge clk)
begin
if (VAR38)
("%VAR15", VAR3);
end
assign VAR54 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50.functional.pp.v | 1,866 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR12,
VAR8,
VAR5 ,
VAR10
);
output VAR3 ;
input VAR4 ;
input VAR12;
input VAR8;
input VAR5 ;
input VAR10 ;
wire VAR1 ;
wire VAR11;
buf VAR2 (VAR1 , VAR4 );
VAR6 VAR7 (VAR11, VAR1, VAR12, VAR8);
buf VAR9 (VAR3 , VAR11 );
endmodule | apache-2.0 |
efabless/openlane | designs/y_dct/src/y_dct.v | 32,954 | module MODULE1(clk, rst, enable, VAR128,
VAR41, VAR87, VAR7, VAR104, VAR189, VAR39, VAR6, VAR62,
VAR249, VAR178, VAR66, VAR267, VAR101, VAR118, VAR56, VAR207,
VAR57, VAR272, VAR154, VAR13, VAR152, VAR304, VAR112, VAR83,
VAR141, VAR168, VAR131, VAR175, VAR99, VAR299, VAR123, VAR220,
VAR289, VAR188, VAR195, VAR81, VAR291... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_tagl_dp.v | 4,582 | module MODULE1(
VAR47, VAR29, VAR34, VAR48,
VAR16, VAR15, VAR32, VAR9, VAR25,
VAR42, VAR39, VAR6, VAR17, VAR24, VAR5
);
input [VAR31-1:0] VAR16; input [VAR31-1:0] VAR15;input [VAR31-1:0] VAR32;input [VAR31-1:0] VAR9;input [VAR31-1:0] VAR25;input [VAR31-1:0] VAR42;
input VAR39;
input VAR6,VAR17;
output VAR47;
output [5:... | gpl-2.0 |
jbelloncastro/amber_arm | hw/vlog/system/system.v | 33,444 | module MODULE1
(
input VAR28,
input VAR384,
input VAR1,
input VAR365,
output VAR82,
output VAR377,
input VAR371,
inout [15:0] VAR22,
output [12:0] VAR310,
output [2:0] VAR35,
output VAR109,
output VAR63,
output VAR275,
output VAR93,
output VAR357,
output VAR338,
output [1:0] VAR284,
inout [1:0] VAR152,
inout [1:0] VAR7... | lgpl-3.0 |
donnaware/AGC | rtl/de0/modules/ng_INT.v | 6,656 | module MODULE1(
input VAR22, input VAR11, input VAR39, input VAR44, input [100:0] VAR7, input [ 15:0] VAR8, output [ 15:0] VAR40, output VAR18 );
VAR36 VAR37(.VAR25({VAR18,VAR23,VAR1,VAR39,VAR24,VAR21,VAR2,VAR4,VAR35,VAR38,VAR27,VAR43,VAR8[15],VAR8[14],VAR15,VAR17 }));
assign VAR18 = !(VAR12 & VAR32 & VAR6 & VAR41);
wi... | gpl-3.0 |
zaqwes8811/spec-emb | soc-guitar-tuner/tuner/fsm/base_fsm.v | 3,821 | module MODULE1(
input clk, VAR18, input [VAR8-1:0] VAR27,
input VAR20,
output reg VAR28,
output reg VAR11,
output reg [11:0] VAR26,
output reg irq,
output VAR22,
output VAR5
);
reg VAR19;
reg VAR25;
reg VAR7;
reg VAR9, VAR24, VAR1;
reg VAR10;
reg VAR15;
reg VAR4;
reg [VAR8-1:0] VAR3;
reg [5:0] VAR2;
reg [5:0] VAR29;
re... | mit |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/EECS301_Lab3_TopLevel.v | 3,789 | module MODULE1
parameter VAR23 = 80000000, parameter VAR12 = 10000000, parameter VAR42 = 1000, parameter VAR14 = 10 )
(
input VAR20,
output [9:0] VAR26,
output [6:0] VAR39,
output [6:0] VAR19,
output [6:0] VAR25,
output [6:0] VAR37,
output [6:0] VAR10,
output [6:0] VAR16,
input [3:0] VAR17,
input [1:0] VAR9
);
localpar... | mit |
asicguy/gplgpu | hdl/mc_graph/mc.v | 20,093 | module MODULE1
(
input VAR210,
input [7:0] VAR75,
input [2:0] VAR105,
input VAR34,
input [1:0] VAR93,
input [7:0] VAR204,
input [3:0] VAR174,
input [VAR16-1:0] VAR66,
input VAR104,
input [(VAR16*8)-1:0] VAR138,
input [(VAR16*4)-1:0] VAR87,
input [2:0] VAR74,
input [31:0] VAR186,
input [3:0] VAR150,
input [1:0] VAR106,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o.symbol.v | 1,394 | module MODULE1 (
input VAR6,
input VAR9,
input VAR3,
input VAR4,
input VAR10,
output VAR1
);
supply1 VAR8;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
eecsninja/duinocube-core | common/tile_reg_decoder.v | 4,425 | module MODULE1(VAR53,
VAR9,
VAR46,
VAR29,
VAR11,
VAR36,
VAR37,
VAR38,
VAR55,
VAR4,
VAR31,
VAR23,
VAR18,
VAR52,
VAR2,
VAR20,
VAR57,
VAR12,
VAR25,
VAR58,
VAR16,
VAR26);
input [1:0] VAR53;
input [VAR43-1:0] VAR9;
wire [VAR28-1:0]
VAR5[VAR24-1:0];
genvar VAR39;
generate
for (VAR39 = 0; VAR39 < VAR24; VAR39 = VAR39 + 1) beg... | gpl-3.0 |
kyzhai/NUNY | src/hardware/six_new2_bb.v | 5,008 | module MODULE1 (
address,
VAR2,
VAR1);
input [9:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/nf2_dma_sync.v | 4,537 | module MODULE1
parameter VAR14 = 4)
(
output reg [VAR14-1:0] VAR12,
output reg [VAR14-1:0] VAR15,
output VAR42,
output VAR39,
input VAR40,
input [VAR4 +3:0] VAR31,
output VAR11,
input VAR23,
output [VAR4 +2:0] VAR36,
input [VAR14-1:0] VAR43,
input [VAR14-1:0] VAR37,
output VAR17,
output [VAR4 +3:0] VAR26,
input VAR22,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapmet1/sky130_fd_sc_ms__tapmet1.pp.blackbox.v | 1,230 | module MODULE1 (
VAR2,
VAR3,
VAR4 ,
VAR1
);
input VAR2;
input VAR3;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/cabac_mvd_top_2p_18xMB_X_TOTAL.v | 2,627 | module MODULE1(
clk ,
VAR18 ,
VAR16 ,
VAR3 ,
VAR14 ,
VAR7 ,
VAR4
);
input clk ; input VAR18 ; input [VAR6-1:0] VAR16 ; input VAR3 ; input [VAR6-1:0] VAR14 ; input [2*(VAR20+1)-1:0] VAR7 ;
output [2*(VAR20+1)-1:0] VAR4 ;
VAR8 #(.VAR11(VAR6), .VAR1(18))
VAR13 (
.VAR15 ( clk ),
.VAR12 ( ~VAR18 ),
.VAR17 ( VAR16 ),
.VAR2 (... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_cpu_top.v | 20,014 | module MODULE1(
output [VAR55-1:0] VAR126,
output VAR57 ,
output VAR94,
output VAR48,
output VAR128,
output VAR5,
output VAR2 ,
output VAR51 ,
output VAR32,
output VAR40,
input [VAR55-1:0] VAR47,
output VAR64,
output [VAR55-1:0] VAR143,
output VAR123,
output [3-1:0] VAR31,
output VAR153,
output VAR44 ,
output VAR169 ,
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn.blackbox.v | 1,278 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR6 ;
input VAR4;
supply1 VAR7;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
argonnexraydetector/RoachFirmPy | ANLYellowBlocks/mkid_dacadc_4x/pcores/dac_mkid_4x_interface_v2_00_a/hdl/verilog/dac_mkid_4x_interface.v | 26,858 | module MODULE1(
input VAR122, input VAR41,
output VAR141, output VAR153,
output VAR22,
output VAR43,
output VAR86,
output VAR138,
output VAR103,
output VAR118,
output [15:0] VAR60, output [15:0] VAR32,
output [15:0] VAR100,
output [15:0] VAR99,
output VAR62,
output VAR181,
output VAR91,
output VAR137,
output VAR27,
inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ha/sky130_fd_sc_hs__ha.functional.pp.v | 2,098 | module MODULE1 (
VAR8,
VAR2,
VAR6,
VAR7 ,
VAR16 ,
VAR10
);
input VAR8;
input VAR2;
output VAR6;
output VAR7 ;
input VAR16 ;
input VAR10 ;
wire VAR5 ;
wire VAR11;
wire VAR4 ;
wire VAR3 ;
and VAR13 (VAR5 , VAR16, VAR10 );
VAR9 VAR1 (VAR11, VAR5, VAR8, VAR2);
buf VAR14 (VAR6 , VAR11 );
xor VAR12 (VAR4 , VAR10, VAR16 );
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21oi/sky130_fd_sc_hd__a21oi.functional.v | 1,420 | module MODULE1 (
VAR3 ,
VAR8,
VAR4,
VAR1
);
output VAR3 ;
input VAR8;
input VAR4;
input VAR1;
wire VAR9 ;
wire VAR7;
and VAR6 (VAR9 , VAR8, VAR4 );
nor VAR5 (VAR7, VAR1, VAR9 );
buf VAR2 (VAR3 , VAR7 );
endmodule | apache-2.0 |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_add.v | 5,282 | module MODULE1 (
clk,
VAR24,
VAR21,
VAR12,
VAR30,
VAR19,
VAR4,
VAR9);
parameter VAR20 = 16;
parameter VAR18 = VAR20 - 1;
input clk;
input [24:0] VAR24;
input [24:0] VAR21;
input [24:0] VAR12;
input [24:0] VAR30;
output [ 7:0] VAR19;
input [VAR18:0] VAR4;
output [VAR18:0] VAR9;
reg [VAR18:0] VAR15 = 'd0;
reg [24:0] VAR2... | mit |
doug65536/crtc | fifo.v | 1,713 | module MODULE1(
clk,
reset,
VAR5,
VAR6,
VAR18,
VAR11,
VAR13,
VAR14,
VAR2
);
parameter VAR7 = 32;
parameter VAR1 = 4;
localparam VAR10 = {1'b1, {(VAR1){1'b0}}};
input clk;
input reset;
input VAR5;
input VAR6;
input [VAR7-1:0] VAR18;
output [VAR7-1:0] VAR11;
output VAR13;
output VAR14;
output VAR2;
reg [VAR7-1:0] VAR16[0... | mit |
eda-globetrotter/MarcheProcessor | wwp/datamem.v | 2,546 | module MODULE1 (VAR3,VAR1,VAR4,clk,VAR2);
output [0:127] VAR3;
input [0:127] VAR1;
input [0:31] VAR4;
input clk;
input [0:1] VAR2;
reg [0:127] VAR3;
reg [127:0] MODULE1 [255:0];
begin
begin
begin
begin
begin
begin | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/SIETransmitter.v | 24,331 | module MODULE1 (VAR67, VAR17, VAR38, VAR59, VAR7, VAR35, VAR13, VAR65, VAR64, VAR26, VAR70, VAR51, VAR81, VAR77, VAR96, VAR9, VAR41, VAR82, VAR22, VAR122, VAR76, VAR33, VAR3, VAR108, clk, VAR60, VAR75, VAR114, rst, VAR43);
input [15:0] VAR17;
input VAR38;
input [4:0] VAR7;
input VAR35;
input [1:0] VAR64;
input [1:0] VA... | gpl-3.0 |
rkrajnc/minimig-de1 | bench/sdm/sdm.v | 4,925 | module MODULE1
(
input clk, input [14:0] VAR26, input [14:0] VAR22, output reg VAR40=0, output reg VAR37=0 );
localparam VAR4 = 15;
localparam VAR9 = 2;
localparam VAR14 = 4;
localparam VAR21 = 2;
localparam VAR32 = 5;
wire [VAR4+2+0 -1:0] VAR3, VAR5;
reg [VAR4+2+0 -1:0] VAR2=0, VAR23=0;
wire [VAR4+VAR21+2-1:0] VAR10, ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a_4.v | 2,221 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR3 ,
VAR8 ,
VAR9,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR8 ;
input VAR9;
input VAR5;
VAR7 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR4 ,
VAR1,
VAR2,
VAR3,
VAR8
);... | apache-2.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/sha256_dsp48e1.v | 11,257 | module MODULE3 (
input clk,
input [511:0] VAR79,
input [255:0] VAR43,
output reg [255:0] VAR55,
output [31:0] VAR153
);
localparam VAR25 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d7... | gpl-3.0 |
nyaxt/dmix | csr_spi.v | 12,691 | module MODULE2(
input wire [7:0] VAR47,
output wire VAR26,
output wire VAR9,
output wire VAR34,
output wire [7:0] VAR13,
output wire VAR41,
output wire VAR60,
output wire [3:0] VAR49);
assign VAR34 = VAR47[7];
function [7:0] VAR78(
input [1:0] VAR12);
begin
case (VAR12)
2'b00: VAR78 = 8'd0;
2'b01: VAR78 = 8'd1;
2'b10: ... | mit |
muraj/trv_proc | rtl/pipe_mult.v | 2,718 | module MODULE1
parameter VAR3 = 32,
parameter VAR12 = 8
)
(
input wire clk,
input wire rst,
input wire en,
input wire [VAR3-1:0] VAR17,
input wire [VAR3-1:0] VAR18,
output wire [VAR3-1:0] VAR21,
output wire VAR7
);
wire [VAR12-2:0] VAR10;
wire [VAR3*(VAR12-1)-1:0] VAR14, VAR20, VAR16;
wire [VAR3-1:0] VAR13, VAR2;
MODUL... | mit |
plindstroem/oh | elink/hdl/etx_arbiter.v | 5,821 | module MODULE1 (
VAR28, VAR1, VAR32, VAR15, VAR31, VAR34,
clk, reset, VAR36, VAR11, VAR25, VAR22,
VAR38, VAR10, VAR29, VAR4, VAR37,
VAR8, VAR9
);
parameter VAR33 = 104;
parameter VAR23 = 0;
input clk;
input reset;
input VAR36;
input [VAR33-1:0] VAR11;
output VAR28;
input VAR25;
input [VAR33-1:0] VAR22;
output VAR1;
inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22ai/sky130_fd_sc_hvl__o22ai.pp.symbol.v | 1,380 | module MODULE1 (
input VAR9 ,
input VAR8 ,
input VAR2 ,
input VAR1 ,
output VAR7 ,
input VAR6 ,
input VAR3,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
samialabri/DE0_Nano_LCD | LCD.v | 3,002 | module MODULE1 (
input clk,
input [7:0] VAR12,
output reg [7:0] VAR1,
output reg VAR10,
output reg VAR3,
output VAR7,
output VAR2,
output VAR13,
output VAR11
);
assign VAR7 = state[0];
assign VAR2 = state[1];
assign VAR13 = state[2];
assign VAR11 = state[3];
localparam VAR4 = 4'b0001;
localparam VAR9 = 4'b0010;
localpa... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.functional.v | 1,040 | module MODULE1( VAR4, VAR1, VAR5 );
input VAR5, VAR4;
output VAR1;
wire VAR3;
not VAR2( VAR3, VAR5 );
wire VAR6;
not VAR8( VAR6, VAR4 );
and VAR7( VAR1, VAR3, VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2_m.v | 2,072 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR9 ,
VAR3,
VAR5,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR4 ;
input VAR9 ;
input VAR3;
input VAR5;
input VAR2 ;
input VAR1 ;
VAR8 VAR6 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR4,
VAR9
);
output VAR7;
... | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/router_wrap.v | 12,165 | module MODULE1
(clk, reset, VAR46, VAR19, VAR7, VAR10,
VAR61, VAR84, VAR18, VAR34, VAR3);
localparam VAR75 = VAR44 * VAR15;
localparam VAR20 = VAR75 * VAR16;
localparam VAR14 = VAR37(VAR20);
localparam VAR26
= (VAR69 + VAR62 - 1) / VAR62;
localparam VAR85 = VAR51(VAR26, VAR17);
localparam VAR74 = VAR37(VAR85);
localpar... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/subsys/e203_subsys_plic.v | 8,218 | module MODULE1(
input VAR112,
output VAR9,
input [VAR157-1:0] VAR85,
input VAR12,
input [VAR127-1:0] VAR101,
input [VAR127/8-1:0] VAR186,
output VAR8,
input VAR108,
output VAR172,
output [VAR127-1:0] VAR84,
output VAR111,
input VAR15,
input VAR48,
input VAR73,
input VAR173,
input VAR11,
input VAR110,
input VAR17,
input... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_pipe_clock.v | 18,886 | module MODULE1 #
(
parameter VAR121 = "1.1", parameter VAR124 = "VAR35", parameter VAR55 = "VAR35", parameter VAR54 = 1, parameter VAR16 = 2, parameter VAR14 = 0, parameter VAR117 = 2, parameter VAR69 = 2, parameter VAR108 = 0
)
(
input VAR59,
input VAR63,
input [VAR54-1:0] VAR135,
input VAR28,
input [VAR54-1:0] VAR72,... | lgpl-3.0 |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/wasca_sysid_qsys_0.v | 2,209 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1481594924 : 305419896;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2.blackbox.v | 1,274 | module MODULE1 (
VAR1,
VAR2,
VAR4
);
output VAR1;
input VAR2;
input VAR4;
supply1 VAR3;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_avlmm_pr_freeze_bridge_0/synth/ghrd_10as066n2_avlmm_pr_freeze_bridge_0.v | 7,375 | module MODULE1 (
input wire VAR28, input wire VAR24, output wire VAR33, input wire VAR30, output wire VAR12, input wire VAR4, output wire VAR16, output wire [9:0] VAR31, output wire [3:0] VAR3, output wire [31:0] VAR15, input wire [31:0] VAR6, output wire [2:0] VAR5, input wire VAR23, output wire VAR26, output wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcon/sky130_fd_sc_hd__fahcon.blackbox.v | 1,369 | module MODULE1 (
VAR3,
VAR6 ,
VAR7 ,
VAR1 ,
VAR2
);
output VAR3;
output VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR2 ;
supply1 VAR8;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_ic_top.v | 10,128 | module MODULE1(
clk, rst,
VAR37, VAR53, VAR52, VAR30, VAR20, VAR61, VAR67,
VAR46, VAR18, VAR22,
VAR14,
VAR73, VAR21, VAR17,
VAR51, VAR7,
VAR33, VAR62, VAR63, VAR65, VAR64,
VAR44, VAR50, VAR54,
VAR60, VAR45, VAR19
);
parameter VAR38 = VAR3;
input clk;
input rst;
output [VAR38-1:0] VAR37;
output [31:0] VAR53;
output VAR5... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o.behavioral.pp.v | 2,064 | module MODULE1 (
VAR17 ,
VAR4 ,
VAR9 ,
VAR6 ,
VAR1 ,
VAR12 ,
VAR8,
VAR16,
VAR5 ,
VAR2
);
output VAR17 ;
input VAR4 ;
input VAR9 ;
input VAR6 ;
input VAR1 ;
input VAR12 ;
input VAR8;
input VAR16;
input VAR5 ;
input VAR2 ;
wire VAR10 ;
wire VAR3 ;
wire VAR11;
and VAR18 (VAR10 , VAR6, VAR4, VAR9 );
or VAR13 (VAR3 , VAR10,... | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.