repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfsbp/sky130_fd_sc_ms__sdfsbp.pp.blackbox.v | 1,471 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR3 ,
VAR2 ,
VAR11 ,
VAR1 ,
VAR5,
VAR4 ,
VAR7 ,
VAR9 ,
VAR8
);
output VAR6 ;
output VAR10 ;
input VAR3 ;
input VAR2 ;
input VAR11 ;
input VAR1 ;
input VAR5;
input VAR4 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
endmodule | apache-2.0 |
theHawke/real-dcpu | ALU/mult16.v | 4,295 | module MODULE1 (
VAR18,
VAR8,
VAR10);
input [15:0] VAR18;
input [15:0] VAR8;
output [31:0] VAR10;
wire [31:0] VAR9;
wire [31:0] VAR10 = VAR9[31:0];
VAR4 VAR7 (
.VAR18 (VAR18),
.VAR8 (VAR8),
.VAR10 (VAR9),
.VAR3 (1'b0),
.VAR11 (1'b1),
.VAR2 (1'b0),
.sum (1'b0));
VAR7.VAR17 = "VAR1=5",
VAR7.VAR13 = "VAR6",
VAR7.VAR14 = ... | gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_cx4/cx4_mul.v | 4,599 | module MODULE1 (
VAR1,
VAR20,
VAR9,
VAR5);
input VAR1;
input [23:0] VAR20;
input [23:0] VAR9;
output [47:0] VAR5;
wire [47:0] VAR16;
wire [47:0] VAR5 = VAR16[47:0];
VAR18 VAR19 (
.VAR1 (VAR1),
.VAR20 (VAR20),
.VAR9 (VAR9),
.VAR5 (VAR16),
.VAR3 (1'b0),
.VAR14 (1'b1),
.VAR15 (1'b0),
.sum (1'b0));
VAR19.VAR6 = "VAR2=9",
... | gpl-2.0 |
Alexoner/RiscCPU | machine.v | 3,884 | module MODULE1( VAR18, VAR13, VAR7, rd,wr, VAR5,
VAR2, VAR3, VAR1, VAR10, VAR6, VAR12 );
output VAR18, VAR13, VAR7, rd, wr, VAR5;
output VAR2, VAR3;
input VAR1, VAR10, VAR6;
input [2:0] VAR12;
reg VAR18, VAR13, VAR7, rd, wr, VAR5;
reg VAR2, VAR3;
reg [2:0] state;
parameter VAR4 = 3 'b000,
VAR14 = 3 'b001,
VAR11 = 3 'b0... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/ccx2mb_v1_00_a/hdl/verilog/ccx2mb.v | 4,845 | module MODULE1 (
VAR3,
VAR22,
VAR6,
VAR4,
VAR5,
VAR25,
VAR21,
VAR23,
VAR1,
VAR18,
VAR14,
VAR12,
VAR11,
VAR27,
VAR15,
VAR17
);
parameter VAR7 = 0;
output [4:0] VAR3;
output VAR22;
output [VAR19-1:0] VAR6;
output VAR4;
output VAR5;
output [VAR26-1:0] VAR25;
output VAR21;
input VAR23;
input VAR1;
input [VAR16-1:0] VAR18;
... | gpl-2.0 |
ThomasLee969/verilog-homework | project/framing_encoding/data_whiting.v | 2,393 | module MODULE1(
output [7:0] dout,
output VAR12,
input [7:0] din,
input VAR6,
input clk,
input VAR14
);
localparam VAR1 = 9'b111111111;
localparam VAR2 = 0,
VAR9 = 1,
VAR15 = 2;
reg [1:0] state, VAR5;
reg [6:0] VAR7, VAR3;
reg [8:0] VAR13, VAR10;
reg [7:0] VAR11, VAR4;
wire [8:0] VAR8 = {VAR13[5] ^ VAR13[0], VAR13[8:1]... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_dacfifo/util_dacfifo.v | 5,637 | module MODULE1 (
VAR29,
VAR20,
VAR11,
VAR12,
VAR23,
VAR19,
VAR7,
VAR18,
VAR25,
VAR16
);
parameter VAR17 = 6;
parameter VAR27 = 128;
input VAR29;
input VAR20;
input VAR11;
input [(VAR27-1):0] VAR12;
output VAR23;
input VAR19;
input VAR7;
input VAR18;
input VAR25;
output [(VAR27-1):0] VAR16;
reg [(VAR17-1):0] VAR15 = 'b0... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_mm_st_converter.v | 6,800 | module MODULE1 # (
parameter
VAR25 = 3,
VAR29 = 25,
VAR8 = 32,
VAR34 = 8,
VAR43 = 4
)
(
VAR13, VAR36,
VAR45, VAR33,
VAR4, VAR38, VAR28, VAR37, VAR1, VAR41, VAR20, VAR10, VAR26, VAR30,
VAR11, VAR15, VAR51, VAR32,
VAR18,
VAR49,
VAR14,
VAR19,
VAR7,
VAR47,
VAR2,
VAR35,
VAR3,
VAR40,
VAR21,
VAR42,
VAR23,
VAR16,
VAR44,
VAR50,... | lgpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_spram_2048x8.v | 10,807 | module MODULE1(
VAR48, VAR42, VAR27,
clk, rst, VAR1, VAR35, VAR13, addr, VAR24, VAR9
);
parameter VAR10 = 11;
parameter VAR39 = 8;
input VAR48;
input [VAR41 - 1:0] VAR27;
output VAR42;
input clk; input rst; input VAR1; input VAR35; input VAR13; input [VAR10-1:0] addr; input [VAR39-1:0] VAR24; output [VAR39-1:0] VAR9;
a... | apache-2.0 |
efabless/openlane | designs/151/src/WriteBackStage.v | 1,396 | module MODULE1 #(
)(
input clk, reset,
input wire [2:0] VAR2,
input wire [1:0] VAR5,
input wire [VAR7-1:0] VAR9,
output reg [VAR7-1:0] VAR8
);
localparam VAR3 = VAR7 - 8;
localparam VAR4 = VAR7 - 16;
wire [31:0] VAR1 =
(VAR9 & (32'hFF << (VAR5 * 8))) >> (VAR5 * 8);
wire [31:0] VAR6 =
(VAR9 & (32'hFFFF << (VAR5 * 8))) >... | apache-2.0 |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_design_PLL.v | 2,144 | module MODULE1(
input wire VAR4,
input wire rst,
output wire VAR57,
output wire VAR63,
output wire VAR65
);
VAR58 #(
.VAR25("false"),
.VAR54("100.0 VAR56"),
.VAR23("VAR55"),
.VAR28(2),
.VAR26("100.000000 VAR56"),
.VAR38("0 VAR29"),
.VAR7(50),
.VAR45("100.000000 VAR56"),
.VAR71("0 VAR29"),
.VAR50(50),
.VAR44("0 VAR56"),... | gpl-2.0 |
Digilent/vivado-library | ip/Pmods/PmodNAV_v1_0/src/PmodNAV.v | 16,718 | module MODULE1
(VAR242,
VAR42,
VAR170,
VAR179,
VAR77,
VAR80,
VAR215,
VAR8,
VAR172,
VAR202,
VAR204,
VAR227,
VAR151,
VAR177,
VAR236,
VAR12,
VAR183,
VAR31,
VAR21,
VAR159,
VAR13,
VAR181,
VAR54,
VAR168,
VAR40,
VAR70,
VAR131,
VAR43,
VAR25,
VAR216,
VAR146,
VAR61,
VAR221,
VAR184,
VAR22,
VAR250,
VAR110,
VAR203,
VAR64,
VAR205,
V... | mit |
chahuja/hilbert-fpga | fft16.v | 15,138 | module MODULE1(VAR6,VAR210,VAR135,VAR146,VAR198,VAR128,VAR102,VAR116,VAR61,VAR62);
parameter VAR80 = 32;
input VAR6;
input VAR210;
input VAR135;
input VAR146;
input VAR198;
input [VAR80-1:0] VAR128;
input [VAR80-1:0] VAR102;
output [VAR80+3:0] VAR116;
output [VAR80+3:0] VAR61;
output reg VAR62;
reg [3:0] VAR14; reg [5:... | gpl-2.0 |
eleqian/WiDSO | CPLD/DSO_LA/src/dso.v | 6,389 | module MODULE1(VAR9, VAR109, din, dout);
parameter VAR124 = 1;
input VAR9;
inout [VAR124-1:0] VAR109;
input [VAR124-1:0] din;
output [VAR124-1:0] dout;
assign dout = VAR109;
assign VAR109 = VAR9 ? din : {VAR124{1'VAR120}};
endmodule
module MODULE3(VAR83, VAR42, VAR128, VAR4);
input VAR83;
input VAR42;
input VAR128;
out... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxtp/sky130_fd_sc_hd__edfxtp.symbol.v | 1,424 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR7 ,
input VAR8
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.functional.v | 1,164 | module MODULE1( VAR14, VAR9, VAR11, VAR6 );
input VAR9, VAR11;
output VAR14, VAR6;
and VAR4( VAR14, VAR9, VAR11 );
wire VAR2;
not VAR5( VAR2, VAR11 );
wire VAR7;
and VAR10( VAR7, VAR2, VAR9 );
wire VAR3;
not VAR8( VAR3, VAR9 );
wire VAR12;
and VAR13( VAR12, VAR3, VAR11 );
or VAR1( VAR6, VAR7, VAR12 );
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v | 6,467 | module MODULE1 #
(
parameter integer VAR19 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR19-1:0] VAR14 ,
input wire [7:0] VAR12 ,
input wire [2:0] VAR9 ,
input wire VAR8 ,
output wire [VAR19-1:0] VAR17 ,
input wire VAR4 ,
output reg VAR25
);
reg VAR21;
wire [11:0] VAR11;
wire [3:0] VAR16;
reg [11:0] VAR15... | gpl-3.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/ip/fifo_EEPROM/fifo_EEPROM_stub.v | 1,436 | module MODULE1(rst, VAR2, VAR5, din, VAR1, VAR6, dout, VAR4,
VAR3)
;
input rst;
input VAR2;
input VAR5;
input [7:0]din;
input VAR1;
input VAR6;
output [7:0]dout;
output VAR4;
output VAR3;
endmodule | gpl-3.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/bus/rtl/bus.v | 7,615 | module MODULE1 (
input wire clk, input wire reset,
output wire [VAR9] VAR6, output wire VAR10, input wire VAR58, input wire [VAR7] VAR47, input wire VAR37, input wire VAR4, input wire [VAR9] VAR31, output wire VAR41, input wire VAR17, input wire [VAR7] VAR57, input wire VAR46, input wire VAR40, input wire [VAR9] VAR11,... | apache-2.0 |
grantae/uart | src/uart_min.v | 3,853 | module MODULE1(
input VAR15,
input reset,
input write,
input [7:0] VAR23, input read,
output [7:0] VAR3, output VAR4,
output [8:0] VAR17,
input VAR14, output VAR5 );
localparam VAR35 = 8; localparam VAR31 = 8;
wire VAR12, VAR16;
wire [7:0] VAR8; wire VAR33; wire VAR10;
reg VAR9 = 0;
reg VAR32 = 0;
wire VAR11;
wire VAR2... | mit |
tmatsuya/milkymist-ml401 | cores/pfpu/rtl/pfpu_alu.v | 4,796 | module MODULE1(
input VAR54,
input VAR27,
input [31:0] VAR24,
input [31:0] VAR17,
input VAR6,
input [3:0] VAR10,
output [31:0] VAR51,
output VAR1,
output reg VAR30,
output VAR11
);
reg [3:0] VAR16;
always @(posedge VAR54) begin
if(VAR27)
VAR16 <= 4'd0;
end
else
VAR16 <= VAR10;
end
always @(posedge VAR54) begin
if(VAR27... | lgpl-3.0 |
hydai/Verilog-Practice | DigitalDesign/101062124_hw4/my_t.v | 1,657 | module MODULE1;
reg [9:0] VAR5 [VAR9-1:0];
parameter period = 20;
parameter delay = 2;
reg clk, VAR7, VAR12, VAR10;
reg [7:0] VAR3;
wire VAR11, VAR8, VAR2, VAR4, VAR14;
wire [7:0] VAR13;
integer VAR6;
VAR1 VAR15 (
clk,
VAR7,
VAR12,
VAR10,
VAR3,
VAR11,
VAR8,
VAR2,
VAR4,
VAR14,
VAR13
);
always #(period/2) clk = ~clk;
beg... | mit |
jmesmon/trifles | verilog/hw2/p11_12.v | 1,536 | module MODULE1(output VAR14, VAR9, input VAR5, VAR19);
xor sum(VAR14,VAR5,VAR19);
and VAR4(VAR9,VAR5,VAR19);
endmodule
module MODULE3(output VAR14, VAR10, input VAR5,VAR19,VAR12);
wire VAR15, VAR1, VAR7;
MODULE1 MODULE3(VAR15,VAR1, VAR5 ,VAR19 ),
ha2(VAR14 ,VAR7, VAR15,VAR12);
or VAR4(VAR10, VAR1,VAR7);
endmodule
modul... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_01/02 verilog/ultrasonido_modulo_2/periferico_ultra/peripheral_ultra.v | 1,527 | module MODULE1(clk , rst , din , VAR9 , addr , rd , wr, dout, VAR2, VAR5 );
input clk;
input rst;
input [15:0]din;
input VAR9;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
output VAR2;
output VAR5;
reg [5:0] VAR1;
reg enable;
wire [7:0] dout; wire VAR12;
VAR8 VAR4(.clk(clk), .reset(rst),.VAR10(dout), .VA... | gpl-3.0 |
vvk/sysrek | skin_color_segm/src/rx_nok/dvi_decoder_nok.v | 9,273 | module MODULE1 (
input wire VAR70, input wire VAR18, input wire VAR112, input wire VAR116, input wire VAR8, input wire VAR17, input wire VAR110, input wire VAR54, input wire VAR115,
output wire reset, output wire VAR43, output wire VAR32, output wire VAR4, output wire VAR10, output wire VAR75, output wire VAR31,
output... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22ai/sky130_fd_sc_hvl__o22ai.behavioral.v | 1,619 | module MODULE1 (
VAR16 ,
VAR7,
VAR15,
VAR14,
VAR4
);
output VAR16 ;
input VAR7;
input VAR15;
input VAR14;
input VAR4;
supply1 VAR11;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR1 ;
wire VAR10 ;
wire VAR13 ;
wire VAR3;
nor VAR12 (VAR10 , VAR14, VAR4 );
nor VAR6 (VAR13 , VAR7, VAR15 );
or VAR9 (VAR3, VAR13, VAR10);
buf VAR2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.v | 2,226 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR5,
VAR10,
VAR2 ,
VAR4
);
output VAR9 ;
output VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR5;
input VAR10;
input VAR2 ;
input VAR4 ;
VAR8 VAR6 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODUL... | apache-2.0 |
nyaxt/dmix | rom_firbank_48_96.v | 1,727 | module MODULE1(
input wire clk,
input wire [4:0] addr,
output wire [23:0] VAR2);
reg [23:0] VAR1;
assign VAR2 = VAR1;
always @(posedge clk) begin
case(addr)
0: VAR1 <= 24'h164B2D; 1: VAR1 <= 24'hF5BAE8; 2: VAR1 <= 24'h0633AB; 3: VAR1 <= 24'hFC29F9; 4: VAR1 <= 24'h0242A4; 5: VAR1 <= 24'hFEC9C7; 6: VAR1 <= 24'h008EDD; 7:... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_clk_wiz_0_0/OpenSSD2_clk_wiz_0_0_clk_wiz.v | 6,585 | module MODULE1
( input VAR49,
output VAR32,
input reset
);
VAR56 VAR12
(.VAR35 (VAR74),
.VAR63 (VAR49));
wire [15:0] VAR34;
wire VAR44;
wire VAR42;
wire VAR13;
wire VAR14;
wire VAR18;
wire VAR23;
wire VAR67;
wire VAR53;
wire VAR27;
wire VAR62;
wire VAR48;
wire VAR55;
wire VAR46;
wire VAR22;
wire VAR79;
wire VAR11;
wire... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_4.behavioral.v | 1,341 | module MODULE1( VAR2, VAR7, VAR6, VAR8, VAR4 );
input VAR8, VAR4, VAR2, VAR6;
output VAR7;
VAR3 VAR1(.VAR2(VAR2),.VAR7(VAR7),.VAR6(VAR6),.VAR8(VAR8),.VAR4(VAR4));
VAR3 VAR5(.VAR2(VAR2),.VAR7(VAR7),.VAR6(VAR6),.VAR8(VAR8),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor3/sky130_fd_sc_hs__xnor3_4.v | 2,057 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR4 ,
VAR8 ,
VAR6,
VAR1
);
output VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR8 ;
input VAR6;
input VAR1;
VAR3 VAR2 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR5,
VAR4,
VAR8
);
output VAR7;
input VAR5;
input VAR4;
in... | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_auto_pc_0/synth/zc702_auto_pc_0.v | 13,143 | module MODULE1 (
VAR22,
VAR10,
VAR52,
VAR106,
VAR99,
VAR14,
VAR114,
VAR21,
VAR7,
VAR96,
VAR79,
VAR4,
VAR110,
VAR101,
VAR15,
VAR56,
VAR86,
VAR105,
VAR47,
VAR100,
VAR109,
VAR102,
VAR92,
VAR66,
VAR3,
VAR57,
VAR33,
VAR80,
VAR50,
VAR46,
VAR48,
VAR45,
VAR88,
VAR65,
VAR42,
VAR53,
VAR39,
VAR63,
VAR29,
VAR6,
VAR68,
VAR13,
VAR34... | mit |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/hpdmc.v | 24,588 | module MODULE3 #(
parameter VAR100 = 1'b0,
parameter VAR119 = 23,
parameter VAR112 = 8
) (
input VAR27,
input VAR7,
input [2:0] VAR73,
input VAR97,
input [15:0] VAR45,
output [15:0] VAR116,
input [VAR119-1:0] VAR81,
input VAR85,
input VAR118,
output VAR71,
input [1:0] VAR33,
input [15:0] VAR92,
output [15:0] VAR86,
out... | gpl-3.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/lab3_hps_0.v | 28,514 | module MODULE1 #(
parameter VAR90 = 2,
parameter VAR123 = 2
) (
output wire VAR87, input wire VAR60, input wire [7:0] VAR134, input wire [31:0] VAR138, input wire [3:0] VAR34, input wire [2:0] VAR29, input wire [1:0] VAR171, input wire [1:0] VAR46, input wire [3:0] VAR172, input wire [2:0] VAR77, input wire VAR21, outp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4b/sky130_fd_sc_ms__nor4b.behavioral.v | 1,510 | module MODULE1 (
VAR14 ,
VAR11 ,
VAR9 ,
VAR7 ,
VAR8
);
output VAR14 ;
input VAR11 ;
input VAR9 ;
input VAR7 ;
input VAR8;
supply1 VAR13;
supply0 VAR2;
supply1 VAR12 ;
supply0 VAR4 ;
wire VAR6 ;
wire VAR10;
not VAR1 (VAR6 , VAR8 );
nor VAR5 (VAR10, VAR11, VAR9, VAR7, VAR6);
buf VAR3 (VAR14 , VAR10 );
endmodule | apache-2.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CoreAPB3/4.0.100/rtl/vlog/amba_bfm/bfm_apbslave.v | 20,989 | module
MODULE1
(
VAR229
,
VAR9
,
VAR108
,
VAR59
,
VAR197
,
VAR201
,
VAR45
,
VAR117
,
VAR135
,
VAR52
)
;
parameter
VAR166
=
10
;
parameter
VAR95
=
256
;
parameter
VAR2
=
32
;
parameter
VAR190
=
" "
;
parameter
VAR129
=
0
;
parameter
VAR132
=
1
;
parameter
VAR75
=
0
;
parameter
VAR98
=
0
;
localparam
VAR35
=
2
;
localpar... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a_2.v | 2,422 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR3 ,
VAR9 ,
VAR6 ,
VAR12 ,
VAR1,
VAR10,
VAR11 ,
VAR4
);
output VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR9 ;
input VAR6 ;
input VAR12 ;
input VAR1;
input VAR10;
input VAR11 ;
input VAR4 ;
VAR7 VAR2 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR1(V... | apache-2.0 |
jameshegarty/rigel | misc/gte_float32_float32_bool.v | 19,527 | module MODULE1 (
VAR233, VAR241, VAR42, out
);
parameter VAR135="VAR264";
input wire VAR233;
input wire VAR241;
input [63 : 0] VAR42;
output [0:0] out;
wire clk;
assign clk=VAR233;
wire [31:0] VAR60;
wire [31:0] VAR13;
wire [0:0] VAR206;
assign VAR60 = VAR42[31:0];
assign VAR13 = VAR42[63:32];
assign out = VAR206;
wire... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/ip_top/memc_ui_top_std.v | 26,961 | module MODULE1 #
(
parameter VAR83 = 100,
parameter VAR51 = 64,
parameter VAR147 = "VAR170",
parameter VAR142 = "0", parameter VAR13 = 3, parameter VAR53 = 2, parameter VAR20 = "8", parameter VAR7 = "VAR119", parameter VAR34 = 1, parameter VAR173 = 5,
parameter VAR219 = 12, parameter VAR11 = "VAR105", parameter VAR86 =... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_div.v | 17,551 | module MODULE1 (
VAR53,
VAR49,
VAR13,
VAR10,
VAR70,
VAR74,
VAR96,
VAR3,
VAR47,
VAR52,
VAR2,
VAR73,
VAR93,
VAR21,
VAR72,
VAR29,
VAR65,
VAR76,
VAR91,
VAR38,
VAR57,
VAR92,
VAR75,
VAR43,
VAR79,
VAR108,
VAR46,
VAR114,
VAR117,
VAR24,
VAR86,
VAR30,
VAR111,
VAR55,
VAR5
);
input [7:0] VAR53; input [1:0] VAR49; input [4:0] VAR13... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.behavioral.pp.v | 1,182 | module MODULE1( VAR2, VAR7, VAR6, VAR5 );
input VAR2;
inout VAR6, VAR5;
output VAR7;
VAR3 VAR1(.VAR2(VAR2),.VAR7(VAR7),.VAR6(VAR6),.VAR5(VAR5));
VAR3 VAR4(.VAR2(VAR2),.VAR7(VAR7),.VAR6(VAR6),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2b/sky130_fd_sc_ls__and2b.functional.v | 1,356 | module MODULE1 (
VAR8 ,
VAR7,
VAR1
);
output VAR8 ;
input VAR7;
input VAR1 ;
wire VAR5 ;
wire VAR3;
not VAR4 (VAR5 , VAR7 );
and VAR2 (VAR3, VAR5, VAR1 );
buf VAR6 (VAR8 , VAR3 );
endmodule | apache-2.0 |
manu3193/TextEditor | Altera_UP_PS2_Data_In.v | 5,138 | module MODULE1 (
clk,
reset,
VAR1,
VAR16,
VAR4,
VAR15,
VAR13,
VAR8,
VAR6 );
input clk;
input reset;
input VAR1;
input VAR16;
input VAR4;
input VAR15;
input VAR13;
output reg [7:0] VAR8;
output reg VAR6;
localparam VAR7 = 3'h0,
VAR14 = 3'h1,
VAR3 = 3'h2,
VAR11 = 3'h3,
VAR12 = 3'h4;
reg [3:0] VAR5;
reg [7:0] VAR2;
reg [2... | mit |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/title1/title1_stub.v | 1,266 | module MODULE1(VAR1, VAR2, VAR4, VAR3, VAR5)
;
input VAR1;
input [0:0]VAR2;
input [13:0]VAR4;
input [11:0]VAR3;
output [11:0]VAR5;
endmodule | gpl-3.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_xbar_0/synth/system_xbar_0.v | 19,540 | module MODULE1 (
VAR1,
VAR131,
VAR101,
VAR67,
VAR122,
VAR2,
VAR29,
VAR92,
VAR118,
VAR59,
VAR93,
VAR19,
VAR15,
VAR58,
VAR129,
VAR13,
VAR69,
VAR110,
VAR75,
VAR119,
VAR114,
VAR91,
VAR130,
VAR63,
VAR116,
VAR57,
VAR23,
VAR126,
VAR103,
VAR84,
VAR80,
VAR50,
VAR108,
VAR54,
VAR34,
VAR112,
VAR16,
VAR36,
VAR65,
VAR105,
VAR94,
VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_dp_macb_r.v | 4,713 | module MODULE1(
VAR27, VAR8, VAR26,
VAR5, VAR4, VAR14,
VAR2, VAR3, VAR7,
VAR17, VAR16, VAR11, VAR35
);
output [149:0] VAR27; output VAR8;
output VAR26;
input VAR5; input VAR4; input VAR14; input VAR2; input VAR3; input [149:0] VAR7; input [149:0] VAR17;
input VAR16;
input VAR11;
input VAR35;
wire VAR24;
wire [149:0] VA... | gpl-2.0 |
jakubfi/mera400f | src/uart.v | 2,988 | module MODULE1(
input clk,
input VAR27,
input [7:0] VAR19,
output [7:0] VAR16,
output VAR17,
output VAR8,
output VAR20,
input VAR24
);
parameter VAR14;
parameter VAR3;
localparam VAR18 = VAR3/VAR14;
localparam VAR22 = VAR25(VAR18+1);
localparam [VAR22-1:0] period = VAR18[VAR22-1:0] - 1'b1;
MODULE2 #(
.VAR22(VAR22),
.pe... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_16.behavioral.pp.v | 1,164 | module MODULE1( VAR3, VAR4, VAR7, VAR5 );
input VAR3;
inout VAR7, VAR5;
output VAR4;
VAR6 VAR2(.VAR3(VAR3),.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5));
VAR6 VAR1(.VAR3(VAR3),.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5)); | apache-2.0 |
asicguy/gplgpu | hdl/altera_project/sfifo_65x128/sfifo_65x128_bb.v | 5,846 | module MODULE1 (
VAR6,
VAR2,
VAR5,
VAR7,
VAR3,
VAR9,
VAR10,
VAR1,
VAR4,
VAR8);
input [64:0] VAR6;
input VAR2;
input VAR5;
input VAR7;
input VAR3;
output [64:0] VAR9;
output VAR10;
output VAR1;
output [6:0] VAR4;
output VAR8;
endmodule | gpl-3.0 |
DSDL2016/project2 | source/lcd_bridge.v | 5,342 | module MODULE1 (
input VAR12,
input reset,
input VAR7,
input [31:0] VAR3,
input VAR16,
output VAR17,
output [7:0] VAR14,
output [4:0] VAR8
);
reg [2:0] state;
reg [17:0] counter;
reg [5:0] VAR9;
reg [8:0] VAR6;
reg VAR4;
reg [7:0] VAR15;
reg VAR10;
wire VAR13;
reg VAR19;
reg VAR18, VAR11;
reg VAR1, VAR5;
reg [8:0] VAR2... | mit |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/fake_hilbert.v | 3,450 | module MODULE1
parameter VAR16 = VAR14-1,
parameter VAR6 = 12,
parameter VAR2 = 4,
parameter VAR3 = VAR2-1,
parameter VAR1 = 3)
(
input VAR5,
input VAR8,
input VAR9,
input VAR11,
input [VAR16:0] VAR18,
output VAR15,
output VAR7,
output VAR12,
output [VAR16:0] VAR4,
output [VAR16:0] VAR17
);
reg [VAR16:0] VAR13 = {VAR14... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbn/sky130_fd_sc_ls__dfbbn.behavioral.pp.v | 2,820 | module MODULE1 (
VAR1 ,
VAR20 ,
VAR6 ,
VAR28 ,
VAR22 ,
VAR12,
VAR7 ,
VAR17 ,
VAR29 ,
VAR21
);
output VAR1 ;
output VAR20 ;
input VAR6 ;
input VAR28 ;
input VAR22 ;
input VAR12;
input VAR7 ;
input VAR17 ;
input VAR29 ;
input VAR21 ;
wire VAR13 ;
wire VAR25 ;
wire VAR11 ;
wire VAR9 ;
wire VAR30 ;
wire VAR26;
wire VAR23 ;... | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/sdram_0.v | 23,440 | module MODULE1 (
clk,
rd,
VAR49,
wr,
VAR65,
VAR39,
VAR76,
VAR55,
VAR71,
VAR27
)
;
output VAR39;
output VAR76;
output VAR55;
output VAR71;
output [ 40: 0] VAR27;
input clk;
input rd;
input VAR49;
input wr;
input [ 40: 0] VAR65;
wire VAR39;
wire VAR76;
wire VAR55;
reg [ 1: 0] VAR48;
reg [ 40: 0] VAR36;
reg [ 40: 0] VAR40... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv.pp.symbol.v | 1,238 | module MODULE1 (
input VAR6 ,
output VAR4 ,
input VAR5 ,
input VAR1,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
CospanDesign/python | game/panda/panda_path/example_project/rtl/dependencies/dual_port_bram.v | 1,422 | module MODULE1 #(
parameter VAR1 = 32,
parameter VAR12 = 10,
parameter VAR7 = "VAR5",
parameter VAR11 = 0
) (
VAR15,
VAR4,
VAR3,
VAR6,
VAR8,
VAR9,
VAR14,
VAR13,
VAR16,
VAR10
);
input VAR15;
input VAR4;
input wire [VAR12 - 1: 0] VAR3;
input wire [VAR1 - 1: 0] VAR6;
output reg [VAR1 - 1: 0] VAR8;
input VAR9;
input VAR14;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah.functional.v | 1,648 | module MODULE1 (
VAR13,
VAR8 ,
VAR5 ,
VAR9 ,
VAR10
);
output VAR13;
output VAR8 ;
input VAR5 ;
input VAR9 ;
input VAR10 ;
wire VAR7;
wire VAR2 ;
wire VAR15 ;
wire VAR4 ;
wire VAR1;
xor VAR14 (VAR7, VAR5, VAR9, VAR10 );
buf VAR3 (VAR8 , VAR7 );
and VAR11 (VAR2 , VAR5, VAR9 );
and VAR12 (VAR15 , VAR5, VAR10 );
and VAR6 (... | apache-2.0 |
jmahler/EECE344-Digital_System_Design | lab01/lattice-grey_code_counter/grey_counter.v | 1,806 | module MODULE1(input clk, output reg [7:0] VAR1);
reg [7:0] VAR2;
always @(posedge clk) begin
if (0 == VAR2)
VAR1 <= 8'b00000000;
end
else if (1 == VAR2)
VAR1[0] <= 1;
else if (2 == VAR2)
VAR1[1] <= 1;
else if (4 == VAR2)
VAR1[2] <= 1;
else if (8 == VAR2)
VAR1[3] <= 1;
else if (16 == VAR2)
VAR1[4] <= 1;
else if (32 == ... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/common/wb_ppfifo_2_mem/rtl/wb_ppfifo_2_mem.v | 9,358 | module MODULE1(
input clk,
input rst,
output [31:0] VAR12,
input VAR19,
input [31:0] VAR26,
input [31:0] VAR31,
output [31:0] VAR22,
input VAR25,
output VAR47,
output VAR36,
output [31:0] VAR15,
input [31:0] VAR27,
input [31:0] VAR21,
output [31:0] VAR46,
input VAR11,
output VAR18,
output VAR8,
output [31:0] VAR45,
out... | mit |
jcrono/sd-host | src/common/serializer.v | 1,201 | module MODULE1(
clk, reset, enable, in,
VAR1, out );
parameter VAR3 = 32; parameter VAR2 = 6;
input clk, reset, enable;
input [VAR3-1:0] in;
output reg VAR1;
output reg out;
reg [5:0] counter;
always@(posedge clk) begin
if (reset==1) begin
counter <= 6'b000000;
VAR1 <=0;
end
else begin
if(enable && ~(counter==VAR3)) be... | gpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/sys_pll/sys_pll/sys_pll_0002.v | 2,206 | module MODULE1(
input wire VAR17,
input wire rst,
output wire VAR32,
output wire VAR7,
output wire VAR12,
output wire VAR9
);
VAR38 #(
.VAR8("false"),
.VAR23("50.0 VAR19"),
.VAR24("VAR37"),
.VAR54(3),
.VAR42("100.000000 VAR19"),
.VAR73("0 VAR70"),
.VAR48(50),
.VAR44("12.000000 VAR19"),
.VAR34("0 VAR70"),
.VAR53(50),
.V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai_4.v | 2,441 | module MODULE1 (
VAR12 ,
VAR9 ,
VAR5 ,
VAR10 ,
VAR3 ,
VAR8 ,
VAR7,
VAR6,
VAR11 ,
VAR4
);
output VAR12 ;
input VAR9 ;
input VAR5 ;
input VAR10 ;
input VAR3 ;
input VAR8 ;
input VAR7;
input VAR6;
input VAR11 ;
input VAR4 ;
VAR2 VAR1 (
.VAR12(VAR12),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3/sky130_fd_sc_hdll__nand3.functional.v | 1,299 | module MODULE1 (
VAR2,
VAR1,
VAR3,
VAR6
);
output VAR2;
input VAR1;
input VAR3;
input VAR6;
wire VAR7;
nand VAR4 (VAR7, VAR3, VAR1, VAR6 );
buf VAR5 (VAR2 , VAR7 );
endmodule | apache-2.0 |
qinfengling/de0nano_musicbox | musicbox.v | 3,840 | module MODULE1(
input clk,
input [7:0] address,
output reg [7:0] VAR13
);
always @(posedge clk)
case(address)
0, 1: VAR13 <= 8'd27; 2: VAR13 <= 8'd29; 3: VAR13 <= 8'd27; 4: VAR13 <= 8'd32; 5: VAR13 <= 8'd31; 6: VAR13 <= 8'd0;
7, 8: VAR13 <= 8'd27; 9: VAR13 <= 8'd29; 10: VAR13 <= 8'd27; 11: VAR13 <= 8'd34; 12: VAR13 <= ... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/vfabric_register.v | 1,647 | module MODULE1(VAR3, VAR10, VAR1, VAR11, VAR12, VAR8, VAR9, VAR13, VAR6, VAR4);
parameter VAR2 = 32;
input VAR3, VAR10, VAR1;
input [VAR2-1:0] VAR11;
input [VAR2-1:0] VAR12;
input VAR8;
output VAR9;
output [VAR2-1:0] VAR13;
output VAR6;
input VAR4;
VAR5 VAR7 (.VAR3(VAR3), .VAR10(VAR10), .VAR1(VAR1),
.VAR8(VAR8), .VAR9(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi.functional.v | 1,543 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR10 ,
VAR4
);
output VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR4;
wire VAR2 ;
wire VAR5 ;
wire VAR3;
not VAR9 (VAR2 , VAR4 );
and VAR1 (VAR5 , VAR7, VAR10 );
nor VAR11 (VAR3, VAR2, VAR5 );
buf VAR6 (VAR8 , VAR3 );
endmodule | apache-2.0 |
freecores/sha3 | low_throughput_core/rtl/padder1.v | 1,135 | module MODULE1(in, VAR1, out);
input [31:0] in;
input [1:0] VAR1;
output reg [31:0] out;
always @ (*)
case (VAR1)
0: out = 32'h1000000;
1: out = {in[31:24], 24'h010000};
2: out = {in[31:16], 16'h0100};
3: out = {in[31:8], 8'h01};
endcase
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai.functional.pp.v | 2,234 | module MODULE1 (
VAR14 ,
VAR1 ,
VAR12 ,
VAR11 ,
VAR20 ,
VAR18 ,
VAR2,
VAR6,
VAR13 ,
VAR17
);
output VAR14 ;
input VAR1 ;
input VAR12 ;
input VAR11 ;
input VAR20 ;
input VAR18 ;
input VAR2;
input VAR6;
input VAR13 ;
input VAR17 ;
wire VAR8 ;
wire VAR10 ;
wire VAR4 ;
wire VAR5;
or VAR7 (VAR8 , VAR20, VAR11 );
or VAR15 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41a/sky130_fd_sc_ms__o41a.pp.blackbox.v | 1,400 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR4 ,
VAR7,
VAR2,
VAR9 ,
VAR8
);
output VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR9 ;
input VAR8 ;
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/8-way_8-parallel/ise/ipcore_dir/dram/example_design/rtl/traffic_gen/mig_7series_v1_9_cmd_prbs_gen.v | 10,591 | module MODULE1 #
(
parameter VAR19 = 100,
parameter VAR1 = "VAR7",
parameter VAR3 = 8,
parameter VAR5 = 29,
parameter VAR22 = 32,
parameter VAR9 = "VAR6", parameter VAR24 = 64, parameter VAR20 = 32,
parameter VAR16 = 32'hFFFFD000,
parameter VAR18 = 32'h00002000,
parameter VAR11 = 32'h00002000,
parameter VAR17 = 32'h000... | mit |
545/Atari7800 | core/ag_6502/trunk/digger/chip1.v | 2,915 | module MODULE3(input clk,
input VAR29, input VAR38,
output wire VAR54, output wire VAR12);
reg VAR3 = 0, VAR52 = 0;
assign VAR54 = VAR52, VAR12 = VAR3;
always @(posedge clk) begin
case ({VAR29, VAR38})
2'b00: VAR3 <= 1;
2'b11: VAR3 <= 0;
2'b10: VAR52 <= 1;
2'b01: VAR52 <= 0;
endcase
end
endmodule
module MODULE1(input c... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.functional.v | 1,158 | module MODULE1( VAR1, VAR2, VAR10 );
input VAR2, VAR1;
output VAR10;
wire VAR5;
and VAR9( VAR5, VAR2, VAR1 );
wire VAR4;
not VAR3( VAR4, VAR2 );
wire VAR11;
not VAR6( VAR11, VAR1 );
wire VAR8;
and VAR7( VAR8, VAR4, VAR11 );
or VAR12( VAR10, VAR5, VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2_2.v | 2,187 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR6 ,
VAR1 ,
VAR2,
VAR3,
VAR5 ,
VAR10
);
output VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR2;
input VAR3;
input VAR5 ;
input VAR10 ;
VAR8 VAR9 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_id_track.v | 6,112 | module MODULE1
parameter VAR24 = 1
) (
input VAR16 ,
input VAR7 ,
input [VAR24-1:0] VAR10 ,
input VAR20 ,
input [VAR24-1:0] VAR13 ,
input [3:0] VAR2 ,
input VAR27,
output [3:0] VAR1 ,
output [3:0] VAR9,
output [3:0] VAR14
);
reg [VAR24:0] VAR17, VAR30, VAR21, VAR22;
reg [3:0] VAR31, VAR4;
reg [3:0] VAR5;
wire [VAR24:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0n/sky130_fd_sc_lp__iso0n.blackbox.v | 1,271 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR3
);
output VAR4 ;
input VAR7 ;
input VAR3;
supply1 VAR6 ;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2.functional.pp.v | 1,902 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR13,
VAR15,
VAR4 ,
VAR11
);
output VAR10 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR13;
input VAR15;
input VAR4 ;
input VAR11 ;
wire VAR12 ;
wire VAR9;
VAR1 VAR2 (VAR12 , VAR6, VAR5, VAR8 );
VAR3 VAR14 (VAR9, VAR12, VAR13, VAR15);
buf VAR7 (VAR10 , VAR9 );
endmodul... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn.symbol.v | 1,341 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR7
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
ptracton/vscale_soc | rtl/uart16550-1.5.4/bench/verilog/uart_log.v | 6,749 | module MODULE1;
parameter VAR10 = "";
integer VAR23;
integer VAR47;
reg VAR26;
integer VAR43;
integer VAR15;
VAR42 VAR26 = 1;
VAR42 VAR43 = 0;
VAR42 VAR15 = 0;
task VAR12;
output VAR27;
begin
VAR23 =
VAR47 =
if ((VAR23 == 0) || (VAR47 == 0))
VAR27 = 1'b0;
end
else
VAR27 = 1'b1;
end
endtask
task VAR4;
begin
VAR39;
VAR44... | mit |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkBoot_ROM.v | 58,273 | module MODULE1(VAR25,
VAR96,
VAR87,
VAR162,
VAR110,
VAR135,
VAR57,
VAR95,
VAR71,
VAR97,
VAR179,
VAR128,
VAR14,
VAR173,
VAR64,
VAR152,
VAR23,
VAR17,
VAR18,
VAR148,
VAR35,
VAR125,
VAR168,
VAR155,
VAR33,
VAR42,
VAR177,
VAR153,
VAR93,
VAR116,
VAR85,
VAR15,
VAR147,
VAR172,
VAR142,
VAR86,
VAR104,
VAR102,
VAR4,
VAR120,
VAR167... | apache-2.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_key_2.v | 1,897 | module MODULE1 (
address,
clk,
VAR1,
VAR4,
VAR6
)
;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input clk;
input VAR1;
input VAR4;
wire VAR3;
wire VAR2;
wire VAR5;
reg [ 31: 0] VAR6;
assign VAR3 = 1;
assign VAR5 = {1 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR4)
begin
if (VAR4 == 0)
VAR6 <= 0;
end
el... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtp/sky130_fd_sc_lp__dlrtp.blackbox.v | 1,366 | module MODULE1 (
VAR7 ,
VAR6,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR6;
input VAR3 ;
input VAR5 ;
supply1 VAR2;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx2mb/rtl/mb2cpx.v | 3,926 | module MODULE1 (
VAR8,
VAR9,
VAR5,
VAR14,
VAR18,
VAR7,
VAR6,
VAR15
);
parameter VAR1 = (((VAR4+1-1)/VAR17)+1);
parameter VAR12 = (VAR17 * VAR1) -
(VAR4+1);
output VAR8;
output [VAR4-1:0] VAR9;
output VAR5;
input VAR14;
input VAR18;
input VAR7;
input VAR6;
input [VAR17-1:0] VAR15;
wire VAR8;
wire [VAR4-1:0] VAR9;
wire V... | gpl-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_ram_arbiter.v | 14,688 | module MODULE1 (
VAR32, VAR25,
VAR27, VAR4, VAR31, VAR5, VAR33,
VAR30, VAR10, VAR50, VAR1, VAR26, VAR22,
VAR45, VAR13, VAR11, VAR17, VAR14,
VAR35, VAR8, VAR29, VAR44, VAR28,
VAR34, VAR36, VAR23, VAR9, VAR42, VAR15,
VAR48, VAR19, VAR46, VAR21, VAR38, VAR47,
VAR40, VAR3, VAR7, VAR6, VAR39
);
input VAR32; input VAR25;
inp... | bsd-3-clause |
ptracton/wb_soc_template | rtl/ZIP/rtl/dblfetch.v | 7,164 | module MODULE1(VAR11, VAR17, VAR1, VAR4,
VAR28, VAR30, VAR14, VAR12, VAR18,
VAR2, VAR25, VAR6, VAR3, VAR7,
VAR27, VAR5, VAR10, VAR22,
VAR13);
parameter VAR26=32, VAR20 = 1;
localparam VAR16=VAR26;
input wire VAR11, VAR17, VAR1, VAR4,
VAR28;
input wire [(VAR16-1):0] VAR30;
output reg [31:0] VAR14;
output reg [(VAR16-1):... | mit |
titorgalaxy/Titor | rtl/verilog/led/LED.v | 1,695 | module MODULE1(
dout,
din,
address,
VAR1,
VAR4,
enable,
VAR2,
reset,
clk
);
output reg [VAR3-1:0] dout;
input wire [VAR3-1:0] din;
input wire [VAR3-1:0] address;
input wire [VAR6-1:0] VAR1;
input wire VAR4;
input wire enable;
output wire [VAR3-1:0] VAR2;
input reset;
input clk;
reg [VAR3-1:0] VAR9;
assign VAR2 = VAR9;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fa/sky130_fd_sc_ms__fa_2.v | 2,278 | module MODULE1 (
VAR3,
VAR4 ,
VAR11 ,
VAR7 ,
VAR1 ,
VAR8,
VAR2,
VAR10 ,
VAR5
);
output VAR3;
output VAR4 ;
input VAR11 ;
input VAR7 ;
input VAR1 ;
input VAR8;
input VAR2;
input VAR10 ;
input VAR5 ;
VAR6 VAR9 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch_1.v | 2,378 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR6,
VAR2 ,
VAR1 ,
VAR9 ,
VAR5
);
output VAR7 ;
input VAR4 ;
input VAR6;
input VAR2 ;
input VAR1 ;
input VAR9 ;
input VAR5 ;
VAR8 VAR3 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR7 ,
VAR4 ,
VAR6
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b_4.v | 2,311 | module MODULE2 (
VAR11 ,
VAR2 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR3,
VAR4,
VAR8 ,
VAR9
);
output VAR11 ;
input VAR2 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR3;
input VAR4;
input VAR8 ;
input VAR9 ;
VAR7 VAR6 (
.VAR11(VAR11),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.... | apache-2.0 |
pwpiwi/proxmark3 | fpga/hi_iso14443a.v | 19,223 | module MODULE1(
VAR23, VAR12, VAR45,
VAR59, VAR62, VAR40, VAR6, VAR4, VAR43,
VAR54, VAR36,
VAR24, VAR32, VAR33, VAR22,
VAR7, VAR14,
VAR42,
VAR35
);
input VAR23, VAR12, VAR45;
output VAR59, VAR62, VAR40, VAR6, VAR4, VAR43;
input [7:0] VAR54;
output VAR36;
input VAR33;
output VAR24, VAR32, VAR22;
input VAR7, VAR14;
outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31o/sky130_fd_sc_hs__a31o.behavioral.v | 1,920 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR5 ,
VAR11 ,
VAR15 ,
VAR2,
VAR10
);
output VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR11 ;
input VAR15 ;
input VAR2;
input VAR10;
wire VAR15 VAR4 ;
wire VAR14 ;
wire VAR6;
and VAR12 (VAR4 , VAR11, VAR9, VAR5 );
or VAR3 (VAR14 , VAR4, VAR15 );
VAR13 VAR7 (VAR6, VAR14, VAR2, VAR10);
buf VA... | apache-2.0 |
qiuzou/nysa_saya | rtl/link/sata_link_layer_write.v | 15,989 | module MODULE1(
input rst, input clk,
input VAR56,
output VAR82,
input en,
output VAR53,
input VAR46,
input VAR26,
input VAR44,
input VAR95,
input VAR17,
input VAR107,
input VAR61,
input VAR15,
input VAR54,
input VAR71,
input VAR69,
output reg VAR57,
output [31:0] VAR19,
output VAR16,
input [31:0] VAR32,
input [3:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn.behavioral.v | 2,976 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR4 ,
VAR15 ,
VAR26 ,
VAR8
);
output VAR6 ;
input VAR10 ;
input VAR4 ;
input VAR15 ;
input VAR26 ;
input VAR8;
supply1 VAR23;
supply0 VAR22;
supply1 VAR24 ;
supply0 VAR18 ;
wire VAR25 ;
wire VAR2 ;
wire VAR7 ;
wire VAR11 ;
reg VAR1 ;
wire VAR32 ;
wire VAR9 ;
wire VAR17 ;
wire VAR21;
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.v | 2,461 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR3 ,
VAR8 ,
VAR6 ,
VAR12 ,
VAR9,
VAR5,
VAR7 ,
VAR2
);
output VAR11 ;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR12 ;
input VAR9;
input VAR5;
input VAR7 ;
input VAR2 ;
VAR10 VAR1 (
.VAR11(VAR11),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR9(... | apache-2.0 |
aj-michael/Digital-Systems | Lab6-Part2/lab6phase2I2C2015fall.v | 2,062 | module MODULE1(VAR6,VAR3,VAR41,VAR8,VAR2,VAR4,VAR28,VAR45,VAR9,VAR14,VAR33,VAR11);
input VAR28, VAR41, VAR45, VAR3;
input [2:0] VAR6;
output VAR2, VAR9, VAR14;
inout VAR4;
output [7:0] VAR8;
output [3:0] VAR11;
output [7:0] VAR33;
parameter VAR36=20'd40000, VAR40=30'd65000000;
wire VAR30;
VAR32 VAR43(VAR45,VAR30,VAR9);... | mit |
kyzhai/NUNY | src/hardware/bg2_new.v | 6,392 | module MODULE1 (
address,
VAR18,
VAR19);
input [14:0] address;
input VAR18;
output [11:0] VAR19;
tri1 VAR18;
wire [11:0] VAR2;
wire [11:0] VAR19 = VAR2[11:0];
VAR9 VAR27 (
.VAR31 (address),
.VAR23 (VAR18),
.VAR45 (VAR2),
.VAR41 (1'b0),
.VAR36 (1'b0),
.VAR32 (1'b1),
.VAR30 (1'b0),
.VAR8 (1'b0),
.VAR46 (1'b1),
.VAR1 (1'b... | gpl-2.0 |
liqimai/ZPC | PersonalComputer/MultiCycleCpu.v | 6,991 | module MODULE1(
input clk,
input VAR2,
input[31:0] VAR9,
input VAR17,
input[31:0] VAR16,
output[31:0] VAR13,
output VAR6,
output VAR5,
output VAR14,
output VAR1,
output[31:0] VAR7,
output VAR15,
input[4:0] VAR8,
output[31:0] VAR3,
output[31:0] VAR12,
output[31:0] VAR11,
output reg[31:0] VAR4
);
reg[31:0] VAR10; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf.behavioral.v | 1,341 | module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR9;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
wire VAR5;
buf VAR8 (VAR5, VAR1 );
buf VAR3 (VAR2 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv.blackbox.v | 1,304 | module MODULE1 (
VAR3,
VAR6
);
output VAR3;
input VAR6;
supply1 VAR4 ;
supply0 VAR1 ;
supply1 VAR7;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/scfifo_32in_32out_1kb/scfifo_32in_32out_1kb_stub.v | 1,441 | module MODULE1(clk, rst, din, VAR1, VAR3, dout, VAR4, VAR2)
;
input clk;
input rst;
input [31:0]din;
input VAR1;
input VAR3;
output [31:0]dout;
output VAR4;
output VAR2;
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/ddr3_s4_uniphy_example.v | 24,101 | module MODULE1 (
input wire VAR10, input wire VAR107, input wire VAR115, output wire [12:0] VAR188, output wire [2:0] VAR157, output wire VAR3, output wire VAR104, output wire VAR195, output wire VAR13, output wire [1:0] VAR73, output wire VAR102, output wire VAR161, output wire VAR145, output wire VAR50, inout wire [1... | lgpl-3.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v | 18,004 | module MODULE1
VAR13 = 2,
VAR15 = 3,
VAR18 = 1,
VAR28 = 4
)
(
VAR25,
VAR31,
VAR17,
VAR8,
VAR9,
VAR4,
VAR3,
VAR20,
VAR12,
VAR35
);
localparam integer VAR1 = 2**VAR28; localparam VAR30 = 2;
localparam VAR29 = 2.5;
input VAR25;
input VAR31;
input [VAR28-1:0] VAR17;
input [VAR15-1:0] VAR8;
input [4:0] VAR9;
input [VAR18-1:... | gpl-3.0 |
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