repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/saed_90/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v | 2,748 | if (VAR9 == VAR30 && VAR19 == VAR46) \
begin: VAR43 \
VAR4 VAR45 \
(.VAR33 (VAR2) \
,.VAR23 (~VAR12) \
,.VAR35 (1'b0) \
,.VAR36 (~VAR27) \
,.VAR14 (VAR6) \
,.VAR17 (VAR37) \
,.VAR5 (VAR22) \
,.VAR8 (VAR21) \
); \
end
module MODULE1 #(parameter VAR18(VAR9 )
,parameter VAR18(VAR19 )
,parameter VAR44 = VAR7(VAR9)
,paramet... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o.behavioral.pp.v | 1,994 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR12 ,
VAR15 ,
VAR16,
VAR9,
VAR5 ,
VAR7
);
output VAR6 ;
input VAR8 ;
input VAR12 ;
input VAR15 ;
input VAR16;
input VAR9;
input VAR5 ;
input VAR7 ;
wire VAR4 ;
wire VAR2 ;
wire VAR10;
and VAR11 (VAR4 , VAR8, VAR12 );
or VAR3 (VAR2 , VAR4, VAR15 );
VAR1 VAR14 (VAR10, VAR2, VAR16, VAR9);
... | apache-2.0 |
AndreaCorallo/KPU | rtl/kpu/tap.v | 19,012 | module MODULE1(
VAR49,
VAR35,
VAR74,
VAR86,
VAR37,
VAR40,
VAR77,
VAR3,
VAR55,
VAR43,
VAR90,
VAR66,
VAR27,
VAR14,
VAR73,
VAR44,
VAR65,
VAR63,
VAR10,
VAR42, VAR91, VAR18, VAR12, VAR69, );
input VAR49; input VAR35; input VAR74; input VAR86; output VAR37; output VAR40;
output VAR77;
output VAR3;
output VAR55;
output VAR43;... | gpl-3.0 |
olajep/oh | src/zcu102/hdl/zcu102_base.v | 18,401 | module MODULE1(
VAR114, VAR51, VAR22, VAR50, VAR75,
VAR23, VAR74, VAR89, VAR53, VAR63,
VAR27, VAR72, VAR108, VAR107, VAR28,
VAR17, VAR59, VAR84, VAR118,
VAR13, VAR4, VAR31, VAR101, VAR49,
VAR26, VAR8, VAR65, VAR29,
VAR64, VAR14, VAR109, VAR79,
VAR131, VAR30, VAR16, VAR123,
VAR56, VAR55, VAR11, VAR116, VAR5, VAR39,
VAR1... | mit |
bigeagle/riffa | fpga/riffa_hdl/syncff.v | 2,623 | module MODULE1
(
input VAR2,
input VAR4,
output VAR7
);
wire VAR8;
VAR5
VAR6
(
.VAR2(VAR2),
.VAR9(VAR4),
.VAR3(VAR8)
);
VAR5 VAR1 (
.VAR2(VAR2),
.VAR9(VAR8),
.VAR3(VAR7)
);
endmodule | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.functional.v | 1,064 | module MODULE1( VAR5, VAR12, VAR4, VAR3, VAR10 );
input VAR4, VAR12, VAR5, VAR10;
output VAR3;
or VAR7( VAR6, VAR12, VAR5 );
VAR2( VAR8, 1'b0, 1'b0, VAR4, VAR6, VAR10 );
wire VAR1;
not VAR9( VAR1, VAR8 );
or VAR11( VAR3, VAR4, VAR1 );
endmodule | apache-2.0 |
Tao-J/nexys3MIPSSoC | data_path.v | 4,918 | module MODULE1(clk,
reset,
VAR61,
VAR10,
VAR1,
VAR42,
VAR55,
VAR44,
VAR50,
VAR12,
VAR25,
VAR60,
VAR56,
VAR3,
VAR52,
VAR49,
VAR47,
VAR45,
VAR68,
VAR65,
VAR36,
VAR62,
VAR59,
VAR41,
VAR70,
VAR23,
);
input clk,reset;
input VAR61,VAR10,VAR1,VAR55,VAR50,VAR60,VAR56,VAR3,VAR59,VAR70,VAR23;
input [1:0] VAR42,VAR12,VAR41;
input... | gpl-3.0 |
alexforencich/xfcp | example/Atlys/fpga/rtl/fpga.v | 4,434 | module MODULE1 (
input wire clk,
input wire VAR35,
input wire VAR64,
input wire VAR27,
input wire VAR39,
input wire VAR37,
input wire VAR24,
input wire [7:0] VAR19,
output wire [7:0] VAR5,
input wire VAR80,
input wire [7:0] VAR42,
input wire VAR3,
input wire VAR70,
output wire VAR30,
input wire VAR56,
output wire [7:0]... | mit |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/ip_dram/controller/mig_7series_v2_3_bank_mach.v | 31,504 | module MODULE1 #
(
parameter VAR33 = 100,
parameter VAR3 = "VAR93",
parameter VAR107 = "1T",
parameter VAR71 = 3,
parameter VAR43 = 2,
parameter VAR42 = "8",
parameter VAR36 = 12,
parameter VAR66 = 4,
parameter VAR27 = 5,
parameter VAR138 = 5,
parameter VAR120 = 8,
parameter VAR152 = "VAR183",
parameter VAR37 = "VAR93"... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.behavioral.v | 18,312 | module MODULE1( VAR44, VAR172, VAR40, VAR85, VAR5, VAR103 );
input VAR85, VAR40, VAR5, VAR44, VAR172;
output VAR103;
reg VAR211;
VAR253 VAR215(.VAR44(VAR44),.VAR172(VAR172),.VAR40(VAR40),.VAR85(VAR85),.VAR5(VAR5),.VAR103(VAR103),.VAR211(VAR211));
VAR253 VAR302(.VAR44(VAR44),.VAR172(VAR172),.VAR40(VAR40),.VAR85(VAR85),.... | apache-2.0 |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/decimal_select.v | 1,436 | module MODULE1(
VAR1,
VAR2
);
input [1:0] VAR1;
output VAR2;
assign VAR2 = (VAR1 == 2'b11) ? 1'b1 :
(VAR1 == 2'b10) ? 1'b1 :
(VAR1 == 2'b01) ? 1'b1 :
1'b1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.behavioral.v | 2,843 | module MODULE1 (
VAR2 ,
VAR16 ,
VAR13 ,
VAR14 ,
VAR22 ,
VAR24
);
output VAR2 ;
input VAR16 ;
input VAR13 ;
input VAR14 ;
input VAR22 ;
input VAR24;
supply1 VAR21;
supply0 VAR23;
supply1 VAR31 ;
supply0 VAR17 ;
wire VAR8 ;
wire VAR30 ;
wire VAR4 ;
reg VAR7 ;
wire VAR20 ;
wire VAR6 ;
wire VAR15 ;
wire VAR12;
wire VAR29 ;... | apache-2.0 |
rkrajnc/minimig-mist | rtl/sdram/tpram_be_512x16.v | 9,733 | module MODULE1 (
VAR30,
VAR4,
VAR29,
VAR14,
VAR36,
VAR5,
VAR55);
input [1:0] VAR30;
input VAR4;
input [15:0] VAR29;
input [8:0] VAR14;
input [8:0] VAR36;
input VAR5;
output [15:0] VAR55;
tri1 [1:0] VAR30;
tri1 VAR4;
tri0 VAR5;
wire [15:0] VAR46;
wire [15:0] VAR55 = VAR46[15:0];
VAR33 VAR40 (
.VAR3 (VAR36),
.VAR30 (VAR3... | gpl-3.0 |
somethingnew2-0/CS552-CPU | RoadRunner/provided_modules/data_mem.v | 1,029 | module MODULE1(clk,addr,VAR2,VAR3,VAR1,VAR4);
input clk;
input [15:0] addr;
input VAR2; input VAR3; input [15:0] VAR1;
output reg [15:0] VAR4;
reg [15:0]VAR5[0:65535];
always @(addr,VAR2,clk)
if (~clk && VAR2 && ~VAR3)
VAR4 <= VAR5[addr];
always @(posedge clk)
if (VAR3 && ~VAR2)
VAR5[addr] <= VAR1;
endmodule | mit |
Tao-J/nexys3MIPSSoC | Muliti_cycle_Cpu.v | 3,008 | module MODULE1( clk,
reset,
VAR6,
VAR14, VAR21, VAR36,
VAR5,
VAR32,
VAR13,
VAR18,
VAR41,
state,
VAR40,
VAR33,
VAR43
);
input clk,reset,VAR6,VAR40,VAR43;
output [31:0] VAR14;
output [31:0] VAR21;
output VAR36, VAR18, VAR41,VAR33;
output [31:0] VAR5;
output [31:0] VAR32;
output [4:0] state;
input [31:0] VAR13;
wire [31:0... | gpl-3.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/mpx/mpx.v | 42,539 | module MODULE1
(
VAR31,
VAR96,
VAR5,
VAR95,
VAR70,
VAR47,
VAR75,
VAR14,
VAR7,
VAR129,
VAR53,
VAR77,
VAR64,
VAR63,
VAR132
);
parameter [31:0] VAR80 = 32'h00000000;
parameter [31:0] VAR15 = 32'h0000003C;
input VAR31 ;
input VAR96 ;
input VAR5 ;
input VAR95 ;
output VAR47 ;
output VAR70 ;
output [31:0] VAR75 ;
output [31:... | mit |
alexforencich/xfcp | lib/eth/example/S10DX_DK/fpga_10g/rtl/fpga.v | 20,371 | module MODULE1 (
input wire VAR164,
input wire VAR280,
input wire VAR275,
output wire [3:0] VAR169,
output wire [3:0] VAR139,
output wire [3:0] VAR226,
input wire [3:0] VAR211,
input wire [3:0] VAR173,
output wire [3:0] VAR105,
output wire [3:0] VAR31,
input wire [3:0] VAR241,
input wire [3:0] VAR50,
input wire VAR149
... | mit |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_sysid_qsys.v | 1,419 | module MODULE1 (
address,
VAR2,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR2;
input VAR3;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1403034160 : 2899645186;
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/ddr3_s4_amphy_controller_phy.v | 16,204 | module MODULE1 (
VAR79,
VAR28,
VAR56,
VAR159,
VAR44,
VAR123,
VAR118,
VAR125,
VAR47,
VAR58,
VAR149,
VAR145,
VAR84,
VAR41,
VAR115,
VAR34,
VAR101,
VAR24,
VAR78,
VAR114,
VAR37,
VAR25,
VAR27,
VAR17,
VAR11,
VAR82,
VAR71,
VAR70,
VAR150,
VAR65,
VAR73,
VAR148,
VAR139,
VAR171,
VAR85,
VAR76,
VAR35,
VAR22,
VAR124,
VAR55,
VAR19,
VA... | lgpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_flash_qspi_top.v | 24,431 | module MODULE1(
input clk,
input VAR108,
input VAR47,
output VAR17,
input [32-1:0] VAR5,
input VAR86,
input [32-1:0] VAR141,
output VAR119,
input VAR35,
output [32-1:0] VAR41,
input VAR197,
output VAR170,
input [32-1:0] VAR178,
input VAR150,
input [32-1:0] VAR185,
output VAR111,
input VAR115,
output [32-1:0] VAR106,
ou... | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_axi_mc_aw_channel.v | 10,654 | module MODULE1 #
(
parameter integer VAR38 = 4,
parameter integer VAR5 = 32,
parameter integer VAR28 = 30,
parameter integer VAR48 = 32,
parameter integer VAR43 = 1,
parameter integer VAR57 = 2,
parameter integer VAR20 = 2,
parameter VAR6 = "VAR24"
)
(
input wire clk ,
input wire reset ,
input wire [VAR38-1:0] VAR56 ,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b_4.v | 2,318 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR3 ,
VAR1 ,
VAR8 ,
VAR10,
VAR6,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR10;
input VAR6;
input VAR2 ;
input VAR7 ;
VAR9 VAR11 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/747b0ef18f7ea24b/ip_design_lms_pcore_0_0_stub.v | 2,559 | module MODULE1(VAR2, VAR5, VAR20,
VAR13, VAR1, VAR18, VAR17, VAR10,
VAR15, VAR12, VAR8, VAR4,
VAR11, VAR6, VAR21, VAR7, VAR3,
VAR19, VAR9, VAR14, VAR16)
;
input VAR2;
input VAR5;
input VAR20;
input VAR13;
input [15:0]VAR1;
input VAR18;
input [31:0]VAR17;
input [3:0]VAR10;
input VAR15;
input VAR12;
input [15:0]VAR8;
inp... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/system_acl_iface_hps.v | 16,175 | module MODULE1 #(
parameter VAR37 = 0,
parameter VAR65 = 0
) (
output wire VAR74, input wire VAR56, output wire [11:0] VAR30, output wire [20:0] VAR15, output wire [3:0] VAR26, output wire [2:0] VAR46, output wire [1:0] VAR18, output wire [1:0] VAR11, output wire [3:0] VAR62, output wire [2:0] VAR7, output wire VAR87, ... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk.v | 7,774 | module MODULE1 (
clk,
VAR31,
VAR9,
VAR8,
VAR11,
VAR27,
VAR12,
VAR22,
VAR2,
VAR17,
VAR16,
VAR18,
VAR15,
VAR21,
VAR1,
VAR6,
VAR29,
VAR4,
VAR10
)
;
output [ 37: 0] VAR27;
output VAR12;
output VAR22;
output VAR2;
output VAR17;
output VAR16;
output VAR18;
output VAR15;
output VAR21;
output VAR1;
output VAR6;
output VAR29;
o... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr_8.v | 2,112 | module MODULE2 (
VAR1 ,
VAR3,
VAR2 ,
VAR4 ,
VAR6
);
input VAR1 ;
input VAR3;
input VAR2 ;
input VAR4 ;
input VAR6 ;
VAR7 VAR5 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR1 ;
supply1 VAR3;
supply0 VAR2 ;
supply1 VAR4 ;
supply0 VAR6 ;
VAR7 VAR5 ();
endmodul... | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_drp.v | 11,712 | module MODULE1 #
(
parameter VAR4 = 2'd1, parameter VAR24 = 1'd0
)
(
input VAR35,
input VAR9,
input VAR7,
input VAR25,
input [15:0] VAR3,
input VAR22,
output [ 8:0] VAR1,
output VAR39,
output [15:0] VAR32,
output VAR12,
output VAR31,
output [ 2:0] VAR8
);
reg VAR26;
reg VAR15;
reg [15:0] VAR20;
reg VAR14;
reg VAR2;
reg... | lgpl-3.0 |
takeshineshiro/fpga_linear_128 | butterfly_radix4_1st.v | 5,671 | module MODULE1(
input clk,
input[15:0] VAR26,
input[15:0] VAR28,
input[15:0] VAR39,
input[15:0] VAR16,
input[15:0] VAR12,
input[15:0] VAR55,
input[15:0] VAR56,
input[15:0] VAR66,
input[15:0] VAR13,
input[15:0] VAR40,
input[15:0] VAR10,
input[15:0] VAR75,
input[15:0] VAR54,
input[15:0] VAR42,
input[15:0] VAR5,
input[15:... | mit |
myriadrf/A2300 | hdl/wca/hal/FifoCore32w8r.v | 14,290 | module MODULE1(
rst,
VAR236,
VAR37,
din,
VAR204,
VAR13,
dout,
VAR245,
VAR327,
VAR323,
VAR89
);
input rst;
input VAR236;
input VAR37;
input [31 : 0] din;
input VAR204;
input VAR13;
output [7 : 0] dout;
output VAR245;
output VAR327;
output VAR323;
output VAR89;
VAR401 #(
.VAR126(0),
.VAR304(0),
.VAR104(0),
.VAR382(0),
.V... | gpl-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/menu_bg/menu_bg_stub.v | 1,268 | module MODULE1(VAR3, VAR1, VAR2, VAR5, VAR4)
;
input VAR3;
input [0:0]VAR1;
input [13:0]VAR2;
input [11:0]VAR5;
output [11:0]VAR4;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinv/sky130_fd_sc_hd__clkinv.behavioral.v | 1,347 | module MODULE1 (
VAR5,
VAR9
);
output VAR5;
input VAR9;
supply1 VAR2;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR3 ;
wire VAR4;
not VAR1 (VAR4, VAR9 );
buf VAR8 (VAR5 , VAR4 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_cpack/util_cpack.v | 12,478 | module MODULE1 (
VAR13,
VAR46,
VAR2,
VAR8,
VAR14,
VAR76,
VAR49,
VAR72,
VAR62,
VAR71,
VAR37,
VAR74,
VAR26,
VAR80,
VAR69,
VAR28,
VAR52,
VAR1,
VAR17,
VAR70,
VAR95,
VAR3,
VAR16,
VAR41,
VAR68,
VAR85,
VAR92,
VAR19,
VAR27);
parameter VAR33 = 32;
parameter VAR64 = 8;
localparam VAR18 = VAR33/16;
localparam VAR67 = 8;
localpara... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp.behavioral.pp.v | 2,097 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR8 ,
VAR11 ,
VAR2 ,
VAR16
);
input VAR12 ;
input VAR1 ;
output VAR8 ;
input VAR11 ;
input VAR2 ;
input VAR16;
wire VAR14 ;
wire VAR10 ;
reg VAR6 ;
wire VAR5 ;
wire VAR15;
wire VAR18 ;
wire VAR4 ;
wire VAR9 ;
wire VAR17 ;
not VAR13 (VAR10 , VAR15 );
VAR7 VAR19 (VAR14 , VAR5, VAR18, VAR1... | apache-2.0 |
securelyfitz/WTFpga | wtfpga-lab-solution/wtfpga.v | 1,062 | module MODULE1(
input VAR12,
input VAR14,
input VAR23,
input VAR6,
input VAR10,
input [7:0] VAR13,
output [4:0] VAR20,
output [6:0] VAR15,
output VAR7
);
wire [7:0] VAR5,VAR25;
wire VAR17;
reg [7:0] VAR11;
wire [7:0] VAR9, sum, VAR18;
assign VAR20[4:0]=VAR13[4:0];
assign sum=VAR11+VAR13;
assign VAR18=VAR11-VAR13;
assig... | gpl-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_ob_adv7181.v | 7,545 | module MODULE1 (
VAR3,
VAR5
);
parameter VAR1 = 16'h0040;
parameter VAR4 = 16'h2df4;
parameter VAR2 = 16'h2e00;
input [ 5: 0] VAR3;
output [26: 0] VAR5;
reg [23: 0] VAR6;
assign VAR5 = {VAR6[23:16], 1'b0,
VAR6[15: 8], 1'b0,
VAR6[ 7: 0], 1'b0};
always @(*)
begin
case (VAR3)
10 : VAR6 <= {8'h40, 16'h1500};
11 : VAR6 <= {... | mit |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | Traductor.v | 1,180 | module MODULE1(in,out,clk,rst);
input wire clk,rst;
input wire [3:0]in;
output reg [10:0]out;
always@(posedge clk, posedge rst)
if (rst)
begin
out <= 11'd0;
end
else
case(in)
4'b0000: out <= 11'd1666;
4'b0001: out <= 11'd999;
4'b0010: out <= 11'd666;
4'b0011: out <= 11'd499;
4'b0100: out <= 11'd399;
4'b0101: out <= 11'... | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/gainMult.v | 2,136 | module MODULE1(
input clk,
input [1:0] VAR7,
input signed [15:0] VAR12,
input signed [6:0] VAR11,
output reg signed [15:0] dout = 16'VAR6,
output reg VAR13 = 1'b0
);
parameter VAR14 = 1; parameter VAR3 = 5; parameter VAR9 = 23;
reg signed [15:0] VAR1 = 16'VAR6; reg signed [6:0] VAR4 = 7'VAR6, VAR8 = 7'VAR6;
reg signed ... | gpl-3.0 |
ShepardSiegel/ocpi | platform/alst4/golden_top.v | 18,152 | module MODULE1 (
input VAR73, input VAR48, input VAR30, input [1:1] VAR50, output VAR122,
output [14:0] VAR23, output [2:0] VAR79, output VAR28, output VAR97, output VAR22, output VAR127, output VAR126, output [7:0] VAR42, inout [63:0] VAR1, inout [7:0] VAR64, inout [7:0] VAR18, output VAR34, output VAR94, output VAR31... | lgpl-3.0 |
htuNCSU/MmcCommunicationVerilog | MAX10_SLAVE/phyInitial.v | 7,663 | module MODULE1 (
input clk,reset,
input VAR47,
input [3:0]VAR52,
input [31:0] VAR1,
input [15:0]VAR2,
inout VAR11,
output VAR18,
output reg [3: 0] VAR39,
output reg VAR36,
output reg [12:0]VAR13,
output [15:0]VAR12,
output VAR44,
output VAR37
);
wire VAR50;
wire VAR3, VAR35, VAR6, VAR25;
wire [15:0] VAR5;
wire [15:0] V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21a/sky130_fd_sc_hvl__o21a.behavioral.pp.v | 2,008 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR12 ,
VAR13 ,
VAR7,
VAR14,
VAR8 ,
VAR16
);
output VAR9 ;
input VAR11 ;
input VAR12 ;
input VAR13 ;
input VAR7;
input VAR14;
input VAR8 ;
input VAR16 ;
wire VAR5 ;
wire VAR2 ;
wire VAR6;
or VAR1 (VAR5 , VAR12, VAR11 );
and VAR10 (VAR2 , VAR5, VAR13 );
VAR4 VAR3 (VAR6, VAR2, VAR7, VAR14)... | apache-2.0 |
neale/CS-program | 474-VLSI/Lab_4/db/frame_rate_altpll.v | 4,559 | module MODULE1
(
VAR2,
clk,
VAR6,
VAR1) ;
input VAR2;
output [4:0] clk;
input [1:0] VAR6;
output VAR1;
tri0 VAR2;
tri0 [1:0] VAR6;
reg VAR4;
wire [4:0] VAR3;
wire VAR7;
wire VAR5; | unlicense |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_pipe_eq.v | 28,158 | module MODULE1
(
input VAR23,
input VAR26,
input VAR34,
input [ 1:0] VAR45,
input [ 3:0] VAR81,
input [ 3:0] VAR68,
input [ 5:0] VAR78,
input [ 1:0] VAR62,
input [ 2:0] VAR90,
input [ 5:0] VAR110,
input [ 3:0] VAR49,
output VAR44,
output [ 4:0] VAR59,
output [ 6:0] VAR27,
output [ 4:0] VAR103,
output [17:0] VAR64,
outp... | lgpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/MicrofonoFIFO/FSM.v | 1,558 | module MODULE1(reset,clk, VAR7, VAR8, VAR5, VAR3, wr, rd);
input wire reset;
input wire clk;
input wire VAR7;
input wire VAR8;
input wire VAR5;
input wire VAR3;
output reg wr;
output reg rd;
localparam VAR6 = 2'b00;
localparam VAR2 = 2'b01;
localparam VAR4 = 2'b11;
reg [1:0] VAR1 = VAR6;
reg [1:0] state = VAR6;
always@... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21a/sky130_fd_sc_hd__o21a.behavioral.v | 1,508 | module MODULE1 (
VAR4 ,
VAR1,
VAR6,
VAR8
);
output VAR4 ;
input VAR1;
input VAR6;
input VAR8;
supply1 VAR5;
supply0 VAR7;
supply1 VAR10 ;
supply0 VAR11 ;
wire VAR2 ;
wire VAR13;
or VAR9 (VAR2 , VAR6, VAR1 );
and VAR3 (VAR13, VAR2, VAR8 );
buf VAR12 (VAR4 , VAR13 );
endmodule | apache-2.0 |
ptracton/vscale_soc | rtl/uart16550-1.5.4/rtl/verilog/uart_rfifo.v | 10,950 | module MODULE1 (clk,
VAR28, VAR37, VAR26,
VAR39, VAR43, VAR14,
VAR35,
VAR17,
VAR22,
VAR1
);
parameter VAR15 = VAR8;
parameter VAR2 = VAR16;
parameter VAR11 = VAR25;
parameter VAR42 = VAR5;
input clk;
input VAR28;
input VAR39;
input VAR43;
input [VAR15-1:0] VAR37;
input VAR22;
input VAR1;
output [VAR15-1:0] VAR26;
outpu... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_SLVT_SS_210930.v | 231,331 | module MODULE1 (VAR6, VAR5, VAR4, VAR11, VAR8);
output VAR6;
input VAR5, VAR4, VAR11, VAR8;
wire VAR3, VAR7, VAR9;
wire VAR1, VAR2, VAR10;
not (VAR1, VAR8);
not (VAR9, VAR11);
not (VAR7, VAR4);
and (VAR2, VAR7, VAR9);
not (VAR3, VAR5);
and (VAR10, VAR3, VAR9);
or (VAR6, VAR10, VAR2, VAR1); | bsd-3-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Lundgren FPU/trunk/fpu_sub.v | 10,546 | module MODULE1( clk, rst, enable, VAR20, VAR16, VAR24, VAR5, VAR19, VAR31);
input clk;
input rst;
input enable;
input [63:0] VAR20, VAR16;
input [2:0] VAR24;
output VAR5;
output [55:0] VAR19;
output [10:0] VAR31;
reg [6:0] VAR2;
reg [6:0] VAR18;
reg [10:0] VAR6;
reg [10:0] VAR8;
reg [51:0] VAR1;
reg [51:0] VAR7;
reg VA... | gpl-3.0 |
ptracton/pmodacl2 | behavioral/wb_bfm/wb_bfm_transactor.v | 5,504 | module MODULE1
parameter VAR8 = 32,
parameter VAR18 = 0,
parameter VAR9 = 5,
parameter VAR2 = 0,
parameter VAR3 = 32'hffffffff)
(input VAR17,
input VAR4,
output [VAR21-1:0] VAR11,
output [VAR8-1:0] VAR14,
output [3:0] VAR1,
output VAR7,
output VAR13,
output VAR16,
output [2:0] VAR6,
output [1:0] VAR15,
input [VAR8-1:0]... | mit |
FPGApeeps/Verilog-65c816 | src/cpu.v | 6,683 | module MODULE1(input wire clk, input wire rst, input wire enable,
input wire [VAR9:0] VAR14,
output reg VAR7,
output reg VAR11,
output reg [VAR2:0] addr,
output reg [VAR9:0] VAR5);
parameter VAR8 = VAR4;
parameter VAR13 = VAR1;
parameter VAR16 = VAR15;
reg [VAR6:0] VAR10;
reg [VAR8:0] state;
reg [VAR8 + 1:0] VAR3;
reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/conb/sky130_fd_sc_hs__conb.pp.blackbox.v | 1,202 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR4,
VAR1
);
output VAR3 ;
output VAR2 ;
input VAR4;
input VAR1;
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/sine_table_11bit_float32.v | 70,742 | module MODULE1
(input VAR2,
input [10:0] VAR1,
output reg [31:0] VAR3);
always @(posedge VAR2) begin
case (VAR1)
11'd0: VAR3 = 32'h0;
11'd1: VAR3 = 32'h3b490fc6;
11'd2: VAR3 = 32'h3bc90f88;
11'd3: VAR3 = 32'h3c16cb58;
11'd4: VAR3 = 32'h3c490e90;
11'd5: VAR3 = 32'h3c7b514b;
11'd6: VAR3 = 32'h3c96c9b6;
11'd7: VAR3 = 32'h... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf.behavioral.pp.v | 1,772 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR7,
VAR3,
VAR4 ,
VAR11
);
output VAR9 ;
input VAR8 ;
input VAR7;
input VAR3;
input VAR4 ;
input VAR11 ;
wire VAR2 ;
wire VAR12;
buf VAR5 (VAR2 , VAR8 );
VAR1 VAR6 (VAR12, VAR2, VAR7, VAR3);
buf VAR10 (VAR9 , VAR12 );
endmodule | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/system/wishbone_arbiter.v | 14,339 | module MODULE1 #(
parameter VAR41 = 32,
parameter VAR23 = 4
)(
input VAR107,
input [31:0] VAR62,
input [VAR23-1:0] VAR70,
input VAR1,
output [VAR41-1:0] VAR38,
input [VAR41-1:0] VAR79,
input VAR73,
input VAR96,
output VAR58,
output VAR32,
input [31:0] VAR101,
input [VAR23-1:0] VAR29,
input VAR112,
output [VAR41-1:0] VA... | lgpl-3.0 |
sorgelig/Apogee_MIST | ram.v | 10,816 | module MODULE1 (
VAR23,
VAR16,
VAR53,
VAR37,
VAR24,
VAR39,
VAR32,
VAR2,
VAR56);
input [14:0] VAR23;
input [14:0] VAR16;
input VAR53;
input [7:0] VAR37;
input [7:0] VAR24;
input VAR39;
input VAR32;
output [7:0] VAR2;
output [7:0] VAR56;
tri1 VAR53;
tri0 VAR39;
tri0 VAR32;
wire [7:0] VAR36;
wire [7:0] VAR42;
wire [7:0] V... | bsd-2-clause |
fpgasystems/Centaur | rtl/fthread/iolib/order_module_backpressure.v | 7,023 | module MODULE1
parameter VAR33 = 6,
parameter VAR8 = 6,
parameter VAR13 = 8,
parameter VAR14 = 512,
parameter VAR6 = 58)
(
input wire clk,
input wire VAR25,
input wire [VAR6-1:0] VAR40,
input wire [VAR13-1:0] VAR46,
input wire VAR7,
output wire VAR19,
output wire [VAR6-1:0] VAR34,
output wire [VAR8-1:0] VAR44,
output w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b_2.v | 2,254 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR2,
VAR6,
VAR3 ,
VAR10
);
output VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR2;
input VAR6;
input VAR3 ;
input VAR10 ;
VAR5 VAR4 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
fallen/milkymist-mmu | boards/milkymist-one/rtl/vga.v | 3,120 | module MODULE1 #(
parameter VAR40 = 4'h0,
parameter VAR70 = 26
) (
input VAR12,
input VAR28,
input VAR32,
input [13:0] VAR2,
input VAR22,
input [31:0] VAR66,
output [31:0] VAR76,
output [VAR70-1:0] VAR51,
output VAR54,
input VAR4,
input [63:0] VAR21,
output VAR25,
output [VAR70-1:0] VAR3,
input [63:0] VAR82,
input VAR1... | lgpl-3.0 |
dvanmali/Superscalar_Pipeline_Processor | pipelinedec.v | 5,658 | module MODULE1(VAR15, VAR18, VAR6, VAR3, VAR1, VAR12, VAR11, VAR8, VAR24, VAR9);
input [5:0] VAR15;
output reg VAR6, VAR18, VAR3;
output reg [3:0] VAR1;
output reg VAR12, VAR11, VAR8, VAR24, VAR9;
reg [11:0] VAR23;
parameter VAR2 = 6'b100011; parameter VAR7 = 6'b101011; parameter VAR20 = 6'b000000; parameter VAR16 = 6'... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2.behavioral.pp.v | 1,850 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR10,
VAR1,
VAR9 ,
VAR11
);
output VAR5 ;
input VAR4 ;
input VAR10;
input VAR1;
input VAR9 ;
input VAR11 ;
wire VAR2 ;
wire VAR12;
buf VAR7 (VAR2 , VAR4 );
VAR3 VAR8 (VAR12, VAR2, VAR10, VAR1);
buf VAR6 (VAR5 , VAR12 );
endmodule | apache-2.0 |
betontalpfa2/AXI2SPI-bridge | hdl/axi_interface.v | 3,459 | module MODULE1(
input VAR15,
input VAR7,
output reg [31:0] VAR25,
output reg VAR5, output reg VAR19,
input wire [31:0] VAR21,
input wire [31:0] VAR17,
input wire [31:0] VAR12,
input [31:0] VAR16, input [2:0] VAR22, output [0:0] VAR2, input [0:0] VAR3, input [31:0] VAR6, input [2:0] VAR29, output [0:0] VAR24, input [0:0... | gpl-3.0 |
MegaShow/college-programming | Homework/Digital Circuits and Logical Design/12BitCounter/PCMain.v | 1,054 | module MODULE1(VAR17, VAR7, VAR16, VAR18, VAR4, VAR23, VAR2);
input VAR17, VAR7;
output [3:0] VAR16;
output reg VAR23;
output reg [3:0] VAR4;
output [7:0] VAR18;
inout VAR2;
reg [31:0] counter;
reg [31:0] VAR19;
reg VAR13;
reg VAR9;
reg VAR22;
VAR6 VAR10(.VAR17(VAR13), .VAR7(VAR7), .VAR9(VAR9), .VAR24(VAR16[3]), .VAR20... | mit |
queq/just-stuff | pov/TopFixed/top_string.v | 1,448 | module MODULE1(VAR8, clk, new, VAR47, string, VAR31, VAR5);
input [6:0] VAR8;
input clk, new, VAR47;
output [76:0] string;
output VAR31, VAR5;
wire VAR16, VAR15;
wire VAR48, VAR14, VAR32, VAR11, VAR28, VAR21, VAR37, VAR13, VAR25, VAR3, VAR23, VAR36, VAR42;
wire [6:0] VAR39;
wire [3:0] VAR27;
VAR40 VAR43 (.clk(clk), .VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi_4.v | 2,261 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR5 ,
VAR3 ,
VAR1,
VAR8,
VAR2 ,
VAR4
);
output VAR10 ;
input VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR1;
input VAR8;
input VAR2 ;
input VAR4 ;
VAR9 VAR6 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
chriz2600/DreamcastHDMI | Core/source/filter/scanline.v | 1,412 | module MODULE1(
input VAR20,
input VAR18,
input VAR19,
input VAR15,
input [8:0] VAR8,
input [23:0] VAR5,
output reg [23:0] VAR2
);
localparam VAR14 = 9'd256;
reg [23:0] VAR1;
reg [8:0] VAR12;
wire [23:0] VAR6;
VAR11 VAR16 (
.VAR20(VAR20),
.VAR5(VAR1),
.VAR3(VAR12),
.VAR2(VAR6)
);
function [8:0] VAR17(
input[16:0] VAR13... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.behavioral.v | 1,101 | module MODULE1( VAR4, VAR2 );
input VAR4;
output VAR2;
VAR3 VAR5(.VAR4(VAR4),.VAR2(VAR2));
VAR3 VAR1(.VAR4(VAR4),.VAR2(VAR2)); | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_dmask_rows_V.v | 2,987 | module MODULE1 (
clk,
VAR17,
VAR6,
VAR7,
VAR12);
parameter VAR9 = 32'd12;
parameter VAR18 = 32'd2;
parameter VAR24 = 32'd3;
input clk;
input [VAR9-1:0] VAR17;
input VAR6;
input [VAR18-1:0] VAR7;
output [VAR9-1:0] VAR12;
reg[VAR9-1:0] VAR19 [0:VAR24-1];
integer VAR20;
always @ (posedge clk)
begin
if (VAR6)
begin
for (VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s.symbol.v | 1,358 | module MODULE1 (
input VAR6,
output VAR2
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
ChrisPVille/RL02 | FPGA/crc16.v | 1,700 | module MODULE1(
input [0:0] VAR3,
input VAR2,
output [15:0] VAR5,
input rst,
input clk);
reg [15:0] VAR1,VAR4;
assign VAR5 = VAR1;
always @(*) begin
VAR4[0] = VAR1[15] ^ VAR3[0];
VAR4[1] = VAR1[0];
VAR4[2] = VAR1[1] ^ VAR1[15] ^ VAR3[0];
VAR4[3] = VAR1[2];
VAR4[4] = VAR1[3];
VAR4[5] = VAR1[4];
VAR4[6] = VAR1[5];
VAR4[7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a.behavioral.v | 1,588 | module MODULE1 (
VAR6 ,
VAR11,
VAR14,
VAR5,
VAR9,
VAR4
);
output VAR6 ;
input VAR11;
input VAR14;
input VAR5;
input VAR9;
input VAR4;
supply1 VAR1;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR8 ;
wire VAR13 ;
wire VAR3;
or VAR10 (VAR13 , VAR14, VAR11 );
and VAR12 (VAR3, VAR5, VAR9, VAR13, VAR4);
buf VAR15 (VAR6 , VAR3 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1.behavioral.v | 1,652 | module MODULE1 (
VAR10,
VAR3,
VAR15
);
output VAR10;
input [7:0] VAR3;
input [7:0] VAR15;
supply1 VAR4;
supply0 VAR13;
supply1 VAR9 ;
supply0 VAR2 ;
bufif1 VAR12 (VAR10 , !VAR3[0], VAR15[0] );
bufif1 VAR7 (VAR10 , !VAR3[1], VAR15[1] );
bufif1 VAR14 (VAR10 , !VAR3[2], VAR15[2] );
bufif1 VAR8 (VAR10 , !VAR3[3], VAR15[3] ... | apache-2.0 |
HashRatio/mm-hashratio | verilog/superkdf9/components/uart_core/rxcver.v | 20,657 | module MODULE1 #(parameter VAR54=8,
parameter VAR43=0)
(
reset,
clk,
VAR27,
VAR23,
VAR40,
VAR12,
VAR13,
VAR16,
VAR10,
VAR56,
VAR63,
VAR15,
VAR65,
VAR57,
VAR35,
VAR38,
VAR47,
VAR5,
VAR19
);
input reset ;
input clk ;
input VAR40 ;
input VAR12 ;
input VAR13 ;
input [1:0] VAR16 ;
input VAR10;
input VAR56;
input VAR63;
outp... | unlicense |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_flash.v | 17,028 | module MODULE1 (
VAR59,
clk,
VAR40,
VAR19,
VAR30,
VAR72,
VAR73,
VAR31,
VAR10,
VAR38,
VAR5,
VAR68,
VAR75,
VAR28,
irq,
VAR84
)
;
output VAR10;
output VAR38;
output VAR5;
output [ 15: 0] VAR68;
output VAR75;
output VAR28;
output irq;
output VAR84;
input VAR59;
input clk;
input [ 15: 0] VAR40;
input [ 2: 0] VAR19;
input VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311oi/sky130_fd_sc_ls__a311oi.behavioral.pp.v | 2,076 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR17 ,
VAR14 ,
VAR18 ,
VAR11 ,
VAR6,
VAR9,
VAR16 ,
VAR7
);
output VAR1 ;
input VAR5 ;
input VAR17 ;
input VAR14 ;
input VAR18 ;
input VAR11 ;
input VAR6;
input VAR9;
input VAR16 ;
input VAR7 ;
wire VAR10 ;
wire VAR3 ;
wire VAR13;
and VAR12 (VAR10 , VAR14, VAR5, VAR17 );
nor VAR4 (VAR3 , ... | apache-2.0 |
jotego/jt12 | hdl/adpcm/jt10_adpcmb_cnt.v | 3,425 | module MODULE1(
input VAR17,
input clk, input VAR2,
input [15:0] VAR7,
input VAR5,
input VAR8,
input VAR11,
input [15:0] VAR4,
input [15:0] VAR16,
input VAR1,
output reg [23:0] addr,
output reg VAR12,
output reg VAR3,
output reg flag,
input VAR13,
output reg VAR9,
output reg VAR6
);
reg [15:0] VAR15;
always @(posedge c... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfstp/sky130_fd_sc_ms__dfstp_4.v | 2,273 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR3 ,
VAR6,
VAR10 ,
VAR7 ,
VAR1 ,
VAR5
);
output VAR2 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
VAR9 VAR8 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODU... | apache-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_serial_bus_controller.v | 10,371 | module MODULE1 (
clk,
reset,
VAR13,
VAR38,
VAR7,
VAR1,
VAR23,
VAR6,
VAR26,
VAR8,
VAR4,
VAR10,
VAR20
);
parameter VAR11 = 26; parameter VAR24 = 4;
parameter VAR27 = 11;
input clk;
input reset;
input VAR13;
input [VAR11: 0] VAR38;
input [VAR11: 0] VAR7;
input [VAR24: 0] VAR1;
input [VAR11: 0] VAR23;
input [VAR11: 0] VAR6... | mit |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab/regfile_beh.v | 1,968 | module MODULE1(VAR1, VAR8, VAR3, VAR7, VAR6, VAR5, clk, VAR4, VAR9);
input [4:0] VAR1, VAR3, VAR6;
input [31:0] VAR5;
input clk, VAR4, VAR9;
output [31:0] VAR8, VAR7;
reg [31:0] register [31:0];
integer VAR2;
begin
end
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3.pp.blackbox.v | 1,302 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR5 ,
VAR3 ,
VAR1,
VAR2,
VAR8 ,
VAR4
);
output VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR1;
input VAR2;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha.symbol.v | 1,274 | module MODULE1 (
input VAR7 ,
input VAR4 ,
output VAR6,
output VAR5
);
supply1 VAR8;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai.functional.pp.v | 1,938 | module MODULE1 (
VAR14,
VAR13,
VAR8 ,
VAR4 ,
VAR1 ,
VAR5
);
input VAR14;
input VAR13;
output VAR8 ;
input VAR4 ;
input VAR1 ;
input VAR5 ;
wire VAR7 ;
wire VAR12 ;
wire VAR6;
or VAR11 (VAR7 , VAR1, VAR4 );
nand VAR2 (VAR12 , VAR5, VAR7 );
VAR10 VAR3 (VAR6, VAR12, VAR14, VAR13);
buf VAR9 (VAR8 , VAR6 );
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/wb/arm2/wb_sram32.v | 6,441 | module MODULE1 #(
parameter VAR9 = 19,
parameter VAR23 = 2 ) (
input clk,
input reset,
input VAR5,
input VAR20,
output reg VAR13,
input VAR16,
input [31:0] VAR25,
input [3:0] VAR17,
input [31:0] VAR24,
output reg [31:0] VAR14,
output reg [VAR9-1:0] VAR6,
inout [31:0] VAR26,
output reg [1:0] VAR8, output reg VAR19, outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/maj3/sky130_fd_sc_hd__maj3.behavioral.pp.v | 2,186 | module MODULE1 (
VAR15 ,
VAR11 ,
VAR1 ,
VAR2 ,
VAR17,
VAR20,
VAR12 ,
VAR4
);
output VAR15 ;
input VAR11 ;
input VAR1 ;
input VAR2 ;
input VAR17;
input VAR20;
input VAR12 ;
input VAR4 ;
wire VAR8 ;
wire VAR19 ;
wire VAR10 ;
wire VAR16 ;
wire VAR9;
or VAR14 (VAR8 , VAR1, VAR11 );
and VAR13 (VAR19 , VAR8, VAR2 );
and VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb.blackbox.v | 1,330 | module MODULE1 (
VAR1 ,
VAR2,
VAR3,
VAR6 ,
VAR9
);
output VAR1 ;
input VAR2;
input VAR3;
input VAR6 ;
input VAR9 ;
supply1 VAR5;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaCordic12.v | 3,550 | module MODULE2 (reset,VAR18,VAR2, VAR3, VAR14, VAR23, VAR11, VAR4, VAR12, VAR19);
parameter VAR20 = 12;
parameter VAR10 = 12;
parameter VAR21 = 0;
input VAR2, reset, VAR18,VAR3;
input signed [VAR20-1:0] VAR14, VAR23, VAR11;
output signed [VAR20-1:0] VAR4, VAR12, VAR19;
wire signed [VAR20-1:0] VAR16 [VAR10-1:1];
wire si... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfsbp/sky130_fd_sc_hs__dfsbp.pp.blackbox.v | 1,315 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR4 ,
VAR1 ,
VAR5,
VAR3 ,
VAR7
);
input VAR6 ;
input VAR2 ;
output VAR4 ;
output VAR1 ;
input VAR5;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_uart/qmfir_240MHz/ISE_project/firdecim_m4_n12.v | 10,893 | module MODULE1(
VAR15, VAR17,
VAR3, VAR31, VAR10, VAR11, VAR13, VAR42, clk, rst, VAR25
);
parameter VAR18 = 16;
parameter VAR26 = 8;
parameter VAR35 = 24;
parameter VAR29 = 2;
output signed [(VAR18-1):0] VAR15;
output VAR17;
input signed [(VAR26-1):0] VAR3; input signed [(VAR26-1):0] VAR31;
input signed [(VAR26-1):0] V... | gpl-2.0 |
aj-michael/Digital-Systems | Lab6-Part2/lab6phase1I2C2015fall.v | 1,428 | module MODULE1(VAR6,VAR14,VAR22,VAR5,VAR21,VAR10);
input VAR6, VAR14, VAR22;
output VAR5, VAR21, VAR10;
wire VAR20;
wire VAR17;
wire VAR7;
wire VAR18;
wire VAR13;
wire VAR9;
wire VAR11;
parameter VAR19 = 20'd40000;
parameter VAR2 = 30'd65000000;
parameter VAR4 = 8'b10101101;
wire [7:0] VAR1;
VAR3 VAR23(VAR20,VAR21,VAR1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.behavioral.v | 1,193 | module MODULE1( VAR5, VAR1, VAR3 );
input VAR3, VAR5;
output VAR1;
VAR6 VAR2(.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3));
VAR6 VAR4(.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
benreynwar/fpga-sdrlib | verilog/flow/split.v | 1,549 | module MODULE1
parameter VAR2 = 2,
parameter VAR3 = 1,
parameter VAR7 = 32
)
(
input clk,
input VAR6,
input wire [VAR7-1:0] VAR8,
input wire VAR5,
output reg [VAR7*VAR2-1:0] VAR9,
output reg VAR4
);
reg [VAR3-1:0] pos;
wire [VAR7*VAR2-1:0] VAR1;
assign VAR1 = VAR8 << VAR7*pos;
always @ (posedge clk)
begin
if (!VAR6)
be... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32a/sky130_fd_sc_hd__o32a.functional.pp.v | 2,188 | module MODULE1 (
VAR14 ,
VAR7 ,
VAR18 ,
VAR17 ,
VAR10 ,
VAR12 ,
VAR2,
VAR5,
VAR16 ,
VAR6
);
output VAR14 ;
input VAR7 ;
input VAR18 ;
input VAR17 ;
input VAR10 ;
input VAR12 ;
input VAR2;
input VAR5;
input VAR16 ;
input VAR6 ;
wire VAR11 ;
wire VAR20 ;
wire VAR4 ;
wire VAR15;
or VAR3 (VAR11 , VAR18, VAR7, VAR17 );
or V... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/DE4_SOPC_burst_0.v | 15,485 | module MODULE1 (
clk,
VAR45,
VAR55,
VAR1,
VAR48,
VAR43,
VAR36,
VAR32,
VAR61,
VAR51,
VAR21,
VAR11,
VAR20,
VAR4,
VAR38,
VAR25,
VAR57,
VAR68,
VAR27,
VAR56,
VAR58,
VAR50,
VAR22,
VAR13,
VAR46
)
;
output [ 28: 0] VAR4;
output [ 10: 0] VAR38;
output VAR25;
output [ 3: 0] VAR57;
output VAR68;
output [ 28: 0] VAR27;
output VAR5... | mit |
QuantumQuadrate/HamamatsuCameralink | async.v | 7,701 | module MODULE4(
input clk,
input VAR33,
input [7:0] VAR16,
output VAR25,
output VAR18
);
parameter VAR28 = 25000000; parameter VAR24 = 115200;
wire VAR8 = 1'b1; else
wire VAR8;
MODULE1 #(VAR28, VAR24) VAR35(.clk(clk), .enable(VAR18), .VAR11(VAR8));
reg [3:0] VAR9 = 0;
wire VAR17 = (VAR9==0);
assign VAR18 = ~VAR17;
reg ... | bsd-3-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Space_Vector_Modulation.v | 5,044 | module MODULE1
(
VAR30,
VAR2,
VAR15,
VAR9,
VAR34,
VAR23
);
input signed [17:0] VAR30; input signed [17:0] VAR2; input signed [17:0] VAR15; output signed [19:0] VAR9; output signed [19:0] VAR34; output signed [19:0] VAR23;
wire signed [17:0] VAR35; wire signed [17:0] VAR8; wire signed [17:0] VAR5; wire signed [17:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvn/sky130_fd_sc_ls__einvn.pp.symbol.v | 1,329 | module MODULE1 (
input VAR6 ,
output VAR1 ,
input VAR7,
input VAR5 ,
input VAR2,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_mem/bsg_mem_1r1w_sync.v | 1,691 | module MODULE1
, parameter VAR11(VAR6)
, parameter VAR20=0
, parameter VAR15=VAR7(VAR6)
, parameter VAR18=1
, parameter VAR14=0
, parameter VAR17=0
)
(
input VAR4
, input VAR13
, input VAR2
, input [VAR15-1:0] VAR3
, input [VAR12-1:0] VAR16
, input VAR10
, input [VAR15-1:0] VAR19
, output logic [VAR12-1:0] VAR1
);
begi... | bsd-3-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_dac_channel.v | 12,756 | module MODULE1 (
VAR3,
VAR25,
VAR53,
VAR66,
VAR55,
VAR26,
VAR11,
VAR12,
VAR58,
VAR50,
VAR42,
VAR19,
VAR65,
VAR21,
VAR27,
VAR43,
VAR71,
VAR17,
VAR1,
VAR7,
VAR40,
VAR23,
VAR32,
VAR34,
VAR38,
VAR33,
VAR4,
VAR54,
VAR52,
VAR51,
VAR22,
VAR9,
VAR13,
VAR46,
VAR39,
VAR36,
VAR16,
VAR14);
parameter VAR30 = 4'h0;
input VAR3;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor2/sky130_fd_sc_ls__xor2_1.v | 2,117 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR9 ,
VAR6,
VAR5,
VAR3 ,
VAR8
);
output VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR8 ;
VAR7 VAR1 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR2,
VAR4,
VAR9
);
output VAR2;
... | apache-2.0 |
red0bear/AES128 | rtl/sBox_8.v | 8,337 | module MODULE1
(
output [7:0] VAR30, output [7:0] VAR4, input [7:0] VAR53,
input VAR48,
input clk
);
localparam VAR20 = 1;
localparam VAR46 = 0;
function [1:0] VAR29;
input [1:0] in;
begin
VAR29 = {in[0], in[1]};
end
endfunction
function [1:0] VAR31;
input [1:0] in;
begin
VAR31 = {^in, in[1]};
end
endfunction
function ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_hl_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.functional.pp.v | 2,084 | module MODULE1 (
VAR1 ,
VAR12 ,
VAR2,
VAR10 ,
VAR7 ,
VAR4
);
output VAR1 ;
input VAR12 ;
input VAR2;
input VAR10 ;
input VAR7 ;
input VAR4 ;
wire VAR11;
wire VAR8 ;
VAR5 VAR6 (VAR11, VAR12, VAR2, VAR7 );
buf VAR3 (VAR8 , VAR11 );
VAR5 VAR9 (VAR1 , VAR8, VAR10, VAR7);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxbp/sky130_fd_sc_hs__sdfxbp.functional.v | 1,916 | module MODULE1 (
VAR11,
VAR8,
VAR10 ,
VAR1 ,
VAR7 ,
VAR12 ,
VAR15 ,
VAR13
);
input VAR11;
input VAR8;
output VAR10 ;
output VAR1 ;
input VAR7 ;
input VAR12 ;
input VAR15 ;
input VAR13 ;
wire VAR6 ;
wire VAR4;
VAR9 VAR2 (VAR4, VAR12, VAR15, VAR13 );
VAR5 VAR17 VAR3 (VAR6 , VAR4, VAR7, VAR11, VAR8);
buf VAR16 (VAR10 , VA... | apache-2.0 |
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