repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ba/sky130_fd_sc_hd__o21ba.symbol.v | 1,386 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR6,
output VAR3
);
supply1 VAR5;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/fei4_rx/sync_master.v | 6,228 | module MODULE1 (
input wire clk, input wire VAR27, input wire VAR59, input wire rst, output wire VAR39, output wire VAR22, output wire VAR36, output wire VAR46, output wire [1:0] VAR7, output reg VAR24 );
wire VAR11;
wire VAR23;
wire VAR16;
wire VAR32;
reg VAR55;
reg VAR51;
reg VAR60;
reg VAR15;
reg VAR37;
reg VAR57;
r... | bsd-3-clause |
asicguy/gplgpu | hdl/altera_project/fifo_99x128/fifo_99x128_bb.v | 5,606 | module MODULE1 (
VAR4,
VAR5,
VAR7,
VAR1,
VAR3,
VAR2,
VAR6,
VAR8);
input VAR4;
input [98:0] VAR5;
input VAR7;
input VAR1;
output VAR3;
output VAR2;
output [98:0] VAR6;
output [6:0] VAR8;
endmodule | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/DecWidthConverter16to32.v | 6,369 | module MODULE1
(
parameter VAR10 = 16,
parameter VAR2 = 32
)
(
VAR19 ,
VAR15 ,
VAR5 ,
VAR13 ,
VAR17 ,
VAR21 ,
VAR20 ,
VAR7 ,
VAR4 ,
VAR3
);
input VAR19 ;
input VAR15 ;
input VAR5 ;
input [VAR10 - 1:0] VAR13 ;
input VAR17 ;
output VAR21 ;
output VAR20 ;
output [VAR2 - 1:0] VAR7 ;
output VAR4 ;
input VAR3 ;
reg [VAR10 - ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fa/sky130_fd_sc_hd__fa_4.v | 2,278 | module MODULE1 (
VAR6,
VAR10 ,
VAR4 ,
VAR11 ,
VAR2 ,
VAR3,
VAR5,
VAR8 ,
VAR9
);
output VAR6;
output VAR10 ;
input VAR4 ;
input VAR11 ;
input VAR2 ;
input VAR3;
input VAR5;
input VAR8 ;
input VAR9 ;
VAR1 VAR7 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.V... | apache-2.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_lin2exp.v | 2,137 | module MODULE1(
input [15:0] VAR2,
output reg [9:0] VAR4,
output reg [2:0] VAR9
);
always @(*) begin
casex( VAR2[15:9] )
7'VAR12: begin
VAR4 = VAR2[15:6];
VAR9 = 3'd7;
end
7'VAR13: begin
VAR4 = VAR2[14:5];
VAR9 = 3'd6;
end
7'VAR11: begin
VAR4 = VAR2[13:4];
VAR9 = 3'd5;
end
7'VAR5: begin
VAR4 = VAR2[12:3];
VAR9 = 3'd4;
... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_biu.v | 40,262 | module MODULE1(
output VAR247,
input VAR201,
output VAR46,
input [VAR102-1:0] VAR69,
input VAR142,
input [VAR313-1:0] VAR117,
input [VAR313/8-1:0] VAR64,
input [1:0] VAR319,
input [1:0] VAR251,
input VAR87,
input VAR122,
input [1:0] VAR49,
output VAR228,
input VAR320,
output VAR141 ,
output VAR124,
output [VAR313-1:0] ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcin/sky130_fd_sc_ls__fahcin.functional.v | 1,752 | module MODULE1 (
VAR3,
VAR18 ,
VAR4 ,
VAR1 ,
VAR11
);
output VAR3;
output VAR18 ;
input VAR4 ;
input VAR1 ;
input VAR11 ;
wire VAR7 ;
wire VAR16;
wire VAR19 ;
wire VAR5 ;
wire VAR17 ;
wire VAR9;
not VAR15 (VAR7 , VAR11 );
xor VAR14 (VAR16, VAR4, VAR1, VAR7 );
buf VAR2 (VAR18 , VAR16 );
and VAR10 (VAR19 , VAR4, VAR1 );
... | apache-2.0 |
ElegantLin/My-CPU | project_4/project_4.srcs/sources_1/imports/Chapter11/pc_reg.v | 2,824 | module MODULE1(
input wire clk,
input wire rst,
input wire[5:0] VAR11,
input wire VAR10,
input wire[VAR3] VAR7,
input wire VAR9,
input wire[VAR3] VAR1,
output reg[VAR14] VAR6,
output reg VAR12
);
always @ (posedge clk) begin
if (VAR12 == VAR8) begin
VAR6 <= 32'h00000000;
end else begin
if(VAR10 == 1'b1) begin
VAR6 <= V... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_sa1/msu.v | 5,888 | module MODULE1(
input VAR31,
input enable,
input [13:0] VAR9,
input [7:0] VAR43,
input VAR15,
input [2:0] VAR39,
input [7:0] VAR10,
output [7:0] VAR4,
input VAR17,
input VAR19,
input VAR41,
output [7:0] VAR37,
output [7:0] VAR28,
output VAR6,
output [31:0] VAR30,
output [15:0] VAR36,
input [5:0] VAR20,
input [5:0] VAR1... | gpl-2.0 |
gtaylormb/fpga_nes | hw/src/cpu/apu/apu_mixer.v | 6,718 | module MODULE1
(
input wire VAR6, input wire VAR2, input wire [3:0] VAR3, input wire [3:0] VAR7, input wire [3:0] VAR16, input wire [3:0] VAR21, input wire [3:0] VAR19, output wire VAR20, output wire [5:0] VAR17
);
wire [3:0] VAR1;
wire [3:0] VAR9;
wire [3:0] VAR13;
wire [3:0] VAR14;
reg [4:0] VAR15;
reg [5:0] VAR18;
r... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr.behavioral.v | 1,493 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR4 ;
supply0 VAR7 ;
supply1 VAR9;
supply1 VAR8 ;
supply0 VAR10 ;
wire VAR2;
buf VAR6 (VAR2, VAR3 );
buf VAR5 (VAR1 , VAR2 );
endmodule | apache-2.0 |
bbrown1867/ObjectTracking | hw/common/fixed_point/qadd.v | 2,436 | module MODULE1 #(
parameter VAR6 = 15,
parameter VAR5 = 32
)
(
input [VAR5-1:0] VAR1,
input [VAR5-1:0] VAR4,
output [VAR5-1:0] VAR3
);
reg [VAR5-1:0] VAR2;
assign VAR3 = VAR2;
always @(VAR1,VAR4) begin
if(VAR1[VAR5-1] == VAR4[VAR5-1]) begin VAR2[VAR5-2:0] = VAR1[VAR5-2:0] + VAR4[VAR5-2:0]; VAR2[VAR5-1] = VAR1[VAR5-1]; ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr.behavioral.pp.v | 1,308 | module MODULE1 (
VAR4 ,
VAR5,
VAR2 ,
VAR3 ,
VAR1
);
input VAR4 ;
input VAR5;
input VAR2 ;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_pcs_pma_gige.v | 15,243 | module MODULE1 (
address,
clk,
VAR7,
VAR59,
VAR159,
VAR65,
VAR147,
VAR122,
VAR143,
VAR17,
read,
VAR1,
VAR152,
VAR156,
VAR54,
reset,
VAR102,
VAR91,
VAR151,
write,
VAR84,
VAR74,
VAR106,
VAR32,
VAR51,
VAR23,
VAR99,
VAR158,
VAR3,
VAR113,
VAR115,
VAR34,
VAR172,
VAR138,
VAR93,
VAR18,
VAR21,
VAR105,
VAR44,
VAR62,
VAR168,
VAR1... | mit |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/32bed0456b8c6008/design_1_xbar_0_stub.v | 3,579 | module MODULE1(VAR38, VAR37, VAR25, VAR3,
VAR28, VAR29, VAR20, VAR4, VAR17, VAR15,
VAR14, VAR21, VAR2, VAR36, VAR31, VAR32,
VAR34, VAR22, VAR33, VAR40, VAR8, VAR23,
VAR10, VAR39, VAR18, VAR24, VAR7, VAR27,
VAR6, VAR30, VAR26, VAR11, VAR19, VAR16,
VAR12, VAR9, VAR5, VAR35, VAR1, VAR13)
;
input VAR38;
input VAR37;
input ... | mit |
sabertazimi/hust-lab | architecture/design/fpga/src/controller.v | 3,400 | module MODULE1
(
input [5:0] VAR12,
input [5:0] VAR5,
output [3:0] VAR6,
output VAR8,
output VAR16,
output VAR18,
output VAR1,
output VAR39,
output VAR32,
output VAR17,
output VAR20,
output VAR23,
output VAR24,
output VAR7,
output VAR33,
output VAR22,
output VAR38,
output VAR31,
output VAR3,
output VAR28
);
wire VAR26,... | mit |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v | 7,553 | module MODULE1
parameter VAR20 = 100,
parameter VAR2 = 3
)
(
VAR14, VAR18,
clk, rst, req, VAR15, VAR17, VAR8
);
input clk;
input rst;
input [VAR2-1:0] req;
wire [VAR2-1:0] VAR1;
reg [VAR2*2-1:0] VAR7;
always @(VAR1)
VAR7 = {VAR1, VAR1};
reg [VAR2*2-1:0] VAR13;
always @(req) VAR13 = {req, req};
reg [VAR2-1:0] VAR11 = {V... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_01/011J1G2/hdl/uart/peripheral_uart.v | 1,672 | module MODULE1(clk , rst , din , VAR2 , addr , rd , wr, dout, VAR6, VAR12 );
input clk;
input rst;
input [15:0]din;
input VAR2;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
output VAR6;
output reg VAR12=0;
reg [2:0] VAR8;
reg [7:0] VAR10;
wire VAR5;
always @(*) VAR3 (addr)
4'h0:begin VAR8 = (VAR2 && rd) ... | gpl-3.0 |
alexforencich/verilog-axis | rtl/axis_pipeline_register.v | 5,328 | module MODULE1 #
(
parameter VAR12 = 8,
parameter VAR17 = (VAR12>8),
parameter VAR6 = ((VAR12+7)/8),
parameter VAR9 = 1,
parameter VAR28 = 0,
parameter VAR38 = 8,
parameter VAR40 = 0,
parameter VAR1 = 8,
parameter VAR20 = 1,
parameter VAR27 = 1,
parameter VAR4 = 2,
parameter VAR14 = 2
)
(
input wire clk,
input wire rst... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbp/sky130_fd_sc_hs__dfbbp.functional.v | 2,242 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR20 ,
VAR7 ,
VAR1 ,
VAR14,
VAR6 ,
VAR4
);
output VAR12 ;
output VAR3 ;
input VAR20 ;
input VAR7 ;
input VAR1 ;
input VAR14;
input VAR6 ;
input VAR4 ;
wire VAR16 ;
wire VAR13 ;
wire VAR11 ;
wire VAR8 ;
wire VAR19;
wire VAR5 ;
not VAR10 (VAR16 , VAR14 );
not VAR17 (VAR13 , VAR1 );
VAR15 ... | apache-2.0 |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/imports/imports/sources_1/imports/Chapter11/openmips.v | 16,842 | module MODULE1(
input wire clk,
input wire rst,
input wire[5:0] VAR283,
input wire[VAR142] VAR150,
output wire[VAR142] VAR41,
output wire VAR157,
input wire[VAR142] VAR236,
output wire[VAR142] VAR136,
output wire[VAR142] VAR88,
output wire VAR260,
output wire[3:0] VAR286,
output VAR49,
output wire VAR3
);
wire[VAR33] V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.behavioral.v | 7,158 | module MODULE1( VAR4, VAR1, VAR7, VAR6, VAR8, VAR9, VAR5 );
input VAR9, VAR5, VAR6, VAR8, VAR1, VAR7;
output VAR4;
VAR2 VAR10(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR6(VAR6),.VAR8(VAR8),.VAR9(VAR9),.VAR5(VAR5));
VAR2 VAR3(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR6(VAR6),.VAR8(VAR8),.VAR9(VAR9),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.v | 2,377 | module MODULE2 (
VAR2 ,
VAR11 ,
VAR6 ,
VAR4 ,
VAR9,
VAR3 ,
VAR10 ,
VAR7 ,
VAR5
);
output VAR2 ;
output VAR11 ;
input VAR6 ;
input VAR4 ;
input VAR9;
input VAR3 ;
input VAR10 ;
input VAR7 ;
input VAR5 ;
VAR8 VAR1 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7)... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/synth/zynq_design_1_auto_pc_0.v | 13,333 | module MODULE1 (
VAR93,
VAR1,
VAR43,
VAR75,
VAR42,
VAR26,
VAR62,
VAR77,
VAR10,
VAR101,
VAR56,
VAR57,
VAR5,
VAR105,
VAR103,
VAR45,
VAR83,
VAR48,
VAR78,
VAR36,
VAR4,
VAR47,
VAR98,
VAR76,
VAR37,
VAR65,
VAR9,
VAR63,
VAR88,
VAR2,
VAR89,
VAR19,
VAR38,
VAR49,
VAR16,
VAR97,
VAR82,
VAR59,
VAR17,
VAR104,
VAR32,
VAR52,
VAR99,
VAR... | mit |
mbuesch/toprammer | libtoprammer/fpga/src/attiny26dip20/attiny26dip20.v | 5,223 | module MODULE1(VAR5, VAR7, write, read, VAR14);
inout [7:0] VAR5;
input VAR7;
input write;
input read;
inout [48:1] VAR14;
reg [7:0] address;
reg [7:0] VAR13;
wire VAR12;
reg VAR3, VAR11, VAR4, VAR18;
reg VAR10, VAR8;
reg [7:0] VAR9;
reg VAR2;
reg VAR15;
reg VAR6;
reg VAR16;
wire VAR17, VAR1;
assign VAR17 = 0;
assign V... | gpl-2.0 |
fpgaminer/fpgaminer-vanitygen | cores/sha256/sha256.v | 5,397 | module MODULE1 (
input clk,
input VAR16,
input [263:0] VAR20,
output reg VAR6 = 1'b0,
output reg [255:0] VAR13 = 256'd0
);
wire [247:0] VAR18 = {8'h80, 176'h00, 64'h0000000000000108};
reg [511:0] VAR3;
reg [255:0] state;
reg [6:0] VAR8;
wire [31:0] VAR24;
MODULE2 MODULE1 (
.clk (clk),
.VAR23 (VAR8[5:0]),
.VAR15 (VAR24)... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3/sky130_fd_sc_hs__and3.pp.symbol.v | 1,247 | module MODULE1 (
input VAR5 ,
input VAR3 ,
input VAR1 ,
output VAR4 ,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_xbar_1/synth/system_xbar_1.v | 28,794 | module MODULE1 (
VAR95,
VAR131,
VAR42,
VAR124,
VAR51,
VAR16,
VAR105,
VAR3,
VAR73,
VAR58,
VAR15,
VAR117,
VAR34,
VAR99,
VAR66,
VAR25,
VAR7,
VAR63,
VAR96,
VAR71,
VAR49,
VAR125,
VAR31,
VAR69,
VAR20,
VAR116,
VAR109,
VAR89,
VAR36,
VAR123,
VAR18,
VAR45,
VAR30,
VAR65,
VAR103,
VAR62,
VAR2,
VAR43,
VAR81,
VAR118
);
input wire VAR... | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/CPU/ARM_CU_ALU.v | 2,514 | module MODULE1( input VAR53 , VAR9 , VAR8 , VAR55,VAR10, input [31:0] VAR48, output [7:0] VAR29, output VAR17,VAR51,VAR7);
wire[31:0] VAR13;
wire VAR4, VAR40, VAR11, VAR58, VAR28, VAR52, VAR17, VAR7, VAR51, VAR35, VAR46, VAR24, VAR31;
wire [4:0] VAR43;
wire [3:0] VAR2;
reg [19:0] VAR3;
wire [31:0] VAR5,VAR32,VAR16,VAR5... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v | 5,312 | module MODULE1(
din,
VAR96,
VAR26,
rst,
VAR45,
VAR105,
dout,
VAR73,
VAR33,
VAR19,
VAR68);
input [35 : 0] din;
input VAR96;
input VAR26;
input rst;
input VAR45;
input VAR105;
output [35 : 0] dout;
output VAR73;
output VAR33;
output [9 : 0] VAR19;
output [9 : 0] VAR68;
VAR17 #(
.VAR35(0),
.VAR58(0),
.VAR22(10),
.VAR81("V... | gpl-2.0 |
omicronns/studies-sys-rek | lab4/zlozony/ipcore_dir/mul_19_12/mul_19_12.v | 50,008 | module MODULE2 (
clk, VAR262, VAR193, VAR60, VAR283
);
input clk;
input VAR262;
input [18 : 0] VAR193;
input [11 : 0] VAR60;
output [30 : 0] VAR283;
wire \VAR173/VAR186 ;
wire \VAR173/VAR81 ;
wire \VAR173/VAR162 ;
wire \VAR173/VAR229 ;
wire \VAR173/VAR226 ;
wire \VAR173/VAR120 ;
wire \VAR173/VAR32 ;
wire \VAR173/VAR196... | mit |
johan92/yafpgatetris | megafunctions/pll/pll_0002.v | 2,135 | module MODULE1(
input wire VAR29,
input wire rst,
output wire VAR71,
output wire VAR37,
output wire VAR62
);
VAR19 #(
.VAR44("true"),
.VAR72("50.0 VAR12"),
.VAR9("VAR49"),
.VAR6(2),
.VAR2("25.174999 VAR12"),
.VAR16("0 VAR66"),
.VAR39(50),
.VAR5("107.892852 VAR12"),
.VAR8("0 VAR66"),
.VAR17(50),
.VAR4("0 VAR12"),
.VAR64... | mit |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_VGA_Controller.v | 9,845 | module MODULE1 (
clk,
reset,
VAR30,
VAR8,
VAR15,
VAR28,
valid,
ready,
VAR19,
VAR47,
VAR13,
VAR51,
VAR57,
VAR27,
VAR38,
VAR55
);
parameter VAR14 = 7;
parameter VAR53 = 29;
parameter VAR31 = 29;
parameter VAR16 = 22;
parameter VAR34 = 19;
parameter VAR9 = 12;
parameter VAR17 = 9;
parameter VAR35 = 2;
parameter VAR5 = 640... | mit |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/FSM_Main.v | 4,251 | module MODULE1(
input VAR10,
input reset,
input VAR15,
input VAR28,
input VAR8,
output VAR11,
output VAR25,
output VAR27,
output VAR3,
output reg VAR12,
output reg VAR7,
output reg VAR9);
reg VAR21, VAR4;
wire VAR16, VAR22;
VAR26 VAR18(
.VAR10(VAR10),
.reset(reset),
.VAR21(VAR21),
.VAR16(VAR16),
.VAR25(VAR25),
.VAR3(VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21o/sky130_fd_sc_hvl__a21o.functional.pp.v | 2,004 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR1 ,
VAR7 ,
VAR16,
VAR6,
VAR9 ,
VAR13
);
output VAR8 ;
input VAR12 ;
input VAR1 ;
input VAR7 ;
input VAR16;
input VAR6;
input VAR9 ;
input VAR13 ;
wire VAR3 ;
wire VAR4 ;
wire VAR14;
and VAR15 (VAR3 , VAR12, VAR1 );
or VAR10 (VAR4 , VAR3, VAR7 );
VAR11 VAR5 (VAR14, VAR4, VAR16, VAR6);
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_1.behavioral.v | 8,908 | module MODULE1( VAR58, VAR14, VAR9, VAR30, VAR25 );
input VAR30, VAR9, VAR58, VAR14;
output VAR25;
reg VAR48;
VAR62 VAR81(.VAR58(VAR58),.VAR14(VAR14),.VAR9(VAR9),.VAR30(VAR30),.VAR25(VAR25),.VAR48(VAR48));
VAR62 VAR70(.VAR58(VAR58),.VAR14(VAR14),.VAR9(VAR9),.VAR30(VAR30),.VAR25(VAR25),.VAR48(VAR48));
not VAR26(VAR29,VA... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/debug/sirv_debug_ram.v | 2,140 | module MODULE1(
input clk,
input VAR3,
input VAR5,
input VAR11,
input [ 3-1:0] VAR10,
input [32-1:0] VAR2,
output [32-1:0] VAR8
);
wire [31:0] VAR1 [0:6];
wire [6:0] VAR12;
assign VAR8 = VAR1[VAR10];
genvar VAR6;
generate
for (VAR6=0; VAR6<7; VAR6=VAR6+1) begin:VAR4
assign VAR12[VAR6] = VAR5 & (~VAR11) & (VAR10 == VAR6... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4bb/sky130_fd_sc_hd__and4bb.behavioral.v | 1,512 | module MODULE1 (
VAR7 ,
VAR6,
VAR12,
VAR14 ,
VAR1
);
output VAR7 ;
input VAR6;
input VAR12;
input VAR14 ;
input VAR1 ;
supply1 VAR5;
supply0 VAR13;
supply1 VAR8 ;
supply0 VAR10 ;
wire VAR2 ;
wire VAR11;
nor VAR9 (VAR2 , VAR6, VAR12 );
and VAR4 (VAR11, VAR2, VAR14, VAR1 );
buf VAR3 (VAR7 , VAR11 );
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/wishbone/legacy/wb_get_block.v | 2,929 | module MODULE1
parameter VAR6 = 5,
parameter VAR1 = VAR6-1,
parameter VAR3 = 3)
(
input VAR18,
input VAR10,
output reg VAR21 = 0,
output reg VAR22 = 0,
output VAR16,
output reg VAR12 = 0,
input VAR20,
input VAR4,
input VAR8,
output [VAR1:0] VAR7,
input VAR14,
output reg VAR15 = 0
);
wire VAR2 = !VAR8 && (VAR22 || VAR13... | lgpl-3.0 |
PeterMagnusson/modexp | src/rtl/blockmem1r1w.v | 2,743 | module MODULE1(
input wire clk,
input wire [07 : 0] VAR5,
output wire [31 : 0] VAR3,
input wire wr,
input wire [07 : 0] VAR1,
input wire [31 : 0] VAR4
);
reg [31 : 0] VAR2 [0 : 255];
reg [31 : 0] VAR6;
assign VAR3 = VAR6;
always @ (posedge clk)
begin : VAR7
if (wr)
VAR2[VAR1] <= VAR4;
VAR6 <= VAR2[VAR5];
end
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111oi/sky130_fd_sc_ls__a2111oi.functional.pp.v | 2,082 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR1 ,
VAR15,
VAR18,
VAR10 ,
VAR16
);
output VAR3 ;
input VAR12 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR1 ;
input VAR15;
input VAR18;
input VAR10 ;
input VAR16 ;
wire VAR14 ;
wire VAR4 ;
wire VAR2;
and VAR17 (VAR14 , VAR12, VAR7 );
nor VAR5 (VAR4 , VAR9, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3_4.v | 2,175 | module MODULE2 (
VAR10 ,
VAR2 ,
VAR7 ,
VAR8 ,
VAR4,
VAR1,
VAR3 ,
VAR5
);
output VAR10 ;
input VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR4;
input VAR1;
input VAR3 ;
input VAR5 ;
VAR6 VAR9 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn.behavioral.pp.v | 3,481 | module MODULE1 (
VAR15 ,
VAR10 ,
VAR14 ,
VAR21 ,
VAR16 ,
VAR4 ,
VAR30 ,
VAR1,
VAR24 ,
VAR28
);
output VAR15 ;
output VAR10 ;
input VAR14 ;
input VAR21 ;
input VAR16 ;
input VAR4 ;
input VAR30 ;
input VAR1;
input VAR24 ;
input VAR28 ;
wire VAR25 ;
wire VAR8 ;
wire VAR13 ;
wire VAR20 ;
reg VAR31 ;
wire VAR22 ;
wire VAR2 ... | apache-2.0 |
subailong/miaow | src/verilog/rtl/vgpr/reg_256x32b_3r_1w.v | 1,904 | module MODULE1
(
VAR10, VAR25, VAR26,
clk, VAR28, VAR15, VAR4, VAR21, VAR29, VAR19
);
input clk;
output [31:0] VAR10;
output [31:0] VAR25;
output [31:0] VAR26;
input [7:0] VAR28;
input [7:0] VAR15;
input [7:0] VAR4;
input [7:0] VAR21;
input VAR29;
input [31:0] VAR19;
wire [8191:0] VAR17;
wire [8191:0] VAR7;
wire [255:0... | bsd-3-clause |
airabinovich/finalArquitectura | REGBANK/REGBANK_banco.v | 1,149 | module MODULE1 #(parameter VAR4=5, VAR9=32)(
input VAR11,
input VAR7,
input [VAR4-1:0] VAR1,
input [VAR4-1:0] VAR5,
input [VAR4-1:0] VAR12,
input [VAR9-1:0] VAR3,
output [VAR9-1:0] VAR8,
output [VAR9-1:0] VAR10
);
localparam VAR2 = 1 << VAR4;
reg [VAR9-1:0] VAR6 [VAR2-1:0];
assign VAR8 = VAR6[VAR1];
assign VAR10 = VAR6... | lgpl-2.1 |
yanhongwang/ColorImage | ForwardSpace/ForwardSpace.v | 9,739 | module MODULE1
(
input[ VAR18 - 1 : 0 ]VAR6,
input[ VAR18 - 1 : 0 ]VAR27,
input[ VAR18 - 1 : 0 ]VAR11,
output wire[ VAR18 - 1 : 0 ]VAR2,
output wire signed[ VAR18 - 1 : 0 ]VAR15,
output wire signed[ VAR18 - 1 : 0 ]VAR16
);
reg[ VAR18 - 1 : 0 ]VAR22;
reg[ VAR18 - 1 : 0 ]VAR19;
reg[ VAR18 - 1 : 0 ]VAR28;
reg[ VAR18 - 1 :... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxtp/sky130_fd_sc_hs__edfxtp.symbol.v | 1,388 | module MODULE1 (
input VAR6 ,
output VAR4 ,
input VAR3 ,
input VAR2
);
supply1 VAR1;
supply0 VAR5;
endmodule | apache-2.0 |
skarpenko/ultiparc | rtl/src/cpu/uparc_lsu.v | 5,550 | module MODULE1(
clk,
VAR10,
addr,
VAR22,
VAR23,
VAR8,
VAR28,
VAR21,
VAR7,
VAR9,
VAR25,
VAR20,
VAR16,
VAR24,
VAR3,
VAR14,
VAR17,
VAR18
);
localparam VAR26 = 1'b0;
localparam VAR4 = 1'b1;
input wire clk;
input wire VAR10;
input wire [VAR2-1:0] addr;
input wire [VAR12-1:0] VAR22;
output reg [VAR12-1:0] VAR23;
input wire [... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_2.behavioral.v | 1,267 | module MODULE1( VAR5, VAR6, VAR2, VAR3 );
input VAR3, VAR2, VAR6;
output VAR5;
VAR4 VAR1(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR3(VAR3));
VAR4 VAR7(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/common/rtl/jbi_1r1w_16x10.v | 6,710 | module MODULE1(
do,
VAR6,
VAR45,
VAR40,
VAR47,
VAR10,
VAR46
);
output [9:0] do;
input [3:0] VAR6;
input [3:0] VAR45;
input [9:0] VAR40;
input VAR47;
input VAR10;
input VAR46;
wire VAR38;
reg [9:0] dout;
wire VAR50;
wire VAR56;
wire VAR3;
wire VAR22;
wire VAR30;
wire VAR43;
wire VAR44;
wire VAR23;
wire VAR53;
wire VAR29... | gpl-2.0 |
a5teri5m/async4ph | basys3/srcs/async.v | 1,904 | module MODULE1 (
input wire clk,
input wire reset,
input wire [3:0] VAR12,
output reg VAR7,
output reg [1:0] VAR2,
output reg VAR5
);
reg [3:0] VAR9, VAR11;
wire VAR10, VAR3;
reg VAR1, VAR4;
wire VAR6, VAR8;
always @(posedge clk) begin
if (reset == 1'b1) begin
VAR9 <= 4'b0;
VAR11 <= 4'b0;
end else begin
VAR9 <= VAR12;
... | mit |
rurume/openrisc_vision_hardware | ISE/or1200_dc_ram.v | 5,355 | module MODULE1(
clk, rst,
VAR10, VAR17, VAR11,
addr, en, VAR15, VAR6, VAR14
);
parameter VAR5 = VAR12;
parameter VAR16 = VAR1;
input clk;
input rst;
input [VAR16-1:0] addr;
input en;
input [3:0] VAR15;
input [VAR5-1:0] VAR6;
output [VAR5-1:0] VAR14;
input VAR10;
input [VAR18 - 1:0] VAR11; output VAR17;
assign VAR14 = {... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/DE4_SOPC_clock_0.v | 23,542 | module MODULE4 (
VAR37,
VAR55,
VAR52,
VAR27
)
;
output VAR27;
input VAR37;
input VAR55;
input VAR52;
reg VAR24;
wire VAR27;
always @(posedge VAR37 or negedge VAR52)
begin
if (VAR52 == 0)
VAR24 <= 0;
end
else
VAR24 <= VAR55;
end
assign VAR27 = VAR55 ^ VAR24;
endmodule
module MODULE2 (
VAR11,
VAR51,
VAR13,
VAR23,
VAR6,
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbp/sky130_fd_sc_hs__dfbbp.functional.pp.v | 2,251 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR7 ,
VAR9 ,
VAR15 ,
VAR19,
VAR21 ,
VAR13
);
output VAR11 ;
output VAR4 ;
input VAR7 ;
input VAR9 ;
input VAR15 ;
input VAR19;
input VAR21 ;
input VAR13 ;
wire VAR14 ;
wire VAR8 ;
wire VAR10 ;
wire VAR12 ;
wire VAR5;
wire VAR1 ;
not VAR2 (VAR14 , VAR19 );
not VAR20 (VAR8 , VAR15 );
VAR3... | apache-2.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/sdspi.v | 2,181 | module MODULE1 (
output reg VAR9, input VAR17,
output reg VAR11,
output reg VAR7,
input VAR16, input VAR14,
input [8:0] VAR10,
output reg [7:0] VAR8,
input VAR19,
input [1:0] VAR2,
input VAR20,
input VAR18,
output reg VAR12
);
wire VAR15;
wire VAR3;
wire VAR6;
reg [7:0] VAR4;
reg VAR1;
reg [7:0] VAR5;
reg [1:0] VAR13;
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_4.behavioral.v | 2,510 | module MODULE1( VAR4, VAR3, VAR1, VAR2 );
input VAR3, VAR4, VAR1;
output VAR2;
VAR6 VAR7(.VAR4(VAR4),.VAR3(VAR3),.VAR1(VAR1),.VAR2(VAR2));
VAR6 VAR5(.VAR4(VAR4),.VAR3(VAR3),.VAR1(VAR1),.VAR2(VAR2)); | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,183 | module MODULE1 (
clk,
VAR13,
VAR18,
VAR20,
VAR26,
VAR29,
VAR30,
VAR23,
VAR15,
VAR9,
VAR16,
VAR7,
VAR8,
VAR12,
VAR17,
VAR10
)
;
output [ 37: 0] VAR29;
output VAR30;
output VAR23;
output VAR15;
output VAR9;
output VAR16;
output VAR7;
output VAR8;
output VAR12;
output VAR17;
output VAR10;
input clk;
input [ 1: 0] VAR13;
i... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfsbp/sky130_fd_sc_hs__dfsbp.functional.pp.v | 1,859 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR13 ,
VAR11 ,
VAR7 ,
VAR4 ,
VAR9
);
input VAR10 ;
input VAR2 ;
output VAR13 ;
output VAR11 ;
input VAR7 ;
input VAR4 ;
input VAR9;
wire VAR12;
wire VAR8 ;
not VAR3 (VAR8 , VAR9 );
VAR14 VAR15 VAR5 (VAR12 , VAR4, VAR7, VAR8, VAR10, VAR2);
buf VAR1 (VAR13 , VAR12 );
not VAR6 (VAR11 , VAR... | apache-2.0 |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/hdl/verilog/tri_intersect_fsub_32ns_32ns_32_9_full_dsp.v | 1,942 | module MODULE1
VAR27 = 0,
VAR6 = 9,
VAR9 = 32,
VAR13 = 32,
VAR16 = 32
)(
input wire clk,
input wire reset,
input wire VAR3,
input wire [VAR9-1:0] VAR19,
input wire [VAR13-1:0] VAR10,
output wire [VAR16-1:0] dout
);
wire VAR8;
wire VAR5;
wire VAR26;
wire [31:0] VAR4;
wire VAR14;
wire [31:0] VAR23;
wire VAR7;
wire [31:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.blackbox.v | 1,311 | module MODULE1 (
VAR3,
VAR2 ,
VAR1 ,
VAR4
);
output VAR3;
input VAR2 ;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2i/sky130_fd_sc_hdll__mux2i_4.v | 2,230 | module MODULE2 (
VAR9 ,
VAR5 ,
VAR2 ,
VAR6 ,
VAR4,
VAR1,
VAR8 ,
VAR10
);
output VAR9 ;
input VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR4;
input VAR1;
input VAR8 ;
input VAR10 ;
VAR3 VAR7 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v | 18,362 | module MODULE1 (
VAR104,
VAR3,
VAR83,
VAR59,
VAR108,
VAR99);
input VAR104;
input VAR3;
output VAR83;
output VAR59;
output VAR108;
output VAR99;
tri0 VAR104;
wire [5:0] VAR110;
wire VAR24;
wire [0:0] VAR76 = 1'h0;
wire [2:2] VAR7 = VAR110[2:2];
wire [1:1] VAR70 = VAR110[1:1];
wire [0:0] VAR93 = VAR110[0:0];
wire VAR83 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.v | 2,034 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR1,
VAR2,
VAR6 ,
VAR7
);
output VAR3 ;
input VAR5 ;
input VAR1;
input VAR2;
input VAR6 ;
input VAR7 ;
VAR8 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR1;
supply0 VAR2;... | apache-2.0 |
jaruiz/ION | src/rtl/cpu.v | 43,722 | module MODULE1
parameter VAR146 = 32'hbfc00000,
parameter VAR243 = 32'hbfc00180
)
(
input VAR174,
input VAR82,
output [31:0] VAR144,
output [1:0] VAR205,
input [31:0] VAR125,
input VAR191,
input [1:0] VAR45,
output [31:0] VAR128,
output [1:0] VAR232,
output [2:0] VAR194,
input [31:0] VAR56,
output [31:0] VAR155,
output... | lgpl-3.0 |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/nios_design_onchip_memory2_0.v | 3,036 | module MODULE1 (
address,
VAR11,
VAR5,
clk,
VAR30,
reset,
VAR8,
write,
VAR32,
VAR25
)
;
parameter VAR26 = "MODULE1.VAR17";
output [ 31: 0] VAR25;
input [ 15: 0] address;
input [ 3: 0] VAR11;
input VAR5;
input clk;
input VAR30;
input reset;
input VAR8;
input write;
input [ 31: 0] VAR32;
wire VAR21;
wire [ 31: 0] VAR25;
... | gpl-2.0 |
phase4ground/DVB-receiver | modem/hdl/library/multiply_accumulate/multiply_accumulate.v | 7,759 | module MODULE1 #
(
parameter integer VAR80 = 16,
parameter integer VAR3 = 16,
parameter integer VAR14 = 48,
parameter integer VAR69 = 0,
parameter integer VAR66 = 1,
parameter integer VAR72 = 1,
parameter integer VAR114 = 1,
parameter integer VAR106 = 0,
parameter integer VAR61 = 0
)
(
input wire VAR57,
input wire rese... | gpl-3.0 |
AndreaCorallo/KPU | rtl/kpu/monitor.v | 3,112 | module MODULE1(
input wire VAR26,
input wire VAR25,
input wire VAR27,
input wire VAR29,
input wire [VAR7-1:0] VAR21,
input wire VAR15,
input wire VAR10,
input wire VAR32,
input wire [VAR7-1:0] VAR18,
input wire [VAR7-1:0] VAR8,
input wire [VAR13-1:0] VAR12,
input wire [VAR7-1:0] VAR11,
input wire [3:0] VAR28,
input wir... | gpl-3.0 |
mriosrivas/logica_booleana | logica_secuencial.v | 1,283 | module MODULE1(
input VAR5,
output reg VAR6,
input clk
);
always @(clk)
VAR6 <= VAR5;
endmodule
module MODULE3(
input VAR5,
output reg VAR6,
input clk
);
always @(posedge clk)
VAR6 <= VAR5;
endmodule
module MODULE2;
reg VAR3, VAR2;
wire VAR4;
MODULE1 MODULE1( .VAR5(VAR3), .VAR6(VAR4), .clk(VAR2) );
begin
begin
begin | apache-2.0 |
wkoszek/hardware | debouncer/debouncer.v | 1,117 | module MODULE1(VAR3, VAR1, do);
parameter VAR4 = 50*1000*1000/16;
input wire VAR3;
input wire VAR1;
output wire do;
reg [30:0] VAR5;
reg VAR2;
reg [1:0] state;
begin
begin
begin | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222o/sky130_fd_sc_ls__a222o.pp.symbol.v | 1,419 | module MODULE1 (
input VAR3 ,
input VAR5 ,
input VAR11 ,
input VAR2 ,
input VAR4 ,
input VAR1 ,
output VAR7 ,
input VAR6 ,
input VAR8,
input VAR9,
input VAR10
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux4/sky130_fd_sc_hvl__mux4.pp.symbol.v | 1,380 | module MODULE1 (
input VAR7 ,
input VAR3 ,
input VAR9 ,
input VAR4 ,
output VAR8 ,
input VAR2 ,
input VAR6 ,
input VAR11 ,
input VAR5,
input VAR1,
input VAR10
);
endmodule | apache-2.0 |
kwantam/multiexp-a5gx | verilog/multiexp_top.v | 35,236 | module MODULE1 #( parameter VAR142 = 11
, parameter VAR119 = 1
)
( input clk
, input VAR161
, input VAR14
, input VAR71
, input VAR109
, output VAR65
, input [31:0] VAR132
, input VAR139
, output VAR151
, input [VAR142:0] VAR98
, input VAR23
, output [31:0] VAR90
, output VAR11
, input [VAR142:0] VAR22
, output [3:0] V... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/video_sys_VGA_Controller.v | 9,843 | module MODULE1 (
clk,
reset,
VAR13,
VAR10,
VAR3,
VAR17,
valid,
ready,
VAR8,
VAR48,
VAR21,
VAR16,
VAR37,
VAR15,
VAR9,
VAR33
);
parameter VAR35 = 9;
parameter VAR52 = 29;
parameter VAR28 = 29;
parameter VAR32 = 20;
parameter VAR29 = 19;
parameter VAR4 = 10;
parameter VAR36 = 9;
parameter VAR19 = 0;
parameter VAR56 = 640;... | gpl-2.0 |
andykarpov/radio-86rk-wxeda | src/video/rambuffer_bb.v | 8,495 | module MODULE1 (
VAR4,
VAR3,
VAR5,
VAR1,
VAR7,
VAR2,
VAR6,
VAR9,
VAR8);
input [16:0] VAR4;
input [16:0] VAR3;
input VAR5;
input [0:0] VAR1;
input [0:0] VAR7;
input VAR2;
input VAR6;
output [0:0] VAR9;
output [0:0] VAR8;
tri1 VAR5;
tri0 VAR2;
tri0 VAR6;
endmodule | bsd-2-clause |
zhangly/azpr_cpu | rtl/io/gpio/rtl/gpio.v | 4,218 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR25, input wire VAR4, input wire VAR23, input wire [VAR17] addr, input wire [VAR18] VAR11, output reg [VAR18] VAR21, output reg VAR9
);
wire [VAR20-1:0] VAR8; reg [VAR20-1:0] VAR13; reg [VAR20-1:0] VAR3; reg [VAR20-1:0] VAR12; integer VAR14;
assign VAR8 = ... | mit |
SWORDfpga/ComputerOrganizationDesign | labs/lab04/lab04/Code/IO/port/Multi_8CH32_IO.v | 1,098 | module MODULE1(input clk,
input rst,
input VAR5, input[2:0]VAR13, input[63:0]VAR9, input[63:0]VAR14, input[31:0] VAR10, input[31:0] VAR11,
input[31:0] VAR1,
input[31:0] VAR8,
input[31:0] VAR3,
input[31:0] VAR4,
input[31:0] VAR6,
input[31:0] VAR7,
output [7:0] VAR2,
output [7:0] VAR12,
output [31:0]VAR15
);
endmodule | gpl-3.0 |
merckhung/zet | cores/vga/rtl/fml/vga_planar_fml.v | 5,697 | module MODULE1 (
input clk,
input rst,
input enable,
output [17:1] VAR33,
input [15:0] VAR25,
output VAR5,
input [3:0] VAR6,
input VAR35,
input [9:0] VAR20,
input [9:0] VAR24,
input VAR19,
input VAR31,
output VAR2,
output reg [3:0] VAR30,
output VAR12
);
reg [11:0] VAR29;
reg [ 5:0] VAR1;
reg [14:0] VAR28;
reg [ 1:0] V... | gpl-3.0 |
Nrpickle/ECE272 | Lab5_TekBotSM/Lab4_SmartTekbotRemote/Lab2_TekbotRemote_schematic_prim.v | 4,507 | module MODULE1 (VAR51, VAR18, VAR32, VAR14, VAR1, VAR59, VAR19) ; input VAR51; input VAR18; input VAR32; output VAR14; output VAR1; output VAR59; output VAR19;
wire VAR56; wire VAR58; wire VAR48; wire VAR10; wire VAR34; wire VAR27; wire VAR21; wire VAR33; wire VAR8; wire VAR43; wire VAR55; wire VAR49; wire VAR9; wire V... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_3.behavioral.pp.v | 1,246 | module MODULE1( VAR7, VAR2, VAR3, VAR5, VAR1 );
input VAR7, VAR2;
inout VAR5, VAR1;
output VAR3;
VAR8 VAR4(.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3),.VAR5(VAR5),.VAR1(VAR1));
VAR8 VAR6(.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/sumadorPuntoFijo.v | 2,312 | module MODULE1#(parameter VAR8 = 24, VAR1 = 4, VAR11 = 19, VAR5 = 1)
(VAR10,VAR4,VAR2,VAR7,VAR12);
input VAR10;
input signed [VAR8-1:0] VAR4,VAR2;
output reg signed [VAR8-1:0] VAR7 = 0;
output VAR12;
reg signed [VAR8-1:0] VAR3 = 0;
reg VAR9 = 0;
reg VAR6 = 0;
always @* begin if(VAR10)
VAR3 <= VAR2 + VAR4;
end
else
VAR3... | gpl-2.0 |
nyaxt/dmix | dcm.v | 1,817 | module MODULE1(
input wire VAR24,
input wire VAR8,
output wire VAR21,
output wire VAR20,
output wire VAR5);
reg [1:0] VAR26;
always @(posedge VAR24)
VAR26 <= VAR26 + 2'b1;
assign VAR21 = VAR26[1];
assign VAR20 = VAR26[0];
assign VAR5 = VAR24;
assign VAR21 = VAR24;
wire VAR1; wire VAR36; wire VAR31; VAR30 #(
.VAR12("1X"... | mit |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/riffa/rxc_engine_ultrascale.v | 19,933 | module MODULE1
parameter VAR91=10,
parameter VAR53 = 0,
parameter VAR4 = 1)
( input VAR17,
input VAR54, input VAR31, output VAR77,
input VAR110,
input VAR50,
input [VAR8-1:0] VAR76,
input [(VAR8/32)-1:0] VAR117,
input [VAR27-1:0] VAR33,
output VAR66,
output [VAR8-1:0] VAR49,
output VAR88,
output [(VAR8/32)-1:0] VAR52,
... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.functional.v | 1,585 | module MODULE1( VAR17, VAR19, VAR11, VAR14 );
input VAR19, VAR17, VAR11;
output VAR14;
wire VAR4;
not VAR3( VAR4, VAR11 );
wire VAR6;
and VAR2( VAR6, VAR4, VAR19, VAR17 );
wire VAR13;
not VAR8( VAR13, VAR17 );
wire VAR7;
and VAR12( VAR7, VAR13, VAR19, VAR11 );
wire VAR18;
not VAR1( VAR18, VAR19 );
wire VAR9;
and VAR16(... | apache-2.0 |
SiLab-Bonn/pyBAR | firmware/mio/src/clk_gen.v | 6,001 | module MODULE1 (
VAR14,
VAR45,
VAR16,
VAR95,
VAR44,
VAR77,
VAR74,
VAR35,
VAR13,
VAR36,
VAR102
);
input wire VAR14;
input wire VAR45;
output wire VAR77;
output wire VAR16;
output wire VAR95;
output wire [7:0] VAR44;
output wire VAR74;
output wire VAR35;
output wire VAR13;
output wire VAR36;
output wire [7:0] VAR102;
wir... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a_0.v | 2,411 | module MODULE1 (
VAR2 ,
VAR12 ,
VAR6 ,
VAR1 ,
VAR8 ,
VAR9 ,
VAR10,
VAR11,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR12 ;
input VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR9 ;
input VAR10;
input VAR11;
input VAR7 ;
input VAR3 ;
VAR4 VAR5 (
.VAR2(VAR2),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR10(... | apache-2.0 |
neale/CS-program | 474-VLSI/Lab_4/db/brightness_clk_2hz_altpll.v | 4,587 | module MODULE1
(
VAR2,
clk,
VAR3,
VAR6) ;
input VAR2;
output [4:0] clk;
input [1:0] VAR3;
output VAR6;
tri0 VAR2;
tri0 [1:0] VAR3;
reg VAR4;
wire [4:0] VAR7;
wire VAR1;
wire VAR5; | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21oi/sky130_fd_sc_hd__a21oi.pp.symbol.v | 1,352 | module MODULE1 (
input VAR7 ,
input VAR3 ,
input VAR5 ,
output VAR8 ,
input VAR6 ,
input VAR2,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v | 4,201 | module MODULE1 (
input wire clk ,
input wire reset ,
output wire VAR17 ,
input wire VAR3 ,
input wire [7:0] VAR15 ,
output wire VAR12 ,
input wire VAR11 ,
output wire VAR16 ,
input wire VAR13 ,
input wire VAR7 ,
output wire VAR10 ,
output wire VAR2
);
localparam VAR8 = 2'b00;
localparam VAR4 = 2'b01;
localparam VAR6 = ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4b/sky130_fd_sc_ls__and4b.pp.blackbox.v | 1,341 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR3 ,
VAR9,
VAR2,
VAR6 ,
VAR5
);
output VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR3 ;
input VAR9;
input VAR2;
input VAR6 ;
input VAR5 ;
endmodule | apache-2.0 |
jmahler/EECE344-Digital_System_Design | lab03/CPLD/spi_ctl.v | 3,950 | module MODULE1(
input VAR1,
VAR11,
VAR2,
output VAR8,
output reg [6:0] VAR7,
inout [7:0] VAR3,
output reg VAR12,
output reg VAR15);
reg [8:0] VAR10;
reg VAR5;
reg [7:0] VAR4;
assign VAR3 = (~(VAR15 | ~VAR12)) ? VAR4 : 8'VAR14;
reg [7:0] VAR9;
wire [7:0] VAR6;
assign VAR6 = {VAR9[6:0], VAR5};
assign VAR8 = VAR9[7];
reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.v | 2,034 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR5,
VAR2,
VAR8 ,
VAR6
);
output VAR1 ;
input VAR7 ;
input VAR5;
input VAR2;
input VAR8 ;
input VAR6 ;
VAR3 VAR4 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1,
VAR7
);
output VAR1;
input VAR7;
supply1 VAR5;
supply0 VAR2;... | apache-2.0 |
MIPSfpga/schoolMIPS | board/zeowaa/zeowaa.v | 1,446 | module MODULE1
(
input VAR1,
input [ 5:2] VAR10,
input [ 7:0] VAR19,
output [11:0] VAR17,
output [ 7:0] VAR13,
output [ 7:0] VAR24,
output VAR12
);
wire VAR14;
wire VAR7 = VAR1;
wire VAR3 = VAR10[4];
wire VAR22 = ~VAR19[ 7] | ~VAR10[5];
wire [ 3:0 ] VAR25 = { ~VAR19[6:5], 2'b00 };
wire [ 4:0 ] VAR4 = ~VAR19[4:0];
wire ... | mit |
joshtm00/Verificaci-n-de-Circuitos-Digitales | Proyecto 1/FIFO_LIFO/DUT.v | 6,407 | module MODULE1 #(parameter VAR6=1'b1, parameter VAR16=32, parameter VAR13=6, parameter VAR7=64)
( input [VAR16-1:0] VAR24,
input VAR1,
input VAR28,
input VAR23,
input VAR17,
input VAR20,
output reg VAR30,
output reg VAR31,
output reg [VAR16-1:0] VAR18
);
wire [VAR16-1:0] VAR19;
wire VAR10;
reg [VAR13-1:0] VAR15;
reg [V... | gpl-3.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_uart_0.v | 26,847 | module MODULE3 (
VAR42,
VAR71,
clk,
VAR43,
VAR31,
VAR88,
VAR5,
VAR61,
VAR92,
VAR59,
VAR15,
VAR96,
VAR18
)
;
output VAR59;
output VAR15;
output VAR96;
output VAR18;
input [ 9: 0] VAR42;
input VAR71;
input clk;
input VAR43;
input VAR31;
input VAR88;
input VAR5;
input [ 7: 0] VAR61;
input VAR92;
reg VAR89;
reg [ 9: 0] VAR... | gpl-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/acl_fp_custom_clz.v | 2,709 | module MODULE1(VAR9, VAR2, VAR4);
input [26:0] VAR9;
output [4:0] VAR2;
output VAR4;
wire VAR10 = ~|VAR9[26:11];
wire VAR11 = ~|VAR9[26:19];
wire VAR8 = ~|VAR9[26:23];
wire VAR5 = ~|VAR9[26:25];
wire VAR1 = ~(|VAR9[10:3]);
wire VAR3 = ~(|VAR9[10:7]);
wire VAR6 = ~(|VAR9[10:9]);
wire VAR7 = ~|VAR9;
assign VAR2[4] = VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a.functional.v | 1,412 | module MODULE1 (
VAR2 ,
VAR5,
VAR7,
VAR6
);
output VAR2 ;
input VAR5;
input VAR7;
input VAR6;
wire VAR8 ;
wire VAR9;
or VAR3 (VAR8 , VAR7, VAR5 );
and VAR1 (VAR9, VAR8, VAR6 );
buf VAR4 (VAR2 , VAR9 );
endmodule | apache-2.0 |
freecores/eco32 | fpga/src/dsp/timing.v | 1,916 | module MODULE1(clk, VAR8,
VAR16, VAR12,
VAR14, VAR17,
VAR6, VAR4, VAR2, VAR13);
input clk;
output VAR8;
output [4:0] VAR16;
output [6:0] VAR12;
output [3:0] VAR14;
output [2:0] VAR17;
output VAR6;
output VAR4;
output VAR2;
output reg VAR13;
reg VAR15;
reg [9:0] VAR11;
reg VAR3, VAR1;
reg [9:0] VAR9;
reg VAR10, VAR7;
re... | bsd-2-clause |
wgml/sysrek | skin_color_segm/median5x5.v | 4,239 | module MODULE1 # (
parameter [9:0] VAR19 = 83 )(
input clk,
input VAR26,
input rst,
input VAR18,
input VAR23,
input VAR31,
input VAR6,
output VAR29,
output VAR28,
output VAR32,
output VAR25
);
wire [3:0] VAR20;
reg [3:0] VAR7 [4:0];
wire [3:0] VAR2;
reg [3:0] VAR4 [4:0];
wire [3:0] VAR8;
reg [3:0] VAR13 [4:0];
wire [3:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311a/sky130_fd_sc_ms__o311a_2.v | 2,422 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR11 ,
VAR2 ,
VAR10 ,
VAR12 ,
VAR5,
VAR7,
VAR1 ,
VAR3
);
output VAR8 ;
input VAR9 ;
input VAR11 ;
input VAR2 ;
input VAR10 ;
input VAR12 ;
input VAR5;
input VAR7;
input VAR1 ;
input VAR3 ;
VAR4 VAR6 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR12(VAR12),
.VA... | apache-2.0 |
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