repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp.pp.symbol.v | 1,329 | module MODULE1 (
input VAR6 ,
output VAR2 ,
input VAR5 ,
input VAR7 ,
input VAR1,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/axi_dmac.v | 17,470 | module MODULE1 (
input VAR25,
input VAR29,
input VAR19,
input [31:0] VAR133,
output VAR83,
input VAR39,
input [31:0] VAR15,
input [ 3:0] VAR177,
output VAR185,
output VAR12,
output [ 1:0] VAR66,
input VAR194,
input VAR58,
input [31:0] VAR32,
output VAR189,
output VAR88,
input VAR55,
output [ 1:0] VAR149,
output [31:0] ... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/hrfp_xilinx_normalize.v | 13,812 | module MODULE1
(input wire clk,
input wire [VAR19:0] VAR24,
input wire [30:0] VAR28,
input wire [7:0] VAR18,
output reg [VAR23-1:0] VAR20,
output reg VAR31,VAR2,
output reg [30:0] VAR7,
output reg [30:0] VAR25,
output reg VAR16,
output reg [VAR19:0] VAR26,
output reg VAR3,
output reg VAR21);
reg [2:0] VAR13;
reg VAR11,... | gpl-3.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/SOC/synthesis/submodules/SoC_nios2_qsys_0_jtag_debug_module_tck.v | 8,222 | module MODULE1 (
VAR20,
VAR35,
VAR31,
VAR8,
VAR12,
VAR34,
VAR37,
VAR38,
VAR2,
VAR36,
VAR7,
VAR24,
VAR30,
VAR5,
VAR23,
VAR3,
VAR39,
VAR17,
VAR13,
VAR14,
VAR33,
VAR22,
VAR18,
VAR27,
VAR21,
VAR28,
VAR29,
VAR10,
VAR9,
VAR16,
VAR6
)
;
output [ 1: 0] VAR29;
output VAR10;
output [ 37: 0] VAR9;
output VAR16;
output VAR6;
input... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_axi.v | 8,721 | module MODULE1 (
VAR36,
VAR22,
VAR35,
VAR24,
VAR3,
VAR23,
VAR21,
VAR9,
VAR27,
VAR1,
VAR34,
VAR25,
VAR13,
VAR38,
VAR11,
VAR32,
VAR28,
VAR18,
VAR6,
VAR30,
VAR15,
VAR14,
VAR20,
VAR16,
VAR2,
VAR8,
VAR31);
parameter VAR33 = 14;
localparam VAR5 = VAR33 - 1;
input VAR36;
input VAR22;
input VAR35;
input [31:0] VAR24;
output VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb.functional.pp.v | 1,998 | module MODULE1 (
VAR5 ,
VAR14 ,
VAR13 ,
VAR10 ,
VAR2 ,
VAR12,
VAR11,
VAR9 ,
VAR15
);
output VAR5 ;
input VAR14 ;
input VAR13 ;
input VAR10 ;
input VAR2 ;
input VAR12;
input VAR11;
input VAR9 ;
input VAR15 ;
wire VAR4 ;
wire VAR7 ;
wire VAR3;
nor VAR16 (VAR4 , VAR14, VAR13 );
and VAR6 (VAR7 , VAR4, VAR10, VAR2 );
VAR8 V... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/up_clkgen.v | 6,016 | module MODULE1 #(
parameter VAR33 = 0) (
output VAR23,
output VAR11,
output reg VAR7,
output reg VAR5,
output reg [11:0] VAR1,
output reg [15:0] VAR18,
input [15:0] VAR22,
input VAR21,
input VAR32,
input VAR3,
input VAR8,
input VAR4,
input [13:0] VAR26,
input [31:0] VAR20,
output reg VAR6,
input VAR16,
input [13:0] VAR... | mit |
vvk/sysrek | arithm/ipcore_dir/multiplier.v | 12,663 | module MODULE2 (
clk, VAR35, VAR100, VAR1
);
input clk;
output [27 : 0] VAR35;
input [13 : 0] VAR100;
input [13 : 0] VAR1;
wire \VAR105/VAR41 ;
wire \VAR105/VAR14 ;
wire \VAR105/VAR21 ;
wire \VAR105/VAR40 ;
wire \VAR105/VAR59 ;
wire \VAR105/VAR36 ;
wire \VAR105/VAR4 ;
wire \VAR105/VAR116 ;
wire \VAR105/VAR84 ;
wire \VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd.pp.symbol.v | 1,197 | module MODULE1 (
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
qmn/riscv-invicta | hardware/src/multiplier.v | 2,028 | module MODULE1 (
output [31:0] VAR4,
input [31:0] VAR2,
input [31:0] VAR3,
input [1:0] VAR5
);
wire [63:0] VAR7 = VAR2[31] ? {32'hFFFFFFFF, VAR2} : {32'h0, VAR2};
wire [63:0] VAR1 = VAR3[31] ? {32'hFFFFFFFF, VAR3} : {32'h0, VAR3};
reg [63:0] VAR8;
always @ (*) begin
case (VAR5)
VAR8 = (VAR7) * (VAR1);
VAR8 = (VAR7) * {... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtn/sky130_fd_sc_hd__dfrtn.symbol.v | 1,431 | module MODULE1 (
input VAR6 ,
output VAR1 ,
input VAR7,
input VAR4
);
supply1 VAR8;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a.pp.blackbox.v | 1,347 | module MODULE1 (
VAR6 ,
VAR1,
VAR2,
VAR7 ,
VAR4 ,
VAR5,
VAR3
);
output VAR6 ;
input VAR1;
input VAR2;
input VAR7 ;
input VAR4 ;
input VAR5;
input VAR3;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_dqs_pad.v | 5,073 | module MODULE1(
VAR20, VAR21, VAR16,
VAR6,
VAR10, VAR25, VAR18, VAR15, VAR1, VAR5,
VAR19, VAR17, VAR8, VAR22,
VAR29, VAR13, VAR2,
VAR27, clk, VAR24, VAR3, VAR26
);
input VAR26; input [8:1] VAR3; input [8:1] VAR24; input clk; input VAR27; input VAR2; input VAR13; input VAR29;input VAR22; input VAR8; input VAR17; input V... | gpl-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_qpll_drp.v | 20,743 | module MODULE1 #
(
parameter VAR60 = "VAR40", parameter VAR27 = "3.0", parameter VAR46 = "VAR44", parameter VAR53 = 0, parameter VAR1 = 2'd3, parameter VAR69 = 3'd6
)
(
input VAR66,
input VAR76,
input VAR9,
input VAR71,
input VAR38,
input VAR70,
input [15:0] VAR20,
input VAR75,
output [ 7:0] VAR5,
output VAR3,
output [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv.symbol.v | 1,238 | module MODULE1 (
input VAR4,
output VAR6
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_qpll_wrapper.v | 29,077 | module MODULE1 #
(
parameter VAR108 = "VAR46", parameter VAR44 = "VAR36", parameter VAR142 = "3.0", parameter VAR23 = "VAR102", parameter VAR101 = 0
)
(
input VAR57,
input VAR93,
output VAR128,
output VAR140,
output VAR31,
input VAR98,
input VAR33,
input VAR121,
input [ 7:0] VAR107,
input VAR114,
input [15:0] VAR127,
i... | lgpl-3.0 |
fredyamalves/Collision-detection-for-a-CPU-FPGA-heterogeneous-System | Verilog design/add3.v | 2,347 | module MODULE1
(
input VAR5,
input [31:0] VAR11,
input [31:0] VAR12,
input [31:0] VAR1,
input reset,
output reg [31:0] VAR18,
output reg VAR16
);
wire VAR4;
wire VAR7;
wire [31:0] VAR14;
wire [31:0] VAR8;
reg VAR10 = 1'b0;
VAR9 VAR17 (
.VAR6 ( 1'b1 ),
.VAR13 ( VAR5 ),
.VAR2 ( VAR11 ),
.VAR3 ( VAR12 ),
.VAR18 ( VAR14 ),... | gpl-3.0 |
parallella/oh | common/hdl/oh_mux9.v | 1,358 | module MODULE1 #( parameter VAR17 = 1 ) (
input VAR1,
input VAR18,
input VAR12,
input VAR9,
input VAR11,
input VAR5,
input VAR13,
input VAR2,
input VAR7,
input [VAR17-1:0] VAR10,
input [VAR17-1:0] VAR8,
input [VAR17-1:0] VAR4,
input [VAR17-1:0] VAR16,
input [VAR17-1:0] VAR15,
input [VAR17-1:0] VAR14,
input [VAR17-1:0] ... | mit |
CatherineH/QubitekkCC | TDH/src/DE0Nano/verilog/twentyonecounter.v | 4,562 | module MODULE1 (
VAR5,
VAR20,
VAR8,
VAR15);
input VAR5;
input VAR20;
input VAR8;
output [20:0] VAR15;
wire [20:0] VAR19;
wire [20:0] VAR15 = VAR19[20:0];
VAR12 VAR17 (
.VAR5 (VAR5),
.VAR20 (VAR20),
.VAR8 (VAR8),
.VAR15 (VAR19),
.VAR21 (1'b0),
.VAR16 (1'b0),
.VAR25 (1'b0),
.VAR23 (1'b1),
.VAR1 (1'b1),
.VAR18 (),
.VAR14 ... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_dc_ram.v | 5,482 | module MODULE1(
clk, rst,
VAR16, VAR14, VAR7,
addr, en, VAR9, VAR17, VAR12
);
parameter VAR5 = VAR18;
parameter VAR2 = VAR10;
input clk;
input rst;
input [VAR2-1:0] addr;
input en;
input [3:0] VAR9;
input [VAR5-1:0] VAR17;
output [VAR5-1:0] VAR12;
input VAR16;
input [VAR13 - 1:0] VAR7; output VAR14;
assign VAR12 = {VAR... | gpl-3.0 |
tugrulyatagan/RISC-processor | xilinx_processor/interrupt.v | 1,255 | module MODULE1(
input VAR7,
input VAR12,
input VAR11,
input VAR4,
input VAR3,
input VAR1,
input [11:0] VAR9,
output reg VAR10,
output reg [11:0] VAR5
);
reg [11:0] VAR2;
reg VAR13;
reg VAR6;
reg VAR8; | gpl-2.0 |
peteg944/music-fpga | Enlightened Main Project/Microphone code (not used)/MicrophoneTop.v | 1,300 | module MODULE1(
output VAR8,
output VAR4,
output VAR3,
input VAR5,
input clk,
input rst,
output [7:0] VAR10
);
localparam VAR1 = 16'h1388; localparam VAR9 = 16'h09C4; reg [12:0] counter;
reg VAR7;
wire [9:0] VAR11;
VAR6 VAR2(VAR8, VAR4, VAR3, VAR5, clk, rst, VAR7, , VAR11);
assign VAR10 = VAR11[9:2];
always @ (posedge ... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/xc3s_ram16x233_d.v | 35,007 | module MODULE1 (VAR4, VAR156, VAR31, VAR76, VAR144, VAR97, VAR114);
parameter VAR87 = 233;
input wire [232:0]VAR4;
input wire [3:0] VAR156, VAR31;
input wire VAR76;
input wire VAR144;
output wire [232:0]VAR97, VAR114;
wire [232:0]VAR95, VAR222;
VAR167 VAR118(VAR222[0], VAR95[0], VAR156[0], VAR156[1], VAR156[2], VAR156[... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decap/sky130_fd_sc_lp__decap_12.v | 1,876 | module MODULE2 (
VAR1,
VAR5,
VAR4 ,
VAR3
);
input VAR1;
input VAR5;
input VAR4 ;
input VAR3 ;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR1;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
VAR6 VAR2 ();
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_41.v | 29,708 | module MODULE4 (
clk,
reset,
VAR182,
VAR81,
VAR33,
VAR224,
VAR170
);
parameter VAR19 = 18;
parameter VAR125 = 41;
parameter VAR88 = 21;
localparam VAR169 = 48;
input clk;
input reset;
input VAR182;
input VAR81;
input [VAR19-1:0] VAR33; output VAR224;
output [VAR19-1:0] VAR170;
localparam VAR209 = 18; localparam VAR247 ... | mit |
donnaware/AGC | rtl/de0/agc/JTAG_Probe.v | 3,863 | module MODULE1 (
VAR27,
VAR31);
input [15:0] VAR27;
output VAR31;
wire VAR18;
wire VAR31 = VAR18;
VAR6 VAR26 (
.VAR27 (VAR27),
.VAR31 (VAR18)
,
.VAR20 (),
.VAR9 (),
.VAR22 (),
.VAR16 (),
.VAR4 (),
.VAR17 (),
.VAR1 (),
.VAR8 (),
.VAR19 (),
.VAR14 (),
.VAR2 (),
.VAR13 (),
.VAR21 (),
.VAR10 (),
.VAR32 (),
.VAR7 (),
.VAR5 ... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/add_rm_hdr/megafunctions/hdr_fifo_bb.v | 5,809 | module MODULE1 (
VAR2,
VAR4,
VAR5,
VAR6,
VAR7,
VAR3,
VAR8,
VAR1,
VAR9);
input VAR2;
input VAR4;
input [71:0] VAR5;
input VAR6;
input VAR7;
output VAR3;
output VAR8;
output VAR1;
output [71:0] VAR9;
endmodule | mit |
zuloloxi/swapforth | j1a/verilog/j4.v | 7,626 | module MODULE1(
input wire clk,
input wire VAR9,
output wire VAR36,
output wire VAR23,
output wire [15:0] VAR8,
output wire VAR24,
output wire [VAR15-1:0] dout,
input wire [VAR15-1:0] VAR46,
output wire [12:0] VAR17,
input wire [15:0] VAR52,
output wire [1:0] VAR54,
output wire [15:0] VAR12,
input wire [3:0] VAR44);
re... | bsd-3-clause |
ncos/Xilinx-Verilog | GYRACC/src/ACC/clkdiv_5hz.v | 2,246 | module MODULE1(
VAR3,
VAR2,
VAR4
);
input VAR3; input VAR2; output VAR4;
reg VAR4;
reg [23:0] VAR1 = 24'h000000;
parameter [23:0] VAR5 = 24'h989680;
always @(posedge VAR3 or posedge VAR2)
if (VAR2 == 1'b1) begin
VAR4 <= 1'b0;
VAR1 <= 24'h000000;
end
else begin
if (VAR1 == VAR5) begin
VAR4 <= (~VAR4);
VAR1 <= 24'h000000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b.pp.symbol.v | 1,325 | module MODULE1 (
input VAR3 ,
input VAR2 ,
output VAR5 ,
input VAR4 ,
input VAR7,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
skarpenko/ultiparc | rtl/src/fabric2_decoder.v | 2,069 | module MODULE1 #(
parameter VAR6 = 11
)
(
VAR4,
VAR2,
VAR5
);
localparam VAR3 = VAR6 + 1;
input wire [VAR1-1:0] VAR4;
output wire [VAR1-1:0] VAR2;
output wire [VAR6-1:0] VAR5;
assign VAR2 = (!VAR4[VAR1-1] ? { 1'b0, VAR4[VAR1-2:0] } :
{ {(VAR3){1'b0}}, VAR4[VAR1-VAR3-1:0] });
assign VAR5 = (VAR4[VAR1-1] ? VAR4[VAR1-2:VA... | bsd-2-clause |
cpulabs/mist1032sa | src/core/core_if.v | 4,823 | module MODULE1 #(
parameter VAR24 = 32'h0
)(
input wire VAR16,
input wire VAR14,
output wire VAR9,
output wire VAR29,
output wire [5:0] VAR45,
output wire VAR15,
output wire VAR37,
output wire [1:0] VAR17,
output wire VAR21,
input wire VAR40,
output wire [1:0] VAR2,
output wire [31:0] VAR30,
output wire [31:0] VAR3,
in... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode_4.v | 1,901 | module MODULE1 (
VAR2,
VAR4,
VAR5 ,
VAR1
);
input VAR2;
input VAR4;
input VAR5 ;
input VAR1 ;
VAR6 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE1 ();
supply1 VAR2;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
VAR6 VAR3 ();
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_1.behavioral.pp.v | 8,974 | module MODULE1( VAR62, VAR59, VAR76, VAR24, VAR91, VAR39, VAR3 );
input VAR24, VAR76, VAR62, VAR59;
inout VAR39, VAR3;
output VAR91;
reg VAR42;
VAR1 VAR19(.VAR62(VAR62),.VAR59(VAR59),.VAR76(VAR76),.VAR24(VAR24),.VAR91(VAR91),.VAR39(VAR39),.VAR3(VAR3),.VAR42(VAR42));
VAR1 VAR32(.VAR62(VAR62),.VAR59(VAR59),.VAR76(VAR76),... | apache-2.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GDAN8M8P6_syn.v | 9,555 | module MODULE1 ( VAR352, VAR172, VAR265, VAR185 );
input [15:0] VAR172;
input [15:0] VAR265;
output [16:0] VAR185;
input VAR352;
wire VAR166, VAR301, VAR327, VAR350, VAR343, VAR161, VAR103, VAR36, VAR225, VAR338, VAR220, VAR335, VAR85, VAR267,
VAR310, VAR1, VAR14, VAR229, VAR318, VAR228, VAR135, VAR193, VAR95, VAR255, ... | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v | 7,727 | module MODULE1 #
(
parameter VAR7 = 100, parameter VAR14 = 64 )
(
input VAR3, input VAR10, input VAR11, input [VAR14-1:0] VAR8, input VAR4, input VAR18, output [VAR14-1:0] VAR16 );
function integer VAR9 (input integer VAR1);
begin
VAR1 = VAR1 - 1;
for (VAR9=1; VAR1>1; VAR9=VAR9+1)
VAR1 = VAR1 >> 1;
end
endfunction
loca... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4/sky130_fd_sc_ms__nand4.pp.symbol.v | 1,303 | module MODULE1 (
input VAR8 ,
input VAR3 ,
input VAR9 ,
input VAR6 ,
output VAR5 ,
input VAR2 ,
input VAR4,
input VAR1,
input VAR7
);
endmodule | apache-2.0 |
jameshegarty/rigel | generators/hardfloat/source/divSqrtRecFN_small.v | 15,509 | module
MODULE2#(
parameter VAR88 = 3, parameter VAR13 = 3, parameter VAR86 = 0
) (
input VAR62,
input VAR24,
input [(VAR79 - 1):0] VAR67,
output VAR73,
input VAR90,
input VAR71,
input [(VAR88 + VAR13):0] VAR78,
input [(VAR88 + VAR13):0] VAR16,
input [2:0] VAR85,
output VAR42,
output VAR75,
output [2:0] VAR37,
output VA... | mit |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_xlconstant_0_0/RAT_xlconstant_0_0_stub.v | 1,169 | module MODULE1(dout)
;
output [9:0]dout;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22oi/sky130_fd_sc_hvl__a22oi.pp.symbol.v | 1,380 | module MODULE1 (
input VAR7 ,
input VAR3 ,
input VAR8 ,
input VAR5 ,
output VAR1 ,
input VAR4 ,
input VAR6,
input VAR2,
input VAR9
);
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/nf2/reference_core/src/nf2_core.v | 31,140 | module MODULE1 #(
parameter VAR56 = 2
)
(
input wire [26:0] VAR179,
input wire VAR10,
output wire [31:0] VAR52,
input wire VAR5,
input wire [31:0] VAR35,
output wire VAR92,
output wire VAR205,
output wire [31:0] VAR190,
output [7:0] VAR228,
output VAR106,
input VAR207,
output VAR238,
output VAR204,
input [7:0] VAR102,
... | mit |
DougFirErickson/parallella-hw | fpga/src/stubs/hdl/ISERDESE2.v | 3,227 | module MODULE1 (
VAR46, VAR23, VAR43, VAR21, VAR28, VAR26, VAR41, VAR32, VAR20, VAR25, VAR31,
VAR1, VAR30, VAR37, VAR40, VAR4, VAR15, VAR14, VAR47, VAR6,
VAR42, VAR10, VAR22, VAR24, VAR5, VAR39, VAR12, VAR45
);
parameter VAR16 = 0; parameter VAR9 = 0; parameter VAR34 = 0; parameter VAR8 = 0; parameter VAR18 = 0; parame... | gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v | 40,363 | module MODULE1 #(
parameter VAR90 = "VAR251",
parameter integer VAR169 = 0,
parameter integer VAR181 = 0,
parameter integer VAR15 = 0,
parameter integer VAR10 = 4,
parameter integer VAR196 = 32,
parameter integer VAR157 = 32,
parameter integer VAR23 = 1,
parameter integer VAR124 = 1,
parameter integer VAR99 = 0,
parame... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode.functional.pp.v | 1,208 | module MODULE1 (
VAR3,
VAR4 ,
VAR2 ,
VAR5 ,
VAR1
);
input VAR3;
input VAR4 ;
input VAR2 ;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/stratix_dmem.v | 7,625 | module MODULE1 (
address,
VAR28,
VAR42,
VAR22,
VAR49,
VAR55,
VAR9);
input [9:0] address;
input [1:0] VAR28;
input VAR42;
input VAR22;
input [15:0] VAR49;
input VAR55;
output [15:0] VAR9;
tri1 [1:0] VAR28;
tri1 VAR42;
tri1 VAR22;
wire [15:0] VAR34;
wire [15:0] VAR9 = VAR34[15:0];
VAR43 VAR20 (
.VAR50 (VAR42),
.VAR3 (VAR... | bsd-3-clause |
aospan/NetUP_Dual_Universal_CI-fpga | ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v | 71,781 | module MODULE1
(
address,
VAR19,
VAR14,
VAR23,
VAR34,
VAR5,
VAR26,
VAR39,
VAR40,
VAR33,
VAR35,
reset,
VAR17,
VAR24) ;
input [15:0] address;
output VAR19;
input [15:0] VAR14;
output [15:0] VAR23;
input VAR34;
output VAR5;
output VAR26;
output VAR39;
input VAR40;
input [8:0] VAR33;
input VAR35;
input reset;
input VAR17;
... | gpl-3.0 |
JakeMercer/mac | MAC/rtl/mac/utilities/utilities.v | 1,939 | module MODULE1 #(
parameter VAR4 = 8,
parameter VAR6 = 8,
parameter VAR7 = 0
)(
output reg [VAR6-1:0] VAR9,
output reg VAR5,
input wire [VAR4-1:0] VAR10,
output reg VAR8,
input wire VAR2
);
integer VAR1;
integer VAR3;
begin
begin
begin
begin
end
begin
begin
begin
end
begin
begin
begin | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad7091_v1_00_a/hdl/verilog/axi_ad7091.v | 11,814 | module MODULE1(
VAR32,
VAR110,
VAR98,
VAR121,
VAR109,
VAR68,
VAR40,
VAR140,
VAR148,
VAR39,
VAR136,
VAR104,
VAR129,
VAR116,
VAR26,
VAR149,
VAR155,
VAR119,
VAR108,
VAR122,
VAR62,
VAR31,
VAR1,
VAR120,
VAR23,
VAR70,
VAR85,
VAR139,
VAR100,
VAR54,
VAR91,
VAR19,
VAR115,
VAR47,
VAR50,
VAR107,
VAR45
);
parameter VAR30 = 0;
para... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_4.behavioral.v | 1,093 | module MODULE1( VAR1, VAR2 );
input VAR1;
output VAR2;
VAR3 VAR4(.VAR1(VAR1),.VAR2(VAR2));
VAR3 VAR5(.VAR1(VAR1),.VAR2(VAR2)); | apache-2.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_processing_system7_0_0/hdl/processing_system7_bfm_v2_0_axi_slave.v | 37,656 | module MODULE1 (
VAR107,
VAR46,
VAR47,
VAR18,
VAR176,
VAR166,
VAR54,
VAR161,
VAR165,
VAR6,
VAR87,
VAR76,
VAR38,
VAR169,
VAR106,
VAR11,
VAR81,
VAR56,
VAR117,
VAR179,
VAR160,
VAR5,
VAR152,
VAR19,
VAR69,
VAR70,
VAR86,
VAR53,
VAR178,
VAR25,
VAR9,
VAR64,
VAR118,
VAR68,
VAR89,
VAR95,
VAR72,
VAR113,
VAR142,
VAR62,
VAR100,
VAR... | bsd-2-clause |
borti4938/sd2snes | verilog/sd2snes_sdd1/mcu_cmd.v | 12,051 | module MODULE1(
input clk,
input VAR56,
input VAR25,
input [7:0] VAR39,
input [7:0] VAR2,
output [2:0] VAR22,
output reg VAR13 = 0,
output VAR12,
output reg VAR15 = 0,
input VAR7,
output [7:0] VAR28,
input [7:0] VAR44,
output [7:0] VAR45,
input [31:0] VAR16,
input [2:0] VAR29,
output [23:0] VAR49,
output [23:0] VAR31,
... | gpl-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_rate_limit.v | 6,470 | module MODULE1 #
(
parameter VAR35 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR35-1:0] VAR28,
input wire VAR25,
output wire VAR12,
input wire VAR21,
input wire VAR4,
output wire [VAR35-1:0] VAR24,
output wire VAR18,
input wire VAR3,
output wire VAR17,
output wire VAR22,
input wire [7:0] VAR29,
input wire [7:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a.pp.blackbox.v | 1,385 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR7 ,
VAR4 ,
VAR6 ,
VAR1,
VAR2,
VAR8 ,
VAR3
);
output VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR1;
input VAR2;
input VAR8 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o_4.v | 2,310 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR3 ,
VAR10 ,
VAR8 ,
VAR4 ,
VAR1,
VAR9
);
output VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR4 ;
input VAR1;
input VAR9;
VAR5 VAR6 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODUL... | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_s00_data_fifo_0/synth/zc702_s00_data_fifo_0.v | 10,808 | module MODULE1 (
VAR20,
VAR21,
VAR101,
VAR57,
VAR99,
VAR16,
VAR92,
VAR41,
VAR46,
VAR80,
VAR45,
VAR86,
VAR29,
VAR24,
VAR87,
VAR83,
VAR12,
VAR2,
VAR113,
VAR17,
VAR55,
VAR52,
VAR23,
VAR66,
VAR61,
VAR32,
VAR112,
VAR25,
VAR56,
VAR34,
VAR110,
VAR109,
VAR40,
VAR8,
VAR105,
VAR49,
VAR70,
VAR79,
VAR72,
VAR5
);
input wire VAR20;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31o/sky130_fd_sc_hd__a31o.functional.pp.v | 2,026 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR1 ,
VAR15 ,
VAR8 ,
VAR5,
VAR9,
VAR12 ,
VAR3
);
output VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR15 ;
input VAR8 ;
input VAR5;
input VAR9;
input VAR12 ;
input VAR3 ;
wire VAR2 ;
wire VAR4 ;
wire VAR17;
and VAR13 (VAR2 , VAR15, VAR7, VAR1 );
or VAR11 (VAR4 , VAR2, VAR8 );
VAR16 VAR14 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr.functional.pp.v | 1,841 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR4 ,
VAR8 ,
VAR1,
VAR5 ,
VAR11
);
output VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR8 ;
input VAR1;
input VAR5 ;
input VAR11 ;
wire VAR2 ;
wire VAR10;
not VAR12 (VAR2 , VAR9 );
VAR3 VAR13 (VAR10, VAR2, VAR1, VAR8);
buf VAR6 (VAR7 , VAR10 );
endmodule | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/daisho-usb3/usb3_descramble.v | 7,460 | module MODULE1 (
input wire VAR34,
input wire VAR41,
input wire VAR8,
input wire enable,
input wire [1:0] VAR32,
input wire [5:0] VAR12,
input wire [1:0] VAR18,
input wire [3:0] VAR21,
input wire [31:0] VAR28,
output reg [3:0] VAR4,
output reg [31:0] VAR40,
output reg VAR25,
output reg VAR43
);
wire [3:0] VAR11 = { (VA... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i.behavioral.v | 1,654 | module MODULE1 (
VAR2 ,
VAR4,
VAR12,
VAR7
);
output VAR2 ;
input VAR4;
input VAR12;
input VAR7 ;
supply1 VAR5;
supply0 VAR11;
supply1 VAR8 ;
supply0 VAR3 ;
wire VAR9;
VAR6 VAR1 (VAR9, VAR4, VAR12, VAR7 );
buf VAR10 (VAR2 , VAR9);
endmodule | apache-2.0 |
cpulabs/mist1032sa | src/dps/device/utim64/dps_utim64.v | 6,674 | module MODULE1(
input wire VAR38, input wire VAR4,
input wire VAR21,
input wire VAR28,
output wire VAR29,
input wire VAR36,
input wire [4:0] VAR9,
input wire [31:0] VAR17,
output wire VAR5,
output wire [31:0] VAR11,
output wire VAR22,
input wire VAR34
);
wire [3:0] VAR6;
wire [3:0] VAR33;
reg [1:0] VAR18;
reg [7:0] VAR... | bsd-2-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_fptoui.v | 2,403 | module MODULE1(VAR11, VAR5,
VAR18, VAR3, VAR25,
VAR23, VAR1, VAR20);
parameter VAR16 = 32;
parameter VAR15 = 3;
parameter VAR6 = 64;
input VAR11, VAR5;
input [VAR16-1:0] VAR18;
input VAR3;
output VAR25;
output [VAR16-1:0] VAR23;
input VAR1;
output VAR20;
reg [VAR15-1:0] VAR21;
wire [VAR16-1:0] VAR2;
wire VAR19;
wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep.symbol.v | 1,543 | module MODULE1 (
input VAR9 ,
output VAR8 ,
input VAR1 ,
input VAR7
);
supply1 VAR3 ;
supply0 VAR5 ;
supply1 VAR2;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b.functional.v | 1,389 | module MODULE1 (
VAR4 ,
VAR5,
VAR1 ,
VAR3
);
output VAR4 ;
input VAR5;
input VAR1 ;
input VAR3 ;
wire VAR9 ;
wire VAR2;
not VAR6 (VAR9 , VAR5 );
and VAR7 (VAR2, VAR3, VAR9, VAR1 );
buf VAR8 (VAR4 , VAR2 );
endmodule | apache-2.0 |
kactus2/ipxactexamplelib | tut.fi/cpu.logic/instruction_decoder/1.0/instruction_decoder.v | 8,411 | module MODULE1 #(
parameter VAR9 = 4, parameter VAR32 = 16, parameter VAR13 = 4, parameter VAR21 = VAR13+2*VAR9+VAR32, parameter VAR30 = 16, parameter VAR40 = 3, parameter VAR11 = 8 ) (
input VAR19, input VAR6,
input [VAR30-1:0] VAR25,
input [VAR30-1:0] VAR4,
input VAR26,
output reg VAR14,
output reg [VAR40-1:0] VAR46,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_nsr/sky130_fd_sc_hd__udp_dff_nsr.symbol.v | 1,408 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR1,
input VAR3 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.v | 2,411 | module MODULE1 (
VAR1 ,
VAR4,
VAR9,
VAR2 ,
VAR6 ,
VAR8,
VAR7,
VAR3 ,
VAR10
);
output VAR1 ;
input VAR4;
input VAR9;
input VAR2 ;
input VAR6 ;
input VAR8;
input VAR7;
input VAR3 ;
input VAR10 ;
VAR11 VAR5 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/image_filter_CvtColor.v | 27,315 | module MODULE1 (
VAR73,
VAR117,
VAR66,
VAR57,
VAR22,
VAR123,
VAR72,
VAR45,
VAR13,
VAR33,
VAR48,
VAR2,
VAR114,
VAR94,
VAR4,
VAR133,
VAR16,
VAR105,
VAR38,
VAR93
);
parameter VAR125 = 1'b1;
parameter VAR21 = 1'b0;
parameter VAR78 = 4'b1;
parameter VAR76 = 4'b10;
parameter VAR27 = 4'b100;
parameter VAR25 = 4'b1000;
paramet... | gpl-3.0 |
silverfoxy/MIPS-Verilog | Pipeline/Core.v | 12,003 | module MODULE1(
input clk,
input VAR5,
output VAR25,
output VAR52,
output VAR23,
output VAR18,
output VAR35,
output VAR20,
output dout,
output VAR37,
output wr,
output VAR16,
output VAR11,
output VAR27,
output VAR44,
output VAR33,
output VAR58,
output VAR41,
output VAR32,
output VAR49,
output VAR63,
output VAR8,
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi_2.v | 2,348 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR1 ,
VAR7,
VAR9,
VAR6,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR7;
input VAR9;
input VAR6;
input VAR8 ;
input VAR2 ;
VAR4 VAR10 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_p_pp_pkg_s/sky130_fd_sc_hs__udp_dff_p_pp_pkg_s.blackbox.v | 1,423 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR6 ,
VAR2,
VAR7 ,
VAR5 ,
VAR4
);
output VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR2;
input VAR7 ;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v | 34,467 | module MODULE1
parameter VAR41 = 1,
parameter VAR133 = 8,
parameter VAR119 = 16,
parameter VAR109 = 0,
parameter VAR17 = 0,
parameter VAR91 = 0,
parameter VAR132 = 0,
parameter VAR76 = 0,
parameter VAR104 = 0,
parameter VAR101 = 0,
parameter VAR100 = 3,
parameter VAR37 = 1,
parameter VAR121 = VAR41 * VAR133,
parameter ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv.symbol.v | 1,264 | module MODULE1 (
input VAR2,
output VAR1
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2_lp.v | 2,195 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR6 ,
VAR4 ,
VAR1,
VAR9,
VAR3 ,
VAR8
);
output VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR4 ;
input VAR1;
input VAR9;
input VAR3 ;
input VAR8 ;
VAR7 VAR2 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111ai/sky130_fd_sc_hs__o2111ai_1.v | 2,334 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR1 ,
VAR5 ,
VAR2 ,
VAR10 ,
VAR6,
VAR7
);
output VAR3 ;
input VAR8 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR10 ;
input VAR6;
input VAR7;
VAR4 VAR9 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODUL... | apache-2.0 |
jhol/butterflylogic | rtl/cdc.v | 9,039 | module MODULE1 #(
parameter integer VAR6 = 1, parameter integer VAR28 = 4, parameter integer VAR21 = 2, parameter VAR17 = 1, parameter VAR30 = 1 )(
input wire VAR7, input wire VAR2, input wire [VAR6-1:0] VAR18, input wire VAR29, output wire VAR8, input wire VAR36, input wire VAR20, output wor [VAR6-1:0] VAR22, output w... | gpl-2.0 |
wamgoo/FPGA-Imaging-Library | Geometry/Rotate/HDL/Rotate.srcs/sources_1/new/SinLUT.v | 18,447 | module MODULE1(VAR3, VAR2);
input[8 : 0] VAR3;
output[19 : 0] VAR2;
reg[19 : 0] VAR1;
assign VAR2 = VAR1;
always@(*) begin
case(VAR3)
0 : VAR1 <= 20'b00000000000000000000;
1 : VAR1 <= 20'b00000001000111011110;
2 : VAR1 <= 20'b00000010001110111100;
3 : VAR1 <= 20'b00000011010110010111;
4 : VAR1 <= 20'b000001000111011011... | lgpl-2.1 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/altera_avalon_st_clock_crosser.v | 4,879 | module MODULE1(
VAR31,
VAR6,
VAR20,
VAR11,
VAR14,
VAR26,
VAR5,
VAR8,
VAR25,
VAR9
);
parameter VAR17 = 1;
parameter VAR12 = 8;
parameter VAR4 = 2;
parameter VAR27 = 2;
parameter VAR16 = 1;
localparam VAR33 = VAR17 * VAR12;
input VAR31;
input VAR6;
output VAR20;
input VAR11;
input [VAR33-1:0] VAR14;
input VAR26;
input VA... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_pattern_fifo.v | 2,756 | module MODULE1 (
VAR31,
VAR39,
VAR32,
VAR3,
VAR5,
VAR6);
input VAR31;
input [8:0] VAR39;
input [4:0] VAR32;
input [4:0] VAR3;
input VAR5;
output [8:0] VAR6;
tri1 VAR31;
tri0 VAR5;
wire [8:0] VAR14;
wire [8:0] VAR6 = VAR14[8:0];
VAR21 VAR54 (
.VAR15 (VAR3),
.VAR46 (VAR31),
.VAR37 (VAR39),
.VAR22 (VAR5),
.VAR33 (VAR32),
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.behavioral.pp.v | 2,782 | module MODULE1( VAR15, VAR20, VAR12, VAR26, VAR13, VAR7 );
input VAR12, VAR20, VAR15;
inout VAR13, VAR7;
output VAR26;
reg VAR3;
VAR14 VAR21(.VAR15(VAR15),.VAR20(VAR20),.VAR12(VAR12),.VAR26(VAR26),.VAR13(VAR13),.VAR7(VAR7),.VAR3(VAR3));
VAR14 VAR2(.VAR15(VAR15),.VAR20(VAR20),.VAR12(VAR12),.VAR26(VAR26),.VAR13(VAR13),.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a222oi/sky130_fd_sc_hd__a222oi_1.v | 2,542 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR11 ,
VAR9 ,
VAR4 ,
VAR8 ,
VAR1 ,
VAR10,
VAR3,
VAR7 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR11 ;
input VAR9 ;
input VAR4 ;
input VAR8 ;
input VAR1 ;
input VAR10;
input VAR3;
input VAR7 ;
input VAR2 ;
VAR12 VAR13 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR4(VAR4),
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand3/sky130_fd_sc_hvl__nand3.pp.blackbox.v | 1,297 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR3 ,
VAR1 ,
VAR2,
VAR6,
VAR5 ,
VAR4
);
output VAR7 ;
input VAR8 ;
input VAR3 ;
input VAR1 ;
input VAR2;
input VAR6;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/Zero_InfMult_Unit.v | 1,459 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR4,
input wire [VAR15-2:0] VAR7,
input wire [VAR15-2:0] VAR17,
output wire VAR13
);
wire VAR18, VAR3;
wire [VAR15-2:0] VAR11;
wire VAR8;
VAR2 #(.VAR9(VAR15-1)) VAR10 (
.VAR7(VAR7),
.VAR17(VAR11),
.VAR1(VAR18)
);
VAR2 #(.VAR9(VAR15-1)) VAR14 (
.VAR7(VAR11),
.... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbuf/sky130_fd_sc_lp__lsbuf.functional.pp.v | 1,862 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR7,
VAR10 ,
VAR4 ,
VAR1,
VAR12 ,
VAR13
);
output VAR9 ;
input VAR8 ;
input VAR7;
input VAR10 ;
input VAR4 ;
input VAR1;
input VAR12 ;
input VAR13 ;
wire VAR6;
wire VAR3 ;
VAR14 VAR2 (VAR6, VAR8, VAR10, VAR4 );
buf VAR5 (VAR3 , VAR6 );
VAR14 VAR11 (VAR9 , VAR3, VAR7, VAR4);
endmodule | apache-2.0 |
phasza/axi_spi_if | axi_slv.v | 12,112 | module MODULE1 #(
parameter VAR51 = 28
) (
input VAR54, input VAR27,
input VAR30,
output VAR47,
input [VAR51-1:0] VAR4,
input VAR2,
input VAR50,
output VAR55,
input [31:0] VAR16,
input [3:0] VAR19,
output VAR38,
input VAR28,
output [1:0] VAR23,
input VAR1,
output VAR21,
input [VAR51-1:0] VAR14,
input [2:0] VAR33,
outpu... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/fifo_with_byteenables.v | 5,519 | module MODULE1 (
clk,
VAR44,
VAR41,
VAR25,
VAR28,
write,
VAR34,
VAR33,
VAR37,
VAR22,
VAR23,
VAR6
);
parameter VAR3 = 32;
parameter VAR32 = 128;
parameter VAR35 = 7; parameter VAR9 = 1;
input clk;
input VAR44;
input VAR41;
input [VAR3-1:0] VAR25;
input [(VAR3/8)-1:0] VAR28;
input write;
input VAR34; output wire [VAR3-1:... | gpl-3.0 |
walkthetalk/fsref | ip/fscpu/src/fscpu.v | 30,934 | module MODULE1 #(
parameter integer VAR64 = 12,
parameter integer VAR208 = 12,
parameter integer VAR249 = 32,
parameter integer VAR68 = 32
)(
input wire clk,
input wire VAR165,
input wire VAR6,
input wire VAR184,
input wire [VAR68-1:0] VAR314,
output wire [VAR208:0] VAR76,
input wire VAR266,
input wire VAR101,
input wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.blackbox.v | 1,197 | module MODULE1 (
VAR3,
VAR5,
VAR1
);
output VAR3;
input VAR5;
input VAR1;
supply1 VAR2;
supply0 VAR4;
endmodule | apache-2.0 |
davidlee80/miaow | src/verilog/rtl/lsu/lsu_transit_table.v | 1,660 | module MODULE1(
VAR15,
VAR11,
VAR18,
VAR9,
VAR7,
VAR20,
VAR10,
VAR22,
VAR21,
VAR14,
VAR16,
VAR4,
VAR5,
clk,
rst
);
input [6:0] VAR15;
input [5:0] VAR11;
input [11:0] VAR18;
input [63:0] VAR9;
input VAR7;
input [3:0] VAR20;
input [3:0] VAR10;
input [31:0] VAR22;
output [63:0] VAR21;
output VAR14;
output [11:0] VAR16;
ou... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b_lp.v | 2,319 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR4 ,
VAR11 ,
VAR10 ,
VAR9,
VAR5,
VAR8 ,
VAR2
);
output VAR7 ;
input VAR1 ;
input VAR4 ;
input VAR11 ;
input VAR10 ;
input VAR9;
input VAR5;
input VAR8 ;
input VAR2 ;
VAR3 VAR6 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.... | apache-2.0 |
kyzhai/NUNY | src/hardware/two_new2_bb.v | 5,008 | module MODULE1 (
address,
VAR2,
VAR1);
input [9:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
cynngah/virtualsynthesizer | vga_adapter.v | 13,730 | module MODULE1(
VAR41,
VAR65,
VAR73,
VAR50, VAR3, VAR38,
VAR37,
VAR56,
VAR52,
VAR28,
VAR48,
VAR30,
VAR26,
VAR57);
parameter VAR54 = 1;
parameter VAR9 = "VAR6";
parameter VAR20 = "320x240";
parameter VAR34 = "VAR45.VAR27";
input VAR41;
input VAR65;
input [((VAR9 == "VAR1") ? (0) : (VAR54*3-1)):0] VAR73;
input [((VAR20 =... | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_phy_oclkdelay_cal.v | 52,403 | module MODULE1 #
(
parameter VAR69 = 100,
parameter VAR100 = 2500,
parameter VAR60 = 4,
parameter VAR106 = "VAR33",
parameter VAR160 = 8,
parameter VAR125 = 3,
parameter VAR138 = 8,
parameter VAR11 = 64,
parameter VAR53 = "VAR55",
parameter VAR48 = "VAR129"
)
(
input clk,
input rst,
input VAR154,
input VAR97,
input [5:... | bsd-2-clause |
horia141/bachelor-thesis | prj/applications/BigSDRAM/BigSDRAMFPGA.v | 2,177 | module MODULE1(VAR22,reset,VAR14,VAR24,VAR28,VAR2,VAR23,VAR17,VAR5,VAR19,VAR3,VAR7,VAR39,VAR11,VAR38);
input wire VAR22;
input wire reset;
output wire [7:0] VAR14;
output wire VAR24;
output wire VAR28;
output wire VAR2;
output wire VAR23;
output wire VAR17;
output wire VAR5;
output wire VAR19;
output wire [1:0] VAR3;
o... | mit |
terriblefire/tf530 | rtl/tf530ram/tf530_ram.v | 4,680 | module MODULE1(
input VAR47,
input VAR42,
input VAR50,
input VAR1,
input [8:2] VAR27,
input [23:12] VAR52,
inout [7:0] VAR37,
input [1:0] VAR46,
input VAR53,
input VAR33,
output VAR26,
input VAR43,
input VAR10,
input VAR49,
input VAR55,
output VAR23,
output VAR16,
output VAR13,
output VAR17,
output VAR29,
output [3:0] ... | gpl-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_YCrCb_to_RGB_converter.v | 12,279 | module MODULE1 (
clk,
VAR43,
reset,
VAR41,
VAR37,
VAR3,
VAR7,
VAR13,
VAR1,
VAR48,
VAR38,
VAR47,
VAR51,
VAR2,
VAR52,
VAR30,
VAR18
);
input clk;
input VAR43;
input reset;
input [ 7: 0] VAR41;
input [ 7: 0] VAR37;
input [ 7: 0] VAR3;
input VAR7;
input VAR13;
input VAR1;
input VAR48;
output reg [ 7: 0] VAR38;
output reg [ ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp.pp.blackbox.v | 1,463 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR11 ,
VAR7 ,
VAR3 ,
VAR5 ,
VAR2 ,
VAR4,
VAR9,
VAR6 ,
VAR1
);
output VAR8 ;
output VAR10 ;
input VAR11 ;
input VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR2 ;
input VAR4;
input VAR9;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
mamijaz/RISC-V | src/riscv_procesor/RISCV_PROCESSOR.v | 23,710 | module MODULE1 #(
parameter VAR160 = 32 ,
parameter VAR144 = 32 ,
parameter VAR86 = 5 ,
parameter VAR97 = 5 ,
parameter VAR39 = 3 ,
parameter VAR146 = 2 ,
parameter VAR20 = 26 ,
parameter VAR50 = 512 ,
parameter VAR175 = 32
) (
input VAR85 ,
input VAR122 ,
output VAR100 ,
output [VAR20-1 : 0] VAR98 ,
input VAR82 ,
outp... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_1.behavioral.pp.v | 18,378 | module MODULE1( VAR283, VAR8, VAR225, VAR175, VAR230, VAR227, VAR257, VAR177 );
input VAR175, VAR225, VAR230, VAR283, VAR8;
inout VAR257, VAR177;
output VAR227;
reg VAR240;
VAR117 VAR279(.VAR283(VAR283),.VAR8(VAR8),.VAR225(VAR225),.VAR175(VAR175),.VAR230(VAR230),.VAR227(VAR227),.VAR257(VAR257),.VAR177(VAR177),.VAR240(V... | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/fpgaTop_sp605.v | 1,097 | module MODULE1(
input wire VAR19, input wire VAR18, input wire VAR2, input wire VAR6, input wire VAR16, output wire [7:0] VAR14, output wire [7:0] VAR10,
input wire [7:0] VAR13,
input wire [7:0] VAR1,
output wire [2:0] VAR3, input wire VAR9, output wire VAR11 );
VAR15 VAR20(
.VAR19 (VAR19),
.VAR18 (VAR18),
.VAR2 (VAR2)... | lgpl-3.0 |
rurume/openrisc_vision_hardware | ISE/uart_debug_if.v | 5,946 | module MODULE1 (
VAR5,
VAR2, VAR8, VAR9, VAR11, VAR14, VAR15, VAR13,
VAR12, VAR1, VAR4, VAR7, VAR6
) ;
input [VAR3-1:0] VAR2;
output [31:0] VAR5;
input [3:0] VAR8;
input [3:0] VAR9;
input [1:0] VAR11; input [4:0] VAR14;
input [7:0] VAR15;
input [7:0] VAR13;
input [7:0] VAR12;
input [VAR10-1:0] VAR1;
input [VAR10-1:0] V... | gpl-2.0 |
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