repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o_1.v | 2,321 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR8 ,
VAR9 ,
VAR1 ,
VAR2 ,
VAR7,
VAR10
);
output VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR2 ;
input VAR7;
input VAR10;
VAR3 VAR5 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai.behavioral.pp.v | 2,059 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR17 ,
VAR3 ,
VAR15 ,
VAR4 ,
VAR9,
VAR2,
VAR12 ,
VAR11
);
output VAR6 ;
input VAR5 ;
input VAR17 ;
input VAR3 ;
input VAR15 ;
input VAR4 ;
input VAR9;
input VAR2;
input VAR12 ;
input VAR11 ;
wire VAR18 ;
wire VAR13 ;
wire VAR1;
or VAR14 (VAR18 , VAR15, VAR3, VAR17, VAR5 );
nand VAR16 (VA... | apache-2.0 |
ultraembedded/riscv | top_cache_axi/src_v/icache_data_ram.v | 2,864 | module MODULE1
(
input VAR5
,input VAR1
,input [ 10:0] VAR3
,input [ 31:0] VAR6
,input VAR8
,output [ 31:0] VAR4
);
reg [31:0] VAR2 [2047:0] ;
reg [31:0] VAR7;
always @ (posedge VAR5)
begin
if (VAR8)
VAR2[VAR3] <= VAR6;
VAR7 <= VAR2[VAR3];
end
assign VAR4 = VAR7;
endmodule | bsd-3-clause |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_jtag.v | 16,863 | module MODULE1 (
clk,
VAR33,
VAR19,
VAR6,
VAR14,
VAR27,
VAR3
)
;
output VAR6;
output [ 7: 0] VAR14;
output VAR27;
output [ 5: 0] VAR3;
input clk;
input [ 7: 0] VAR33;
input VAR19;
wire VAR6;
wire [ 7: 0] VAR14;
wire VAR27;
wire [ 5: 0] VAR3;
always @(posedge clk)
begin
if (VAR19)
("%VAR2", VAR33);
end
assign VAR3 = {6{... | mit |
SiLab-Bonn/basil | basil/firmware/modules/tlu/tlu_controller.v | 3,361 | module MODULE1 #(
parameter VAR38 = 16'h0000,
parameter VAR2 = 16'h0000,
parameter VAR22 = 16,
parameter VAR16 = 8,
parameter VAR26 = 8,
parameter VAR31 = 17,
parameter VAR18 = 32
) (
input wire VAR44,
input wire VAR19,
input wire [VAR22-1:0] VAR27,
inout wire [7:0] VAR40,
input wire VAR9,
input wire VAR15,
input wire ... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_invctl.v | 23,833 | module MODULE1(
VAR12, VAR87, VAR98, VAR125,
VAR1, VAR119, VAR88,
VAR53, VAR63, VAR60, VAR10, VAR109,
VAR39, VAR100,
VAR117, VAR20, VAR104,
VAR110, VAR108, VAR7
);
input VAR53,
VAR63,
VAR60;
input [2:0] VAR10;
input VAR109;
input [VAR69:5] VAR39;
input VAR100;
input [1:0] VAR117;
input VAR20;
input VAR104;
input [VAR69... | gpl-2.0 |
csail-csg/recycle-bsv-lib | src/v/EHR_8.v | 3,684 | module MODULE1 (
VAR17,
VAR30,
VAR4,
VAR31,
VAR25,
VAR22,
VAR3,
VAR33,
VAR2,
VAR11,
VAR15,
VAR8,
VAR32,
VAR28,
VAR5,
VAR18,
VAR9,
VAR34,
VAR23,
VAR35,
VAR21,
VAR29,
VAR37,
VAR14,
VAR36,
VAR7
);
parameter VAR20 = 1;
parameter VAR27 = 0;
input VAR17;
input VAR30;
output [VAR20-1:0] VAR4;
input [VAR20-1:0] VAR31;
input VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b.functional.v | 1,432 | module MODULE1 (
VAR1 ,
VAR10,
VAR9 ,
VAR6 ,
VAR8
);
output VAR1 ;
input VAR10;
input VAR9 ;
input VAR6 ;
input VAR8 ;
wire VAR7 ;
wire VAR4;
not VAR2 (VAR7 , VAR10 );
nand VAR3 (VAR4, VAR8, VAR6, VAR9, VAR7);
buf VAR5 (VAR1 , VAR4 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_tag/bsg_tag_master_decentralized.v | 9,143 | module MODULE1
import VAR21::VAR9;
,VAR3(VAR16)
,VAR3(VAR10)
,VAR22=1
,VAR14=VAR4(VAR18)
,VAR5=VAR4(VAR16)
)
(
input VAR20
,input VAR30
,input [VAR14-1:0] VAR17
,output VAR9 [VAR16-1:0] VAR24
);
localparam VAR8 = VAR19(VAR18,VAR10);
localparam VAR15 = VAR6(VAR18,VAR10);
localparam VAR31 = VAR4(VAR8+1);
if (VAR22 > 2)
a... | bsd-3-clause |
anderson1008/NOCulator | hring/hw/buffered/src/c_tree_arbiter.v | 3,552 | module MODULE1
(clk, reset, VAR13, req, VAR16);
parameter VAR3 = 16;
parameter VAR17 = 4;
localparam VAR6 = VAR3 / VAR17;
parameter VAR12 = VAR4;
parameter VAR2 = VAR14;
input clk;
input reset;
input VAR13;
input [0:VAR3-1] req;
output [0:VAR3-1] VAR16;
wire [0:VAR3-1] VAR16;
wire [0:VAR17-1] VAR7;
wire [0:VAR17-1] VAR... | mit |
adamgreig/bladeRF | hdl/fpga/ip/opencores/i2c/bench/verilog/spi_slave_model.v | 3,840 | module MODULE1 (
input wire VAR5;
input wire VAR12
input wire VAR7;
output wire do
);
wire VAR8 = 1'b1;
wire VAR1 = 1'b0;
wire VAR10 = 1'b0;
reg [7:0] VAR13 [7:0]; reg [2:0] VAR3; reg [7:0] VAR9;
reg [7:0] VAR6, VAR2;
reg [2:0] VAR11;
reg VAR14;
wire clk;
assign clk = VAR1 ^ VAR10 ^ VAR12;
always @(posedge clk)
VAR6 <=... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfsbp/sky130_fd_sc_ls__sdfsbp.symbol.v | 1,524 | module MODULE1 (
input VAR4 ,
output VAR1 ,
output VAR3 ,
input VAR11,
input VAR7 ,
input VAR5 ,
input VAR9
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufinv/sky130_fd_sc_hd__bufinv.pp.blackbox.v | 1,259 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR5,
VAR1,
VAR3 ,
VAR2
);
output VAR6 ;
input VAR4 ;
input VAR5;
input VAR1;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.functional.v | 1,142 | module MODULE1( VAR7, VAR12, VAR5 );
input VAR12, VAR7;
output VAR5;
wire VAR11;
not VAR4( VAR11, VAR7 );
wire VAR3;
and VAR1( VAR3, VAR11, VAR12 );
wire VAR6;
not VAR10( VAR6, VAR12 );
wire VAR9;
and VAR8( VAR9, VAR6, VAR7 );
or VAR2( VAR5, VAR3, VAR9 );
endmodule | apache-2.0 |
cathalmccabe/PYNQ | boards/ip/io_switch_1.1/src/io_switch_bit.v | 9,346 | module MODULE1 #(
parameter VAR14 = 6,
parameter VAR49 = 8,
parameter VAR15 = 2
)
(
input [7:0] VAR5,
input VAR17,
output reg VAR37,
output reg VAR60,
output VAR58,
input VAR57,
input VAR22,
output VAR9,
input VAR21,
output VAR59,
input VAR56,
output VAR3,
input VAR33,
input VAR54,
output VAR10,
input VAR31,
input VAR2... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode_8.v | 1,901 | module MODULE2 (
VAR4,
VAR2,
VAR3 ,
VAR5
);
input VAR4;
input VAR2;
input VAR3 ;
input VAR5 ;
VAR1 VAR6 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 ();
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR5 ;
VAR1 VAR6 ();
endmodule | apache-2.0 |
q3k/q3kmips | rtl/verilog/qm_top.v | 4,788 | module MODULE1(
input wire clk
);
reg VAR40;
reg VAR34;
reg VAR10;
reg [3:0] VAR84;
reg VAR61;
reg VAR4;
wire VAR54;
wire VAR32;
wire VAR28;
wire [3:0] VAR73;
wire VAR45;
wire VAR38;
reg [31:0] VAR78;
reg [31:0] VAR13;
reg [31:0] VAR33;
reg [31:0] VAR3;
reg [31:0] VAR72;
reg [31:0] VAR56;
reg [31:0] VAR42;
wire [31:0] ... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.functional.v | 1,734 | module MODULE1( VAR20, VAR22, VAR25, VAR17, VAR5, VAR23, VAR7 );
input VAR17, VAR25, VAR20, VAR5, VAR22, VAR7;
output VAR23;
not VAR16( VAR13, VAR5 );
wire VAR9;
not VAR24( VAR9, VAR25 );
wire VAR26;
not VAR21( VAR26, VAR20 );
wire VAR14;
and VAR11( VAR14, VAR9, VAR26 );
wire VAR19;
not VAR4( VAR19, VAR22 );
wire VAR15... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuflp/sky130_fd_sc_lp__clkbuflp.blackbox.v | 1,249 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR6;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4b/sky130_fd_sc_hd__or4b.symbol.v | 1,317 | module MODULE1 (
input VAR4 ,
input VAR5 ,
input VAR7 ,
input VAR8,
output VAR9
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
RP7/R7-OCM | src/rtl/A2S_controller.v | 2,951 | module MODULE1(
rst,
VAR6,
sync,
VAR12,
VAR2,
VAR16,
VAR28,
VAR5,
VAR8,
VAR23,
VAR21,
VAR26,
VAR7,
VAR14,
VAR27,
VAR9,
VAR10,
VAR19,
VAR20
);
parameter VAR22 = 3'd0;
parameter VAR17 = 3'd1;
parameter VAR4 = 3'd2;
parameter VAR11 = 3'd3;
input rst,VAR6,sync,VAR12;
output[4:0] VAR2;
input VAR23;
input VAR21;
output reg[3... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/system_acl_iface_acl_kernel_interface.v | 60,109 | module MODULE1 (
input wire VAR307, input wire VAR268, output wire VAR358, output wire [31:0] VAR198, output wire VAR79, input wire [0:0] VAR121, input wire [31:0] VAR331, input wire [13:0] VAR127, input wire VAR58, input wire VAR258, input wire [3:0] VAR4, input wire VAR301, input wire VAR248, input wire [63:0] VAR150... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_4.v | 2,084 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR6,
VAR3,
VAR4 ,
VAR7
);
output VAR2 ;
input VAR1 ;
input VAR6;
input VAR3;
input VAR4 ;
input VAR7 ;
VAR8 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR6;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvp/sky130_fd_sc_hd__einvp.blackbox.v | 1,268 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR7
);
output VAR1 ;
input VAR2 ;
input VAR7;
supply1 VAR4;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
Koheron/zynq-sdk | fpga/cores/axi_sts_register_v1_0/axi_sts_register.v | 3,321 | module MODULE1 #
(
parameter integer VAR35 = 1024,
parameter integer VAR17 = 32,
parameter integer VAR26 = 16
)
(
input wire VAR3,
input wire VAR18,
input wire [VAR35-1:0] VAR28,
input wire [VAR26-1:0] VAR11, input wire VAR22, output wire VAR25, input wire [VAR17-1:0] VAR1, input wire VAR6, output wire VAR13, output wi... | mit |
ptracton/Picoblaze | library/gpio/gpio_bit.v | 1,459 | module MODULE1 (
VAR2,
VAR4,
clk, VAR5, VAR1
) ;
input clk;
input VAR5;
input VAR1;
output VAR2;
inout VAR4;
wire VAR2;
wire VAR6;
assign VAR4 = (VAR5) ? VAR1 : 1'VAR3;
assign VAR2 = (!VAR5) ? VAR4 : 1'VAR3;
endmodule | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_8c_v1_00_a/hdl/verilog/user_logic.v | 7,479 | module MODULE1 (
VAR22,
VAR36,
VAR26,
VAR18,
VAR37,
VAR1,
VAR27,
VAR43,
VAR41,
VAR40,
VAR16,
VAR32,
VAR17,
VAR39,
VAR20,
VAR31,
VAR23,
VAR11,
VAR33,
VAR6,
VAR15,
VAR3,
VAR38,
VAR2,
VAR42,
VAR12,
VAR8,
VAR25,
VAR14,
VAR7);
parameter VAR19 = 32;
parameter VAR34 = 32;
input VAR22;
input VAR36;
input [ 7:0] VAR26;
input [ ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s.behavioral.v | 1,757 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR3,
VAR1
);
output VAR9 ;
input VAR10 ;
input VAR3;
input VAR1;
wire VAR2 ;
wire VAR8;
buf VAR6 (VAR2 , VAR10 );
VAR4 VAR5 (VAR8, VAR2, VAR3, VAR1);
buf VAR7 (VAR9 , VAR8 );
endmodule | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_auto_us_0/synth/system_auto_us_0.v | 14,593 | module MODULE1 (
VAR83,
VAR70,
VAR90,
VAR4,
VAR64,
VAR38,
VAR54,
VAR56,
VAR71,
VAR32,
VAR37,
VAR65,
VAR67,
VAR7,
VAR44,
VAR50,
VAR2,
VAR91,
VAR9,
VAR53,
VAR19,
VAR18,
VAR30,
VAR68,
VAR86,
VAR43,
VAR52,
VAR97,
VAR16,
VAR23,
VAR28,
VAR29,
VAR22,
VAR74,
VAR6,
VAR69,
VAR34,
VAR75,
VAR39,
VAR3,
VAR88,
VAR72,
VAR31,
VAR40,
V... | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_inferram.v | 15,962 | module MODULE1(clk, VAR11, VAR1, VAR6, VAR19, VAR10, VAR5, VAR21, VAR12);
parameter VAR18 = "VAR13";
parameter VAR3 = "VAR9";
parameter VAR7 = 1024;
parameter VAR17 = 10;
parameter VAR8 = 8;
parameter VAR22 = 4;
parameter VAR16 = 0;
input clk;
input [VAR22-1:0] VAR11;
input [VAR22-1:0] VAR1;
input [VAR17-1:0] VAR6;
inp... | gpl-3.0 |
kristianpaul/milkyminer | cores/fpgaminer/rtl/async_receiver.v | 3,510 | module MODULE1(clk, VAR9, VAR15, VAR7, VAR6, VAR12);
input clk, VAR9;
output VAR15; output [7:0] VAR7;
parameter VAR10 = 80000000; parameter VAR16 = 115200;
output VAR6; output VAR12;
parameter VAR18 = VAR16*8;
parameter VAR2 = 16;
wire [VAR2:0] VAR13 = ((VAR18<<(VAR2-7))+(VAR10>>8))/(VAR10>>7);
reg [VAR2:0] VAR8;
alwa... | lgpl-3.0 |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/raw2rgb/raw2rgb.v | 4,444 | module MODULE1(
VAR10,
VAR26,
VAR28,
VAR19,
VAR6,
VAR15,
VAR25,
VAR22,
VAR17,
VAR27
);
input [10:0] VAR6;
input [10:0] VAR15;
input [11:0] VAR25;
input VAR22;
input VAR17;
input VAR27;
output [11:0] VAR10;
output [11:0] VAR26;
output [11:0] VAR28;
output VAR19;
reg [11:0] VAR12;
reg [12:0] VAR2;
reg [11:0] VAR18;
reg V... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/ll8_to_fifo36.v | 2,799 | module MODULE1
(input clk, input reset, input VAR7,
input [7:0] VAR17,
input VAR1,
input VAR12,
input VAR8,
output VAR18,
output [35:0] VAR14,
output VAR15,
input VAR9 );
wire VAR4 = VAR15 & VAR9;
wire VAR19 = ~VAR1;
wire VAR13 = ~VAR12;
wire VAR5 = ~VAR8;
wire VAR16;
assign VAR18 = ~VAR16;
reg VAR2, VAR3;
reg [1:0] VA... | gpl-2.0 |
oblivioncth/DE0-Verilog-Processor | src/reg_8x8_bit.v | 4,521 | module MODULE1(
VAR14,
reset,
VAR59,
VAR35,
VAR39,
VAR48,
VAR70,
VAR22,
VAR24,
VAR58,
VAR30,
VAR57,
VAR23,
VAR68,
VAR27,
VAR65,
VAR42
);
input wire VAR14;
input wire VAR59;
input wire reset;
input wire [2:0] VAR39;
input wire [2:0] VAR48;
input wire [7:0] VAR70;
input wire [2:0] VAR35;
output wire [7:0] VAR22;
output w... | mit |
GuzTech/swapforth | j1a/icestorm/uart.v | 4,330 | module MODULE2(
input wire clk,
input wire VAR23,
input wire [31:0] VAR28,
input wire VAR32,
output wire VAR13);
parameter VAR27 = 1000000;
wire [38:0] VAR21 = VAR27;
reg [38:0] VAR6;
wire [38:0] VAR26 = VAR6[38] ? ({4'd0, VAR28}) : (({4'd0, VAR28}) - VAR21);
wire [38:0] VAR15 = VAR32 ? 0 : (VAR6 + VAR26);
wire VAR11 =... | bsd-3-clause |
cpulabs/gci-std-display | rtl/lib/gci_std_display_async_fifo.v | 3,962 | module MODULE1 #(
parameter VAR16 = 16,
parameter VAR17 = 4,
parameter VAR11 = 2
)(
input VAR14,
input VAR22,
input VAR26,
input VAR32,
input [VAR16-1:0] VAR18,
output VAR20,
input VAR3,
input VAR12,
output [VAR16-1:0] VAR6,
output VAR9
);
wire [VAR11:0] VAR13;
wire VAR10;
wire [VAR11:0] VAR25;
wire VAR31;
reg [VAR16-1... | bsd-2-clause |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_VCU118/mkFPR_RegFile.v | 7,015 | module MODULE1(VAR77,
VAR2,
VAR43,
VAR31,
VAR70,
VAR34,
VAR16,
VAR8,
VAR60,
VAR74,
VAR51,
VAR75,
VAR12,
VAR15,
VAR36,
VAR50,
VAR10);
input VAR77;
input VAR2;
input VAR43;
output VAR31;
input VAR70;
output VAR34;
input [4 : 0] VAR16;
output [63 : 0] VAR8;
input [4 : 0] VAR60;
output [63 : 0] VAR74;
input [4 : 0] VAR51;
... | apache-2.0 |
VCTLabs/DE1_SOC_Linux_FB | ip/TERASIC_AUDIO/AUDIO_ADC.v | 3,851 | module MODULE1(
clk,
reset,
read,
VAR27,
VAR14,
VAR12,
VAR21,
VAR22,
VAR15
);
parameter VAR19 = 32;
input clk;
input reset;
input read;
output [(VAR19-1):0] VAR27;
output VAR14;
input VAR12;
input VAR21;
input VAR22;
input VAR15;
reg [4:0] VAR17; reg VAR3;
reg VAR4;
reg [(VAR19-1):0] VAR7;
reg [(VAR19-1):0] VAR24;
reg ... | epl-1.0 |
jmahler/EECE344-Digital_System_Design | lab03/CPLD/main.v | 1,867 | module MODULE1(
input VAR22,
VAR36,
VAR34,
VAR4,
output VAR33,
output [16:0] VAR35,
inout [7:0] VAR16,
output VAR11,
VAR26,
VAR39,
VAR14,
VAR29,
VAR18,
VAR23,
VAR31,
output [7:0] VAR12,
VAR19,
input [7:0] VAR38);
wire [6:0] address;
wire [7:0] VAR5;
VAR9 VAR13(.VAR9(VAR4));
wire VAR15,
VAR25,
VAR32,
VAR17,
VAR7;
decode... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_16b_es_v1_00_a/hdl/verilog/cf_h2v.v | 15,195 | module MODULE1 (
VAR25,
VAR51,
VAR17,
VAR101,
VAR66,
VAR72,
VAR3,
VAR15,
VAR30,
VAR42,
VAR26,
VAR110,
VAR62,
VAR44,
VAR82,
VAR77,
VAR96,
VAR45,
VAR81,
VAR71,
VAR16,
VAR27,
VAR80);
input VAR25;
input [15:0] VAR51;
input VAR17;
output VAR101;
input VAR66;
output VAR72;
output [ 7:0] VAR3;
output [63:0] VAR15;
output VAR3... | mit |
PiJoules/Zybo-Vision-Processing | hdmi_passthrough_720p.srcs/sources_1/bd/design_1/hdl/design_1.v | 4,025 | module MODULE1
(VAR21,
VAR18,
VAR47,
VAR3,
VAR1,
VAR49,
clk,
VAR35,
VAR45,
VAR60,
VAR67,
VAR20,
VAR82,
VAR41,
VAR50,
VAR65,
VAR74,
VAR40);
input VAR21;
output VAR18;
output VAR47;
input VAR3;
output VAR1;
output VAR49;
input clk;
input VAR35;
input VAR45;
input [2:0]VAR60;
input [2:0]VAR67;
output [0:0]VAR20;
output [0... | unlicense |
scalable-networks/ext | uhd/fpga/usrp2/timing/time_compare.v | 1,063 | module MODULE1
(input [63:0] VAR2,
input [63:0] VAR3,
output VAR5,
output VAR6,
output VAR1,
output VAR4);
assign VAR5 = VAR2 == VAR3;
assign VAR1 = VAR2 > VAR3;
assign VAR6 = ~VAR5 & ~VAR1;
assign VAR4 = 0;
endmodule | gpl-2.0 |
sergev/vak-opensource | hardware/basys3/abacus/BIN_DEC1.v | 1,090 | module MODULE1(
input [15:0] VAR2,
output reg [19:0] VAR4
);
reg [35:0] VAR1;
integer VAR3;
always @(*)
begin
for(VAR3 = 0; VAR3 <= 35; VAR3 = VAR3+1)
VAR1[VAR3] = 0;
VAR1[18:3] = VAR2;
repeat(13)
begin
if(VAR1[19:16] > 4)
VAR1[19:16] = VAR1[19:16] + 3;
if(VAR1[23:20] > 4)
VAR1[23:20] = VAR1[23:20] + 3;
if(VAR1[27:24] ... | apache-2.0 |
ridecore/ridecore | src/fpga/oldest_finder.v | 3,108 | module MODULE2 #(
parameter VAR4 = 1,
parameter VAR11 = 8
)
(
input wire [2*VAR4-1:0] VAR2,
input wire [2*VAR11-1:0] VAR15,
output wire [VAR4-1:0] VAR1,
output wire [VAR11-1:0] VAR14
);
wire [VAR4-1:0] VAR6 = VAR2[0+:VAR4];
wire [VAR4-1:0] VAR10 = VAR2[VAR4+:VAR4];
wire [VAR11-1:0] VAR17 = VAR15[0+:VAR11];
wire [VAR11-... | bsd-3-clause |
TUM-LIS/faultify | analysis/power/fpu100_div/pDFlipFlops_switchOff.v | 23,157 | module MODULE27 (VAR2,VAR34,VAR18,VAR39);
parameter VAR20=1'b0;
output VAR2;
input VAR34;
input VAR18;
input VAR39;
wire VAR38;
VAR36 VAR21 (.VAR2(VAR2),.VAR34(VAR38),.VAR18(VAR18));
and (VAR38,VAR34,VAR39);
endmodule
module MODULE40 (VAR2,VAR34,VAR18,VAR39);
parameter VAR20 = 1'b0;
output VAR2;
input VAR34;
input VAR... | gpl-2.0 |
zhangly/azpr_cpu | rtl/io/uart/rtl/uart_ctrl.v | 3,786 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR32, input wire VAR25, input wire VAR19, input wire [VAR11] addr, input wire [VAR20] VAR23, output reg [VAR20] VAR3, output reg VAR18,
output reg VAR21, output reg VAR26,
input wire VAR15, input wire VAR13, input wire [VAR29] VAR6, input wire VAR31, input ... | mit |
timtian090/Playground | UVM/UVMPlayground/Lab1/Lab1-Project/Lab1_Frustration_Module.v | 4,935 | module MODULE1
(
output reg [9:0] VAR12,
output [6:0] VAR20, output [6:0] VAR6, output [6:0] VAR3, output [6:0] VAR15, output [6:0] VAR8, output [6:0] VAR18,
input [3:0] VAR2,
input VAR7
);
reg [3:0] VAR14;
wire [3:0] VAR1;
wire [3:0] VAR9;
wire [3:0] VAR19;
wire [3:0] VAR10;
assign VAR1 = VAR2[0] ? 4'h1 : 4'h0; assign... | mit |
rkrajnc/minimig-mist | rtl/minimig/agnus.v | 16,170 | module MODULE1
(
input clk, input VAR122, input VAR74, input reset, input VAR35, input rd, input VAR78, input VAR123, input [15:0] VAR38, output [15:0] VAR91, input [8:1] VAR53, output reg [20:1] VAR47, output [8:1] VAR90, output reg VAR79, output reg VAR115, output reg VAR32, output VAR111, output VAR112, output VAR10... | gpl-3.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_dff.v | 2,469 | module MODULE1
(clk, reset, VAR2, VAR7, VAR1);
parameter VAR8 = 32;
parameter VAR4 = 0;
parameter VAR6 = VAR3;
parameter [VAR4:(VAR4+VAR8)-1] VAR5 = {VAR8{1'b0}};
input clk;
input reset;
input VAR2;
input [VAR4:(VAR4+VAR8)-1] VAR7;
output [VAR4:(VAR4+VAR8)-1] VAR1;
reg [VAR4:(VAR4+VAR8)-1] VAR1;
generate
case(VAR6)
alw... | gpl-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/SEG7_Display.v | 1,394 | module MODULE1 (
input wire VAR5, input wire VAR11, input wire [31:0] VAR7, output wire [6:0] VAR8, output wire [6:0] VAR3, output wire [6:0] VAR6, output wire [6:0] VAR10, output wire [6:0] VAR1, output wire [6:0] VAR13, output wire [6:0] VAR12, output wire [6:0] VAR9, input wire VAR2 );
VAR4 VAR14 (
.VAR5 (VAR5), .VA... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/4-way_2-tree/src/riffa/riffa.v | 39,381 | module MODULE1
parameter VAR303 = 12,
parameter VAR207 = 512, parameter VAR274 = 5, parameter VAR136 = "VAR326",
parameter VAR306 = "VAR227", parameter VAR62 = 0, parameter VAR22 = 10)
(input VAR235,
input VAR245,
output VAR195,
input VAR165,
input VAR203,
input [VAR283-1:0] VAR241,
input VAR49,
input [(VAR283/32)-1:0]... | mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v | 1,424 | module MODULE1(VAR5, VAR4, VAR6, VAR1, VAR7, VAR8, VAR2, VAR3)
;
input VAR5;
input [0:0]VAR4;
input [8:0]VAR6;
input [63:0]VAR1;
input VAR7;
input VAR8;
input [8:0]VAR2;
output [63:0]VAR3;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo.behavioral.pp.v | 2,063 | module MODULE1 (
VAR2 ,
VAR14 ,
VAR1 ,
VAR16,
VAR13,
VAR10,
VAR12 ,
VAR11
);
output VAR2 ;
input VAR14 ;
input VAR1 ;
input VAR16;
input VAR13;
input VAR10;
input VAR12 ;
input VAR11 ;
wire VAR3 ;
wire VAR6 ;
wire VAR7;
nand VAR15 (VAR3 , VAR1, VAR14 );
nand VAR9 (VAR6 , VAR16, VAR3 );
VAR8 VAR4 (VAR7, VAR6, VAR13, VAR... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/video_sys_jtag_uart_0.v | 23,341 | module MODULE6 (
clk,
VAR59,
VAR30,
valid
)
;
input clk;
input [ 7: 0] VAR59;
input VAR30;
input valid;
reg [31:0] VAR10; VAR43 VAR10 =
always @(posedge clk) begin
if (valid && VAR30) begin
("%VAR76", ((VAR59 == 8'hd) ? 8'ha : VAR59));
VAR80 (VAR10);
end
end
endmodule
module MODULE4 (
clk,
VAR67,
VAR47,
VAR15,
VAR32,
V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311ai/sky130_fd_sc_ms__o311ai_2.v | 2,435 | module MODULE2 (
VAR4 ,
VAR12 ,
VAR1 ,
VAR5 ,
VAR6 ,
VAR2 ,
VAR7,
VAR3,
VAR9 ,
VAR10
);
output VAR4 ;
input VAR12 ;
input VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR7;
input VAR3;
input VAR9 ;
input VAR10 ;
VAR8 VAR11 (
.VAR4(VAR4),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o_1.v | 2,469 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR3 ,
VAR4 ,
VAR6 ,
VAR10 ,
VAR5,
VAR12,
VAR9 ,
VAR11
);
output VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR10 ;
input VAR5;
input VAR12;
input VAR9 ;
input VAR11 ;
VAR1 VAR7 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(V... | apache-2.0 |
hoglet67/CoPro6502 | src/wb/arm2/wb_switch.v | 4,250 | module MODULE1 #(
parameter VAR7 = 32'h00000000,
parameter VAR29 = 32'h00000000,
parameter VAR5 = 32'h00000000,
parameter VAR39 = 32'h00000000,
parameter VAR45 = 32'h00000000,
parameter VAR28 = 32'h00000000,
parameter VAR17 = 32'h00000000,
parameter VAR11 = 32'h00000000
)(
input [31:0] VAR1,
output [31:0] VAR2,
input [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbp/sky130_fd_sc_hd__sdfbbp.functional.pp.v | 2,572 | module MODULE1 (
VAR15 ,
VAR2 ,
VAR12 ,
VAR3 ,
VAR9 ,
VAR24 ,
VAR11 ,
VAR5,
VAR7 ,
VAR18 ,
VAR23 ,
VAR16
);
output VAR15 ;
output VAR2 ;
input VAR12 ;
input VAR3 ;
input VAR9 ;
input VAR24 ;
input VAR11 ;
input VAR5;
input VAR7 ;
input VAR18 ;
input VAR23 ;
input VAR16 ;
wire VAR6 ;
wire VAR19 ;
wire VAR21 ;
wire VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi.behavioral.pp.v | 2,076 | module MODULE1 (
VAR12 ,
VAR8 ,
VAR6 ,
VAR1 ,
VAR16 ,
VAR5 ,
VAR4,
VAR3,
VAR14 ,
VAR10
);
output VAR12 ;
input VAR8 ;
input VAR6 ;
input VAR1 ;
input VAR16 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR14 ;
input VAR10 ;
wire VAR11 ;
wire VAR17 ;
wire VAR2;
and VAR13 (VAR11 , VAR1, VAR8, VAR6 );
nor VAR7 (VAR17 , VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv_16.v | 2,001 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR8,
VAR2,
VAR6 ,
VAR5
);
output VAR4 ;
input VAR3 ;
input VAR8;
input VAR2;
input VAR6 ;
input VAR5 ;
VAR7 VAR1 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
supply1 VAR8;
supply0 VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn_4.v | 2,148 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR9,
VAR7,
VAR1,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR9;
input VAR7;
input VAR1;
input VAR8 ;
input VAR4 ;
VAR3 VAR5 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6 ,
VAR2 ,
VAR9
);
output VAR6 ;... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/i2c/rtl/i2c_sctrl.v | 17,614 | module MODULE1 (
VAR58, VAR47, VAR48, VAR121, VAR21,
VAR77, VAR5, VAR54, VAR56, VAR89,
VAR128, VAR61, VAR42, VAR100,
VAR50, VAR101, VAR131, VAR6, VAR133,
VAR41, VAR7, VAR93, VAR36,
VAR73, VAR31, VAR110, VAR25,
VAR65, VAR92, VAR116,
VAR104, clk, VAR81, VAR126, VAR9,
VAR106, VAR2, VAR1, VAR75,
VAR4, VAR18, VAR8, VAR96,
V... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_iqcor_1.v | 5,549 | module MODULE1 (
clk,
VAR4,
VAR10,
VAR14,
VAR3,
VAR2,
VAR5,
VAR7,
VAR15);
parameter VAR31 = 0;
input clk;
input [15:0] VAR4;
input [15:0] VAR10;
output [15:0] VAR14;
input VAR3;
input [15:0] VAR2;
input [15:0] VAR5;
input [15:0] VAR7;
input [15:0] VAR15;
reg [15:0] VAR13 = 'd0;
reg [15:0] VAR8 = 'd0;
reg VAR29 = 'd0;
r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fah/sky130_fd_sc_ls__fah.symbol.v | 1,296 | module MODULE1 (
input VAR5 ,
input VAR2 ,
input VAR3 ,
output VAR6,
output VAR9
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_phy_dm_iob.v | 3,422 | module MODULE1
(
input VAR9,
input VAR2,
input VAR14,
input VAR22,
output VAR17
);
wire VAR18;
wire VAR20;
VAR19 VAR10
(
.VAR23 (VAR20),
.VAR12 (VAR9),
.VAR4 (1'b1),
.VAR7 (VAR2),
.VAR24 (1'b0),
.VAR8 (1'b0)
) ;
VAR15 #
(
.VAR5("VAR25"),
.VAR6("VAR3")
)
VAR26
(
.VAR23 (VAR18),
.VAR12 (VAR9),
.VAR4 (VAR20),
.VAR16 (VAR1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1p/sky130_fd_sc_lp__iso1p.functional.v | 1,181 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR3;
or VAR2 (VAR1 , VAR4, VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfsbp/sky130_fd_sc_hs__sdfsbp.pp.blackbox.v | 1,414 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR3 ,
VAR5 ,
VAR4 ,
VAR1 ,
VAR6,
VAR7 ,
VAR2
);
input VAR8 ;
input VAR9 ;
output VAR3 ;
output VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR6;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
DreamIP/GPStudio | support/io/d5m/hdl/I2C_Controller.v | 4,040 | module MODULE1 (
VAR1,
VAR7, VAR17, VAR11, VAR15, VAR16,
VAR6, VAR5
);
input VAR1;
input [31:0]VAR11;
input VAR15;
input VAR5;
inout VAR17;
output VAR7;
output VAR16;
output VAR6;
reg VAR10;
reg VAR4;
reg VAR16;
reg [31:0]VAR3;
reg [6:0]VAR14;
wire VAR7=VAR4 | ( ((VAR14 >= 4) & (VAR14 <=39))? ~VAR1 :0 );
wire VAR17=VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand2/sky130_fd_sc_hvl__nand2.behavioral.pp.v | 1,801 | module MODULE1 (
VAR5 ,
VAR12 ,
VAR9 ,
VAR2,
VAR10,
VAR3 ,
VAR6
);
output VAR5 ;
input VAR12 ;
input VAR9 ;
input VAR2;
input VAR10;
input VAR3 ;
input VAR6 ;
wire VAR1 ;
wire VAR8;
nand VAR13 (VAR1 , VAR9, VAR12 );
VAR11 VAR7 (VAR8, VAR1, VAR2, VAR10);
buf VAR4 (VAR5 , VAR8 );
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_POST_FIFO.v | 13,452 | module MODULE1(
rst,
VAR102,
VAR407,
din,
VAR252,
VAR221,
dout,
VAR213,
VAR378,
valid
);
input rst;
input VAR102;
input VAR407;
input [63 : 0] din;
input VAR252;
input VAR221;
output [7 : 0] dout;
output VAR213;
output VAR378;
output valid;
VAR408 #(
.VAR155(0),
.VAR78(0),
.VAR23(0),
.VAR183(0),
.VAR35(0),
.VAR110(0),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_lvc_wpad/sky130_fd_io__top_power_lvc_wpad.pp.symbol.v | 1,913 | module MODULE1 (
inout VAR2 ,
inout VAR20 ,
inout VAR17 ,
inout VAR5 ,
inout VAR6 ,
inout VAR9 ,
inout VAR7 ,
inout VAR14 ,
inout VAR12 ,
inout VAR13 ,
inout VAR18 ,
inout VAR4 ,
inout VAR15 ,
inout VAR8 ,
inout VAR10,
inout VAR16,
inout VAR1 ,
inout VAR19 ,
inout VAR11 ,
inout VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp.symbol.v | 1,338 | module MODULE1 (
input VAR1 ,
output VAR6 ,
output VAR5,
input VAR8
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/axi_dmac_regmap_request.v | 10,612 | module MODULE1 #(
parameter VAR53 = 0,
parameter VAR49 = 1,
parameter VAR63 = 1,
parameter VAR58 = 7,
parameter VAR13 = 32,
parameter VAR21 = 24,
parameter VAR4 = 3,
parameter VAR22 = 0,
parameter VAR32 = 1,
parameter VAR67 = 1,
parameter VAR40 = 0,
parameter VAR14 = 0
) (
input clk,
input reset,
output VAR8,
output VA... | mit |
csturton/wirepatch | system/hardware/cores/or1200/or1200_except.v | 22,227 | module MODULE1
(
clk, rst,
VAR65, VAR97, VAR116, VAR21, VAR85, VAR138,
VAR32, VAR108, VAR105, VAR46, VAR43, VAR145,
VAR148, VAR102, VAR33, VAR144, VAR86, VAR126,
VAR87, VAR3, VAR139, VAR39, VAR64, VAR13, VAR44,
VAR135, VAR66, VAR92, VAR81, VAR60,
VAR96, VAR25, VAR80, VAR55, VAR115, VAR136,
VAR119, VAR50, VAR77, VAR57, ... | mit |
pavel-demin/red-pitaya-notes | cores/axis_bram_reader_v1_0/axis_bram_reader.v | 2,978 | module MODULE1 #
(
parameter integer VAR2 = 32,
parameter integer VAR20 = 32,
parameter integer VAR12 = 10,
parameter VAR7 = "VAR5"
)
(
input wire VAR10,
input wire VAR6,
input wire [VAR12-1:0] VAR25,
output wire [VAR12-1:0] VAR14,
input wire VAR16,
output wire [VAR2-1:0] VAR17,
output wire VAR22,
output wire VAR24,
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3/sky130_fd_sc_hs__and3_4.v | 2,037 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR4 ,
VAR2 ,
VAR6,
VAR1
);
output VAR8 ;
input VAR3 ;
input VAR4 ;
input VAR2 ;
input VAR6;
input VAR1;
VAR5 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR8,
VAR3,
VAR4,
VAR2
);
output VAR8;
input VAR3;
input VAR4;
in... | apache-2.0 |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/submodules/altera_reset_controller.v | 12,020 | module MODULE1
parameter VAR34 = 6,
parameter VAR61 = 0,
parameter VAR44 = 0,
parameter VAR46 = 0,
parameter VAR36 = 0,
parameter VAR28 = 0,
parameter VAR27 = 0,
parameter VAR65 = 0,
parameter VAR29 = 0,
parameter VAR35 = 0,
parameter VAR77 = 0,
parameter VAR9 = 0,
parameter VAR25 = 0,
parameter VAR72 = 0,
parameter VA... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpu/integracion_fisica/front_end/source/RecursiveKOA_Weighted.v | 6,488 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR31,
input wire [VAR22-1:0] VAR17,
input wire [VAR22-1:0] VAR25,
output wire [2*VAR22-1:0] VAR34
);
wire [1:0] VAR35;
wire [3:0] VAR36;
assign VAR35 = 2'b00;
assign VAR36 = 4'b0000;
wire [VAR22/2-1:0] VAR16;
wire [VAR22/2:0] VAR33;
wire [VAR22/2-3:0] VAR20;
... | gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v | 4,201 | module MODULE1 (
input wire clk ,
input wire reset ,
output wire VAR5 ,
input wire VAR2 ,
input wire [7:0] VAR13 ,
output wire VAR7 ,
input wire VAR4 ,
output wire VAR12 ,
input wire VAR17 ,
input wire VAR1 ,
output wire VAR14 ,
output wire VAR8
);
localparam VAR15 = 2'b00;
localparam VAR16 = 2'b01;
localparam VAR9 = 2... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | AD9273_SPI_Config.v | 7,846 | module MODULE1(
input VAR26,
input VAR20,
inout VAR2,
output VAR36
);
parameter
VAR31 = 8'h18,
VAR1 = 8'h2F,
VAR37 = 8'h10,
VAR9 = 8'h0F,
VAR58 = 8'h0F, VAR44 = 8'h01,
VAR19 = 8'h00,
VAR52 = 8'h00,
VAR39 = 8'h01,
VAR27 = 8'h00, VAR55 = 8'h0E, VAR24 = 8'h20,
VAR33 = 8'h0E, VAR40 = 8'h08,
VAR51 = 8'h00, VAR38 = 8'h31,
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o.behavioral.pp.v | 2,199 | module MODULE1 (
VAR5 ,
VAR17 ,
VAR14 ,
VAR13 ,
VAR12 ,
VAR16 ,
VAR15,
VAR7,
VAR3 ,
VAR20
);
output VAR5 ;
input VAR17 ;
input VAR14 ;
input VAR13 ;
input VAR12 ;
input VAR16 ;
input VAR15;
input VAR7;
input VAR3 ;
input VAR20 ;
wire VAR8 ;
wire VAR2 ;
wire VAR6 ;
wire VAR19;
and VAR1 (VAR8 , VAR13, VAR12 );
and VAR9 (... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpu/integracion_fisica/front_end/source/submidRecursiveKOA.v | 5,166 | module MODULE1
(
input wire clk,
input wire [VAR5-1:0] VAR6,
input wire [VAR5-1:0] VAR29,
output reg [2*VAR5-1:0] VAR31
);
wire [1:0] VAR28;
wire [3:0] VAR10;
assign VAR28 = 2'b00;
assign VAR10 = 4'b0000;
wire [VAR5/2-1:0] VAR9;
wire [VAR5/2:0] VAR22;
wire [VAR5/2-3:0] VAR1;
wire [VAR5/2-4:0] VAR25;
reg [4*(VAR5/2)+2:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv.pp.symbol.v | 1,264 | module MODULE1 (
input VAR5 ,
output VAR4 ,
input VAR3 ,
input VAR6,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_4.functional.v | 1,384 | module MODULE1( VAR7, VAR11, VAR9, VAR15, VAR2, VAR5, VAR8 );
input VAR8, VAR5, VAR7, VAR9, VAR11, VAR2;
output VAR15;
wire VAR4;
not VAR14( VAR4, VAR11 );
wire VAR18;
not VAR12( VAR18, VAR2 );
wire VAR3;
and VAR19( VAR3, VAR4, VAR18, VAR8 );
wire VAR10;
and VAR6( VAR10, VAR18, VAR5, VAR11 );
wire VAR16;
and VAR20( VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.v | 2,358 | module MODULE1 (
VAR6 ,
VAR4,
VAR10 ,
VAR9 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR3
);
output VAR6 ;
input VAR4;
input VAR10 ;
input VAR9 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR3 ;
VAR1 VAR7 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODU... | apache-2.0 |
ncos/Xilinx-Verilog | SINGEN/src/SPI/spi_master.v | 2,169 | module MODULE1#
(
parameter integer VAR14 = 15 )
(
input clk,
input wire VAR16,
output reg VAR2=0,
input VAR18,
output wire VAR7,
input VAR8,
output wire VAR10,
input VAR21,
output wire VAR20,
input [VAR14-1:0] VAR12,
output reg [VAR14-1:0] VAR4=0,
input VAR17,
output wire VAR11,
output wire VAR3
);
reg [VAR14-1:0] VAR... | mit |
olajep/oh | src/common/dv/dut_fifo_generic.v | 1,364 | module MODULE1(
VAR19, VAR17, VAR3, VAR7, VAR4,
VAR14, VAR2, VAR5, VAR12, VAR18, VAR10, VAR9, VAR11
);
parameter VAR15 = 1;
parameter VAR16 = 104;
input VAR14;
input VAR2;
input VAR5;
input [VAR15*VAR15-1:0] VAR12;
input VAR18;
output VAR19;
output VAR17;
input [VAR15-1:0] VAR10;
input [VAR15*VAR16-1:0] VAR9;
output [V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4/sky130_fd_sc_ms__nand4.functional.pp.v | 1,846 | module MODULE1 (
VAR3 ,
VAR13 ,
VAR11 ,
VAR7 ,
VAR4 ,
VAR14,
VAR5,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR13 ;
input VAR11 ;
input VAR7 ;
input VAR4 ;
input VAR14;
input VAR5;
input VAR2 ;
input VAR6 ;
wire VAR8 ;
wire VAR9;
nand VAR12 (VAR8 , VAR4, VAR7, VAR11, VAR13 );
VAR15 VAR10 (VAR9, VAR8, VAR14, VAR5);
buf VAR1 (... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v | 13,896 | module MODULE1 #
(
parameter VAR14 = 100, parameter VAR17 = 3000, parameter VAR18 = 2, parameter VAR4 = "VAR3", parameter VAR10 = "VAR27", parameter VAR1 = 2, parameter VAR2 = 1, parameter VAR20 = 2, parameter VAR8 = 1
)
(
input VAR7, input VAR24, input VAR29, output VAR16, output clk, output VAR12, output VAR28, input... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv.behavioral.v | 1,347 | module MODULE1 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR7;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR6 ;
wire VAR9;
not VAR2 (VAR9, VAR3 );
buf VAR4 (VAR8 , VAR9 );
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/sd_spi.v | 2,229 | module MODULE1
(input clk,
input rst,
output reg VAR1,
output VAR8,
input VAR3,
input [7:0] VAR2,
input [7:0] VAR10,
output [7:0] VAR16,
input VAR7,
output ready);
reg [7:0] VAR17;
reg [3:0] VAR14;
wire VAR12 = (VAR17 == 8'd0);
wire VAR5 = (VAR17 != 8'd0);
wire VAR9 = (VAR17 == VAR2);
wire VAR4 = (VAR17 == (VAR2>>1));
... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_pio_1.v | 1,840 | module MODULE1 (
address,
clk,
VAR6,
VAR4,
VAR5
)
;
output [ 31: 0] VAR5;
input [ 2: 0] address;
input clk;
input [ 31: 0] VAR6;
input VAR4;
wire VAR3;
wire [ 31: 0] VAR1;
wire [ 31: 0] VAR2;
reg [ 31: 0] VAR5;
assign VAR3 = 1;
assign VAR2 = {32 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR4)
begin
if (... | gpl-3.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/ExecutePipeline.v | 2,159 | module MODULE1(
input [31:0] VAR28,
input [31:0] VAR32,
input [31:0] VAR34,
input [31:0] VAR15,
input [31:0] VAR13,
input [31:0] VAR22,
input [31:0] VAR7,
input reset,
input VAR14,
input VAR8,
input VAR1,
input [1:0] VAR10,
input [7:0] VAR31,
output [31:0] VAR29,
output [31:0] VAR20,
output [31:0] VAR25,
output [31:0] ... | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/int16_float32.v | 22,565 | module MODULE1
(
VAR15,
VAR3,
VAR5,
VAR12,
VAR11,
VAR1) ;
input VAR15;
input VAR3;
input VAR5;
input [15:0] VAR12;
input [3:0] VAR11;
output [15:0] VAR1;
tri0 VAR15;
tri1 VAR3;
tri0 VAR5;
reg [1:0] VAR7;
reg [15:0] VAR4;
reg [15:0] VAR8;
reg VAR14;
reg VAR13;
wire [4:0] VAR10;
wire VAR16;
wire [7:0] VAR2;
wire [79:0] V... | apache-2.0 |
rohit91/novena-sd-fpga | novena-sd.srcs/sources_1/ip/clk_wiz_v3_5_1/ddr3_clkgen/example_design/ddr3_clkgen_exdes.v | 5,764 | module MODULE1
parameter VAR16 = 100
)
( input VAR19,
input VAR21,
output [3:1] VAR7,
output [3:1] VAR13,
input VAR14,
output VAR4
);
localparam VAR11 = 16;
localparam VAR18 = 3;
genvar VAR5;
wire VAR20 = !VAR4 || VAR14 || VAR21;
reg [VAR18:1] VAR23;
reg [VAR18:1] VAR1;
reg [VAR18:1] VAR24;
reg [VAR18:1] VAR3;
wire [VA... | apache-2.0 |
jobisoft/jTDC | modules/VFB6/pll_vfb6_400.v | 2,770 | module MODULE1 ( VAR40,
VAR7,
VAR41,
VAR13 );
input wire VAR40;
output wire VAR7;
output wire VAR41;
output wire VAR13;
wire VAR9;
wire VAR36;
wire VAR21;
wire VAR11;
VAR23 VAR43 (
.VAR39 (VAR9),
.VAR12 (VAR40));
wire VAR2;
wire VAR8;
wire VAR28;
wire VAR26;
wire VAR27;
wire VAR34;
VAR17
.VAR6 ("VAR52"),
.VAR3 ("VAR48"... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtp/sky130_fd_sc_hdll__dlrtp_4.v | 2,378 | module MODULE1 (
VAR5 ,
VAR1,
VAR7 ,
VAR10 ,
VAR6 ,
VAR4 ,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR1;
input VAR7 ;
input VAR10 ;
input VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR2 ;
VAR9 VAR8 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODU... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0.v | 11,766 | module MODULE1 (
input wire VAR23, input wire VAR11, input wire VAR52, output wire VAR4, output wire VAR9, output wire VAR42, output wire [12:0] VAR62, output wire [2:0] VAR5, output wire VAR10, output wire VAR16, output wire VAR35, output wire VAR6, output wire [1:0] VAR8, output wire VAR67, output wire VAR32, output ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.v | 2,461 | module MODULE2 (
VAR9 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR10 ,
VAR4 ,
VAR3,
VAR6,
VAR7 ,
VAR12
);
output VAR9 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR10 ;
input VAR4 ;
input VAR3;
input VAR6;
input VAR7 ;
input VAR12 ;
VAR11 VAR8 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.v | 2,128 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR9 ,
VAR3,
VAR5,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR3;
input VAR5;
input VAR6 ;
input VAR4 ;
VAR2 VAR8 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR1 ,
VAR7,
VAR9
);
output VAR1 ... | apache-2.0 |
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