repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux4/sky130_fd_sc_ls__mux4.pp.blackbox.v | 1,376 | module MODULE1 (
VAR2 ,
VAR11 ,
VAR8 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR9 ,
VAR3,
VAR7,
VAR4 ,
VAR6
);
output VAR2 ;
input VAR11 ;
input VAR8 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR9 ;
input VAR3;
input VAR7;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o_lp.v | 2,477 | module MODULE2 (
VAR11 ,
VAR6 ,
VAR7 ,
VAR5 ,
VAR1 ,
VAR2 ,
VAR10,
VAR4,
VAR12 ,
VAR3
);
output VAR11 ;
input VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR10;
input VAR4;
input VAR12 ;
input VAR3 ;
VAR9 VAR8 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR10(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1_4.v | 2,240 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR7 ,
VAR3,
VAR6,
VAR9 ,
VAR4
);
output VAR5 ;
input [15:0] VAR2 ;
input [15:0] VAR7 ;
input VAR3;
input VAR6;
input VAR9 ;
input VAR4 ;
VAR8 VAR1 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR5,
VAR2,
VAR7
);... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0_bb.v | 3,368 | module MODULE1 (
input wire VAR7, output wire [5:0] VAR12, output wire [31:0] VAR31, output wire [31:0] VAR26, output wire [7:0] VAR15, output wire [2:0] VAR4, output wire [1:0] VAR33, output wire VAR44, output wire [3:0] VAR48, output wire [2:0] VAR16, output wire [3:0] VAR41, output wire VAR3, input wire VAR19, outpu... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2.behavioral.v | 8,998 | module MODULE1( VAR80, VAR19, VAR3, VAR65, VAR15 );
input VAR80, VAR19, VAR65, VAR3;
output VAR15;
reg VAR4;
VAR42 VAR75(.VAR80(VAR80),.VAR19(VAR19),.VAR3(VAR3),.VAR65(VAR65),.VAR15(VAR15),.VAR4(VAR4));
VAR42 VAR35(.VAR80(VAR80),.VAR19(VAR19),.VAR3(VAR3),.VAR65(VAR65),.VAR15(VAR15),.VAR4(VAR4));
not VAR24(VAR71,VAR19);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufbuf/sky130_fd_sc_hd__bufbuf.blackbox.v | 1,224 | module MODULE1 (
VAR6,
VAR3
);
output VAR6;
input VAR3;
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/riffa/rxr_engine_classic.v | 25,328 | module MODULE1
parameter VAR73 = 128,
parameter VAR85=10)
( input VAR28,
input VAR99, input VAR37, output VAR71,
input [VAR73-1:0] VAR27,
input VAR58,
input VAR132,
input [VAR126-1:0] VAR18,
input VAR141,
input [VAR126-1:0] VAR59,
input [VAR157-1:0] VAR24,
output [VAR73-1:0] VAR144,
output VAR149,
output [(VAR73/32)-1:... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_gl.v | 7,662 | module MODULE1(VAR40 ,VAR56 ,VAR43 ,
VAR58 ,VAR61 ,VAR29 ,VAR69 ,
VAR86 ,VAR82 ,VAR5 ,VAR16 ,
VAR48 ,VAR45 ,VAR24 ,VAR47 ,VAR70 ,
VAR52 );
output [7:0] VAR40 ;
output [7:0] VAR58 ;
output [7:0] VAR61 ;
output [7:0] VAR29 ;
output [7:0] VAR69 ;
output [7:0] VAR86 ;
output [7:0] VAR82 ;
output [7:0] VAR5 ;
output [7:0] V... | gpl-2.0 |
Canaan-Creative/MM | verilog/superkdf9/components/uart_core/rxcver_fifo.v | 6,110 | module MODULE1 (VAR22, VAR41, VAR1, VAR3, VAR43, VAR18, VAR11, VAR42, VAR16,
VAR6, VAR29);
input [10:0] VAR22;
input VAR41;
input VAR1;
input VAR3;
input VAR43;
output [7:0] VAR18;
output [2:0] VAR11;
output VAR42;
output VAR16;
output VAR6;
output VAR29;
wire[7:0] VAR5;
parameter VAR21 = VAR31;
generate
if (VAR21 == "... | unlicense |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/altgx_reconfig.v | 20,865 | module MODULE1
(
address,
VAR14,
VAR2,
VAR7,
VAR23,
VAR20,
VAR13,
VAR15,
VAR12,
VAR42,
VAR37,
VAR11,
VAR32) ;
input [15:0] address;
output VAR14;
input [15:0] VAR2;
output [15:0] VAR7;
input VAR23;
output VAR20;
output VAR13;
output VAR15;
input VAR12;
input [8:0] VAR42;
input VAR37;
input VAR11;
input VAR32;
tri0 [15:... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.functional.pp.v | 1,410 | module MODULE1( VAR10, VAR16, VAR2, VAR15, VAR9, VAR13, VAR5, VAR7, VAR20 );
input VAR5, VAR13, VAR10, VAR2, VAR16, VAR9;
inout VAR7, VAR20;
output VAR15;
wire VAR3;
not VAR4( VAR3, VAR16 );
wire VAR12;
not VAR6( VAR12, VAR9 );
wire VAR1;
and VAR18( VAR1, VAR3, VAR12, VAR5 );
wire VAR11;
and VAR17( VAR11, VAR12, VAR13,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.blackbox.v | 1,247 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR3;
endmodule | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/RegistroCargaInterfaz.v | 4,000 | module MODULE1 #(parameter VAR44 = 32)
(VAR39,VAR10,VAR37,VAR22,VAR7,VAR36,
VAR19,VAR43,VAR25,VAR31,VAR34,VAR42,
VAR11,VAR5,VAR26,VAR45,VAR27,VAR24,VAR32,VAR23,VAR6,VAR18,VAR12,VAR2,VAR1,
VAR20,VAR33,VAR21,VAR41);
genvar VAR35;
input VAR39,VAR7,VAR10,VAR37;
input signed [VAR44-1:0] VAR22;
input [8:0] VAR36;
wire [21:0]... | gpl-2.0 |
dhytxz/PolyPC | hardware/ip_repo/hapara_lmb_dma_dup/src/hapara_lmb_dma_dup.v | 10,380 | module MODULE1 #(
parameter integer VAR11 = 32,
parameter integer VAR42 = 4
)
(
input [VAR11 - 1 : 0] VAR9,
input [VAR11 - 1 : 0] VAR97,
output [VAR11 - 1 : 0] VAR1,
input [VAR11 / 8 - 1 : 0] VAR84,
input VAR7,
input VAR38,
input VAR96,
input [VAR11 - 1 : 0] VAR21,
input [VAR11 - 1 : 0] VAR111,
output [VAR11 - 1 : 0] V... | gpl-2.0 |
FAST-Switch/fast | projects/openflow-switch/hw-src/nmp_cb08.v | 32,605 | module MODULE1(
VAR6,
VAR62,
VAR393, VAR403,
VAR22,
VAR197,
VAR178,
VAR24,
VAR147,
VAR364,
VAR161,
VAR2, VAR295, VAR239 );
input VAR6;
input VAR62;
input VAR393;
output [7:0] VAR403;
output [7:0] VAR22;
input [3:0] VAR197;
output [3:0] VAR178;
input [3:0] VAR24;
output [3:0] VAR147;
output VAR364;
inout [3:0] VAR161;
i... | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/rtl/system.v | 37,722 | module MODULE1 (
output wire VAR48,
input wire VAR310,
input wire VAR253,
input wire VAR219,
input wire VAR207,
input wire VAR267,
output wire VAR227,
inout wire [15:0] VAR325,
inout wire [1:0] VAR211,
inout wire [1:0] VAR303,
output wire [12:0] VAR174,
output wire [2:0] VAR84,
output wire VAR45,
output wire VAR343,
ou... | bsd-2-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_mem/bsg_mem_2r1w_sync.v | 3,066 | module MODULE1 #( parameter VAR22(VAR28 )
, parameter VAR22(VAR6 )
, parameter VAR42 = 0
, parameter VAR19 = VAR21(VAR6)
, parameter VAR33 = 1
, parameter VAR36 = 0
)
( input VAR23
, input VAR1
, input VAR37
, input [VAR19-1:0] VAR12
, input [VAR28-1:0] VAR41
, input VAR2
, input [VAR19-1:0] VAR29
, output logic [VAR28... | bsd-3-clause |
sigilance/tera-computer | src/tera.v | 2,618 | module MODULE1;
reg VAR4 = 1'b0;
reg VAR28 = 1'b1;
wire VAR31, VAR22;
assign VAR31 = VAR4;
assign VAR22 = VAR28;
reg VAR35 = 1'b0;
wire [7:0] VAR32, VAR37;
wire VAR36;
VAR30 VAR21 (VAR32, VAR37, VAR36, VAR31, VAR22);
wire [7:0] VAR15, VAR8, VAR19, VAR20, VAR1;
wire VAR9;
VAR17 VAR24 (VAR15, VAR32);
VAR34 VAR38 (VAR8, V... | mit |
aj-michael/Digital-Systems | MultiplicationUnit/DataUnit.v | 1,077 | module MODULE1(VAR20, VAR21, VAR7, VAR2, VAR1, reset, VAR4);
input VAR4, reset;
input [3:0] VAR21, VAR7;
input [2:0] VAR2, VAR1;
output [7:0] VAR20;
wire [3:0] VAR5;
VAR3 VAR18(VAR7,VAR5,1'b0,1'b0,VAR2[2],VAR1[2],reset,VAR4);
VAR11 VAR14(VAR21[3],1'b0,VAR21[2],1'b0,VAR21[1],1'b0,VAR21[0],1'b0,1'b0,VAR5[0],VAR22,VAR19,V... | mit |
peteasa/parallella-fpga | AdaptevaLib/ip_repo/axi_traffic_controller_1.0/hdl/axi_traffic_controller_v1_0.v | 3,046 | module MODULE1 #
(
parameter VAR25 = "VAR17",
parameter VAR18 = "VAR45",
parameter VAR36 = "VAR11",
parameter VAR35 = "VAR64",
parameter VAR56 = 32'hAA000000,
parameter VAR10 = 32'h40000000,
parameter integer VAR23 = 32,
parameter integer VAR50 = 32,
parameter integer VAR57 = 4
)
(
input wire VAR9,
output wire VAR66,
o... | lgpl-3.0 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0_stub.v | 3,501 | module MODULE1(VAR38, VAR6, VAR22, VAR17,
VAR26, VAR21, VAR29, VAR5, VAR37, VAR18,
VAR34, VAR31, VAR28, VAR40, VAR12, VAR13,
VAR2, VAR8, VAR20, VAR35, VAR39, VAR27,
VAR36, VAR32, VAR14, VAR33, VAR4, VAR1,
VAR11, VAR7, VAR24, VAR10, VAR3, VAR25,
VAR9, VAR19, VAR30, VAR23, VAR15, VAR16)
;
input VAR38;
input VAR6;
input [... | mit |
alexforencich/verilog-ethernet | rtl/axis_xgmii_tx_64.v | 22,392 | module MODULE1 #
(
parameter VAR3 = 64,
parameter VAR1 = (VAR3/8),
parameter VAR9 = (VAR3/8),
parameter VAR27 = 1,
parameter VAR16 = 1,
parameter VAR31 = 64,
parameter VAR8 = 4'h6,
parameter VAR23 = 16'h6666,
parameter VAR28 = 0,
parameter VAR24 = 96,
parameter VAR26 = VAR28,
parameter VAR4 = 16,
parameter VAR7 = (VAR2... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/SCFIFO_64x64_withCount.v | 2,693 | module MODULE1
(
input VAR5 ,
input VAR8 ,
input [63:0] VAR13 ,
input VAR9 ,
output VAR10 ,
output [63:0] VAR2 ,
input VAR1 ,
output VAR14 ,
output [5:0] VAR7
);
VAR12
VAR16
(
.clk (VAR5 ),
.VAR11 (VAR8 ),
.din (VAR13 ),
.VAR4 (VAR9 ),
.VAR17 (VAR10 ),
.dout (VAR2 ),
.VAR15 (VAR1 ),
.VAR6 (VAR14 ),
.VAR3 (VAR7 )
);
end... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.functional.v | 2,099 | module MODULE1( VAR23, VAR25, VAR9, VAR20, VAR6, VAR2 );
input VAR2, VAR6, VAR25, VAR23, VAR20;
output VAR9;
wire VAR16;
not VAR18( VAR16, VAR2 );
wire VAR21;
not VAR15( VAR21, VAR25 );
wire VAR7;
not VAR4( VAR7, VAR20 );
wire VAR14;
and VAR8( VAR14, VAR16, VAR21, VAR7 );
wire VAR5;
not VAR22( VAR5, VAR23 );
wire VAR12... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a.behavioral.v | 1,947 | module MODULE1 (
VAR1 ,
VAR12 ,
VAR3 ,
VAR5 ,
VAR2 ,
VAR8 ,
VAR15,
VAR13
);
output VAR1 ;
input VAR12 ;
input VAR3 ;
input VAR5 ;
input VAR2 ;
input VAR8 ;
input VAR15;
input VAR13;
wire VAR2 VAR6 ;
wire VAR9 ;
wire VAR4;
or VAR10 (VAR6 , VAR3, VAR12, VAR5 );
and VAR7 (VAR9 , VAR6, VAR2, VAR8 );
VAR11 VAR16 (VAR4, VAR9... | apache-2.0 |
jotego/jt51 | hdl/filter/jt51_fir4.v | 2,143 | module MODULE1
(
input clk,
input rst,
input VAR10,
input signed [VAR15-1:0] VAR14,
input signed [VAR15-1:0] VAR3,
output signed [VAR5-1:0] VAR9,
output signed [VAR5-1:0] VAR12,
output VAR1
);
parameter VAR7=9;
parameter VAR16=21;
parameter VAR11=5;
parameter VAR2=1;
reg signed [VAR7-1:0] VAR8;
wire [VAR11-1:0] VAR13;
... | gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_1/hdl/verilog/feedforward_dadd_64ns_64ns_64_5_full_dsp.v | 1,936 | module MODULE1
VAR26 = 0,
VAR11 = 5,
VAR17 = 64,
VAR18 = 64,
VAR21 = 64
)(
input wire clk,
input wire reset,
input wire VAR8,
input wire [VAR17-1:0] VAR9,
input wire [VAR18-1:0] VAR3,
output wire [VAR21-1:0] dout
);
wire VAR24;
wire VAR19;
wire VAR2;
wire [63:0] VAR16;
wire VAR20;
wire [63:0] VAR13;
wire VAR5;
wire [63... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.functional.v | 1,040 | module MODULE1( VAR2, VAR3, VAR7 );
input VAR7, VAR2;
output VAR3;
wire VAR8;
not VAR6( VAR8, VAR7 );
wire VAR1;
not VAR4( VAR1, VAR2 );
and VAR5( VAR3, VAR8, VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31o/sky130_fd_sc_hdll__a31o_4.v | 2,353 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR11 ,
VAR1 ,
VAR3 ,
VAR2,
VAR6,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR5 ;
input VAR11 ;
input VAR1 ;
input VAR3 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR8 ;
VAR10 VAR9 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR... | apache-2.0 |
INTI-CMNB/Lattuino_IP_Core | devices/tm16b.v | 4,555 | module MODULE1
parameter VAR1=24,
parameter VAR10=1
)
(
input VAR8, input VAR21, input [0:0] VAR5, output [7:0] VAR20, input [7:0] VAR3, input VAR9, input VAR15, output VAR23, output reg VAR11,
input VAR18
);
localparam integer VAR14=VAR17(VAR1);
reg [15:0] VAR2=0;
reg [15:0] VAR4=0;
wire VAR6; wire VAR16;
reg [VAR14-1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor2/sky130_fd_sc_hvl__nor2.pp.blackbox.v | 1,264 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR7 ,
VAR6,
VAR5,
VAR3 ,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
nyaxt/dmix | uart.v | 3,304 | module MODULE1(
input wire clk,
input wire VAR20,
output wire VAR24,
output wire [7:0] VAR12,
output wire VAR15,
input wire [7:0] VAR9,
input wire VAR1,
output wire VAR6);
wire VAR8;
wire VAR18;
reg [10:0] VAR26;
VAR14 VAR26 = 11'd567; VAR5
always @(posedge clk) begin
if (VAR26 == 0) begin
VAR26 <= VAR27;
end else begi... | mit |
asicguy/gplgpu | hdl/de_temp/dex_smdisp.v | 3,683 | module MODULE1
(
input VAR5,
input VAR4,
input VAR1,
input VAR3,
input VAR7,
input VAR16,
input VAR10,
input VAR17,
output reg VAR20,
output reg VAR2,
output reg VAR15,
output reg VAR18,
output reg VAR6,
output reg [1:0] VAR8
);
parameter
VAR14=2'b00,
VAR12=2'b01,
VAR11=2'b10;
reg [1:0] VAR19;
always @(posedge VAR5 or ... | gpl-3.0 |
rfotino/consolite-hardware | src/random.v | 1,509 | module MODULE1
(
input clk,
input VAR3,
input [VAR2-1:0] VAR1,
output reg [VAR4-1:0] rnd
); | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s.pp.symbol.v | 1,325 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/dcache_pipe.v | 55,921 | module MODULE4 (
VAR11,
sel,
VAR26
);
parameter VAR30 = 0;
parameter VAR99 = 1;
input [VAR99-1:0] VAR11;
input sel;
output [VAR99-1:0] VAR26;
assign VAR26 = (sel)?VAR30:VAR11;
endmodule
module MODULE2 (
clk,
reset,
VAR288,
VAR8,
VAR34,
VAR42,
VAR253,
VAR133,
VAR41,
VAR45,
VAR142,
VAR252
);
parameter VAR280 = 8;
paramet... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbp/sky130_fd_sc_ls__dlrbp.behavioral.pp.v | 2,490 | module MODULE1 (
VAR14 ,
VAR21 ,
VAR3,
VAR15 ,
VAR9 ,
VAR16 ,
VAR1 ,
VAR24 ,
VAR17
);
output VAR14 ;
output VAR21 ;
input VAR3;
input VAR15 ;
input VAR9 ;
input VAR16 ;
input VAR1 ;
input VAR24 ;
input VAR17 ;
wire VAR12 ;
reg VAR10 ;
wire VAR11 ;
wire VAR13 ;
wire VAR18 ;
wire VAR20;
wire VAR22 ;
wire VAR4 ;
wire VAR2... | apache-2.0 |
pollow/Single_Cycle_CPU | ipcore_dir/RAM_A.v | 4,001 | module MODULE1(
VAR15,
VAR43,
clk,
VAR13,
VAR57
);
input [10 : 0] VAR15;
input [31 : 0] VAR43;
input clk;
input VAR13;
output [31 : 0] VAR57;
VAR58 #(
.VAR48(11),
.VAR16("0"),
.VAR14(2048),
.VAR47("VAR39"),
.VAR12(1),
.VAR45(1),
.VAR19(0),
.VAR3(0),
.VAR50(0),
.VAR8(0),
.VAR30(0),
.VAR21(0),
.VAR35(0),
.VAR54(0),
.VAR3... | gpl-3.0 |
trun/fpgaboy | src/io/video/vga_controller.v | 1,681 | module MODULE1(VAR4, reset, VAR8, VAR10, VAR3, VAR5);
input VAR4;
input reset;
output VAR8;
output VAR10;
output [9:0] VAR3;
output [9:0] VAR5;
reg VAR8, VAR10;
reg [9:0] VAR3, VAR5;
wire [9:0] VAR2, VAR1;
parameter VAR9 = 525;
parameter VAR12 = 800;
parameter VAR17 = 640;
parameter VAR16 = 480;
parameter VAR11 = 16;
p... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_rst_ps7_0_100M_0/led_controller_design_rst_ps7_0_100M_0_stub.v | 1,918 | module MODULE1(VAR4, VAR9, VAR10,
VAR2, VAR5, VAR6, VAR7, VAR1,
VAR3, VAR8)
;
input VAR4;
input VAR9;
input VAR10;
input VAR2;
input VAR5;
output VAR6;
output [0:0]VAR7;
output [0:0]VAR1;
output [0:0]VAR3;
output [0:0]VAR8;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbn/sky130_fd_sc_lp__sdfbbn.functional.pp.v | 2,700 | module MODULE1 (
VAR25 ,
VAR10 ,
VAR1 ,
VAR12 ,
VAR13 ,
VAR11 ,
VAR6 ,
VAR17,
VAR9 ,
VAR15 ,
VAR26 ,
VAR14
);
output VAR25 ;
output VAR10 ;
input VAR1 ;
input VAR12 ;
input VAR13 ;
input VAR11 ;
input VAR6 ;
input VAR17;
input VAR9 ;
input VAR15 ;
input VAR26 ;
input VAR14 ;
wire VAR2 ;
wire VAR5 ;
wire VAR8 ;
wire VAR... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/loop_limiter_siso.v | 3,497 | module MODULE1
(
VAR19,
VAR2,
VAR4,
VAR3,
VAR6,
VAR14,
VAR9,
VAR5
);
parameter VAR8 = 16;
parameter VAR13 = 2;
parameter VAR7 = 1;
parameter VAR16 = 1;
input VAR19;
input VAR2;
input VAR4;
output VAR3;
output VAR6;
input VAR14;
input VAR9;
input VAR5;
parameter VAR15 = 2'b00;
parameter VAR21 = 2'b01;
parameter VAR11 = ... | mit |
zhelnio/mil1553-spi | src/board/DE0/AlteraMemory.v | 9,385 | module MODULE1 (
VAR10,
VAR15,
VAR41,
VAR39,
VAR59,
VAR55,
VAR56);
input VAR10;
input [15:0] VAR15;
input [7:0] VAR41;
input VAR39;
input [7:0] VAR59;
input VAR55;
output [15:0] VAR56;
tri1 VAR10;
tri1 VAR39;
tri0 VAR55;
wire [15:0] VAR44;
wire [15:0] VAR56 = VAR44[15:0];
VAR17 VAR22 (
.VAR7 (VAR59),
.VAR51 (VAR10),
.V... | mit |
miamiasheep/nctu-dlab-99 | hw/binary_multiplier.v | 2,154 | module MODULE1(
input VAR19, reset, VAR23,
input [7:0] VAR8, VAR17,
output [15:0] VAR12,
output VAR6
);
wire VAR11, VAR22, VAR13, VAR4, VAR9, VAR1, VAR15;
MODULE2 MODULE1(VAR19, reset, VAR23, VAR9, VAR1, VAR15, VAR6, VAR11, VAR22, VAR13, VAR4);
VAR7 VAR5(VAR19, reset, VAR8, VAR17, VAR11, VAR22, VAR13, VAR4,
VAR12, VAR9... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/math_real.v | 15,174 | module MODULE1 ;
localparam VAR43 = 2.7182818284;
localparam VAR30 = 0.3678794411;
localparam VAR54 = 3.1415926536;
localparam VAR12 = 6.2831853071;
localparam VAR25 = 0.3183098861;
localparam VAR17 = 1.5707963267;
localparam VAR26 = 1.0471975511;
localparam VAR8 = 0.7853981633;
localparam VAR69 = 4.7123889803;
localpa... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_cpu.v | 28,747 | module MODULE1 #(
parameter VAR171 = 1
)(
output [VAR179-1:0] VAR154,
output VAR147 ,
output VAR183,
output VAR83,
output VAR76,
output VAR2,
output VAR33 ,
output VAR93 ,
output VAR46,
output VAR142,
output VAR137,
output VAR116,
input [VAR179-1:0] VAR164,
output [VAR179-1:0] VAR38,
output VAR71,
output [3-1:0] VAR84,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211oi/sky130_fd_sc_lp__a211oi.blackbox.v | 1,368 | module MODULE1 (
VAR2 ,
VAR9,
VAR8,
VAR4,
VAR5
);
output VAR2 ;
input VAR9;
input VAR8;
input VAR4;
input VAR5;
supply1 VAR7;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2.blackbox.v | 1,296 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR6;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bwjx1c64a/ExUnitW.v | 16,433 | module MODULE1(
VAR54, reset,
VAR112, VAR165,
VAR2, VAR271,
VAR246,
VAR34, VAR240,
VAR288, VAR110,
VAR186
);
input VAR54; input reset;
output[31:0] VAR112; inout[127:0] VAR165; output VAR2; output VAR271; input VAR246;
output[31:0] VAR34; inout[31:0] VAR240; output VAR288; output VAR110; input[1:0] VAR186;
assign VAR11... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_statisticalInformation_0.v | 1,968 | module MODULE1 (
address,
clk,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 31: 0] VAR2;
input VAR1;
wire VAR6;
wire [ 31: 0] VAR5;
wire [ 31: 0] VAR4;
reg [ 31: 0] VAR3;
assign VAR6 = 1;
assign VAR4 = {32 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR1)
begin
if (... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_project/dpram_128_32x32_be/dpram_128_32x32_be_bb.v | 7,494 | module MODULE1 (
VAR6,
VAR7,
VAR5,
VAR1,
VAR2,
VAR3,
VAR8,
VAR4);
input [127:0] VAR6;
input VAR7;
input [3:0] VAR5;
input [5:0] VAR1;
input [15:0] VAR2;
input VAR3;
input VAR8;
output [31:0] VAR4;
endmodule | gpl-3.0 |
n8thenetninja/Cloud-Car | VeriLog/QuartusProjects/ServoController/i2cslave/trunk/model/i2c_master_bit_ctrl.v | 17,484 | module MODULE1(
clk, rst, VAR19,
VAR7, VAR43, VAR32, VAR42, VAR6, VAR41, din, dout,
VAR18, VAR17, VAR23, VAR16, VAR10, VAR5
);
input clk;
input rst;
input VAR19;
input VAR43;
input [15:0] VAR7;
input [3:0] VAR32;
output VAR42; reg VAR42;
output VAR6; reg VAR6;
output VAR41; reg VAR41;
input din;
output dout;
reg dout;
... | gpl-3.0 |
titorgalaxy/Titor | rtl/verilog/core/Barrel_Processor.v | 9,497 | module MODULE1 (
VAR180,
VAR149,
VAR20,
VAR74,
VAR163,
VAR49,
VAR121,
VAR17,
VAR44,
VAR92,
VAR164,
VAR24,
VAR94,
VAR102,
VAR115,
VAR139,
VAR84,
VAR10,
VAR39,
interrupt,
VAR159,
VAR79,
VAR50,
clk,
reset
);
output wire [VAR169-1:0] VAR180;
input wire [VAR169-1:0] VAR149;
output wire [VAR169-1:0] VAR20;
output wire VAR74;... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/ucb_bus_in.v | 7,241 | module MODULE1 (
VAR33, VAR35, VAR38,
VAR30, clk, VAR11, VAR37, VAR21
);
parameter VAR20 = 32;
parameter VAR24 = 64;
input VAR30;
input clk;
input VAR11;
input [VAR20-1:0] VAR37;
output VAR33;
output VAR35;
output [VAR24+63:0] VAR38;
input VAR21;
wire VAR41;
wire VAR10;
wire [VAR20-1:0] VAR15;
wire VAR43;
wire VAR13;
w... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v | 3,548 | if (VAR39 == VAR40 && VAR9 == VAR33) \
begin: VAR13 \
VAR18 VAR6 \
(.VAR32 (VAR31 ) \
,.VAR14 (VAR34) \
,.VAR41 (~VAR19 ) \
,.VAR20 (~VAR37) \
,.VAR15 (~VAR17 ) \
,.VAR30 (VAR5) \
,.VAR8 (VAR35) \
,.VAR1 (1'd0 ) \
,.VAR36 (3'd3 ) \
,.VAR3 (2'd1 ) \
,.VAR26 (1'd0 ) \
,.VAR7 (1'b1 ) \
); \
end
if (VAR39 == VAR40 && VAR9 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/diode/sky130_fd_sc_hvl__diode.functional.pp.v | 1,204 | module MODULE1 (
VAR4,
VAR5 ,
VAR2 ,
VAR1 ,
VAR3
);
input VAR4;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211a/sky130_fd_sc_hd__o211a.functional.pp.v | 2,036 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR7 ,
VAR17 ,
VAR11 ,
VAR4,
VAR8,
VAR9 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR17 ;
input VAR11 ;
input VAR4;
input VAR8;
input VAR9 ;
input VAR3 ;
wire VAR10 ;
wire VAR13 ;
wire VAR15;
or VAR16 (VAR10 , VAR7, VAR5 );
and VAR12 (VAR13 , VAR10, VAR17, VAR11 );
VAR14 VAR... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/hw-src/pkt_mux.v | 3,911 | module MODULE1(
input clk,
input reset,
input [339:0] VAR18,
input VAR1,
input [339:0] VAR22, input VAR13,
output reg [4:0] VAR9,
output reg VAR14,
output reg [63:0] VAR28,
output reg VAR33,
output reg VAR11,
output reg [7:0] VAR23,
output reg [127:0] VAR12,
output reg [127:0] VAR2,
output reg [71:0] VAR17
);
reg VAR6,... | apache-2.0 |
walkthetalk/fsref | ip/axis_scaler/src/include/scaler_2d.v | 7,191 | module MODULE1 # (
parameter integer VAR74 = 10,
parameter integer VAR26 = 10,
parameter integer VAR14 = 10,
parameter integer VAR10 = 10,
parameter integer VAR76 = 4 ,
parameter integer VAR75 = 2 ,
parameter integer VAR49 = 0 , parameter integer VAR87 = 2
) (
input wire clk,
input wire VAR65,
input wire [VAR26-1 : 0] ... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ethmac/eth_miim.v | 15,759 | module MODULE1
(
VAR50,
VAR12,
VAR11,
VAR26,
VAR19,
VAR52,
VAR15,
VAR39,
VAR62,
VAR60,
VAR6,
VAR10,
VAR23,
VAR8,
VAR37,
VAR34,
VAR2,
VAR59,
VAR9,
VAR5,
VAR64
);
input VAR50; input VAR12; input [7:0] VAR11; input [15:0] VAR19; input [4:0] VAR52; input [4:0] VAR15; input VAR26; input VAR39; input VAR62; input VAR60; inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hs__udp_dlatch_p_pp_pg_n.symbol.v | 1,438 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR4 ,
input VAR5,
input VAR6 ,
input VAR2
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/flop_rptrs_xc5.v | 33,057 | module MODULE1(
VAR6, VAR31, VAR80, VAR64, VAR8,
VAR32, VAR45, VAR17, VAR59,
VAR72, VAR70, VAR39, VAR77, VAR18, VAR46,
VAR14, VAR44, VAR15, VAR50, VAR52, VAR69,
VAR37
);
output [25:0] VAR59; output VAR17; output VAR45; output VAR32; output VAR8; output VAR64; output VAR80; output VAR31; output [5:0] VAR6;
input VAR37; ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp.symbol.v | 1,493 | module MODULE1 (
input VAR1 ,
output VAR10 ,
input VAR8 ,
input VAR3,
input VAR9,
input VAR4
);
supply1 VAR2;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.symbol.v | 1,505 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR1 ,
input VAR5 ,
input VAR7,
input VAR6 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0p/sky130_fd_sc_hd__lpflow_inputiso0p.symbol.v | 1,434 | module MODULE1 (
input VAR7 ,
output VAR5 ,
input VAR3
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
sheridp/OK_WB_Bridge | OK_WB_Bridge.v | 2,017 | module MODULE1(
input wire [30:0] VAR34,
output wire [16:0] VAR28,
input wire VAR6,
input wire VAR4,
input wire VAR19,
input wire VAR24,
input wire [7:0] VAR31,
input wire VAR21,
input wire [31:0] VAR18,
output wire [31:0] VAR9
);
wire VAR29;
wire VAR42;
wire [15:0] VAR26;
wire [15:0] VAR39;
wire [15:0] VAR35;
wire VAR... | lgpl-3.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/code/MUX8_1.v | 2,686 | module MODULE1(
input [2:0] address,
output reg VAR1,
output reg VAR15,
output reg VAR7,
output reg VAR4,
output reg VAR26,
output reg VAR16,
output reg VAR17,
output reg VAR8,
input [127:0] VAR24,
input [127:0] VAR12,
input [127:0] VAR18,
input [127:0] VAR11,
input [127:0] VAR25,
input [127:0] VAR5,
input [127:0] VAR9... | gpl-2.0 |
secworks/salsa20 | src/rtl/salsa20_core.v | 40,383 | module MODULE1(
input wire clk,
input wire VAR230,
input wire VAR116,
input wire VAR49,
input wire [255 : 0] VAR44,
input wire VAR82,
input wire [63 : 0] VAR23,
input wire [4 : 0] VAR246,
input wire [511 : 0] VAR217,
output wire ready,
output wire [511 : 0] VAR31,
output wire VAR125
);
parameter VAR153 = 1'b0;
paramete... | bsd-2-clause |
ncos/Xilinx-Verilog | ZOLED/src/OLED/SpiCtrl.v | 4,105 | module MODULE1(
VAR7,
VAR9,
VAR10,
VAR4,
VAR13,
VAR12,
VAR11
);
input VAR7;
input VAR9;
input VAR10;
input [7:0] VAR4;
output VAR13;
output VAR12;
output VAR11;
wire VAR13, VAR12, VAR11;
reg [39:0] VAR3 = "VAR15";
reg [7:0] VAR6 = 8'h00; reg [3:0] VAR16 = 4'h0; wire VAR8; reg [4:0] counter = 5'b00000; reg VAR5 = 1'b1;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o_4.v | 2,317 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR1 ,
VAR4,
VAR7
);
output VAR3 ;
input VAR8 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR4;
input VAR7;
VAR2 VAR9 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODUL... | apache-2.0 |
kyzhai/NUNY | src/hardware/ninja2_bb.v | 4,986 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
olajep/oh | src/adi/hdl/library/axi_hdmi_tx/axi_hdmi_tx_core.v | 17,898 | module MODULE1 #(
parameter VAR107 = 0,
parameter VAR115 = 0) (
input VAR27,
input VAR97,
output reg VAR68,
output reg VAR66,
output reg VAR108,
output reg [15:0] VAR28,
output reg [15:0] VAR105,
output reg VAR25,
output reg VAR152,
output reg VAR106,
output reg [23:0] VAR37,
output reg VAR70,
output reg VAR95,
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfsbp/sky130_fd_sc_ls__dfsbp.blackbox.v | 1,356 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR1
);
output VAR9 ;
output VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR1;
supply1 VAR4;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/SHD_top.v | 6,313 | module MODULE1 #(parameter VAR31 = 128, VAR50 = 8, VAR38 = 8) (
input VAR20,
input VAR26, output VAR16,
input VAR68,
output VAR25,
input VAR76,
input[31:0] VAR34,
input[30:0] VAR9,
input[VAR31 - 1:0] VAR59,
input VAR56,
output VAR12,
output VAR45,
output VAR65,
input VAR44,
output VAR28,
output[31:0] VAR43,
output[30:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3/sky130_fd_sc_hd__or3.pp.symbol.v | 1,274 | module MODULE1 (
input VAR7 ,
input VAR1 ,
input VAR6 ,
output VAR8 ,
input VAR3 ,
input VAR2,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/sprite_renderer.v | 4,430 | module MODULE1(clk, VAR9, VAR24, VAR30, VAR3, VAR6,
VAR40, VAR34);
input clk;
input VAR9; input VAR24; input VAR30; output reg [3:0] VAR3; input [7:0] VAR6; output reg VAR40; output VAR34;
reg [2:0] state; reg [3:0] VAR27; reg [3:0] VAR21;
reg [7:0] VAR22;
localparam VAR10 = 0;
localparam VAR20 = 1;
localparam VAR12 = ... | gpl-3.0 |
pradeep9676/pradeep_9676 | LZD_32bit.v | 1,052 | module MODULE1( in, out, valid
);
input [31:0]in;
output reg [4:0]out;
output reg valid;
wire VAR3,VAR4;
wire [3:0]VAR2, VAR1;
begin
begin
begin
end
begin
begin | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_127.v | 1,538 | module MODULE2 (
VAR5,
VAR6
);
input [31:0] VAR5;
output [31:0]
VAR6;
wire [31:0]
VAR9,
VAR1,
VAR8,
VAR4,
VAR10,
VAR14,
VAR11,
VAR2,
VAR7;
assign VAR9 = VAR5;
assign VAR1 = VAR9 << 10;
assign VAR8 = VAR9 + VAR1;
assign VAR7 = VAR11 - VAR2;
assign VAR11 = VAR14 - VAR8;
assign VAR14 = VAR10 << 5;
assign VAR4 = VAR9 << 5;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn.functional.pp.v | 1,870 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR13,
VAR5,
VAR10,
VAR12 ,
VAR3
);
output VAR1 ;
input VAR9 ;
input VAR13;
input VAR5;
input VAR10;
input VAR12 ;
input VAR3 ;
wire VAR11 ;
wire VAR8;
VAR7 VAR2 (VAR11 , VAR9, VAR5, VAR10 );
VAR7 VAR6 (VAR8, VAR13, VAR5, VAR10 );
bufif0 VAR4 (VAR1 , VAR11, VAR8);
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/prcfg/qpsk/FIR_Interpolation.v | 19,435 | module MODULE1
(
clk,
VAR34,
reset,
VAR117,
VAR90,
VAR50,
VAR128
);
input clk;
input VAR34;
input reset;
input signed [15:0] VAR117; input signed [15:0] VAR90; output signed [15:0] VAR50; output signed [15:0] VAR128;
parameter signed [15:0] VAR44 = 16'b1111111100110010; parameter signed [15:0] VAR114 = 16'b111111100010... | lgpl-3.0 |
m-labs/milkymist | cores/ac97/rtl/ac97_transceiver.v | 2,228 | module MODULE1(
input VAR27,
input VAR13,
input VAR18,
input VAR22,
input VAR9,
output reg VAR5,
output reg VAR8,
output VAR15,
input VAR28,
output VAR20,
output VAR14,
output VAR26,
input VAR2,
input VAR19,
input VAR32
);
reg VAR1;
always @(negedge VAR18) VAR1 <= VAR9;
reg VAR17;
always @(negedge VAR18) VAR17 <= VAR8;... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a222oi/sky130_fd_sc_hd__a222oi.symbol.v | 1,418 | module MODULE1 (
input VAR4,
input VAR7,
input VAR9,
input VAR5,
input VAR11,
input VAR8,
output VAR2
);
supply1 VAR3;
supply0 VAR10;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a222oi/sky130_fd_sc_hdll__a222oi.behavioral.pp.v | 2,437 | module MODULE1 (
VAR21 ,
VAR16 ,
VAR12 ,
VAR1 ,
VAR2 ,
VAR8 ,
VAR17 ,
VAR18,
VAR14,
VAR4 ,
VAR20
);
output VAR21 ;
input VAR16 ;
input VAR12 ;
input VAR1 ;
input VAR2 ;
input VAR8 ;
input VAR17 ;
input VAR18;
input VAR14;
input VAR4 ;
input VAR20 ;
wire VAR15 ;
wire VAR13 ;
wire VAR7 ;
wire VAR3 ;
wire VAR6;
nand VAR5 ... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/axi_clock_converter_v2_1/e5ab369d/hdl/verilog/axi_clock_converter_v2_1_axic_sample_cycle_ratio.v | 5,910 | module MODULE1 # (
parameter VAR9 = 2 )
(
input wire VAR4,
input wire VAR15,
output wire VAR3,
output wire VAR8
);
localparam VAR17 = VAR9 > 2 ? VAR9-1 : VAR9-1;
reg VAR7 = 0;
reg VAR13;
reg VAR2;
wire VAR14;
wire VAR1;
reg [VAR17-1:0] VAR16;
reg VAR11;
generate
if (VAR9 == 1) begin : VAR12
assign VAR3 = 1'b1;
assign V... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/uart/rtl/uart_transceiver.v | 3,806 | module MODULE1(
input VAR2,
input VAR16,
input VAR12,
output reg VAR9,
input [15:0] VAR11,
output reg [7:0] VAR21,
output reg VAR10,
input [7:0] VAR13,
input VAR19,
output reg VAR7
);
reg [15:0] VAR4;
wire VAR6;
assign VAR6 = (VAR4 == 16'd0);
always @(posedge VAR16) begin
if(VAR2)
VAR4 <= VAR11 - 16'b1;
end
else begin
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai.pp.blackbox.v | 1,408 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR9,
VAR6,
VAR2 ,
VAR10
);
output VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR9;
input VAR6;
input VAR2 ;
input VAR10 ;
endmodule | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/Hex Encoder.v | 1,060 | module MODULE1(
input [4:0] VAR2,
output reg [6:0] VAR1
);
always @(VAR2)
begin
case(VAR2)
5'b0000: VAR1 <= ~7'b0111111;
5'b0001: VAR1 <= ~7'b0000110;
5'b0010: VAR1 <= ~7'b1011011;
5'b0011: VAR1 <= ~7'b1001111;
5'b0100: VAR1 <= ~7'b1100110;
5'b0101: VAR1 <= ~7'b1101101;
5'b0110: VAR1 <= ~7'b1111101;
5'b0111: VAR1 <= ~7... | gpl-2.0 |
flycrow/pyxdl | logicanalyzer/tracer.v | 4,296 | module MODULE1(
input wire VAR13,
input wire VAR32,
input wire [63:0] VAR24,
input wire [31:0] VAR15,
output reg [31:0] VAR36,
output reg VAR28,
input wire [31:0] VAR9,
input wire VAR29,
input wire VAR14);
reg [63:0] VAR22;
reg [63:0] VAR25;
reg VAR12;
reg [10:0] VAR19;
reg [63:0] VAR30;
wire [63:0] VAR5;
reg VAR2;
reg... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp.blackbox.v | 1,540 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR12 ,
VAR2 ,
VAR4 ,
VAR10 ,
VAR11 ,
VAR6
);
output VAR7 ;
output VAR5 ;
input VAR12 ;
input VAR2 ;
input VAR4 ;
input VAR10 ;
input VAR11 ;
input VAR6;
supply1 VAR9;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4.pp.symbol.v | 1,291 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR8 ,
input VAR4 ,
output VAR5 ,
input VAR9 ,
input VAR7,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvpwrvgnd/sky130_fd_sc_hdll__tapvpwrvgnd.behavioral.pp.v | 1,208 | module MODULE1 (
VAR3,
VAR4,
VAR1 ,
VAR2
);
input VAR3;
input VAR4;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
efabless/openlane | designs/151/src/DataSRAMs.v | 1,993 | module MODULE1 #(
parameter VAR10 = 2,
parameter VAR2 = 512
)(
input clk,
input VAR24,
input [VAR10-1:0] addr,
input [VAR2-1:0] VAR21,
output [VAR2-1:0] VAR6
);
wire VAR13 = 1'b0; wire VAR8 = 1'b0;
wire [6:0] VAR18 = {{7-VAR10{1'b0}}, addr};
wire [5:0] VAR12 = VAR18[5:0];
wire [127:0] VAR29 = VAR21[127:0];
wire [127:0]... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/ethmac/eth_rxstatem.v | 7,059 | module MODULE1 (VAR11, VAR5, VAR4, VAR3, VAR24, VAR17, VAR12, VAR9,
VAR14, VAR18, VAR22, VAR16, VAR8, VAR20,
VAR23
);
parameter VAR6 = 1;
input VAR11;
input VAR5;
input VAR4;
input VAR3;
input VAR24;
input VAR12;
input VAR17;
input VAR9;
input VAR14;
input VAR18;
output [1:0] VAR22;
output VAR16;
output VAR23;
output V... | mit |
scalable-networks/ext | uhd/fpga/usrp2/boot_cpld/boot_cpld.v | 2,807 | module MODULE1
(input VAR49,
output VAR10,
output [2:0] VAR7,
output [8:0] VAR14,
input VAR47,
output VAR34,
output VAR21,
output VAR15,
input VAR53,
input VAR16, input VAR32, input VAR26, input VAR28,
input VAR20,
output VAR25, output VAR43,
input VAR54,
output VAR55,
output VAR38,
input VAR12,
input VAR6,
input VAR51... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/rtl/bw_clk_cl_jbi_jbus.v | 1,967 | module MODULE1(VAR10,VAR11 ,VAR5 ,VAR1 ,VAR13 ,VAR8 ,
VAR2 ,VAR9 ,VAR12 ,VAR4 ,VAR14 ,VAR3 );
output VAR10 ;
output VAR11 ;
output VAR5 ;
output VAR1 ;
input VAR13 ;
input VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR12 ;
input VAR4 ;
input VAR14 ;
input VAR3 ;
VAR7 VAR6 (
.VAR1 (VAR1 ),
.VAR10 (VAR10 ),
.VAR11 (VAR11 ),
... | gpl-2.0 |
Arlet/vga16 | line.v | 5,708 | module MODULE1(
input clk,
output reg [9:0] VAR68 = 0, output VAR63, input [9:0] VAR62, input [9:0] VAR38, input [9:0] VAR29, input [9:0] VAR39, input [15:0] VAR24, input VAR52,
input VAR51,
input VAR64,
output reg VAR42,
output reg [15:0] VAR32 );
reg [9:0] VAR3 = 0;
reg [9:0] VAR14 = 0; reg [9:0] VAR16 = 0; reg [10:0... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b_2.v | 2,311 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR8 ,
VAR9 ,
VAR6 ,
VAR2,
VAR5,
VAR10 ,
VAR3
);
output VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR9 ;
input VAR6 ;
input VAR2;
input VAR5;
input VAR10 ;
input VAR3 ;
VAR4 VAR11 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR... | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_latch_and.v | 4,384 | module MODULE1 #
(
parameter VAR2 = "VAR7"
)
(
input wire VAR5,
input wire VAR3,
output wire VAR4
);
generate
if ( VAR2 == "VAR11" ) begin : VAR9
assign VAR4 = VAR5 & ~VAR3;
end else begin : VAR6
wire VAR10;
assign VAR10 = ~VAR3;
VAR8 VAR12
(
.VAR4(VAR4),
.VAR1(VAR5),
.VAR13(VAR10)
);
end
endgenerate
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtn/sky130_fd_sc_ms__sdfrtn.blackbox.v | 1,440 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR9
);
output VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR9;
supply1 VAR4;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd/sky130_fd_sc_ms__tapvgnd.pp.symbol.v | 1,258 | module MODULE1 (
input VAR3 ,
input VAR4,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.