repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/ui/ui_wr_data.v | 20,961 | module MODULE1 #
(
parameter VAR76 = 100,
parameter VAR42 = 256,
parameter VAR63 = 32,
parameter VAR32 = "VAR101",
parameter VAR15 = 2 ,
parameter VAR20 = "VAR101",
parameter VAR36 = 5
)
(
VAR74, VAR71, VAR61, VAR6, VAR39,
VAR18,
rst, clk, VAR108, VAR70, VAR103, VAR86,
VAR97, VAR24, VAR5, VAR17, VAR25,
VAR99, VAR87
);
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p.functional.pp.v | 1,867 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR4,
VAR1 ,
VAR8 ,
VAR3 ,
VAR12
);
output VAR10 ;
input VAR7 ;
input VAR4;
input VAR1 ;
input VAR8 ;
input VAR3 ;
input VAR12 ;
wire VAR13 ;
wire VAR6;
not VAR11 (VAR13 , VAR4 );
and VAR9 (VAR6, VAR7, VAR13 );
VAR5 VAR2 (VAR10 , VAR6, VAR1, VAR8);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ebufn/sky130_fd_sc_hd__ebufn.blackbox.v | 1,278 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR7
);
output VAR2 ;
input VAR3 ;
input VAR7;
supply1 VAR5;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
mda-ut/SubZero | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/imu_controller.v | 1,231 | module MODULE1(
input VAR1,
input [3:0]addr,
input read,
output reg [31:0] VAR11,
input VAR10,
input VAR4,
input VAR9,
input VAR3,
output VAR2,
output VAR14,
output VAR12
);
wire [8*32-1:0] VAR7;
VAR6 VAR6(
.VAR8(1'b1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(),
.VAR13(),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR14(VAR14),... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.functional.pp.v | 1,745 | module MODULE1( VAR20, VAR17, VAR3, VAR4, VAR10, VAR13, VAR11, VAR28, VAR22 );
input VAR4, VAR3, VAR10, VAR20, VAR17, VAR11, VAR28, VAR22;
output VAR13;
not VAR25( VAR6, VAR10 );
wire VAR12;
not VAR2( VAR12, VAR3 );
wire VAR24;
not VAR18( VAR24, VAR20 );
wire VAR26;
and VAR5( VAR26, VAR12, VAR24 );
wire VAR27;
not VAR7... | apache-2.0 |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/submodules/lights_nios2_qsys_0_jtag_debug_module_sysclk.v | 6,945 | module MODULE1 (
clk,
VAR8,
VAR27,
VAR17,
VAR14,
VAR21,
VAR7,
VAR9,
VAR31,
VAR26,
VAR11,
VAR4,
VAR6,
VAR16,
VAR12,
VAR30,
VAR28,
VAR13,
VAR33
)
;
output [ 37: 0] VAR21;
output VAR7;
output VAR9;
output VAR31;
output VAR26;
output VAR11;
output VAR4;
output VAR6;
output VAR16;
output VAR12;
output VAR30;
output VAR28;
o... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/add_hdr.v | 6,756 | module MODULE1
parameter VAR5 = 64,
parameter VAR39=VAR5/8,
parameter VAR35 = 'hff,
parameter VAR7 = 0
)
(
VAR15,
VAR38,
VAR1,
VAR27,
VAR6,
VAR36,
VAR25,
VAR43,
reset,
clk
);
input [VAR5-1:0] VAR15;
input [VAR39-1:0] VAR38;
input VAR1;
output reg VAR27;
output reg [VAR5-1:0] VAR6;
output reg [VAR39-1:0] VAR36;
output r... | apache-2.0 |
Giako68/SD_RAM_VIDEO | Serializer_10_1.v | 3,544 | module MODULE1
( input [9:0] VAR6,
input VAR9,
input VAR3,
input VAR5,
output VAR7
);
reg VAR1;
reg [9:0] VAR10; reg [4:0] VAR4; wire VAR2;
wire VAR8;
begin
begin
begin
end
begin | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0n/sky130_fd_sc_lp__iso0n.behavioral.v | 1,293 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR7
);
output VAR1 ;
input VAR6 ;
input VAR7;
supply1 VAR4 ;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR8 ;
and VAR5 (VAR1 , VAR6, VAR7 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_aluor32.v | 3,356 | module MODULE1
(
out,
in
);
input [31:0] in;
output out;
wire VAR14;
wire VAR11;
wire VAR15;
wire VAR12;
wire VAR16;
wire VAR18;
wire VAR24;
wire VAR17;
wire VAR7;
wire VAR19;
wire VAR13;
wire VAR9;
wire VAR6;
wire VAR5;
wire VAR20;
wire VAR2;
wire VAR22;
wire VAR10;
wire VAR1;
wire VAR3;
wire VAR4;
wire VAR21;
wire VA... | gpl-2.0 |
ymei/TMSPlane | Firmware/src/aurora64b66b/fifo_over_ufc.v | 3,080 | module MODULE1
parameter VAR18 = 32,
parameter VAR6 = 64
)
(
input VAR10,
input VAR23,
output reg VAR7,
output [7:0] VAR13,
input VAR1,
output [VAR6-1:0] VAR5,
output reg VAR11,
input [VAR6-1:0] VAR12,
input VAR15,
output VAR9,
output [VAR18-1:0] VAR3,
output VAR8,
input VAR2,
input [VAR18-1:0] VAR16,
output reg VAR17,... | bsd-3-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/yf32/mem_ctrl.v | 13,658 | module MODULE1 (clk, reset, VAR38, VAR12, VAR14, VAR9,
VAR28, VAR13, VAR44, VAR17, VAR2,
VAR39, VAR24, VAR1, VAR41, VAR42);
parameter VAR15 = 1'b0;
parameter VAR23 = 2'b00;
parameter VAR37 = 2'b01;
parameter VAR4 = 2'b10;
parameter VAR6 = 2'b11;
input clk;
input reset;
input VAR38;
input VAR12;
input [31:0] VAR14;
inpu... | mit |
dawsonjon/fpu | double_adder/file_reader_b.v | 1,284 | module MODULE1(VAR3,clk,rst,VAR1,VAR9);
integer VAR5;
integer VAR8;
input clk;
input rst;
output [63:0] VAR1;
output VAR9;
input VAR3;
reg [63:0] VAR6;
reg VAR7;
reg [31:0] VAR4;
reg [31:0] VAR2;
reg [1:0] state;
begin
begin
begin
begin
begin
begin | mit |
nyaxt/dmix | ise/tepla/main.v | 1,746 | module MODULE1(
input VAR31,
input VAR12,
input VAR17,
output VAR3,
output [3:0] VAR5,
output [3:0] VAR15,
output [3:0] VAR26,
output VAR9,
output VAR14,
output VAR1,
output VAR2,
output VAR25,
output VAR21,
output VAR10,
output VAR13,
output VAR11,
output VAR6,
output VAR24,
output VAR22,
output VAR19,
output VAR4,
ou... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_axis_xx_v1_00_a/hdl/verilog/axi_axis_rx_core.v | 5,018 | module MODULE1 (
VAR34,
VAR5,
VAR17,
VAR3,
VAR1,
VAR14,
VAR26,
VAR15,
VAR31,
VAR36,
VAR27,
VAR22,
VAR28,
VAR7,
VAR11,
VAR35);
parameter VAR23 = 64;
localparam VAR32 = VAR23 - 1;
input VAR34;
input VAR5;
input [VAR32:0] VAR17;
input VAR3;
output VAR1;
output VAR14;
output [VAR32:0] VAR26;
input VAR15;
input VAR31;
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o.blackbox.v | 1,394 | module MODULE1 (
VAR4 ,
VAR8,
VAR5,
VAR9,
VAR7,
VAR6
);
output VAR4 ;
input VAR8;
input VAR5;
input VAR9;
input VAR7;
input VAR6;
supply1 VAR3;
supply0 VAR1;
supply1 VAR10 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s.functional.pp.v | 1,868 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR7,
VAR12,
VAR9 ,
VAR4
);
output VAR3 ;
input VAR8 ;
input VAR7;
input VAR12;
input VAR9 ;
input VAR4 ;
wire VAR6 ;
wire VAR1;
buf VAR10 (VAR6 , VAR8 );
VAR11 VAR5 (VAR1, VAR6, VAR7, VAR12);
buf VAR2 (VAR3 , VAR1 );
endmodule | apache-2.0 |
danidim13/labo-digitales | Experimento1/MiniAlu.v | 4,665 | module MODULE1
(
input wire VAR17,
input wire VAR5,
output wire [7:0] VAR34
);
wire [15:0] VAR52,VAR38;
reg VAR23,VAR18;
wire [27:0] VAR26;
wire [3:0] VAR37;
reg [15:0] VAR7;
wire [7:0] VAR27,VAR31,VAR28, VAR10;
wire [15:0] VAR29,VAR21,VAR14,VAR19,VAR2,VAR51,VAR13;
wire VAR12, VAR20, VAR43, VAR35;
VAR36 VAR50
(
.VAR6( ... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_jesd_mon.v | 8,786 | module MODULE1 (
VAR15,
VAR5,
VAR23,
VAR26,
VAR9,
VAR21,
VAR18,
VAR8,
VAR3,
VAR13,
VAR16,
VAR6,
VAR2);
input VAR15;
input VAR5;
input [31:0] VAR23;
input [ 3:0] VAR26;
input [ 3:0] VAR9;
input [ 3:0] VAR21;
input VAR18;
input VAR8;
output VAR3;
output VAR13;
output [ 3:0] VAR16;
output [ 3:0] VAR6;
output [55:0] VAR2;
... | mit |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_ethmac/eth_crc.v | 7,113 | module MODULE1 (VAR3, VAR1, VAR2, VAR9, VAR5, VAR7, VAR6);
parameter VAR4 = 1;
input VAR3;
input VAR1;
input [3:0] VAR2;
input VAR9;
input VAR5;
output [31:0] VAR7;
output VAR6;
reg [31:0] VAR7;
wire [31:0] VAR8;
assign VAR8[0] = VAR9 & (VAR2[0] ^ VAR7[28]);
assign VAR8[1] = VAR9 & (VAR2[1] ^ VAR2[0] ^ VAR7[28] ^ VAR7[... | lgpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_datamux.v | 1,691 | module MODULE1(VAR2, sel, VAR10);
parameter VAR5 = 8;
parameter VAR1 = 1;
parameter VAR9 = 2;
input [VAR9 * VAR5 - 1 : 0] VAR2;
input [VAR1 - 1 : 0] sel;
output [VAR5 - 1 : 0] VAR10;
wire [VAR5 - 1 : 0] VAR15 [0 : VAR9 - 1];
assign VAR10 = VAR15[sel];
genvar VAR12;
generate
for(VAR12 = 0 ; VAR12 < VAR9 ; VAR12 = VAR12 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tap/sky130_fd_sc_hd__tap_2.v | 1,877 | module MODULE2 (
VAR6,
VAR2,
VAR1 ,
VAR5
);
input VAR6;
input VAR2;
input VAR1 ;
input VAR5 ;
VAR4 VAR3 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 ();
supply1 VAR6;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR5 ;
VAR4 VAR3 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31ai/sky130_fd_sc_ms__o31ai_2.v | 2,335 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR3 ,
VAR11 ,
VAR7 ,
VAR2,
VAR9,
VAR6 ,
VAR4
);
output VAR10 ;
input VAR8 ;
input VAR3 ;
input VAR11 ;
input VAR7 ;
input VAR2;
input VAR9;
input VAR6 ;
input VAR4 ;
VAR1 VAR5 (
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.... | apache-2.0 |
JorisBolsens/PYNQ | Pynq-Z1/vivado/ip/arduino_io_switch_1.0/hdl/arduino_io_switch_v1_0.v | 9,870 | module MODULE1 #
(
parameter integer VAR4 = 32,
parameter integer VAR21 = 4
)
(
input [5:0] VAR66,
output [5:0] VAR28,
output [5:0] VAR11,
input [1:0] VAR8,
output [1:0] VAR13,
output [1:0] VAR90,
input [11:0] VAR2,
output [11:0] VAR12,
output [11:0] VAR71,
input VAR14,
output VAR124,
output VAR22,
input VAR102,
output... | bsd-3-clause |
toomij/DE2Labs | Lab2/b2d.v | 5,235 | module MODULE2(VAR10,VAR9,VAR8,VAR6,VAR2);
input [17:0] VAR10;
output [0:6] VAR9,VAR8,VAR6,VAR2;
MODULE1 VAR5 (VAR10[3:0], VAR9);
MODULE1 VAR7 (VAR10[7:4], VAR8);
MODULE1 VAR1 (VAR10[11:8], VAR6);
MODULE1 VAR11 (VAR10[15:12], VAR2);
endmodule
module MODULE1 (VAR4,VAR3);
input [3:0] VAR4;
output [0:6] VAR3;
assign VAR3[... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22a/sky130_fd_sc_hs__o22a_4.v | 2,212 | module MODULE2 (
VAR4 ,
VAR9 ,
VAR2 ,
VAR7 ,
VAR6 ,
VAR1,
VAR5
);
output VAR4 ;
input VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR5;
VAR8 VAR3 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR4 ,
VAR9,
VAR2,
VAR7,
VAR6
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311ai/sky130_fd_sc_ls__o311ai.blackbox.v | 1,381 | module MODULE1 (
VAR8 ,
VAR5,
VAR2,
VAR6,
VAR10,
VAR1
);
output VAR8 ;
input VAR5;
input VAR2;
input VAR6;
input VAR10;
input VAR1;
supply1 VAR3;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
lsnow/mips32 | cloz.v | 1,541 | module MODULE1(
VAR3, VAR1,
VAR4);
input [31:0] VAR3;
input VAR1;
output [31:0] VAR4;
wire [31:0] VAR2 = 32'b0;
wire [31:0] VAR7;
wire [15:0] VAR5;
wire [7:0] VAR8;
wire [3:0] VAR6;
assign VAR7 = VAR1 ? ~VAR3 : VAR3;
assign VAR2[4] = (VAR7[31:16] == 16'b0);
assign VAR5 = VAR2[4] ? VAR7[15:0] : VAR7[31:16];
assign VAR2[... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtn/sky130_fd_sc_ms__dfrtn.functional.v | 1,775 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR5 ,
VAR12
);
output VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR12;
wire VAR1 ;
wire VAR10 ;
wire VAR2;
not VAR8 (VAR10 , VAR12 );
not VAR9 (VAR2, VAR3 );
VAR13 VAR11 VAR7 (VAR1 , VAR5, VAR2, VAR10);
buf VAR4 (VAR6 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a_1.v | 2,322 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR1 ,
VAR4 ,
VAR9 ,
VAR11,
VAR7,
VAR2 ,
VAR10
);
output VAR3 ;
input VAR8 ;
input VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR11;
input VAR7;
input VAR2 ;
input VAR10 ;
VAR6 VAR5 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR2(VAR2),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai.behavioral.pp.v | 2,048 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR12 ,
VAR7 ,
VAR9 ,
VAR1,
VAR10,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR6 ;
input VAR12 ;
input VAR7 ;
input VAR9 ;
input VAR1;
input VAR10;
input VAR8 ;
input VAR2 ;
wire VAR14 ;
wire VAR4 ;
wire VAR16;
or VAR5 (VAR14 , VAR12, VAR6 );
nand VAR13 (VAR4 , VAR9, VAR14, VAR7 );
VAR11 VAR17 ... | apache-2.0 |
jayant-sharma/matrix | hdl/mat/hankel_matrix_2.v | 1,189 | module MODULE1 #(
parameter VAR4 = 4,
parameter VAR8 = 4,
parameter VAR6 = 16,
parameter VAR7 = 8
)(
input clk,
input VAR13,
input [VAR6-1:0] VAR15,
output reg [VAR7-1:0] addr,
output reg rd
);
reg [VAR6-1:0] VAR14 [0:VAR4-1] [0:VAR8-1];
reg [7:0] VAR5,VAR3,VAR11,VAR12,state;
reg [VAR6-1:0] VAR17;
reg [VAR7-1:0] VAR9;
... | unlicense |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_PRE_FIFO.v | 13,456 | module MODULE1(
rst,
VAR245,
VAR218,
din,
VAR146,
VAR31,
dout,
VAR68,
VAR30,
valid
);
input rst;
input VAR245;
input VAR218;
input [255 : 0] din;
input VAR146;
input VAR31;
output [63 : 0] dout;
output VAR68;
output VAR30;
output valid;
VAR338 #(
.VAR24(0),
.VAR168(0),
.VAR62(0),
.VAR391(0),
.VAR80(0),
.VAR200(0),
.VAR... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Rotor_Acceleration_To_Velocity.v | 3,395 | module MODULE1
(
VAR15,
reset,
VAR20,
VAR19,
VAR13,
VAR12
);
input VAR15;
input reset;
input VAR20;
input VAR19;
input signed [17:0] VAR13; output signed [31:0] VAR12;
wire signed [31:0] VAR23; wire signed [17:0] VAR6; wire signed [35:0] VAR1; wire signed [31:0] VAR14; wire signed [32:0] VAR21; wire signed [32:0] VAR22... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isolatch/sky130_fd_sc_lp__isolatch.symbol.v | 1,339 | module MODULE1 (
input VAR7 ,
output VAR4 ,
input VAR2
);
supply1 VAR6;
supply1 VAR3 ;
supply0 VAR1 ;
supply1 VAR8 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1n/sky130_fd_sc_lp__inputiso1n.blackbox.v | 1,355 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR2
);
output VAR7 ;
input VAR6 ;
input VAR2;
supply1 VAR1;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_axis_dma_rx.v | 10,160 | module MODULE1 (
VAR74,
VAR71,
VAR59,
VAR70,
VAR58,
VAR28,
VAR2,
VAR50,
VAR64,
VAR47,
VAR56,
VAR69,
VAR41,
VAR60,
VAR5,
VAR52,
VAR39);
parameter VAR4 = 64;
localparam VAR21 = VAR4 - 1;
localparam VAR75 = 6'd3;
localparam VAR38 = 6'd60;
localparam VAR48 = VAR4/8;
input VAR74;
input VAR71;
output VAR59;
output VAR70;
out... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.functional.pp.v | 1,745 | module MODULE1( VAR11, VAR14, VAR25, VAR10, VAR4, VAR22, VAR3, VAR15, VAR17 );
input VAR10, VAR25, VAR4, VAR11, VAR14, VAR3, VAR15, VAR17;
output VAR22;
not VAR24( VAR1, VAR4 );
wire VAR13;
not VAR20( VAR13, VAR25 );
wire VAR2;
not VAR21( VAR2, VAR11 );
wire VAR7;
and VAR23( VAR7, VAR13, VAR2 );
wire VAR19;
not VAR27( ... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/8-way/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_wrlvl_off_delay.v | 8,955 | module MODULE1 #
(
parameter VAR34 = 100,
parameter VAR23 = 3636,
parameter VAR35 = 2,
parameter VAR19 = 4,
parameter VAR28= 46,
parameter VAR30 = 3,
parameter VAR43 = 8,
parameter VAR22 = 3
)
(
input clk,
input rst,
input VAR15,
input VAR13,
output reg [VAR30:0] VAR31,
output reg VAR27,
output reg VAR45,
output reg VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai.behavioral.v | 1,623 | module MODULE1 (
VAR13 ,
VAR16,
VAR14,
VAR11,
VAR1
);
output VAR13 ;
input VAR16;
input VAR14;
input VAR11;
input VAR1;
supply1 VAR12;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR9 ;
wire VAR6 ;
wire VAR4 ;
wire VAR8;
nor VAR3 (VAR6 , VAR11, VAR1 );
nor VAR5 (VAR4 , VAR16, VAR14 );
or VAR10 (VAR8, VAR4, VAR6);
buf VAR15 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxbp/sky130_fd_sc_hd__dfxbp.symbol.v | 1,338 | module MODULE1 (
input VAR3 ,
output VAR8 ,
output VAR6,
input VAR1
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3/sky130_fd_sc_ls__and3.functional.v | 1,275 | module MODULE1 (
VAR2,
VAR4,
VAR3,
VAR1
);
output VAR2;
input VAR4;
input VAR3;
input VAR1;
wire VAR5;
and VAR6 (VAR5, VAR1, VAR4, VAR3 );
buf VAR7 (VAR2 , VAR5 );
endmodule | apache-2.0 |
AmeerAbdelhadi/Multiported-RAM | mpram_gen.v | 4,459 | module MODULE1
localparam VAR2 = VAR9(VAR11); integer VAR3;
reg [VAR16-1:0] VAR14 [0:VAR11-1]; VAR5
if (VAR4)
for (VAR3=0; VAR3<VAR11; VAR3=VAR3+1) VAR14[VAR3] = {VAR16{1'b0}};
else
if (VAR10 != "")
always @(posedge clk) begin
for (VAR3=1; VAR3<=VAR15; VAR3=VAR3+1)
if (VAR12[VAR3-1]) VAR14[VAR1[VAR3*VAR2-1 -: VAR2]] <=... | bsd-3-clause |
mshr-h/fibonacci_verilog | fpga/de1soc/fpga_top.v | 2,215 | module MODULE1
(
input wire VAR25,
input wire VAR13,
input wire VAR1,
input wire VAR21,
output wire [6:0] VAR17,
output wire [6:0] VAR9,
output wire [6:0] VAR8,
output wire [6:0] VAR12,
output wire [6:0] VAR23,
output wire [6:0] VAR18,
input wire [3:0] VAR26,
input wire [9:0] VAR20,
output wire [9:0] VAR7
);
parameter
... | mit |
yyang29/MIPS | design/mips_decode.v | 3,220 | module MODULE1(
VAR2, VAR9, VAR3, VAR4, VAR8,
VAR10, VAR5
);
input [5:0] VAR10, VAR5;
output reg VAR2, VAR9, VAR3, VAR8;
output reg [3:0] VAR4;
always @(*) begin
VAR4 = 4'VAR7;
VAR2 = 1'b0;
VAR9 = 1'b0;
VAR3 = 1'b0;
VAR8 = 1'VAR1;
case(VAR10)
case(VAR5)
begin
VAR4 = VAR6;
VAR2 = 1'b1;
VAR8 = 1'b0;
end
VAR9 = 1'b1;
defa... | gpl-2.0 |
ptracton/wb_soc_template | rtl/lm32_top/rtl/verilog/lm32_monitor_ram.v | 238,577 | module MODULE1 (VAR90, VAR5, VAR53, VAR14, VAR247,
VAR199, VAR73, VAR141, VAR75, VAR140, VAR243, VAR178, VAR239, VAR22);
input [31:0] VAR90;
input [31:0] VAR5;
input [8:0] VAR53;
input [8:0] VAR14;
input VAR247;
input VAR199;
input VAR73;
input VAR141;
input VAR75;
input VAR140;
input VAR243;
input VAR178;
output [31:0... | mit |
asicguy/gplgpu | hdl/math/flt_recip_orig.v | 10,905 | module MODULE2
(
input clk,
input [31:0] VAR20,
output [31:0] VAR29
);
wire [7:0] VAR14;
MODULE1 MODULE2
(
.clk (clk),
.VAR31 (VAR20[22:16]),
.VAR1 (VAR14)
);
MODULE3 MODULE1
(
.clk (clk),
.VAR30 (VAR14),
.VAR20 (VAR20),
.VAR29 (VAR29)
);
endmodule
module MODULE1
(
input clk,
input [6:0] VAR31,
output reg [7:0] VAR1
);... | gpl-3.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_lane_init_sm.v | 20,206 | module MODULE1
(
VAR46, VAR37,
VAR21,
VAR5,
VAR9,
VAR18,
VAR13,
VAR60,
VAR31,
VAR52,
VAR41,
VAR50,
VAR28,
VAR39,
VAR66,
VAR62,
VAR22,
VAR29,
VAR67,
VAR4,
VAR49,
VAR54
);
input VAR46; input VAR37;
input [1:0] VAR21; input [1:0] VAR5; input [1:0] VAR9; input VAR18;
output VAR13; output VAR60; output VAR31;
output VAR52;
... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v | 2,096 | module MODULE1 #( parameter VAR21(VAR25 )
, parameter VAR21(VAR24 )
, parameter VAR10 = VAR26(VAR24)
, parameter VAR8 = 1
, parameter VAR6 = 1
)
( input VAR5
, input VAR7
, input [VAR25-1:0] VAR18
, input [VAR10-1:0] VAR22
, input VAR15
, input [VAR25-1:0] VAR11
, input VAR16
, output logic [VAR25-1:0] VAR4
);
wire VAR... | bsd-3-clause |
liqimai/ZPC | PersonalComputer/MemoryManagerUnit.v | 2,244 | module MODULE1(
input clk, input VAR13,
input[14:0] VAR1,
input VAR15,
input VAR3,
input VAR11,
input VAR2,
input[31:0] VAR4,
input VAR16,
output[31:0] VAR8,
output reg VAR5,
output VAR17, output VAR7, output VAR6,
output VAR18,
output VAR9
);
parameter VAR10 = 40;
parameter VAR14 = 25;
parameter VAR12 = 14'h3000; | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_2.behavioral.pp.v | 2,214 | module MODULE1( VAR11, VAR3, VAR4, VAR10, VAR7 );
input VAR11, VAR3;
inout VAR10, VAR7;
output VAR4;
reg VAR5;
VAR8 VAR2(.VAR11(VAR11),.VAR3(VAR3),.VAR4(VAR4),.VAR10(VAR10),.VAR7(VAR7),.VAR5(VAR5));
VAR8 VAR9(.VAR11(VAR11),.VAR3(VAR3),.VAR4(VAR4),.VAR10(VAR10),.VAR7(VAR7),.VAR5(VAR5));
not VAR12(VAR6,VAR3);
buf VAR1(VA... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/sfp/sfp2gmii.v | 16,013 | module MODULE1 (
VAR14,
VAR17,
VAR15,
VAR16,
VAR27,
VAR18,
VAR11,
VAR8,
VAR33,
VAR4,
VAR3,
VAR26,
VAR20,
VAR25,
VAR22,
VAR12,
VAR19,
VAR9,
address,
read,
VAR13,
write,
clk,
reset,
VAR2,
VAR21,
VAR23,
VAR28,
VAR1);
output [7:0] VAR14;
output VAR17;
output VAR15;
output VAR16;
output VAR27;
output [15:0] VAR18;
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b_2.v | 2,254 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR8 ,
VAR2 ,
VAR1,
VAR5,
VAR6 ,
VAR7
);
output VAR10 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR6 ;
input VAR7 ;
VAR3 VAR9 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
meteorcloudy/CPU_verilog | diff_d2e.v | 1,657 | module MODULE1(
clk,VAR4,
VAR23,VAR40,VAR36,VAR13,VAR37,VAR22,VAR48,rd,VAR6,VAR46,VAR38,VAR12,VAR1,VAR5,VAR19,
VAR44,VAR18,VAR32,VAR14,VAR45,VAR3,VAR35,VAR24,VAR41,VAR20,VAR43,VAR7,VAR49,VAR30,VAR50
);
input clk,VAR4;
input VAR23,VAR40,VAR36,VAR13,VAR37,VAR22;
input [3:0] VAR48;
input [4:0] rd,VAR12;
input[31:0] VAR6,V... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/07TOUCH/Version_02/02 verilog/ModulosBasicos/FIFO/fifo.v | 2,358 | module MODULE1
parameter VAR7 = 10,
parameter VAR16 = 8
)
(
input clk, reset,
input rd, wr,
input [VAR16-1:0] VAR5,
output [VAR16-1:0] VAR13,
output VAR8,
output VAR12
);
parameter VAR4 = (1 << VAR7);
reg [VAR16-1:0] VAR11 [VAR4-1:0];
reg [VAR7-1:0] VAR3, VAR10;
reg [VAR7-1:0] VAR9, VAR2;
reg VAR15, VAR17, VAR14, VAR6;... | gpl-3.0 |
jakubfi/mera400f | src/pd.v | 11,497 | module MODULE1(
input VAR166,
input [0:15] VAR75, input VAR230, input VAR108, input VAR44, output [0:15] VAR46, input VAR223, output VAR130, output VAR33, output VAR218, output VAR202, output in, output VAR187, output VAR5, output VAR80, output VAR214, output VAR42, output VAR73, output VAR173, output VAR106, output VA... | gpl-2.0 |
Jam-G/MIPS | select.v | 2,837 | module MODULE2(
input [31:0] VAR7,
input [31:0] VAR8,
input VAR4,
output reg [31:0] out
);
always@(VAR7 or VAR8 or VAR4)
case(VAR4)
1'b0:out=VAR7;
1'b1:out=VAR8;
default:out=32'b0;
endcase
endmodule
module MODULE10(
input [7:0] VAR7,
input [7:0] VAR8,
input VAR4,
output reg [7:0] out
);
always@(VAR7 or VAR8 or VAR4)
ca... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4.symbol.v | 1,321 | module MODULE1 (
input VAR4,
input VAR6,
input VAR8,
input VAR1,
output VAR5
);
supply1 VAR7;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
titorgalaxy/lzw | hw/src/RightShift.v | 1,653 | module MODULE1(
VAR4,
VAR6,
VAR1
);
parameter VAR7=0;
localparam VAR3=(1<<VAR7);
output reg [VAR3-1:0] VAR4; input [VAR3-1:0] VAR6; input [VAR7-1:0] VAR1;
reg [VAR3-1:0] VAR5 [VAR7+1-1:0];
always @ begin
if(VAR1[VAR2]) begin
VAR5[VAR2] <= VAR5[VAR2+1][VAR3-1:(1<<VAR2)];
end
else begin
VAR5[VAR2] <= VAR5[VAR2+1];
end
en... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/decap/sky130_fd_sc_ms__decap.pp.symbol.v | 1,200 | module MODULE1 (
input VAR2 ,
input VAR1,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
yugr/primogen | boards/icestick/src/clk_gen.v | 1,059 | module MODULE1 #(
parameter VAR13 = 16
) (
input VAR8,
output clk,
output ready);
localparam VAR9 =
VAR13 == 16 ? 0 :
VAR13 == 36 ? 0 :
-1;
localparam VAR10 =
VAR13 == 16 ? 84 :
VAR13 == 36 ? 47 :
-1;
localparam VAR5 =
VAR13 == 16 ? 6 :
VAR13 == 36 ? 4 :
-1;
localparam VAR15 =
VAR13 == 16 ? 1 :
VAR13 == 36 ? 1 :
-1;
ge... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostSlaveMux/hostSlaveMuxBI.v | 4,807 | module MODULE1 (VAR13, VAR10, address, VAR5, VAR11, VAR6, VAR14,
VAR4, VAR2, VAR7, VAR1, VAR9);
input [7:0] VAR13;
input address;
input VAR5;
input VAR11;
input VAR6;
input VAR14;
output [7:0] VAR10;
input VAR2;
output VAR4;
input VAR7;
output VAR1;
output VAR9;
wire [7:0] VAR13;
wire address;
wire VAR5;
wire VAR11;
wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi.pp.symbol.v | 1,396 | module MODULE1 (
input VAR10 ,
input VAR3 ,
input VAR9 ,
input VAR1 ,
input VAR5 ,
output VAR8 ,
input VAR2 ,
input VAR7,
input VAR6,
input VAR4
);
endmodule | apache-2.0 |
xiedidan/gpsdo-alpha | LCDBridge/LcdBridge.v | 5,873 | module MODULE2(VAR13, clk, VAR16, VAR7, VAR40, VAR17, VAR37, VAR22, VAR38, VAR9);
input VAR13, clk, VAR37, VAR22, VAR38;
output VAR16, VAR7, VAR40, VAR9;
inout [7:0] VAR17;
wire [7:0] VAR36;
wire VAR5; assign VAR17 = VAR5 ? VAR36 : 8'VAR32;
wire [7:0] VAR19, VAR6, VAR26;
wire VAR20;
MODULE1 MODULE2(VAR13, clk, VAR20);
... | gpl-3.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/Dc2Tile.v | 6,346 | module MODULE1(
VAR11, reset,
VAR43, VAR25,
VAR6, VAR19,
VAR34, VAR36,
VAR15,
VAR20, VAR40, VAR27,
VAR37, VAR1, VAR32,
VAR44, VAR22, VAR33,
VAR5, VAR12, VAR21
);
input VAR11; input reset; input[31:0] VAR43; input[127:0] VAR25; input VAR34; input VAR36; input[4:0] VAR15;
output[127:0] VAR6; output[1:0] VAR19;
input[127:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311oi/sky130_fd_sc_hs__a311oi_2.v | 2,323 | module MODULE2 (
VAR1 ,
VAR10 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR5 ,
VAR2,
VAR4
);
output VAR1 ;
input VAR10 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR4;
VAR7 VAR6 (
.VAR1(VAR1),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4/sky130_fd_sc_hdll__and4.symbol.v | 1,296 | module MODULE1 (
input VAR7,
input VAR4,
input VAR8,
input VAR9,
output VAR2
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
sorgelig/ZX_Spectrum-128K_MIST | vram.v | 9,306 | module MODULE1 (
VAR58,
VAR2,
VAR43,
VAR28,
VAR24,
VAR25);
input VAR58;
input [7:0] VAR2;
input [14:0] VAR43;
input [14:0] VAR28;
input VAR24;
output [7:0] VAR25;
tri1 VAR58;
tri0 VAR24;
wire [7:0] VAR53;
wire [7:0] VAR25 = VAR53[7:0];
VAR4 VAR7 (
.VAR39 (VAR28),
.VAR57 (VAR58),
.VAR50 (VAR2),
.VAR44 (VAR24),
.VAR14 (V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2/sky130_fd_sc_ls__and2.functional.v | 1,254 | module MODULE1 (
VAR2,
VAR5,
VAR3
);
output VAR2;
input VAR5;
input VAR3;
wire VAR6;
and VAR4 (VAR6, VAR5, VAR3 );
buf VAR1 (VAR2 , VAR6 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/rom_shared.v | 10,660 | module MODULE1 (
VAR29,
VAR23,
VAR31,
VAR8,
VAR21,
VAR36,
VAR48,
VAR46);
input VAR29;
input [11:0] VAR23;
input [11:0] VAR31;
input VAR8;
input VAR21;
input VAR36;
output [31:0] VAR48;
output [31:0] VAR46;
tri0 VAR29;
tri1 VAR8;
tri1 VAR21;
tri1 VAR36;
wire [31:0] VAR25;
wire [31:0] VAR19;
wire VAR17 = 1'h0;
wire [31:0... | mit |
peteasa/oh | src/elink/hdl/etx.v | 8,299 | module MODULE1(
VAR56, VAR43, VAR52, VAR50, VAR61,
VAR40, VAR60, VAR3, VAR28, VAR19, VAR39,
VAR58, VAR59, VAR15, VAR35, VAR29,
VAR11,
VAR17, VAR4, VAR44, VAR27, VAR12,
VAR34, VAR10, VAR53, VAR48,
VAR23, VAR6, VAR38, VAR5, VAR36
);
parameter VAR51 = 32;
parameter VAR54 = 32;
parameter VAR25 = 104;
parameter VAR42 = 6;
p... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/SPI_Controller/hdl/verilog/spi_top.v | 12,501 | module MODULE1
(
VAR39, VAR41, VAR18, VAR72, VAR69, VAR49,
VAR10, VAR64, VAR8, VAR23, VAR63, VAR45,
VAR26, VAR70, VAR28, VAR2
);
parameter VAR17 = 1;
input VAR39; input VAR41; input [31:0] VAR18; input [32-1:0] VAR72; output [32-1:0] VAR69; input [3:0] VAR49; input VAR10; input VAR64; input VAR8; output VAR23; output V... | bsd-2-clause |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController/src/sys_rst.v | 5,673 | module MODULE1
(
input VAR10,
input VAR24,
input VAR18,
input VAR8,
input VAR20,
input VAR23,
output VAR6,
output VAR15
);
localparam VAR12 = 9;
localparam VAR13 = 380;
localparam VAR3 = 50;
localparam VAR22 = 6'b000001;
localparam VAR19 = 6'b000010;
localparam VAR9 = 6'b000100;
localparam VAR4 = 6'b001000;
localparam ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ebufn/sky130_fd_sc_hs__ebufn_1.v | 2,018 | module MODULE1 (
VAR1 ,
VAR6,
VAR4 ,
VAR5,
VAR7
);
input VAR1 ;
input VAR6;
output VAR4 ;
input VAR5;
input VAR7;
VAR3 VAR2 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR1 ,
VAR6,
VAR4
);
input VAR1 ;
input VAR6;
output VAR4 ;
supply1 VAR5;
supply0 VAR7;
VAR3 VAR2 (
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_2.v | 2,135 | module MODULE2 (
VAR1,
VAR3,
VAR8 ,
VAR4 ,
VAR7,
VAR5
);
output VAR1;
input VAR3;
input VAR8 ;
input VAR4 ;
input VAR7;
input VAR5;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR1,
VAR3,
VAR8 ,
VAR4
);
output VAR1;
input VAR3;
input VAR8 ;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2_4.v | 2,102 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR2 ,
VAR4,
VAR5,
VAR3 ,
VAR9
);
output VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR4;
input VAR5;
input VAR3 ;
input VAR9 ;
VAR1 VAR8 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR6,
VAR7,
VAR2
);
output VAR6;
... | apache-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/11-general/pipeline.v | 18,529 | module MODULE1
parameter VAR161=32, parameter VAR20=5
)
(
input wire clk,
input wire reset,
input wire VAR183,
output wire [VAR161-1:0] VAR74,
output wire [VAR161-1:0] VAR102,
output wire [VAR161-1:0] VAR217,
output wire [VAR161-1:0] VAR235,
output wire [VAR161-1:0] VAR121,
output wire [VAR161-1:0] VAR96,
output wire [... | gpl-3.0 |
TWW12/lzw | ip_repo/edit_axi_compression_v1_0.ip_user_files/ip/bram_4096/bram_4096_stub.v | 1,345 | module MODULE1(VAR5, VAR4, VAR1, VAR6, VAR3, VAR2)
;
input VAR5;
input VAR4;
input [0:0]VAR1;
input [11:0]VAR6;
input [19:0]VAR3;
output [19:0]VAR2;
endmodule | unlicense |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_ACAIIN8Q4_syn.v | 8,054 | module MODULE1 ( VAR277, VAR7, VAR55, VAR15 );
input [15:0] VAR7;
input [15:0] VAR55;
output [16:0] VAR15;
input VAR277;
wire VAR318, VAR4, VAR140, VAR49, VAR44, VAR212, VAR200, VAR221, VAR155, VAR84, VAR32, VAR317, VAR287, VAR316,
VAR93, VAR262, VAR120, VAR225, VAR135, VAR239, VAR11, VAR112, VAR13, VAR258, VAR36, VAR3... | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v | 11,918 | module MODULE1 (
output wire [14:0] VAR48, output wire [2:0] VAR39, output wire VAR35, output wire VAR47, output wire VAR69, output wire VAR12, output wire VAR54, output wire VAR9, output wire VAR31, output wire VAR42, inout wire [31:0] VAR14, inout wire [3:0] VAR22, inout wire [3:0] VAR73, output wire VAR21, output wi... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.behavioral.v | 2,508 | module MODULE1 (
VAR10,
VAR2 ,
VAR4,
VAR1
);
output VAR10;
input VAR2 ;
input VAR4;
input VAR1 ;
supply1 VAR13;
supply0 VAR18;
supply1 VAR15 ;
supply0 VAR8 ;
wire VAR20 ;
wire VAR14 ;
wire VAR25 ;
wire VAR19 ;
wire VAR3 ;
wire VAR9 ;
wire VAR16;
reg VAR23 ;
wire VAR6 ;
wire VAR5 ;
wire VAR12 ;
not VAR11 (VAR14 , VAR20 ... | apache-2.0 |
ace8957/EECE6017C | memory.v | 6,370 | module MODULE1 (
address,
VAR19,
VAR45);
input [4:0] address;
input VAR19;
output [8:0] VAR45;
tri1 VAR19;
wire [8:0] VAR43;
wire [8:0] VAR45 = VAR43[8:0];
VAR46 VAR27 (
.VAR39 (address),
.VAR14 (VAR19),
.VAR22 (VAR43),
.VAR12 (1'b0),
.VAR3 (1'b0),
.VAR13 (1'b1),
.VAR21 (1'b0),
.VAR49 (1'b0),
.VAR16 (1'b1),
.VAR40 (1'b... | gpl-2.0 |
csail-csg/connectal | verilog/PositiveReset.v | 2,850 | module MODULE1 (
VAR5,
VAR6,
VAR1
);
parameter VAR3 = 1 ;
input VAR6 ;
input VAR5 ;
output VAR1 ;
reg VAR4 ;
reg [VAR3:1] VAR2 ;
wire [VAR3+1:0] VAR9 = {VAR2, VAR4, 1'b0} ;
assign VAR1 = VAR2[VAR3] ;
always @( posedge VAR6 ) begin
if (VAR5 == VAR7)
begin
VAR4 <= 1;
VAR2 <= VAR8 -1 ;
end
else
begin
VAR4 <= VAR9[0];
VAR2... | mit |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/Resize.v | 17,627 | module MODULE1 (
VAR25,
VAR5,
VAR72,
VAR27,
VAR45,
VAR36,
VAR9,
VAR29,
VAR33,
VAR2,
VAR61,
VAR28,
VAR62,
VAR49,
VAR75,
VAR1,
VAR76,
VAR77,
VAR39,
VAR6,
VAR79,
VAR48,
VAR40,
VAR13,
VAR37,
VAR80,
VAR20,
VAR42,
VAR51,
VAR64,
VAR56,
VAR15,
VAR69,
VAR30,
VAR14,
VAR22,
VAR11,
VAR16,
VAR81,
VAR82,
VAR26,
VAR60,
VAR55,
VAR4,
V... | mit |
davidkoltak/tawas-core | ip/tawas/rtl/tawas_ls.v | 7,521 | module MODULE1
(
input clk,
input rst,
input [31:0] VAR56,
input [31:0] VAR50,
input [31:0] VAR49,
input [31:0] VAR60,
input [31:0] VAR45,
input [31:0] VAR8,
input [31:0] VAR42,
input [31:0] VAR53,
input VAR40,
input VAR16,
input [2:0] VAR4,
input [31:0] VAR5,
input VAR65,
input [14:0] VAR43,
output reg VAR59,
output r... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_mm_st_converter.v | 10,940 | module MODULE1 # (
parameter
VAR26 = 3,
VAR8 = 25,
VAR25 = 32,
VAR32 = 8,
VAR52 = 4,
VAR64 = 0
)
(
VAR5, VAR30,
VAR10, VAR41,
VAR56, VAR58, VAR20, VAR17, VAR34, VAR51, VAR42, VAR45, VAR31, VAR13,
VAR38, VAR43, VAR27, VAR66,
VAR60,
VAR63,
VAR9,
VAR16,
VAR50,
VAR4,
VAR24,
VAR22,
VAR55,
VAR49,
VAR46,
VAR36,
VAR59,
VAR19,
... | gpl-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/float_mega/float_div/float_div_bb.v | 3,591 | module MODULE1 (
VAR1,
VAR5,
VAR3,
VAR4,
VAR6,
VAR2);
input VAR1;
input [31:0] VAR5;
input [31:0] VAR3;
output VAR4;
output VAR6;
output [31:0] VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode.behavioral.v | 1,185 | module MODULE1 (
VAR1
);
input VAR1;
supply1 VAR2;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
CMCammarano/EE-454-Portable-Ultrasound | Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v | 10,352 | module MODULE1
(
input clk,
input VAR32,
input VAR51,
input [4095:0] VAR44, input [8:0] VAR42,
output [4095:0] VAR18,
output [7:0] VAR27
);
localparam VAR39 = 16; localparam VAR6 = 32; reg [VAR6 * 256 - 1 : 0] VAR37; reg [15:0] VAR29; reg [15:0] VAR1; reg [15:0] VAR49;
reg [8:0] VAR47;
reg [4096:0] VAR50;
reg [7:0] VAR... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_velocityControlHdl.v | 8,576 | module MODULE1
(
VAR48,
reset,
VAR36,
VAR10,
VAR49,
VAR45,
VAR60,
VAR54,
VAR38,
VAR56,
VAR47,
VAR2,
VAR12,
VAR37,
VAR1,
VAR40,
VAR26,
VAR6
);
input VAR48;
input reset;
input VAR36;
input VAR10;
input signed [17:0] VAR49; input signed [17:0] VAR45; input signed [17:0] VAR60; input signed [17:0] VAR54; input signed [17:0... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/wishbone/legacy/wb4_get_block.v | 3,010 | module MODULE1
parameter VAR15 = VAR17-1,
parameter VAR10 = 5,
parameter VAR16 = VAR10-1,
parameter VAR5 = 3)
(
input VAR8,
input VAR2,
output reg VAR14 = 1'b0,
output reg VAR19 = 1'b0,
output VAR18,
input VAR3,
input VAR1,
input VAR7,
input VAR11,
output [VAR16:0] VAR9,
input VAR13,
output reg VAR6 = 1'b0
);
reg [VAR1... | lgpl-3.0 |
ankitshah009/Double_base_Number_system_parallel_adder | DBNS_Project_files_ISE/trial.v | 4,359 | ?module MODULE1(
VAR5,
VAR7,
out);
parameter VAR8 = 5;
input VAR5;
input [VAR8-1:0] VAR7;
output out;wire [VAR8-1:0] VAR7;
wire VAR5;
reg [VAR8-1:0] out;
reg [3:0] VAR18;
reg [3:0] VAR11 = VAR8;
reg [3:0] VAR1 = 4'h0;
reg [VAR8-1:0] VAR4;
reg [4:0] VAR10;
reg [3:0] VAR23 = 4'h0;
reg [3:0] VAR20 = 4'h0;
reg [3:0] VAR3 =... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_jid_to_yid_table.v | 9,236 | module MODULE1 (
VAR66, VAR5,
VAR74, VAR6, VAR32, VAR51, VAR29, clk, VAR47
);
input [3:0] VAR74;
output [9:0] VAR66;
input [3:0] VAR6;
output [9:0] VAR5;
input VAR32;
input [3:0] VAR51;
input [9:0] VAR29;
input clk;
input VAR47;
wire VAR14, VAR42, VAR26, VAR58, VAR11, VAR67, VAR65, VAR64;
wire VAR55, VAR68, VAR70, VAR6... | gpl-2.0 |
alan4186/Hardware-CNN | Hardware/v/sub_sample.v | 1,499 | module MODULE1( input VAR1,
input reset,
input [VAR12:0] VAR5, output [VAR4:0] VAR18
);
wire [VAR4:0] VAR2 [(VAR10*2)-1-1:0];
assign VAR18 = VAR2[0] / VAR10;
genvar VAR7;
generate
for(VAR7=(VAR10*2)-2; VAR7 >=1; VAR7=VAR7-2) begin : VAR3
MODULE2 MODULE1(
.VAR1(VAR1),
.reset(reset),
.VAR17(VAR2[VAR7-1]),
.VAR9(VAR2[VAR7... | mit |
alan4186/ParCNN | DE2_115_CAMERA/v/Line_Buffer1.v | 4,806 | module MODULE1 (
VAR5,
VAR19,
VAR6,
VAR13,
VAR18,
VAR21);
input VAR5;
input VAR19;
input [11:0] VAR6;
output [11:0] VAR13;
output [11:0] VAR18;
output [11:0] VAR21;
tri1 VAR5;
wire [23:0] VAR1;
wire [11:0] VAR20;
wire [23:12] VAR12 = VAR1[23:12];
wire [11:0] VAR15 = VAR1[11:0];
wire [11:0] VAR21 = VAR12[23:12];
wire [1... | mit |
AloriumTechnology/XLR8Pong | extras/rtl/vid_driver.v | 15,268 | module MODULE1(clk,
VAR32,
VAR62,
VAR52,
VAR28,
VAR34,
VAR40,
VAR21,
VAR31,
VAR37,
VAR18,
VAR8,
VAR3
);
input clk;
input VAR32;
input VAR62;
input wire[8:0] VAR52;
input wire[7:0] VAR28;
input wire[7:0] VAR34;
input wire[7:0] VAR40;
input VAR37;
input VAR18;
input VAR8;
input wire[1:0] VAR3;
output reg VAR21;
output VA... | lgpl-3.0 |
zhangly/azpr_cpu | rtl/bus/rtl/bus_arbiter.v | 4,118 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR2, output reg VAR6, input wire VAR4, output reg VAR12, input wire VAR1, output reg VAR11, input wire VAR10, output reg VAR13 );
reg [VAR7] VAR17;
always @(*) begin
VAR6 = VAR5;
VAR12 = VAR5;
VAR11 = VAR5;
VAR13 = VAR5;
case (VAR17)
end
end
end
end
endcase... | mit |
mlab/pvs | hdl_harness/mode_setter.v | 4,539 | module MODULE1
(
VAR33,
VAR7,
VAR20,
VAR13,
VAR23,
VAR16,
VAR5,
VAR3,
VAR15,
);
input VAR33;
input VAR7;
input VAR20;
output VAR13;
output VAR23;
output [15:0] VAR16;
output [15:0] VAR5;
output VAR3;
output VAR15;
parameter VAR10 = 1'b0;
parameter VAR34 = 1'b1;
parameter VAR21 = 16'd33334; parameter VAR27 = 4'd4;
wire ... | gpl-3.0 |
thinkoco/de1_soc_opencl | de1soc_sharedonly_vga/ip/vga_pll/vga_pll/vga_pll_0002.v | 2,230 | module MODULE1(
input wire VAR69,
input wire rst,
output wire VAR17,
output wire VAR25,
output wire VAR9
);
VAR22 #(
.VAR1("false"),
.VAR53("50.0 VAR12"),
.VAR8("VAR63"),
.VAR39(2),
.VAR43("65.000000 VAR12"),
.VAR29("0 VAR11"),
.VAR6(50),
.VAR52("130.000000 VAR12"),
.VAR51("0 VAR11"),
.VAR62(50),
.VAR26("0 VAR12"),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1n/sky130_fd_sc_lp__inputiso1n.functional.pp.v | 1,857 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR6,
VAR12 ,
VAR3 ,
VAR5 ,
VAR1
);
output VAR11 ;
input VAR2 ;
input VAR6;
input VAR12 ;
input VAR3 ;
input VAR5 ;
input VAR1 ;
wire VAR10 ;
wire VAR4;
not VAR9 (VAR10 , VAR6 );
or VAR7 (VAR4, VAR2, VAR10 );
VAR8 VAR13 (VAR11 , VAR4, VAR12, VAR3);
endmodule | apache-2.0 |
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